1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ 2|* *| 3|* Global Instruction Selector for the X86 target *| 4|* *| 5|* Automatically generated file, do not edit! *| 6|* *| 7\*===----------------------------------------------------------------------===*/ 8 9#ifdef GET_GLOBALISEL_PREDICATE_BITSET 10const unsigned MAX_SUBTARGET_PREDICATES = 133; 11using PredicateBitset = llvm::PredicateBitsetImpl<MAX_SUBTARGET_PREDICATES>; 12#endif // ifdef GET_GLOBALISEL_PREDICATE_BITSET 13 14#ifdef GET_GLOBALISEL_TEMPORARIES_DECL 15 mutable MatcherState State; 16 typedef ComplexRendererFns(X86InstructionSelector::*ComplexMatcherMemFn)(MachineOperand &) const; 17 typedef void(X86InstructionSelector::*CustomRendererFn)(MachineInstrBuilder &, const MachineInstr &, int) const; 18 const ISelInfoTy<PredicateBitset, ComplexMatcherMemFn, CustomRendererFn> ISelInfo; 19 static X86InstructionSelector::ComplexMatcherMemFn ComplexPredicateFns[]; 20 static X86InstructionSelector::CustomRendererFn CustomRenderers[]; 21 bool testImmPredicate_I64(unsigned PredicateID, int64_t Imm) const override; 22 bool testImmPredicate_APInt(unsigned PredicateID, const APInt &Imm) const override; 23 bool testImmPredicate_APFloat(unsigned PredicateID, const APFloat &Imm) const override; 24 const int64_t *getMatchTable() const override; 25 bool testMIPredicate_MI(unsigned PredicateID, const MachineInstr &MI, const std::array<const MachineOperand *, 3> &Operands) const override; 26#endif // ifdef GET_GLOBALISEL_TEMPORARIES_DECL 27 28#ifdef GET_GLOBALISEL_TEMPORARIES_INIT 29, State(0), 30ISelInfo(TypeObjects, NumTypeObjects, FeatureBitsets, ComplexPredicateFns, CustomRenderers) 31#endif // ifdef GET_GLOBALISEL_TEMPORARIES_INIT 32 33#ifdef GET_GLOBALISEL_IMPL 34// Bits for subtarget features that participate in instruction matching. 35enum SubtargetFeatureBits : uint8_t { 36 Feature_TruePredicateBit = 54, 37 Feature_HasCMOVBit = 23, 38 Feature_NoCMOVBit = 120, 39 Feature_HasMMXBit = 95, 40 Feature_Has3DNowBit = 97, 41 Feature_HasSSE1Bit = 40, 42 Feature_UseSSE1Bit = 47, 43 Feature_HasSSE2Bit = 39, 44 Feature_UseSSE2Bit = 48, 45 Feature_HasSSE3Bit = 31, 46 Feature_UseSSE3Bit = 57, 47 Feature_HasSSSE3Bit = 96, 48 Feature_UseSSSE3Bit = 58, 49 Feature_UseSSE41Bit = 55, 50 Feature_UseSSE42Bit = 61, 51 Feature_HasSSE4ABit = 71, 52 Feature_NoAVXBit = 67, 53 Feature_HasAVXBit = 49, 54 Feature_HasAVX2Bit = 43, 55 Feature_HasAVX1OnlyBit = 41, 56 Feature_HasAVX512Bit = 80, 57 Feature_UseAVXBit = 45, 58 Feature_NoAVX512Bit = 36, 59 Feature_HasCDIBit = 84, 60 Feature_HasVPOPCNTDQBit = 89, 61 Feature_HasERIBit = 88, 62 Feature_HasDQIBit = 82, 63 Feature_NoDQIBit = 59, 64 Feature_HasBWIBit = 83, 65 Feature_NoBWIBit = 56, 66 Feature_HasVLXBit = 81, 67 Feature_NoVLXBit = 35, 68 Feature_NoVLX_Or_NoBWIBit = 53, 69 Feature_HasVNNIBit = 91, 70 Feature_HasVP2INTERSECTBit = 93, 71 Feature_HasBF16Bit = 94, 72 Feature_HasFP16Bit = 86, 73 Feature_HasAVXVNNIINT8Bit = 78, 74 Feature_HasAVXVNNIBit = 72, 75 Feature_NoVLX_Or_NoVNNIBit = 73, 76 Feature_HasBITALGBit = 92, 77 Feature_HasPOPCNTBit = 60, 78 Feature_HasAESBit = 64, 79 Feature_HasVAESBit = 66, 80 Feature_NoVLX_Or_NoVAESBit = 65, 81 Feature_HasFXSRBit = 32, 82 Feature_HasX87Bit = 30, 83 Feature_HasXSAVEBit = 109, 84 Feature_HasXSAVEOPTBit = 110, 85 Feature_HasXSAVECBit = 111, 86 Feature_HasXSAVESBit = 112, 87 Feature_HasPCLMULBit = 68, 88 Feature_NoVLX_Or_NoVPCLMULQDQBit = 69, 89 Feature_HasVPCLMULQDQBit = 70, 90 Feature_HasGFNIBit = 75, 91 Feature_HasFMABit = 33, 92 Feature_HasFMA4Bit = 37, 93 Feature_NoFMA4Bit = 34, 94 Feature_HasXOPBit = 38, 95 Feature_HasTBMBit = 8, 96 Feature_NoTBMBit = 125, 97 Feature_HasLWPBit = 9, 98 Feature_HasMOVBEBit = 2, 99 Feature_HasRDRANDBit = 3, 100 Feature_HasF16CBit = 74, 101 Feature_HasFSGSBaseBit = 113, 102 Feature_HasLZCNTBit = 5, 103 Feature_HasBMIBit = 6, 104 Feature_HasBMI2Bit = 7, 105 Feature_NoBMI2Bit = 124, 106 Feature_HasVBMIBit = 85, 107 Feature_HasVBMI2Bit = 90, 108 Feature_HasIFMABit = 87, 109 Feature_HasAVXIFMABit = 76, 110 Feature_NoVLX_Or_NoIFMABit = 77, 111 Feature_HasRTMBit = 101, 112 Feature_HasSHABit = 63, 113 Feature_HasRDSEEDBit = 4, 114 Feature_HasSSEPrefetchBit = 50, 115 Feature_NoSSEPrefetchBit = 98, 116 Feature_HasPREFETCHIBit = 17, 117 Feature_HasPrefetchWBit = 99, 118 Feature_HasPREFETCHWT1Bit = 100, 119 Feature_HasMWAITXBit = 123, 120 Feature_HasCLDEMOTEBit = 21, 121 Feature_HasMOVDIRIBit = 11, 122 Feature_HasMOVDIR64BBit = 12, 123 Feature_HasPTWRITEBit = 116, 124 Feature_FPStackf32Bit = 28, 125 Feature_FPStackf64Bit = 29, 126 Feature_HasCLFLUSHBit = 51, 127 Feature_HasCLFLUSHOPTBit = 19, 128 Feature_HasCLWBBit = 20, 129 Feature_HasWBNOINVDBit = 108, 130 Feature_HasRDPIDBit = 115, 131 Feature_HasWAITPKGBit = 10, 132 Feature_HasINVPCIDBit = 114, 133 Feature_HasCX8Bit = 121, 134 Feature_HasCX16Bit = 122, 135 Feature_HasENQCMDBit = 13, 136 Feature_HasAMXFP16Bit = 106, 137 Feature_HasCMPCCXADDBit = 18, 138 Feature_HasAVXNECONVERTBit = 79, 139 Feature_HasKLBit = 102, 140 Feature_HasRAOINTBit = 107, 141 Feature_HasSERIALIZEBit = 14, 142 Feature_HasTSXLDTRKBit = 15, 143 Feature_HasAMXTILEBit = 103, 144 Feature_HasAMXBF16Bit = 105, 145 Feature_HasAMXINT8Bit = 104, 146 Feature_HasUINTRBit = 16, 147 Feature_HasCRC32Bit = 62, 148 Feature_Not64BitModeBit = 0, 149 Feature_In64BitModeBit = 1, 150 Feature_IsLP64Bit = 118, 151 Feature_NotLP64Bit = 117, 152 Feature_NotWin64WithoutFPBit = 119, 153 Feature_IsPSBit = 128, 154 Feature_NotPSBit = 127, 155 Feature_KernelCodeBit = 129, 156 Feature_NearDataBit = 131, 157 Feature_IsNotPICBit = 130, 158 Feature_OptForSizeBit = 44, 159 Feature_OptForMinSizeBit = 42, 160 Feature_OptForSpeedBit = 126, 161 Feature_UseIncDecBit = 22, 162 Feature_NoSSE41_Or_OptForSizeBit = 46, 163 Feature_CallImmAddrBit = 132, 164 Feature_FavorMemIndirectCallBit = 24, 165 Feature_HasFastSHLDRotateBit = 27, 166 Feature_HasMFenceBit = 52, 167 Feature_UseIndirectThunkCallsBit = 26, 168 Feature_NotUseIndirectThunkCallsBit = 25, 169}; 170 171PredicateBitset X86InstructionSelector:: 172computeAvailableModuleFeatures(const X86Subtarget *Subtarget) const { 173 PredicateBitset Features; 174 if (true) 175 Features.set(Feature_TruePredicateBit); 176 if (Subtarget->canUseCMOV()) 177 Features.set(Feature_HasCMOVBit); 178 if (!Subtarget->canUseCMOV()) 179 Features.set(Feature_NoCMOVBit); 180 if (Subtarget->hasMMX()) 181 Features.set(Feature_HasMMXBit); 182 if (Subtarget->hasThreeDNow()) 183 Features.set(Feature_Has3DNowBit); 184 if (Subtarget->hasSSE1()) 185 Features.set(Feature_HasSSE1Bit); 186 if (Subtarget->hasSSE1() && !Subtarget->hasAVX()) 187 Features.set(Feature_UseSSE1Bit); 188 if (Subtarget->hasSSE2()) 189 Features.set(Feature_HasSSE2Bit); 190 if (Subtarget->hasSSE2() && !Subtarget->hasAVX()) 191 Features.set(Feature_UseSSE2Bit); 192 if (Subtarget->hasSSE3()) 193 Features.set(Feature_HasSSE3Bit); 194 if (Subtarget->hasSSE3() && !Subtarget->hasAVX()) 195 Features.set(Feature_UseSSE3Bit); 196 if (Subtarget->hasSSSE3()) 197 Features.set(Feature_HasSSSE3Bit); 198 if (Subtarget->hasSSSE3() && !Subtarget->hasAVX()) 199 Features.set(Feature_UseSSSE3Bit); 200 if (Subtarget->hasSSE41() && !Subtarget->hasAVX()) 201 Features.set(Feature_UseSSE41Bit); 202 if (Subtarget->hasSSE42() && !Subtarget->hasAVX()) 203 Features.set(Feature_UseSSE42Bit); 204 if (Subtarget->hasSSE4A()) 205 Features.set(Feature_HasSSE4ABit); 206 if (!Subtarget->hasAVX()) 207 Features.set(Feature_NoAVXBit); 208 if (Subtarget->hasAVX()) 209 Features.set(Feature_HasAVXBit); 210 if (Subtarget->hasAVX2()) 211 Features.set(Feature_HasAVX2Bit); 212 if (Subtarget->hasAVX() && !Subtarget->hasAVX2()) 213 Features.set(Feature_HasAVX1OnlyBit); 214 if (Subtarget->hasAVX512()) 215 Features.set(Feature_HasAVX512Bit); 216 if (Subtarget->hasAVX() && !Subtarget->hasAVX512()) 217 Features.set(Feature_UseAVXBit); 218 if (!Subtarget->hasAVX512()) 219 Features.set(Feature_NoAVX512Bit); 220 if (Subtarget->hasCDI()) 221 Features.set(Feature_HasCDIBit); 222 if (Subtarget->hasVPOPCNTDQ()) 223 Features.set(Feature_HasVPOPCNTDQBit); 224 if (Subtarget->hasERI()) 225 Features.set(Feature_HasERIBit); 226 if (Subtarget->hasDQI()) 227 Features.set(Feature_HasDQIBit); 228 if (!Subtarget->hasDQI()) 229 Features.set(Feature_NoDQIBit); 230 if (Subtarget->hasBWI()) 231 Features.set(Feature_HasBWIBit); 232 if (!Subtarget->hasBWI()) 233 Features.set(Feature_NoBWIBit); 234 if (Subtarget->hasVLX()) 235 Features.set(Feature_HasVLXBit); 236 if (!Subtarget->hasVLX()) 237 Features.set(Feature_NoVLXBit); 238 if (!Subtarget->hasVLX() || !Subtarget->hasBWI()) 239 Features.set(Feature_NoVLX_Or_NoBWIBit); 240 if (Subtarget->hasVNNI()) 241 Features.set(Feature_HasVNNIBit); 242 if (Subtarget->hasVP2INTERSECT()) 243 Features.set(Feature_HasVP2INTERSECTBit); 244 if (Subtarget->hasBF16()) 245 Features.set(Feature_HasBF16Bit); 246 if (Subtarget->hasFP16()) 247 Features.set(Feature_HasFP16Bit); 248 if (Subtarget->hasAVXVNNIINT8()) 249 Features.set(Feature_HasAVXVNNIINT8Bit); 250 if (Subtarget->hasAVXVNNI()) 251 Features.set(Feature_HasAVXVNNIBit); 252 if (!Subtarget->hasVLX() || !Subtarget->hasVNNI()) 253 Features.set(Feature_NoVLX_Or_NoVNNIBit); 254 if (Subtarget->hasBITALG()) 255 Features.set(Feature_HasBITALGBit); 256 if (Subtarget->hasPOPCNT()) 257 Features.set(Feature_HasPOPCNTBit); 258 if (Subtarget->hasAES()) 259 Features.set(Feature_HasAESBit); 260 if (Subtarget->hasVAES()) 261 Features.set(Feature_HasVAESBit); 262 if (!Subtarget->hasVLX() || !Subtarget->hasVAES()) 263 Features.set(Feature_NoVLX_Or_NoVAESBit); 264 if (Subtarget->hasFXSR()) 265 Features.set(Feature_HasFXSRBit); 266 if (Subtarget->hasX87()) 267 Features.set(Feature_HasX87Bit); 268 if (Subtarget->hasXSAVE()) 269 Features.set(Feature_HasXSAVEBit); 270 if (Subtarget->hasXSAVEOPT()) 271 Features.set(Feature_HasXSAVEOPTBit); 272 if (Subtarget->hasXSAVEC()) 273 Features.set(Feature_HasXSAVECBit); 274 if (Subtarget->hasXSAVES()) 275 Features.set(Feature_HasXSAVESBit); 276 if (Subtarget->hasPCLMUL()) 277 Features.set(Feature_HasPCLMULBit); 278 if (!Subtarget->hasVLX() || !Subtarget->hasVPCLMULQDQ()) 279 Features.set(Feature_NoVLX_Or_NoVPCLMULQDQBit); 280 if (Subtarget->hasVPCLMULQDQ()) 281 Features.set(Feature_HasVPCLMULQDQBit); 282 if (Subtarget->hasGFNI()) 283 Features.set(Feature_HasGFNIBit); 284 if (Subtarget->hasFMA()) 285 Features.set(Feature_HasFMABit); 286 if (Subtarget->hasFMA4()) 287 Features.set(Feature_HasFMA4Bit); 288 if (!Subtarget->hasFMA4()) 289 Features.set(Feature_NoFMA4Bit); 290 if (Subtarget->hasXOP()) 291 Features.set(Feature_HasXOPBit); 292 if (Subtarget->hasTBM()) 293 Features.set(Feature_HasTBMBit); 294 if (!Subtarget->hasTBM()) 295 Features.set(Feature_NoTBMBit); 296 if (Subtarget->hasLWP()) 297 Features.set(Feature_HasLWPBit); 298 if (Subtarget->hasMOVBE()) 299 Features.set(Feature_HasMOVBEBit); 300 if (Subtarget->hasRDRAND()) 301 Features.set(Feature_HasRDRANDBit); 302 if (Subtarget->hasF16C()) 303 Features.set(Feature_HasF16CBit); 304 if (Subtarget->hasFSGSBase()) 305 Features.set(Feature_HasFSGSBaseBit); 306 if (Subtarget->hasLZCNT()) 307 Features.set(Feature_HasLZCNTBit); 308 if (Subtarget->hasBMI()) 309 Features.set(Feature_HasBMIBit); 310 if (Subtarget->hasBMI2()) 311 Features.set(Feature_HasBMI2Bit); 312 if (!Subtarget->hasBMI2()) 313 Features.set(Feature_NoBMI2Bit); 314 if (Subtarget->hasVBMI()) 315 Features.set(Feature_HasVBMIBit); 316 if (Subtarget->hasVBMI2()) 317 Features.set(Feature_HasVBMI2Bit); 318 if (Subtarget->hasIFMA()) 319 Features.set(Feature_HasIFMABit); 320 if (Subtarget->hasAVXIFMA()) 321 Features.set(Feature_HasAVXIFMABit); 322 if (!Subtarget->hasVLX() || !Subtarget->hasIFMA()) 323 Features.set(Feature_NoVLX_Or_NoIFMABit); 324 if (Subtarget->hasRTM()) 325 Features.set(Feature_HasRTMBit); 326 if (Subtarget->hasSHA()) 327 Features.set(Feature_HasSHABit); 328 if (Subtarget->hasRDSEED()) 329 Features.set(Feature_HasRDSEEDBit); 330 if (Subtarget->hasSSEPrefetch()) 331 Features.set(Feature_HasSSEPrefetchBit); 332 if (!Subtarget->hasSSEPrefetch()) 333 Features.set(Feature_NoSSEPrefetchBit); 334 if (Subtarget->hasPREFETCHI()) 335 Features.set(Feature_HasPREFETCHIBit); 336 if (Subtarget->hasPrefetchW()) 337 Features.set(Feature_HasPrefetchWBit); 338 if (Subtarget->hasPREFETCHWT1()) 339 Features.set(Feature_HasPREFETCHWT1Bit); 340 if (Subtarget->hasMWAITX()) 341 Features.set(Feature_HasMWAITXBit); 342 if (Subtarget->hasCLDEMOTE()) 343 Features.set(Feature_HasCLDEMOTEBit); 344 if (Subtarget->hasMOVDIRI()) 345 Features.set(Feature_HasMOVDIRIBit); 346 if (Subtarget->hasMOVDIR64B()) 347 Features.set(Feature_HasMOVDIR64BBit); 348 if (Subtarget->hasPTWRITE()) 349 Features.set(Feature_HasPTWRITEBit); 350 if (!Subtarget->hasSSE1()) 351 Features.set(Feature_FPStackf32Bit); 352 if (!Subtarget->hasSSE2()) 353 Features.set(Feature_FPStackf64Bit); 354 if (Subtarget->hasCLFLUSH()) 355 Features.set(Feature_HasCLFLUSHBit); 356 if (Subtarget->hasCLFLUSHOPT()) 357 Features.set(Feature_HasCLFLUSHOPTBit); 358 if (Subtarget->hasCLWB()) 359 Features.set(Feature_HasCLWBBit); 360 if (Subtarget->hasWBNOINVD()) 361 Features.set(Feature_HasWBNOINVDBit); 362 if (Subtarget->hasRDPID()) 363 Features.set(Feature_HasRDPIDBit); 364 if (Subtarget->hasWAITPKG()) 365 Features.set(Feature_HasWAITPKGBit); 366 if (Subtarget->hasINVPCID()) 367 Features.set(Feature_HasINVPCIDBit); 368 if (Subtarget->hasCX8()) 369 Features.set(Feature_HasCX8Bit); 370 if (Subtarget->hasCX16()) 371 Features.set(Feature_HasCX16Bit); 372 if (Subtarget->hasENQCMD()) 373 Features.set(Feature_HasENQCMDBit); 374 if (Subtarget->hasAMXFP16()) 375 Features.set(Feature_HasAMXFP16Bit); 376 if (Subtarget->hasCMPCCXADD()) 377 Features.set(Feature_HasCMPCCXADDBit); 378 if (Subtarget->hasAVXNECONVERT()) 379 Features.set(Feature_HasAVXNECONVERTBit); 380 if (Subtarget->hasKL()) 381 Features.set(Feature_HasKLBit); 382 if (Subtarget->hasRAOINT()) 383 Features.set(Feature_HasRAOINTBit); 384 if (Subtarget->hasSERIALIZE()) 385 Features.set(Feature_HasSERIALIZEBit); 386 if (Subtarget->hasTSXLDTRK()) 387 Features.set(Feature_HasTSXLDTRKBit); 388 if (Subtarget->hasAMXTILE()) 389 Features.set(Feature_HasAMXTILEBit); 390 if (Subtarget->hasAMXBF16()) 391 Features.set(Feature_HasAMXBF16Bit); 392 if (Subtarget->hasAMXINT8()) 393 Features.set(Feature_HasAMXINT8Bit); 394 if (Subtarget->hasUINTR()) 395 Features.set(Feature_HasUINTRBit); 396 if (Subtarget->hasCRC32()) 397 Features.set(Feature_HasCRC32Bit); 398 if (!Subtarget->is64Bit()) 399 Features.set(Feature_Not64BitModeBit); 400 if (Subtarget->is64Bit()) 401 Features.set(Feature_In64BitModeBit); 402 if (Subtarget->isTarget64BitLP64()) 403 Features.set(Feature_IsLP64Bit); 404 if (!Subtarget->isTarget64BitLP64()) 405 Features.set(Feature_NotLP64Bit); 406 if (Subtarget->isTargetPS()) 407 Features.set(Feature_IsPSBit); 408 if (!Subtarget->isTargetPS()) 409 Features.set(Feature_NotPSBit); 410 if (TM.getCodeModel() == CodeModel::Kernel) 411 Features.set(Feature_KernelCodeBit); 412 if (TM.getCodeModel() == CodeModel::Small ||TM.getCodeModel() == CodeModel::Kernel) 413 Features.set(Feature_NearDataBit); 414 if (!TM.isPositionIndependent()) 415 Features.set(Feature_IsNotPICBit); 416 if (Subtarget->isLegalToCallImmediateAddr()) 417 Features.set(Feature_CallImmAddrBit); 418 if (!Subtarget->slowTwoMemOps()) 419 Features.set(Feature_FavorMemIndirectCallBit); 420 if (Subtarget->hasFastSHLDRotate()) 421 Features.set(Feature_HasFastSHLDRotateBit); 422 if (Subtarget->hasMFence()) 423 Features.set(Feature_HasMFenceBit); 424 if (Subtarget->useIndirectThunkCalls()) 425 Features.set(Feature_UseIndirectThunkCallsBit); 426 if (!Subtarget->useIndirectThunkCalls()) 427 Features.set(Feature_NotUseIndirectThunkCallsBit); 428 return Features; 429} 430 431void X86InstructionSelector::setupGeneratedPerFunctionState(MachineFunction &MF) { 432 AvailableFunctionFeatures = computeAvailableFunctionFeatures((const X86Subtarget *)&MF.getSubtarget(), &MF); 433} 434PredicateBitset X86InstructionSelector:: 435computeAvailableFunctionFeatures(const X86Subtarget *Subtarget, const MachineFunction *MF) const { 436 PredicateBitset Features; 437 if (!Subtarget->isTargetWin64() ||Subtarget->getFrameLowering()->hasFP(*MF)) 438 Features.set(Feature_NotWin64WithoutFPBit); 439 if (shouldOptForSize(MF)) 440 Features.set(Feature_OptForSizeBit); 441 if (MF->getFunction().hasMinSize()) 442 Features.set(Feature_OptForMinSizeBit); 443 if (!shouldOptForSize(MF)) 444 Features.set(Feature_OptForSpeedBit); 445 if (!Subtarget->slowIncDec() || shouldOptForSize(MF)) 446 Features.set(Feature_UseIncDecBit); 447 if (shouldOptForSize(MF) || !Subtarget->hasSSE41()) 448 Features.set(Feature_NoSSE41_Or_OptForSizeBit); 449 return Features; 450} 451 452// LLT Objects. 453enum { 454 GILLT_s1, 455 GILLT_s8, 456 GILLT_s16, 457 GILLT_s32, 458 GILLT_s64, 459 GILLT_s80, 460 GILLT_s128, 461 GILLT_v2s1, 462 GILLT_v2s64, 463 GILLT_v4s1, 464 GILLT_v4s32, 465 GILLT_v4s64, 466 GILLT_v8s1, 467 GILLT_v8s16, 468 GILLT_v8s32, 469 GILLT_v8s64, 470 GILLT_v16s1, 471 GILLT_v16s8, 472 GILLT_v16s16, 473 GILLT_v16s32, 474 GILLT_v32s1, 475 GILLT_v32s8, 476 GILLT_v32s16, 477 GILLT_v64s1, 478 GILLT_v64s8, 479}; 480const static size_t NumTypeObjects = 25; 481const static LLT TypeObjects[] = { 482 LLT::scalar(1), 483 LLT::scalar(8), 484 LLT::scalar(16), 485 LLT::scalar(32), 486 LLT::scalar(64), 487 LLT::scalar(80), 488 LLT::scalar(128), 489 LLT::vector(ElementCount::getFixed(2), 1), 490 LLT::vector(ElementCount::getFixed(2), 64), 491 LLT::vector(ElementCount::getFixed(4), 1), 492 LLT::vector(ElementCount::getFixed(4), 32), 493 LLT::vector(ElementCount::getFixed(4), 64), 494 LLT::vector(ElementCount::getFixed(8), 1), 495 LLT::vector(ElementCount::getFixed(8), 16), 496 LLT::vector(ElementCount::getFixed(8), 32), 497 LLT::vector(ElementCount::getFixed(8), 64), 498 LLT::vector(ElementCount::getFixed(16), 1), 499 LLT::vector(ElementCount::getFixed(16), 8), 500 LLT::vector(ElementCount::getFixed(16), 16), 501 LLT::vector(ElementCount::getFixed(16), 32), 502 LLT::vector(ElementCount::getFixed(32), 1), 503 LLT::vector(ElementCount::getFixed(32), 8), 504 LLT::vector(ElementCount::getFixed(32), 16), 505 LLT::vector(ElementCount::getFixed(64), 1), 506 LLT::vector(ElementCount::getFixed(64), 8), 507}; 508 509// Feature bitsets. 510enum { 511 GIFBS_Invalid, 512 GIFBS_FPStackf32, 513 GIFBS_FPStackf64, 514 GIFBS_Has3DNow, 515 GIFBS_HasAVX, 516 GIFBS_HasAVX1Only, 517 GIFBS_HasAVX2, 518 GIFBS_HasAVX512, 519 GIFBS_HasAVXNECONVERT, 520 GIFBS_HasBITALG, 521 GIFBS_HasBMI, 522 GIFBS_HasBMI2, 523 GIFBS_HasBWI, 524 GIFBS_HasCDI, 525 GIFBS_HasCRC32, 526 GIFBS_HasDQI, 527 GIFBS_HasFP16, 528 GIFBS_HasFastSHLDRotate, 529 GIFBS_HasKL, 530 GIFBS_HasLWP, 531 GIFBS_HasMFence, 532 GIFBS_HasMMX, 533 GIFBS_HasMOVBE, 534 GIFBS_HasMWAITX, 535 GIFBS_HasPTWRITE, 536 GIFBS_HasRTM, 537 GIFBS_HasSERIALIZE, 538 GIFBS_HasSHA, 539 GIFBS_HasSSE1, 540 GIFBS_HasSSE2, 541 GIFBS_HasSSE3, 542 GIFBS_HasSSE4A, 543 GIFBS_HasTBM, 544 GIFBS_HasTSXLDTRK, 545 GIFBS_HasVLX, 546 GIFBS_HasVPOPCNTDQ, 547 GIFBS_HasWAITPKG, 548 GIFBS_HasWBNOINVD, 549 GIFBS_HasX87, 550 GIFBS_HasXOP, 551 GIFBS_In64BitMode, 552 GIFBS_NoDQI, 553 GIFBS_Not64BitMode, 554 GIFBS_UseAVX, 555 GIFBS_UseIncDec, 556 GIFBS_UseSSE1, 557 GIFBS_UseSSE2, 558 GIFBS_UseSSE41, 559 GIFBS_UseSSSE3, 560 GIFBS_HasAES_HasAVX, 561 GIFBS_HasAES_NoAVX, 562 GIFBS_HasAMXBF16_In64BitMode, 563 GIFBS_HasAMXFP16_In64BitMode, 564 GIFBS_HasAMXINT8_In64BitMode, 565 GIFBS_HasAMXTILE_In64BitMode, 566 GIFBS_HasAVX_In64BitMode, 567 GIFBS_HasAVX_NoBWI, 568 GIFBS_HasAVX_NoVLX, 569 GIFBS_HasAVX_NoVLX_Or_NoBWI, 570 GIFBS_HasAVX2_NoVLX, 571 GIFBS_HasAVX2_NoVLX_Or_NoBWI, 572 GIFBS_HasAVX512_HasVAES, 573 GIFBS_HasAVX512_HasVLX, 574 GIFBS_HasAVX512_HasVPCLMULQDQ, 575 GIFBS_HasAVX512_NoBWI, 576 GIFBS_HasAVX512_NoDQI, 577 GIFBS_HasAVX512_NoVLX, 578 GIFBS_HasBF16_HasVLX, 579 GIFBS_HasBITALG_HasVLX, 580 GIFBS_HasBITALG_NoVLX, 581 GIFBS_HasBWI_HasVLX, 582 GIFBS_HasBWI_NoVLX, 583 GIFBS_HasCDI_HasVLX, 584 GIFBS_HasCDI_NoVLX, 585 GIFBS_HasDQI_HasVLX, 586 GIFBS_HasDQI_NoBWI, 587 GIFBS_HasDQI_NoVLX, 588 GIFBS_HasFMA4_NoAVX512, 589 GIFBS_HasFMA4_NoVLX, 590 GIFBS_HasFP16_HasVLX, 591 GIFBS_HasFSGSBase_In64BitMode, 592 GIFBS_HasPCLMUL_NoAVX, 593 GIFBS_HasPTWRITE_In64BitMode, 594 GIFBS_HasRDPID_In64BitMode, 595 GIFBS_HasRDPID_Not64BitMode, 596 GIFBS_HasUINTR_In64BitMode, 597 GIFBS_HasVAES_HasVLX, 598 GIFBS_HasVAES_NoVLX, 599 GIFBS_HasVLX_HasVPCLMULQDQ, 600 GIFBS_HasVLX_HasVPOPCNTDQ, 601 GIFBS_HasVPCLMULQDQ_NoVLX, 602 GIFBS_HasVPOPCNTDQ_NoVLX, 603 GIFBS_HasWAITPKG_In64BitMode, 604 GIFBS_HasWAITPKG_Not64BitMode, 605 GIFBS_In64BitMode_UseSSE2, 606 GIFBS_Not64BitMode_OptForSize, 607 GIFBS_NotWin64WithoutFP_OptForMinSize, 608 GIFBS_HasAES_HasAVX_NoVLX_Or_NoVAES, 609 GIFBS_HasAVX_HasPCLMUL_NoVLX_Or_NoVPCLMULQDQ, 610 GIFBS_HasDQI_HasVLX_NoBWI, 611 GIFBS_HasFMA_NoAVX512_NoFMA4, 612 GIFBS_HasFMA_NoFMA4_NoVLX, 613}; 614const static PredicateBitset FeatureBitsets[] { 615 {}, // GIFBS_Invalid 616 {Feature_FPStackf32Bit, }, 617 {Feature_FPStackf64Bit, }, 618 {Feature_Has3DNowBit, }, 619 {Feature_HasAVXBit, }, 620 {Feature_HasAVX1OnlyBit, }, 621 {Feature_HasAVX2Bit, }, 622 {Feature_HasAVX512Bit, }, 623 {Feature_HasAVXNECONVERTBit, }, 624 {Feature_HasBITALGBit, }, 625 {Feature_HasBMIBit, }, 626 {Feature_HasBMI2Bit, }, 627 {Feature_HasBWIBit, }, 628 {Feature_HasCDIBit, }, 629 {Feature_HasCRC32Bit, }, 630 {Feature_HasDQIBit, }, 631 {Feature_HasFP16Bit, }, 632 {Feature_HasFastSHLDRotateBit, }, 633 {Feature_HasKLBit, }, 634 {Feature_HasLWPBit, }, 635 {Feature_HasMFenceBit, }, 636 {Feature_HasMMXBit, }, 637 {Feature_HasMOVBEBit, }, 638 {Feature_HasMWAITXBit, }, 639 {Feature_HasPTWRITEBit, }, 640 {Feature_HasRTMBit, }, 641 {Feature_HasSERIALIZEBit, }, 642 {Feature_HasSHABit, }, 643 {Feature_HasSSE1Bit, }, 644 {Feature_HasSSE2Bit, }, 645 {Feature_HasSSE3Bit, }, 646 {Feature_HasSSE4ABit, }, 647 {Feature_HasTBMBit, }, 648 {Feature_HasTSXLDTRKBit, }, 649 {Feature_HasVLXBit, }, 650 {Feature_HasVPOPCNTDQBit, }, 651 {Feature_HasWAITPKGBit, }, 652 {Feature_HasWBNOINVDBit, }, 653 {Feature_HasX87Bit, }, 654 {Feature_HasXOPBit, }, 655 {Feature_In64BitModeBit, }, 656 {Feature_NoDQIBit, }, 657 {Feature_Not64BitModeBit, }, 658 {Feature_UseAVXBit, }, 659 {Feature_UseIncDecBit, }, 660 {Feature_UseSSE1Bit, }, 661 {Feature_UseSSE2Bit, }, 662 {Feature_UseSSE41Bit, }, 663 {Feature_UseSSSE3Bit, }, 664 {Feature_HasAESBit, Feature_HasAVXBit, }, 665 {Feature_HasAESBit, Feature_NoAVXBit, }, 666 {Feature_HasAMXBF16Bit, Feature_In64BitModeBit, }, 667 {Feature_HasAMXFP16Bit, Feature_In64BitModeBit, }, 668 {Feature_HasAMXINT8Bit, Feature_In64BitModeBit, }, 669 {Feature_HasAMXTILEBit, Feature_In64BitModeBit, }, 670 {Feature_HasAVXBit, Feature_In64BitModeBit, }, 671 {Feature_HasAVXBit, Feature_NoBWIBit, }, 672 {Feature_HasAVXBit, Feature_NoVLXBit, }, 673 {Feature_HasAVXBit, Feature_NoVLX_Or_NoBWIBit, }, 674 {Feature_HasAVX2Bit, Feature_NoVLXBit, }, 675 {Feature_HasAVX2Bit, Feature_NoVLX_Or_NoBWIBit, }, 676 {Feature_HasAVX512Bit, Feature_HasVAESBit, }, 677 {Feature_HasAVX512Bit, Feature_HasVLXBit, }, 678 {Feature_HasAVX512Bit, Feature_HasVPCLMULQDQBit, }, 679 {Feature_HasAVX512Bit, Feature_NoBWIBit, }, 680 {Feature_HasAVX512Bit, Feature_NoDQIBit, }, 681 {Feature_HasAVX512Bit, Feature_NoVLXBit, }, 682 {Feature_HasBF16Bit, Feature_HasVLXBit, }, 683 {Feature_HasBITALGBit, Feature_HasVLXBit, }, 684 {Feature_HasBITALGBit, Feature_NoVLXBit, }, 685 {Feature_HasBWIBit, Feature_HasVLXBit, }, 686 {Feature_HasBWIBit, Feature_NoVLXBit, }, 687 {Feature_HasCDIBit, Feature_HasVLXBit, }, 688 {Feature_HasCDIBit, Feature_NoVLXBit, }, 689 {Feature_HasDQIBit, Feature_HasVLXBit, }, 690 {Feature_HasDQIBit, Feature_NoBWIBit, }, 691 {Feature_HasDQIBit, Feature_NoVLXBit, }, 692 {Feature_HasFMA4Bit, Feature_NoAVX512Bit, }, 693 {Feature_HasFMA4Bit, Feature_NoVLXBit, }, 694 {Feature_HasFP16Bit, Feature_HasVLXBit, }, 695 {Feature_HasFSGSBaseBit, Feature_In64BitModeBit, }, 696 {Feature_HasPCLMULBit, Feature_NoAVXBit, }, 697 {Feature_HasPTWRITEBit, Feature_In64BitModeBit, }, 698 {Feature_HasRDPIDBit, Feature_In64BitModeBit, }, 699 {Feature_HasRDPIDBit, Feature_Not64BitModeBit, }, 700 {Feature_HasUINTRBit, Feature_In64BitModeBit, }, 701 {Feature_HasVAESBit, Feature_HasVLXBit, }, 702 {Feature_HasVAESBit, Feature_NoVLXBit, }, 703 {Feature_HasVLXBit, Feature_HasVPCLMULQDQBit, }, 704 {Feature_HasVLXBit, Feature_HasVPOPCNTDQBit, }, 705 {Feature_HasVPCLMULQDQBit, Feature_NoVLXBit, }, 706 {Feature_HasVPOPCNTDQBit, Feature_NoVLXBit, }, 707 {Feature_HasWAITPKGBit, Feature_In64BitModeBit, }, 708 {Feature_HasWAITPKGBit, Feature_Not64BitModeBit, }, 709 {Feature_In64BitModeBit, Feature_UseSSE2Bit, }, 710 {Feature_Not64BitModeBit, Feature_OptForSizeBit, }, 711 {Feature_NotWin64WithoutFPBit, Feature_OptForMinSizeBit, }, 712 {Feature_HasAESBit, Feature_HasAVXBit, Feature_NoVLX_Or_NoVAESBit, }, 713 {Feature_HasAVXBit, Feature_HasPCLMULBit, Feature_NoVLX_Or_NoVPCLMULQDQBit, }, 714 {Feature_HasDQIBit, Feature_HasVLXBit, Feature_NoBWIBit, }, 715 {Feature_HasFMABit, Feature_NoAVX512Bit, Feature_NoFMA4Bit, }, 716 {Feature_HasFMABit, Feature_NoFMA4Bit, Feature_NoVLXBit, }, 717}; 718 719// ComplexPattern predicates. 720enum { 721 GICP_Invalid, 722}; 723// See constructor for table contents 724 725// PatFrag predicates. 726enum { 727 GIPFP_I64_Predicate_AndMask64 = GIPFP_I64_Invalid + 1, 728 GIPFP_I64_Predicate_BTCBTSMask64, 729 GIPFP_I64_Predicate_BTRMask64, 730 GIPFP_I64_Predicate_PrefetchWT1Level, 731 GIPFP_I64_Predicate_i16immSExt8, 732 GIPFP_I64_Predicate_i32immSExt8, 733 GIPFP_I64_Predicate_i64immSExt32, 734 GIPFP_I64_Predicate_i64immSExt8, 735 GIPFP_I64_Predicate_i64immZExt32, 736 GIPFP_I64_Predicate_i64immZExt32SExt8, 737 GIPFP_I64_Predicate_i64timmSExt32, 738 GIPFP_I64_Predicate_immff00_ffff, 739}; 740bool X86InstructionSelector::testImmPredicate_I64(unsigned PredicateID, int64_t Imm) const { 741 switch (PredicateID) { 742 case GIPFP_I64_Predicate_AndMask64: { 743 744 return isMask_64(Imm) && !isUInt<32>(Imm); 745 746 llvm_unreachable("ImmediateCode should have returned"); 747 return false; 748 } 749 case GIPFP_I64_Predicate_BTCBTSMask64: { 750 751 return !isInt<32>(Imm) && isPowerOf2_64(Imm); 752 753 llvm_unreachable("ImmediateCode should have returned"); 754 return false; 755 } 756 case GIPFP_I64_Predicate_BTRMask64: { 757 758 return !isUInt<32>(Imm) && !isInt<32>(Imm) && isPowerOf2_64(~Imm); 759 760 llvm_unreachable("ImmediateCode should have returned"); 761 return false; 762 } 763 case GIPFP_I64_Predicate_PrefetchWT1Level: { 764 765 return Imm < 3; 766 767 llvm_unreachable("ImmediateCode should have returned"); 768 return false; 769 } 770 case GIPFP_I64_Predicate_i16immSExt8: { 771 return isInt<8>(Imm); 772 llvm_unreachable("ImmediateCode should have returned"); 773 return false; 774 } 775 case GIPFP_I64_Predicate_i32immSExt8: { 776 return isInt<8>(Imm); 777 llvm_unreachable("ImmediateCode should have returned"); 778 return false; 779 } 780 case GIPFP_I64_Predicate_i64immSExt32: { 781 return isInt<32>(Imm); 782 llvm_unreachable("ImmediateCode should have returned"); 783 return false; 784 } 785 case GIPFP_I64_Predicate_i64immSExt8: { 786 return isInt<8>(Imm); 787 llvm_unreachable("ImmediateCode should have returned"); 788 return false; 789 } 790 case GIPFP_I64_Predicate_i64immZExt32: { 791 return isUInt<32>(Imm); 792 llvm_unreachable("ImmediateCode should have returned"); 793 return false; 794 } 795 case GIPFP_I64_Predicate_i64immZExt32SExt8: { 796 797 return isUInt<32>(Imm) && isInt<8>(static_cast<int32_t>(Imm)); 798 799 llvm_unreachable("ImmediateCode should have returned"); 800 return false; 801 } 802 case GIPFP_I64_Predicate_i64timmSExt32: { 803 return isInt<32>(Imm); 804 llvm_unreachable("ImmediateCode should have returned"); 805 return false; 806 } 807 case GIPFP_I64_Predicate_immff00_ffff: { 808 809 return Imm >= 0xff00 && Imm <= 0xffff; 810 811 llvm_unreachable("ImmediateCode should have returned"); 812 return false; 813 } 814 } 815 llvm_unreachable("Unknown predicate"); 816 return false; 817} 818// PatFrag predicates. 819enum { 820 GIPFP_APFloat_Predicate_fpimm0 = GIPFP_APFloat_Invalid + 1, 821 GIPFP_APFloat_Predicate_fpimm1, 822 GIPFP_APFloat_Predicate_fpimmneg0, 823 GIPFP_APFloat_Predicate_fpimmneg1, 824}; 825bool X86InstructionSelector::testImmPredicate_APFloat(unsigned PredicateID, const APFloat & Imm) const { 826 switch (PredicateID) { 827 case GIPFP_APFloat_Predicate_fpimm0: { 828 829 return Imm.isExactlyValue(+0.0); 830 831 llvm_unreachable("ImmediateCode should have returned"); 832 return false; 833 } 834 case GIPFP_APFloat_Predicate_fpimm1: { 835 836 return Imm.isExactlyValue(+1.0); 837 838 llvm_unreachable("ImmediateCode should have returned"); 839 return false; 840 } 841 case GIPFP_APFloat_Predicate_fpimmneg0: { 842 843 return Imm.isExactlyValue(-0.0); 844 845 llvm_unreachable("ImmediateCode should have returned"); 846 return false; 847 } 848 case GIPFP_APFloat_Predicate_fpimmneg1: { 849 850 return Imm.isExactlyValue(-1.0); 851 852 llvm_unreachable("ImmediateCode should have returned"); 853 return false; 854 } 855 } 856 llvm_unreachable("Unknown predicate"); 857 return false; 858} 859bool X86InstructionSelector::testImmPredicate_APInt(unsigned PredicateID, const APInt & Imm) const { 860 llvm_unreachable("Unknown predicate"); 861 return false; 862} 863bool X86InstructionSelector::testMIPredicate_MI(unsigned PredicateID, const MachineInstr & MI, const std::array<const MachineOperand *, 3> &Operands) const { 864 const MachineFunction &MF = *MI.getParent()->getParent(); 865 const MachineRegisterInfo &MRI = MF.getRegInfo(); 866 (void)MRI; 867 llvm_unreachable("Unknown predicate"); 868 return false; 869} 870 871X86InstructionSelector::ComplexMatcherMemFn 872X86InstructionSelector::ComplexPredicateFns[] = { 873 nullptr, // GICP_Invalid 874}; 875 876// Custom renderers. 877enum { 878 GICR_Invalid, 879}; 880X86InstructionSelector::CustomRendererFn 881X86InstructionSelector::CustomRenderers[] = { 882 nullptr, // GICR_Invalid 883}; 884 885bool X86InstructionSelector::selectImpl(MachineInstr &I, CodeGenCoverage &CoverageInfo) const { 886 MachineFunction &MF = *I.getParent()->getParent(); 887 MachineRegisterInfo &MRI = MF.getRegInfo(); 888 const PredicateBitset AvailableFeatures = getAvailableFeatures(); 889 NewMIVector OutMIs; 890 State.MIs.clear(); 891 State.MIs.push_back(&I); 892 893 if (executeMatchTable(*this, OutMIs, State, ISelInfo, getMatchTable(), TII, MRI, TRI, RBI, AvailableFeatures, CoverageInfo)) { 894 return true; 895 } 896 897 return false; 898} 899 900const int64_t *X86InstructionSelector::getMatchTable() const { 901 constexpr static int64_t MatchTable0[] = { 902 GIM_SwitchOpcode, /*MI*/0, /*[*/46, 227, /*)*//*default:*//*Label 61*/ 63086, 903 /*TargetOpcode::G_ADD*//*Label 0*/ 186, 904 /*TargetOpcode::G_SUB*//*Label 1*/ 1803, 905 /*TargetOpcode::G_MUL*//*Label 2*/ 2884, 0, 0, 0, 0, 0, 0, 906 /*TargetOpcode::G_AND*//*Label 3*/ 3954, 907 /*TargetOpcode::G_OR*//*Label 4*/ 9364, 908 /*TargetOpcode::G_XOR*//*Label 5*/ 13234, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 909 /*TargetOpcode::G_CONCAT_VECTORS*//*Label 6*/ 20965, 0, 0, 910 /*TargetOpcode::G_BITCAST*//*Label 7*/ 21121, 0, 0, 0, 0, 911 /*TargetOpcode::G_INTRINSIC_LRINT*//*Label 8*/ 22667, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 912 /*TargetOpcode::G_INTRINSIC*//*Label 9*/ 22990, 913 /*TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS*//*Label 10*/ 28683, 914 /*TargetOpcode::G_ANYEXT*//*Label 11*/ 31047, 915 /*TargetOpcode::G_TRUNC*//*Label 12*/ 31458, 916 /*TargetOpcode::G_CONSTANT*//*Label 13*/ 32316, 917 /*TargetOpcode::G_FCONSTANT*//*Label 14*/ 32585, 0, 0, 918 /*TargetOpcode::G_SEXT*//*Label 15*/ 32736, 0, 919 /*TargetOpcode::G_ZEXT*//*Label 16*/ 33596, 920 /*TargetOpcode::G_SHL*//*Label 17*/ 34384, 921 /*TargetOpcode::G_LSHR*//*Label 18*/ 34977, 922 /*TargetOpcode::G_ASHR*//*Label 19*/ 35554, 923 /*TargetOpcode::G_FSHL*//*Label 20*/ 36131, 924 /*TargetOpcode::G_FSHR*//*Label 21*/ 36338, 925 /*TargetOpcode::G_ROTR*//*Label 22*/ 36545, 926 /*TargetOpcode::G_ROTL*//*Label 23*/ 38007, 927 /*TargetOpcode::G_ICMP*//*Label 24*/ 39515, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 928 /*TargetOpcode::G_UMULH*//*Label 25*/ 41072, 929 /*TargetOpcode::G_SMULH*//*Label 26*/ 41260, 930 /*TargetOpcode::G_UADDSAT*//*Label 27*/ 41448, 931 /*TargetOpcode::G_SADDSAT*//*Label 28*/ 41809, 932 /*TargetOpcode::G_USUBSAT*//*Label 29*/ 42170, 933 /*TargetOpcode::G_SSUBSAT*//*Label 30*/ 42531, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 934 /*TargetOpcode::G_FADD*//*Label 31*/ 42892, 935 /*TargetOpcode::G_FSUB*//*Label 32*/ 43714, 936 /*TargetOpcode::G_FMUL*//*Label 33*/ 44536, 937 /*TargetOpcode::G_FMA*//*Label 34*/ 45358, 0, 938 /*TargetOpcode::G_FDIV*//*Label 35*/ 46532, 0, 0, 0, 0, 0, 0, 0, 0, 939 /*TargetOpcode::G_FNEG*//*Label 36*/ 47354, 940 /*TargetOpcode::G_FPEXT*//*Label 37*/ 47445, 941 /*TargetOpcode::G_FPTRUNC*//*Label 38*/ 47924, 942 /*TargetOpcode::G_FPTOSI*//*Label 39*/ 48230, 943 /*TargetOpcode::G_FPTOUI*//*Label 40*/ 48638, 944 /*TargetOpcode::G_SITOFP*//*Label 41*/ 48805, 945 /*TargetOpcode::G_UITOFP*//*Label 42*/ 49937, 946 /*TargetOpcode::G_FABS*//*Label 43*/ 50675, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 947 /*TargetOpcode::G_SMIN*//*Label 44*/ 50766, 948 /*TargetOpcode::G_SMAX*//*Label 45*/ 51703, 949 /*TargetOpcode::G_UMIN*//*Label 46*/ 52640, 950 /*TargetOpcode::G_UMAX*//*Label 47*/ 53577, 951 /*TargetOpcode::G_ABS*//*Label 48*/ 54514, 0, 0, 952 /*TargetOpcode::G_BR*//*Label 49*/ 55213, 0, 0, 0, 0, 0, 953 /*TargetOpcode::G_CTTZ_ZERO_UNDEF*//*Label 50*/ 55226, 954 /*TargetOpcode::G_CTLZ*//*Label 51*/ 55311, 0, 955 /*TargetOpcode::G_CTPOP*//*Label 52*/ 55870, 956 /*TargetOpcode::G_BSWAP*//*Label 53*/ 56974, 0, 0, 0, 0, 957 /*TargetOpcode::G_FSQRT*//*Label 54*/ 57064, 0, 0, 0, 0, 0, 0, 0, 958 /*TargetOpcode::G_STRICT_FADD*//*Label 55*/ 57844, 959 /*TargetOpcode::G_STRICT_FSUB*//*Label 56*/ 58666, 960 /*TargetOpcode::G_STRICT_FMUL*//*Label 57*/ 59488, 961 /*TargetOpcode::G_STRICT_FDIV*//*Label 58*/ 60310, 0, 962 /*TargetOpcode::G_STRICT_FMA*//*Label 59*/ 61132, 963 /*TargetOpcode::G_STRICT_FSQRT*//*Label 60*/ 62306, 964 // Label 0: @186 965 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 25, /*)*//*default:*//*Label 78*/ 1802, 966 /*GILLT_s8*//*Label 62*/ 216, 967 /*GILLT_s16*//*Label 63*/ 330, 968 /*GILLT_s32*//*Label 64*/ 502, 969 /*GILLT_s64*//*Label 65*/ 674, 0, 0, 0, 970 /*GILLT_v2s64*//*Label 66*/ 874, 0, 971 /*GILLT_v4s32*//*Label 67*/ 955, 972 /*GILLT_v4s64*//*Label 68*/ 1158, 0, 973 /*GILLT_v8s16*//*Label 69*/ 1216, 974 /*GILLT_v8s32*//*Label 70*/ 1419, 975 /*GILLT_v8s64*//*Label 71*/ 1477, 0, 976 /*GILLT_v16s8*//*Label 72*/ 1509, 977 /*GILLT_v16s16*//*Label 73*/ 1590, 978 /*GILLT_v16s32*//*Label 74*/ 1648, 0, 979 /*GILLT_v32s8*//*Label 75*/ 1680, 980 /*GILLT_v32s16*//*Label 76*/ 1738, 0, 981 /*GILLT_v64s8*//*Label 77*/ 1770, 982 // Label 62: @216 983 GIM_Try, /*On fail goto*//*Label 79*/ 329, 984 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s8, 985 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s8, 986 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR8RegClassID, 987 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR8RegClassID, 988 GIM_Try, /*On fail goto*//*Label 80*/ 258, // Rule ID 21047 // 989 GIM_CheckFeatures, GIFBS_UseIncDec, 990 GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 1, 991 // (add:{ *:[i8] } GR8:{ *:[i8] }:$src, 1:{ *:[i8] }) => (INC8r:{ *:[i8] }:{ *:[i32] } GR8:{ *:[i8] }:$src) 992 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::INC8r, 993 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 994 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 995 GIR_EraseFromParent, /*InsnID*/0, 996 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 997 // GIR_Coverage, 21047, 998 GIR_Done, 999 // Label 80: @258 1000 GIM_Try, /*On fail goto*//*Label 81*/ 282, // Rule ID 21051 // 1001 GIM_CheckFeatures, GIFBS_UseIncDec, 1002 GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1, 1003 // (add:{ *:[i8] } GR8:{ *:[i8] }:$src, -1:{ *:[i8] }) => (DEC8r:{ *:[i8] }:{ *:[i32] } GR8:{ *:[i8] }:$src) 1004 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::DEC8r, 1005 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 1006 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 1007 GIR_EraseFromParent, /*InsnID*/0, 1008 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1009 // GIR_Coverage, 21051, 1010 GIR_Done, 1011 // Label 81: @282 1012 GIM_Try, /*On fail goto*//*Label 82*/ 312, // Rule ID 21003 // 1013 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 1014 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 1015 // MIs[1] Operand 1 1016 // No operand predicates 1017 GIM_CheckIsSafeToFold, /*InsnID*/1, 1018 // (add:{ *:[i8] } GR8:{ *:[i8] }:$src1, (imm:{ *:[i8] }):$src2) => (ADD8ri:{ *:[i8] }:{ *:[i32] } GR8:{ *:[i8] }:$src1, (imm:{ *:[i8] }):$src2) 1019 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::ADD8ri, 1020 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 1021 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 1022 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // src2 1023 GIR_EraseFromParent, /*InsnID*/0, 1024 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1025 // GIR_Coverage, 21003, 1026 GIR_Done, 1027 // Label 82: @312 1028 GIM_Try, /*On fail goto*//*Label 83*/ 328, // Rule ID 20995 // 1029 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::GR8RegClassID, 1030 // (add:{ *:[i8] } GR8:{ *:[i8] }:$src1, GR8:{ *:[i8] }:$src2) => (ADD8rr:{ *:[i8] }:{ *:[i32] } GR8:{ *:[i8] }:$src1, GR8:{ *:[i8] }:$src2) 1031 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::ADD8rr, 1032 GIR_AddImplicitDef, /*InsnID*/0, X86::EFLAGS, 1033 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1034 // GIR_Coverage, 20995, 1035 GIR_Done, 1036 // Label 83: @328 1037 GIM_Reject, 1038 // Label 79: @329 1039 GIM_Reject, 1040 // Label 63: @330 1041 GIM_Try, /*On fail goto*//*Label 84*/ 501, 1042 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16, 1043 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16, 1044 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR16RegClassID, 1045 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR16RegClassID, 1046 GIM_Try, /*On fail goto*//*Label 85*/ 373, // Rule ID 20859 // 1047 GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 128, 1048 // (add:{ *:[i16] } GR16:{ *:[i16] }:$src1, 128:{ *:[i16] }) => (SUB16ri8:{ *:[i16] }:{ *:[i32] } GR16:{ *:[i16] }:$src1, -128:{ *:[i16] }) 1049 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SUB16ri8, 1050 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 1051 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 1052 GIR_AddImm, /*InsnID*/0, /*Imm*/-128, 1053 GIR_EraseFromParent, /*InsnID*/0, 1054 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1055 // GIR_Coverage, 20859, 1056 GIR_Done, 1057 // Label 85: @373 1058 GIM_Try, /*On fail goto*//*Label 86*/ 397, // Rule ID 21048 // 1059 GIM_CheckFeatures, GIFBS_UseIncDec, 1060 GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 1, 1061 // (add:{ *:[i16] } GR16:{ *:[i16] }:$src, 1:{ *:[i16] }) => (INC16r:{ *:[i16] }:{ *:[i32] } GR16:{ *:[i16] }:$src) 1062 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::INC16r, 1063 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 1064 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 1065 GIR_EraseFromParent, /*InsnID*/0, 1066 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1067 // GIR_Coverage, 21048, 1068 GIR_Done, 1069 // Label 86: @397 1070 GIM_Try, /*On fail goto*//*Label 87*/ 421, // Rule ID 21052 // 1071 GIM_CheckFeatures, GIFBS_UseIncDec, 1072 GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1, 1073 // (add:{ *:[i16] } GR16:{ *:[i16] }:$src, -1:{ *:[i16] }) => (DEC16r:{ *:[i16] }:{ *:[i32] } GR16:{ *:[i16] }:$src) 1074 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::DEC16r, 1075 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 1076 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 1077 GIR_EraseFromParent, /*InsnID*/0, 1078 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1079 // GIR_Coverage, 21052, 1080 GIR_Done, 1081 // Label 87: @421 1082 GIM_Try, /*On fail goto*//*Label 88*/ 454, // Rule ID 21006 // 1083 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 1084 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 1085 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_i16immSExt8, 1086 // MIs[1] Operand 1 1087 // No operand predicates 1088 GIM_CheckIsSafeToFold, /*InsnID*/1, 1089 // (add:{ *:[i16] } GR16:{ *:[i16] }:$src1, (imm:{ *:[i16] })<<P:Predicate_i16immSExt8>>:$src2) => (ADD16ri8:{ *:[i16] }:{ *:[i32] } GR16:{ *:[i16] }:$src1, (imm:{ *:[i16] })<<P:Predicate_i16immSExt8>>:$src2) 1090 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::ADD16ri8, 1091 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 1092 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 1093 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // src2 1094 GIR_EraseFromParent, /*InsnID*/0, 1095 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1096 // GIR_Coverage, 21006, 1097 GIR_Done, 1098 // Label 88: @454 1099 GIM_Try, /*On fail goto*//*Label 89*/ 484, // Rule ID 21004 // 1100 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 1101 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 1102 // MIs[1] Operand 1 1103 // No operand predicates 1104 GIM_CheckIsSafeToFold, /*InsnID*/1, 1105 // (add:{ *:[i16] } GR16:{ *:[i16] }:$src1, (imm:{ *:[i16] }):$src2) => (ADD16ri:{ *:[i16] }:{ *:[i32] } GR16:{ *:[i16] }:$src1, (imm:{ *:[i16] }):$src2) 1106 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::ADD16ri, 1107 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 1108 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 1109 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // src2 1110 GIR_EraseFromParent, /*InsnID*/0, 1111 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1112 // GIR_Coverage, 21004, 1113 GIR_Done, 1114 // Label 89: @484 1115 GIM_Try, /*On fail goto*//*Label 90*/ 500, // Rule ID 20996 // 1116 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::GR16RegClassID, 1117 // (add:{ *:[i16] } GR16:{ *:[i16] }:$src1, GR16:{ *:[i16] }:$src2) => (ADD16rr:{ *:[i16] }:{ *:[i32] } GR16:{ *:[i16] }:$src1, GR16:{ *:[i16] }:$src2) 1118 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::ADD16rr, 1119 GIR_AddImplicitDef, /*InsnID*/0, X86::EFLAGS, 1120 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1121 // GIR_Coverage, 20996, 1122 GIR_Done, 1123 // Label 90: @500 1124 GIM_Reject, 1125 // Label 84: @501 1126 GIM_Reject, 1127 // Label 64: @502 1128 GIM_Try, /*On fail goto*//*Label 91*/ 673, 1129 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 1130 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 1131 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID, 1132 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR32RegClassID, 1133 GIM_Try, /*On fail goto*//*Label 92*/ 545, // Rule ID 20861 // 1134 GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 128, 1135 // (add:{ *:[i32] } GR32:{ *:[i32] }:$src1, 128:{ *:[i32] }) => (SUB32ri8:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src1, -128:{ *:[i32] }) 1136 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SUB32ri8, 1137 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 1138 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 1139 GIR_AddImm, /*InsnID*/0, /*Imm*/-128, 1140 GIR_EraseFromParent, /*InsnID*/0, 1141 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1142 // GIR_Coverage, 20861, 1143 GIR_Done, 1144 // Label 92: @545 1145 GIM_Try, /*On fail goto*//*Label 93*/ 569, // Rule ID 21049 // 1146 GIM_CheckFeatures, GIFBS_UseIncDec, 1147 GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 1, 1148 // (add:{ *:[i32] } GR32:{ *:[i32] }:$src, 1:{ *:[i32] }) => (INC32r:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src) 1149 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::INC32r, 1150 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 1151 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 1152 GIR_EraseFromParent, /*InsnID*/0, 1153 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1154 // GIR_Coverage, 21049, 1155 GIR_Done, 1156 // Label 93: @569 1157 GIM_Try, /*On fail goto*//*Label 94*/ 593, // Rule ID 21053 // 1158 GIM_CheckFeatures, GIFBS_UseIncDec, 1159 GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1, 1160 // (add:{ *:[i32] } GR32:{ *:[i32] }:$src, -1:{ *:[i32] }) => (DEC32r:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src) 1161 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::DEC32r, 1162 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 1163 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 1164 GIR_EraseFromParent, /*InsnID*/0, 1165 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1166 // GIR_Coverage, 21053, 1167 GIR_Done, 1168 // Label 94: @593 1169 GIM_Try, /*On fail goto*//*Label 95*/ 626, // Rule ID 21007 // 1170 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 1171 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 1172 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_i32immSExt8, 1173 // MIs[1] Operand 1 1174 // No operand predicates 1175 GIM_CheckIsSafeToFold, /*InsnID*/1, 1176 // (add:{ *:[i32] } GR32:{ *:[i32] }:$src1, (imm:{ *:[i32] })<<P:Predicate_i32immSExt8>>:$src2) => (ADD32ri8:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src1, (imm:{ *:[i32] })<<P:Predicate_i32immSExt8>>:$src2) 1177 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::ADD32ri8, 1178 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 1179 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 1180 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // src2 1181 GIR_EraseFromParent, /*InsnID*/0, 1182 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1183 // GIR_Coverage, 21007, 1184 GIR_Done, 1185 // Label 95: @626 1186 GIM_Try, /*On fail goto*//*Label 96*/ 656, // Rule ID 21005 // 1187 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 1188 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 1189 // MIs[1] Operand 1 1190 // No operand predicates 1191 GIM_CheckIsSafeToFold, /*InsnID*/1, 1192 // (add:{ *:[i32] } GR32:{ *:[i32] }:$src1, (imm:{ *:[i32] }):$src2) => (ADD32ri:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src1, (imm:{ *:[i32] }):$src2) 1193 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::ADD32ri, 1194 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 1195 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 1196 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // src2 1197 GIR_EraseFromParent, /*InsnID*/0, 1198 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1199 // GIR_Coverage, 21005, 1200 GIR_Done, 1201 // Label 96: @656 1202 GIM_Try, /*On fail goto*//*Label 97*/ 672, // Rule ID 20997 // 1203 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::GR32RegClassID, 1204 // (add:{ *:[i32] } GR32:{ *:[i32] }:$src1, GR32:{ *:[i32] }:$src2) => (ADD32rr:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src1, GR32:{ *:[i32] }:$src2) 1205 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::ADD32rr, 1206 GIR_AddImplicitDef, /*InsnID*/0, X86::EFLAGS, 1207 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1208 // GIR_Coverage, 20997, 1209 GIR_Done, 1210 // Label 97: @672 1211 GIM_Reject, 1212 // Label 91: @673 1213 GIM_Reject, 1214 // Label 65: @674 1215 GIM_Try, /*On fail goto*//*Label 98*/ 873, 1216 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 1217 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 1218 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID, 1219 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR64RegClassID, 1220 GIM_Try, /*On fail goto*//*Label 99*/ 717, // Rule ID 20863 // 1221 GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 128, 1222 // (add:{ *:[i64] } GR64:{ *:[i64] }:$src1, 128:{ *:[i64] }) => (SUB64ri8:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src1, -128:{ *:[i64] }) 1223 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SUB64ri8, 1224 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 1225 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 1226 GIR_AddImm, /*InsnID*/0, /*Imm*/-128, 1227 GIR_EraseFromParent, /*InsnID*/0, 1228 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1229 // GIR_Coverage, 20863, 1230 GIR_Done, 1231 // Label 99: @717 1232 GIM_Try, /*On fail goto*//*Label 100*/ 742, // Rule ID 20868 // 1233 GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 2147483648, 1234 // (add:{ *:[i64] } GR64:{ *:[i64] }:$src1, 2147483648:{ *:[i64] }) => (SUB64ri32:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src1, -2147483648:{ *:[i64] }) 1235 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SUB64ri32, 1236 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 1237 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 1238 GIR_AddImm, /*InsnID*/0, /*Imm*/-2147483648, 1239 GIR_EraseFromParent, /*InsnID*/0, 1240 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1241 // GIR_Coverage, 20868, 1242 GIR_Done, 1243 // Label 100: @742 1244 GIM_Try, /*On fail goto*//*Label 101*/ 766, // Rule ID 21050 // 1245 GIM_CheckFeatures, GIFBS_UseIncDec, 1246 GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 1, 1247 // (add:{ *:[i64] } GR64:{ *:[i64] }:$src, 1:{ *:[i64] }) => (INC64r:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src) 1248 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::INC64r, 1249 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 1250 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 1251 GIR_EraseFromParent, /*InsnID*/0, 1252 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1253 // GIR_Coverage, 21050, 1254 GIR_Done, 1255 // Label 101: @766 1256 GIM_Try, /*On fail goto*//*Label 102*/ 790, // Rule ID 21054 // 1257 GIM_CheckFeatures, GIFBS_UseIncDec, 1258 GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1, 1259 // (add:{ *:[i64] } GR64:{ *:[i64] }:$src, -1:{ *:[i64] }) => (DEC64r:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src) 1260 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::DEC64r, 1261 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 1262 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 1263 GIR_EraseFromParent, /*InsnID*/0, 1264 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1265 // GIR_Coverage, 21054, 1266 GIR_Done, 1267 // Label 102: @790 1268 GIM_Try, /*On fail goto*//*Label 103*/ 823, // Rule ID 21008 // 1269 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 1270 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 1271 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_i64immSExt8, 1272 // MIs[1] Operand 1 1273 // No operand predicates 1274 GIM_CheckIsSafeToFold, /*InsnID*/1, 1275 // (add:{ *:[i64] } GR64:{ *:[i64] }:$src1, (imm:{ *:[i64] })<<P:Predicate_i64immSExt8>>:$src2) => (ADD64ri8:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src1, (imm:{ *:[i64] })<<P:Predicate_i64immSExt8>>:$src2) 1276 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::ADD64ri8, 1277 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 1278 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 1279 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // src2 1280 GIR_EraseFromParent, /*InsnID*/0, 1281 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1282 // GIR_Coverage, 21008, 1283 GIR_Done, 1284 // Label 103: @823 1285 GIM_Try, /*On fail goto*//*Label 104*/ 856, // Rule ID 21009 // 1286 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 1287 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 1288 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_i64immSExt32, 1289 // MIs[1] Operand 1 1290 // No operand predicates 1291 GIM_CheckIsSafeToFold, /*InsnID*/1, 1292 // (add:{ *:[i64] } GR64:{ *:[i64] }:$src1, (imm:{ *:[i64] })<<P:Predicate_i64immSExt32>>:$src2) => (ADD64ri32:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src1, (imm:{ *:[i64] })<<P:Predicate_i64immSExt32>>:$src2) 1293 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::ADD64ri32, 1294 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 1295 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 1296 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // src2 1297 GIR_EraseFromParent, /*InsnID*/0, 1298 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1299 // GIR_Coverage, 21009, 1300 GIR_Done, 1301 // Label 104: @856 1302 GIM_Try, /*On fail goto*//*Label 105*/ 872, // Rule ID 20998 // 1303 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::GR64RegClassID, 1304 // (add:{ *:[i64] } GR64:{ *:[i64] }:$src1, GR64:{ *:[i64] }:$src2) => (ADD64rr:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src1, GR64:{ *:[i64] }:$src2) 1305 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::ADD64rr, 1306 GIR_AddImplicitDef, /*InsnID*/0, X86::EFLAGS, 1307 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1308 // GIR_Coverage, 20998, 1309 GIR_Done, 1310 // Label 105: @872 1311 GIM_Reject, 1312 // Label 98: @873 1313 GIM_Reject, 1314 // Label 66: @874 1315 GIM_Try, /*On fail goto*//*Label 106*/ 954, 1316 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, 1317 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 1318 GIM_Try, /*On fail goto*//*Label 107*/ 907, // Rule ID 2232 // 1319 GIM_CheckFeatures, GIFBS_HasAVX_NoVLX, 1320 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 1321 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 1322 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 1323 // (add:{ *:[v2i64] } VR128:{ *:[v2i64] }:$src1, VR128:{ *:[v2i64] }:$src2) => (VPADDQrr:{ *:[v2i64] } VR128:{ *:[v2i64] }:$src1, VR128:{ *:[v2i64] }:$src2) 1324 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPADDQrr, 1325 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1326 // GIR_Coverage, 2232, 1327 GIR_Done, 1328 // Label 107: @907 1329 GIM_Try, /*On fail goto*//*Label 108*/ 930, // Rule ID 2234 // 1330 GIM_CheckFeatures, GIFBS_UseSSE2, 1331 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 1332 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 1333 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 1334 // (add:{ *:[v2i64] } VR128:{ *:[v2i64] }:$src1, VR128:{ *:[v2i64] }:$src2) => (PADDQrr:{ *:[v2i64] } VR128:{ *:[v2i64] }:$src1, VR128:{ *:[v2i64] }:$src2) 1335 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::PADDQrr, 1336 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1337 // GIR_Coverage, 2234, 1338 GIR_Done, 1339 // Label 108: @930 1340 GIM_Try, /*On fail goto*//*Label 109*/ 953, // Rule ID 4290 // 1341 GIM_CheckFeatures, GIFBS_HasAVX512_HasVLX, 1342 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID, 1343 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID, 1344 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128XRegClassID, 1345 // (add:{ *:[v2i64] } VR128X:{ *:[v2i64] }:$src1, VR128X:{ *:[v2i64] }:$src2) => (VPADDQZ128rr:{ *:[v2i64] } VR128X:{ *:[v2i64] }:$src1, VR128X:{ *:[v2i64] }:$src2) 1346 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPADDQZ128rr, 1347 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1348 // GIR_Coverage, 4290, 1349 GIR_Done, 1350 // Label 109: @953 1351 GIM_Reject, 1352 // Label 106: @954 1353 GIM_Reject, 1354 // Label 67: @955 1355 GIM_Try, /*On fail goto*//*Label 110*/ 1157, 1356 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, 1357 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 1358 GIM_Try, /*On fail goto*//*Label 111*/ 1026, // Rule ID 16322 // 1359 GIM_CheckFeatures, GIFBS_HasXOP, 1360 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 1361 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 1362 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL, 1363 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, 1364 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, 1365 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::VR128RegClassID, 1366 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/X86::VR128RegClassID, 1367 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 1368 GIM_CheckIsSafeToFold, /*InsnID*/1, 1369 // (add:{ *:[v4i32] } (mul:{ *:[v4i32] } VR128:{ *:[v4i32] }:$src1, VR128:{ *:[v4i32] }:$src2), VR128:{ *:[v4i32] }:$src3) => (VPMACSDDrr:{ *:[v4i32] } VR128:{ *:[v4i32] }:$src1, VR128:{ *:[v4i32] }:$src2, VR128:{ *:[v4i32] }:$src3) 1370 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VPMACSDDrr, 1371 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 1372 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1 1373 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src2 1374 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src3 1375 GIR_EraseFromParent, /*InsnID*/0, 1376 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1377 // GIR_Coverage, 16322, 1378 GIR_Done, 1379 // Label 111: @1026 1380 GIM_Try, /*On fail goto*//*Label 112*/ 1087, // Rule ID 23056 // 1381 GIM_CheckFeatures, GIFBS_HasXOP, 1382 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 1383 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 1384 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 1385 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL, 1386 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, 1387 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, 1388 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::VR128RegClassID, 1389 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/X86::VR128RegClassID, 1390 GIM_CheckIsSafeToFold, /*InsnID*/1, 1391 // (add:{ *:[v4i32] } VR128:{ *:[v4i32] }:$src3, (mul:{ *:[v4i32] } VR128:{ *:[v4i32] }:$src1, VR128:{ *:[v4i32] }:$src2)) => (VPMACSDDrr:{ *:[v4i32] } VR128:{ *:[v4i32] }:$src1, VR128:{ *:[v4i32] }:$src2, VR128:{ *:[v4i32] }:$src3) 1392 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VPMACSDDrr, 1393 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 1394 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1 1395 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src2 1396 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src3 1397 GIR_EraseFromParent, /*InsnID*/0, 1398 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1399 // GIR_Coverage, 23056, 1400 GIR_Done, 1401 // Label 112: @1087 1402 GIM_Try, /*On fail goto*//*Label 113*/ 1110, // Rule ID 2226 // 1403 GIM_CheckFeatures, GIFBS_HasAVX_NoVLX, 1404 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 1405 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 1406 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 1407 // (add:{ *:[v4i32] } VR128:{ *:[v4i32] }:$src1, VR128:{ *:[v4i32] }:$src2) => (VPADDDrr:{ *:[v4i32] } VR128:{ *:[v4i32] }:$src1, VR128:{ *:[v4i32] }:$src2) 1408 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPADDDrr, 1409 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1410 // GIR_Coverage, 2226, 1411 GIR_Done, 1412 // Label 113: @1110 1413 GIM_Try, /*On fail goto*//*Label 114*/ 1133, // Rule ID 2228 // 1414 GIM_CheckFeatures, GIFBS_UseSSE2, 1415 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 1416 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 1417 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 1418 // (add:{ *:[v4i32] } VR128:{ *:[v4i32] }:$src1, VR128:{ *:[v4i32] }:$src2) => (PADDDrr:{ *:[v4i32] } VR128:{ *:[v4i32] }:$src1, VR128:{ *:[v4i32] }:$src2) 1419 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::PADDDrr, 1420 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1421 // GIR_Coverage, 2228, 1422 GIR_Done, 1423 // Label 114: @1133 1424 GIM_Try, /*On fail goto*//*Label 115*/ 1156, // Rule ID 4317 // 1425 GIM_CheckFeatures, GIFBS_HasAVX512_HasVLX, 1426 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID, 1427 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID, 1428 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128XRegClassID, 1429 // (add:{ *:[v4i32] } VR128X:{ *:[v4i32] }:$src1, VR128X:{ *:[v4i32] }:$src2) => (VPADDDZ128rr:{ *:[v4i32] } VR128X:{ *:[v4i32] }:$src1, VR128X:{ *:[v4i32] }:$src2) 1430 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPADDDZ128rr, 1431 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1432 // GIR_Coverage, 4317, 1433 GIR_Done, 1434 // Label 115: @1156 1435 GIM_Reject, 1436 // Label 110: @1157 1437 GIM_Reject, 1438 // Label 68: @1158 1439 GIM_Try, /*On fail goto*//*Label 116*/ 1215, 1440 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s64, 1441 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s64, 1442 GIM_Try, /*On fail goto*//*Label 117*/ 1191, // Rule ID 2236 // 1443 GIM_CheckFeatures, GIFBS_HasAVX2_NoVLX, 1444 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID, 1445 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256RegClassID, 1446 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256RegClassID, 1447 // (add:{ *:[v4i64] } VR256:{ *:[v4i64] }:$src1, VR256:{ *:[v4i64] }:$src2) => (VPADDQYrr:{ *:[v4i64] } VR256:{ *:[v4i64] }:$src1, VR256:{ *:[v4i64] }:$src2) 1448 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPADDQYrr, 1449 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1450 // GIR_Coverage, 2236, 1451 GIR_Done, 1452 // Label 117: @1191 1453 GIM_Try, /*On fail goto*//*Label 118*/ 1214, // Rule ID 4281 // 1454 GIM_CheckFeatures, GIFBS_HasAVX512_HasVLX, 1455 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID, 1456 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID, 1457 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256XRegClassID, 1458 // (add:{ *:[v4i64] } VR256X:{ *:[v4i64] }:$src1, VR256X:{ *:[v4i64] }:$src2) => (VPADDQZ256rr:{ *:[v4i64] } VR256X:{ *:[v4i64] }:$src1, VR256X:{ *:[v4i64] }:$src2) 1459 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPADDQZ256rr, 1460 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1461 // GIR_Coverage, 4281, 1462 GIR_Done, 1463 // Label 118: @1214 1464 GIM_Reject, 1465 // Label 116: @1215 1466 GIM_Reject, 1467 // Label 69: @1216 1468 GIM_Try, /*On fail goto*//*Label 119*/ 1418, 1469 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, 1470 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 1471 GIM_Try, /*On fail goto*//*Label 120*/ 1287, // Rule ID 16321 // 1472 GIM_CheckFeatures, GIFBS_HasXOP, 1473 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 1474 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 1475 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL, 1476 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, 1477 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, 1478 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::VR128RegClassID, 1479 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/X86::VR128RegClassID, 1480 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 1481 GIM_CheckIsSafeToFold, /*InsnID*/1, 1482 // (add:{ *:[v8i16] } (mul:{ *:[v8i16] } VR128:{ *:[v8i16] }:$src1, VR128:{ *:[v8i16] }:$src2), VR128:{ *:[v8i16] }:$src3) => (VPMACSWWrr:{ *:[v8i16] } VR128:{ *:[v8i16] }:$src1, VR128:{ *:[v8i16] }:$src2, VR128:{ *:[v8i16] }:$src3) 1483 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VPMACSWWrr, 1484 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 1485 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1 1486 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src2 1487 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src3 1488 GIR_EraseFromParent, /*InsnID*/0, 1489 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1490 // GIR_Coverage, 16321, 1491 GIR_Done, 1492 // Label 120: @1287 1493 GIM_Try, /*On fail goto*//*Label 121*/ 1348, // Rule ID 23055 // 1494 GIM_CheckFeatures, GIFBS_HasXOP, 1495 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 1496 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 1497 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 1498 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL, 1499 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, 1500 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, 1501 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::VR128RegClassID, 1502 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/X86::VR128RegClassID, 1503 GIM_CheckIsSafeToFold, /*InsnID*/1, 1504 // (add:{ *:[v8i16] } VR128:{ *:[v8i16] }:$src3, (mul:{ *:[v8i16] } VR128:{ *:[v8i16] }:$src1, VR128:{ *:[v8i16] }:$src2)) => (VPMACSWWrr:{ *:[v8i16] } VR128:{ *:[v8i16] }:$src1, VR128:{ *:[v8i16] }:$src2, VR128:{ *:[v8i16] }:$src3) 1505 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VPMACSWWrr, 1506 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 1507 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1 1508 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src2 1509 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src3 1510 GIR_EraseFromParent, /*InsnID*/0, 1511 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1512 // GIR_Coverage, 23055, 1513 GIR_Done, 1514 // Label 121: @1348 1515 GIM_Try, /*On fail goto*//*Label 122*/ 1371, // Rule ID 2220 // 1516 GIM_CheckFeatures, GIFBS_HasAVX_NoVLX_Or_NoBWI, 1517 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 1518 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 1519 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 1520 // (add:{ *:[v8i16] } VR128:{ *:[v8i16] }:$src1, VR128:{ *:[v8i16] }:$src2) => (VPADDWrr:{ *:[v8i16] } VR128:{ *:[v8i16] }:$src1, VR128:{ *:[v8i16] }:$src2) 1521 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPADDWrr, 1522 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1523 // GIR_Coverage, 2220, 1524 GIR_Done, 1525 // Label 122: @1371 1526 GIM_Try, /*On fail goto*//*Label 123*/ 1394, // Rule ID 2222 // 1527 GIM_CheckFeatures, GIFBS_UseSSE2, 1528 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 1529 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 1530 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 1531 // (add:{ *:[v8i16] } VR128:{ *:[v8i16] }:$src1, VR128:{ *:[v8i16] }:$src2) => (PADDWrr:{ *:[v8i16] } VR128:{ *:[v8i16] }:$src1, VR128:{ *:[v8i16] }:$src2) 1532 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::PADDWrr, 1533 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1534 // GIR_Coverage, 2222, 1535 GIR_Done, 1536 // Label 123: @1394 1537 GIM_Try, /*On fail goto*//*Label 124*/ 1417, // Rule ID 4338 // 1538 GIM_CheckFeatures, GIFBS_HasBWI_HasVLX, 1539 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID, 1540 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID, 1541 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128XRegClassID, 1542 // (add:{ *:[v8i16] } VR128X:{ *:[v8i16] }:$src1, VR128X:{ *:[v8i16] }:$src2) => (VPADDWZ128rr:{ *:[v8i16] } VR128X:{ *:[v8i16] }:$src1, VR128X:{ *:[v8i16] }:$src2) 1543 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPADDWZ128rr, 1544 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1545 // GIR_Coverage, 4338, 1546 GIR_Done, 1547 // Label 124: @1417 1548 GIM_Reject, 1549 // Label 119: @1418 1550 GIM_Reject, 1551 // Label 70: @1419 1552 GIM_Try, /*On fail goto*//*Label 125*/ 1476, 1553 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s32, 1554 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s32, 1555 GIM_Try, /*On fail goto*//*Label 126*/ 1452, // Rule ID 2230 // 1556 GIM_CheckFeatures, GIFBS_HasAVX2_NoVLX, 1557 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID, 1558 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256RegClassID, 1559 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256RegClassID, 1560 // (add:{ *:[v8i32] } VR256:{ *:[v8i32] }:$src1, VR256:{ *:[v8i32] }:$src2) => (VPADDDYrr:{ *:[v8i32] } VR256:{ *:[v8i32] }:$src1, VR256:{ *:[v8i32] }:$src2) 1561 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPADDDYrr, 1562 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1563 // GIR_Coverage, 2230, 1564 GIR_Done, 1565 // Label 126: @1452 1566 GIM_Try, /*On fail goto*//*Label 127*/ 1475, // Rule ID 4308 // 1567 GIM_CheckFeatures, GIFBS_HasAVX512_HasVLX, 1568 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID, 1569 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID, 1570 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256XRegClassID, 1571 // (add:{ *:[v8i32] } VR256X:{ *:[v8i32] }:$src1, VR256X:{ *:[v8i32] }:$src2) => (VPADDDZ256rr:{ *:[v8i32] } VR256X:{ *:[v8i32] }:$src1, VR256X:{ *:[v8i32] }:$src2) 1572 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPADDDZ256rr, 1573 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1574 // GIR_Coverage, 4308, 1575 GIR_Done, 1576 // Label 127: @1475 1577 GIM_Reject, 1578 // Label 125: @1476 1579 GIM_Reject, 1580 // Label 71: @1477 1581 GIM_Try, /*On fail goto*//*Label 128*/ 1508, // Rule ID 4272 // 1582 GIM_CheckFeatures, GIFBS_HasAVX512, 1583 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s64, 1584 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s64, 1585 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 1586 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR512RegClassID, 1587 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR512RegClassID, 1588 // (add:{ *:[v8i64] } VR512:{ *:[v8i64] }:$src1, VR512:{ *:[v8i64] }:$src2) => (VPADDQZrr:{ *:[v8i64] } VR512:{ *:[v8i64] }:$src1, VR512:{ *:[v8i64] }:$src2) 1589 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPADDQZrr, 1590 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1591 // GIR_Coverage, 4272, 1592 GIR_Done, 1593 // Label 128: @1508 1594 GIM_Reject, 1595 // Label 72: @1509 1596 GIM_Try, /*On fail goto*//*Label 129*/ 1589, 1597 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, 1598 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, 1599 GIM_Try, /*On fail goto*//*Label 130*/ 1542, // Rule ID 2214 // 1600 GIM_CheckFeatures, GIFBS_HasAVX_NoVLX_Or_NoBWI, 1601 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 1602 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 1603 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 1604 // (add:{ *:[v16i8] } VR128:{ *:[v16i8] }:$src1, VR128:{ *:[v16i8] }:$src2) => (VPADDBrr:{ *:[v16i8] } VR128:{ *:[v16i8] }:$src1, VR128:{ *:[v16i8] }:$src2) 1605 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPADDBrr, 1606 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1607 // GIR_Coverage, 2214, 1608 GIR_Done, 1609 // Label 130: @1542 1610 GIM_Try, /*On fail goto*//*Label 131*/ 1565, // Rule ID 2216 // 1611 GIM_CheckFeatures, GIFBS_UseSSE2, 1612 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 1613 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 1614 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 1615 // (add:{ *:[v16i8] } VR128:{ *:[v16i8] }:$src1, VR128:{ *:[v16i8] }:$src2) => (PADDBrr:{ *:[v16i8] } VR128:{ *:[v16i8] }:$src1, VR128:{ *:[v16i8] }:$src2) 1616 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::PADDBrr, 1617 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1618 // GIR_Coverage, 2216, 1619 GIR_Done, 1620 // Label 131: @1565 1621 GIM_Try, /*On fail goto*//*Label 132*/ 1588, // Rule ID 4356 // 1622 GIM_CheckFeatures, GIFBS_HasBWI_HasVLX, 1623 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID, 1624 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID, 1625 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128XRegClassID, 1626 // (add:{ *:[v16i8] } VR128X:{ *:[v16i8] }:$src1, VR128X:{ *:[v16i8] }:$src2) => (VPADDBZ128rr:{ *:[v16i8] } VR128X:{ *:[v16i8] }:$src1, VR128X:{ *:[v16i8] }:$src2) 1627 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPADDBZ128rr, 1628 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1629 // GIR_Coverage, 4356, 1630 GIR_Done, 1631 // Label 132: @1588 1632 GIM_Reject, 1633 // Label 129: @1589 1634 GIM_Reject, 1635 // Label 73: @1590 1636 GIM_Try, /*On fail goto*//*Label 133*/ 1647, 1637 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s16, 1638 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s16, 1639 GIM_Try, /*On fail goto*//*Label 134*/ 1623, // Rule ID 2224 // 1640 GIM_CheckFeatures, GIFBS_HasAVX2_NoVLX_Or_NoBWI, 1641 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID, 1642 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256RegClassID, 1643 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256RegClassID, 1644 // (add:{ *:[v16i16] } VR256:{ *:[v16i16] }:$src1, VR256:{ *:[v16i16] }:$src2) => (VPADDWYrr:{ *:[v16i16] } VR256:{ *:[v16i16] }:$src1, VR256:{ *:[v16i16] }:$src2) 1645 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPADDWYrr, 1646 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1647 // GIR_Coverage, 2224, 1648 GIR_Done, 1649 // Label 134: @1623 1650 GIM_Try, /*On fail goto*//*Label 135*/ 1646, // Rule ID 4332 // 1651 GIM_CheckFeatures, GIFBS_HasBWI_HasVLX, 1652 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID, 1653 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID, 1654 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256XRegClassID, 1655 // (add:{ *:[v16i16] } VR256X:{ *:[v16i16] }:$src1, VR256X:{ *:[v16i16] }:$src2) => (VPADDWZ256rr:{ *:[v16i16] } VR256X:{ *:[v16i16] }:$src1, VR256X:{ *:[v16i16] }:$src2) 1656 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPADDWZ256rr, 1657 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1658 // GIR_Coverage, 4332, 1659 GIR_Done, 1660 // Label 135: @1646 1661 GIM_Reject, 1662 // Label 133: @1647 1663 GIM_Reject, 1664 // Label 74: @1648 1665 GIM_Try, /*On fail goto*//*Label 136*/ 1679, // Rule ID 4299 // 1666 GIM_CheckFeatures, GIFBS_HasAVX512, 1667 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s32, 1668 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s32, 1669 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 1670 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR512RegClassID, 1671 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR512RegClassID, 1672 // (add:{ *:[v16i32] } VR512:{ *:[v16i32] }:$src1, VR512:{ *:[v16i32] }:$src2) => (VPADDDZrr:{ *:[v16i32] } VR512:{ *:[v16i32] }:$src1, VR512:{ *:[v16i32] }:$src2) 1673 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPADDDZrr, 1674 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1675 // GIR_Coverage, 4299, 1676 GIR_Done, 1677 // Label 136: @1679 1678 GIM_Reject, 1679 // Label 75: @1680 1680 GIM_Try, /*On fail goto*//*Label 137*/ 1737, 1681 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v32s8, 1682 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v32s8, 1683 GIM_Try, /*On fail goto*//*Label 138*/ 1713, // Rule ID 2218 // 1684 GIM_CheckFeatures, GIFBS_HasAVX2_NoVLX_Or_NoBWI, 1685 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID, 1686 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256RegClassID, 1687 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256RegClassID, 1688 // (add:{ *:[v32i8] } VR256:{ *:[v32i8] }:$src1, VR256:{ *:[v32i8] }:$src2) => (VPADDBYrr:{ *:[v32i8] } VR256:{ *:[v32i8] }:$src1, VR256:{ *:[v32i8] }:$src2) 1689 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPADDBYrr, 1690 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1691 // GIR_Coverage, 2218, 1692 GIR_Done, 1693 // Label 138: @1713 1694 GIM_Try, /*On fail goto*//*Label 139*/ 1736, // Rule ID 4350 // 1695 GIM_CheckFeatures, GIFBS_HasBWI_HasVLX, 1696 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID, 1697 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID, 1698 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256XRegClassID, 1699 // (add:{ *:[v32i8] } VR256X:{ *:[v32i8] }:$src1, VR256X:{ *:[v32i8] }:$src2) => (VPADDBZ256rr:{ *:[v32i8] } VR256X:{ *:[v32i8] }:$src1, VR256X:{ *:[v32i8] }:$src2) 1700 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPADDBZ256rr, 1701 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1702 // GIR_Coverage, 4350, 1703 GIR_Done, 1704 // Label 139: @1736 1705 GIM_Reject, 1706 // Label 137: @1737 1707 GIM_Reject, 1708 // Label 76: @1738 1709 GIM_Try, /*On fail goto*//*Label 140*/ 1769, // Rule ID 4326 // 1710 GIM_CheckFeatures, GIFBS_HasBWI, 1711 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v32s16, 1712 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v32s16, 1713 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 1714 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR512RegClassID, 1715 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR512RegClassID, 1716 // (add:{ *:[v32i16] } VR512:{ *:[v32i16] }:$src1, VR512:{ *:[v32i16] }:$src2) => (VPADDWZrr:{ *:[v32i16] } VR512:{ *:[v32i16] }:$src1, VR512:{ *:[v32i16] }:$src2) 1717 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPADDWZrr, 1718 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1719 // GIR_Coverage, 4326, 1720 GIR_Done, 1721 // Label 140: @1769 1722 GIM_Reject, 1723 // Label 77: @1770 1724 GIM_Try, /*On fail goto*//*Label 141*/ 1801, // Rule ID 4344 // 1725 GIM_CheckFeatures, GIFBS_HasBWI, 1726 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v64s8, 1727 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v64s8, 1728 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 1729 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR512RegClassID, 1730 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR512RegClassID, 1731 // (add:{ *:[v64i8] } VR512:{ *:[v64i8] }:$src1, VR512:{ *:[v64i8] }:$src2) => (VPADDBZrr:{ *:[v64i8] } VR512:{ *:[v64i8] }:$src1, VR512:{ *:[v64i8] }:$src2) 1732 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPADDBZrr, 1733 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1734 // GIR_Coverage, 4344, 1735 GIR_Done, 1736 // Label 141: @1801 1737 GIM_Reject, 1738 // Label 78: @1802 1739 GIM_Reject, 1740 // Label 1: @1803 1741 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 25, /*)*//*default:*//*Label 158*/ 2883, 1742 /*GILLT_s8*//*Label 142*/ 1833, 1743 /*GILLT_s16*//*Label 143*/ 1899, 1744 /*GILLT_s32*//*Label 144*/ 1998, 1745 /*GILLT_s64*//*Label 145*/ 2097, 0, 0, 0, 1746 /*GILLT_v2s64*//*Label 146*/ 2199, 0, 1747 /*GILLT_v4s32*//*Label 147*/ 2280, 1748 /*GILLT_v4s64*//*Label 148*/ 2361, 0, 1749 /*GILLT_v8s16*//*Label 149*/ 2419, 1750 /*GILLT_v8s32*//*Label 150*/ 2500, 1751 /*GILLT_v8s64*//*Label 151*/ 2558, 0, 1752 /*GILLT_v16s8*//*Label 152*/ 2590, 1753 /*GILLT_v16s16*//*Label 153*/ 2671, 1754 /*GILLT_v16s32*//*Label 154*/ 2729, 0, 1755 /*GILLT_v32s8*//*Label 155*/ 2761, 1756 /*GILLT_v32s16*//*Label 156*/ 2819, 0, 1757 /*GILLT_v64s8*//*Label 157*/ 2851, 1758 // Label 142: @1833 1759 GIM_Try, /*On fail goto*//*Label 159*/ 1898, 1760 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s8, 1761 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s8, 1762 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR8RegClassID, 1763 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR8RegClassID, 1764 GIM_Try, /*On fail goto*//*Label 160*/ 1881, // Rule ID 21018 // 1765 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 1766 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 1767 // MIs[1] Operand 1 1768 // No operand predicates 1769 GIM_CheckIsSafeToFold, /*InsnID*/1, 1770 // (sub:{ *:[i8] } GR8:{ *:[i8] }:$src1, (imm:{ *:[i8] }):$src2) => (SUB8ri:{ *:[i8] }:{ *:[i32] } GR8:{ *:[i8] }:$src1, (imm:{ *:[i8] }):$src2) 1771 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SUB8ri, 1772 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 1773 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 1774 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // src2 1775 GIR_EraseFromParent, /*InsnID*/0, 1776 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1777 // GIR_Coverage, 21018, 1778 GIR_Done, 1779 // Label 160: @1881 1780 GIM_Try, /*On fail goto*//*Label 161*/ 1897, // Rule ID 21010 // 1781 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::GR8RegClassID, 1782 // (sub:{ *:[i8] } GR8:{ *:[i8] }:$src1, GR8:{ *:[i8] }:$src2) => (SUB8rr:{ *:[i8] }:{ *:[i32] } GR8:{ *:[i8] }:$src1, GR8:{ *:[i8] }:$src2) 1783 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::SUB8rr, 1784 GIR_AddImplicitDef, /*InsnID*/0, X86::EFLAGS, 1785 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1786 // GIR_Coverage, 21010, 1787 GIR_Done, 1788 // Label 161: @1897 1789 GIM_Reject, 1790 // Label 159: @1898 1791 GIM_Reject, 1792 // Label 143: @1899 1793 GIM_Try, /*On fail goto*//*Label 162*/ 1997, 1794 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16, 1795 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16, 1796 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR16RegClassID, 1797 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR16RegClassID, 1798 GIM_Try, /*On fail goto*//*Label 163*/ 1950, // Rule ID 21021 // 1799 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 1800 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 1801 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_i16immSExt8, 1802 // MIs[1] Operand 1 1803 // No operand predicates 1804 GIM_CheckIsSafeToFold, /*InsnID*/1, 1805 // (sub:{ *:[i16] } GR16:{ *:[i16] }:$src1, (imm:{ *:[i16] })<<P:Predicate_i16immSExt8>>:$src2) => (SUB16ri8:{ *:[i16] }:{ *:[i32] } GR16:{ *:[i16] }:$src1, (imm:{ *:[i16] })<<P:Predicate_i16immSExt8>>:$src2) 1806 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SUB16ri8, 1807 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 1808 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 1809 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // src2 1810 GIR_EraseFromParent, /*InsnID*/0, 1811 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1812 // GIR_Coverage, 21021, 1813 GIR_Done, 1814 // Label 163: @1950 1815 GIM_Try, /*On fail goto*//*Label 164*/ 1980, // Rule ID 21019 // 1816 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 1817 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 1818 // MIs[1] Operand 1 1819 // No operand predicates 1820 GIM_CheckIsSafeToFold, /*InsnID*/1, 1821 // (sub:{ *:[i16] } GR16:{ *:[i16] }:$src1, (imm:{ *:[i16] }):$src2) => (SUB16ri:{ *:[i16] }:{ *:[i32] } GR16:{ *:[i16] }:$src1, (imm:{ *:[i16] }):$src2) 1822 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SUB16ri, 1823 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 1824 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 1825 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // src2 1826 GIR_EraseFromParent, /*InsnID*/0, 1827 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1828 // GIR_Coverage, 21019, 1829 GIR_Done, 1830 // Label 164: @1980 1831 GIM_Try, /*On fail goto*//*Label 165*/ 1996, // Rule ID 21011 // 1832 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::GR16RegClassID, 1833 // (sub:{ *:[i16] } GR16:{ *:[i16] }:$src1, GR16:{ *:[i16] }:$src2) => (SUB16rr:{ *:[i16] }:{ *:[i32] } GR16:{ *:[i16] }:$src1, GR16:{ *:[i16] }:$src2) 1834 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::SUB16rr, 1835 GIR_AddImplicitDef, /*InsnID*/0, X86::EFLAGS, 1836 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1837 // GIR_Coverage, 21011, 1838 GIR_Done, 1839 // Label 165: @1996 1840 GIM_Reject, 1841 // Label 162: @1997 1842 GIM_Reject, 1843 // Label 144: @1998 1844 GIM_Try, /*On fail goto*//*Label 166*/ 2096, 1845 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 1846 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 1847 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID, 1848 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR32RegClassID, 1849 GIM_Try, /*On fail goto*//*Label 167*/ 2049, // Rule ID 21022 // 1850 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 1851 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 1852 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_i32immSExt8, 1853 // MIs[1] Operand 1 1854 // No operand predicates 1855 GIM_CheckIsSafeToFold, /*InsnID*/1, 1856 // (sub:{ *:[i32] } GR32:{ *:[i32] }:$src1, (imm:{ *:[i32] })<<P:Predicate_i32immSExt8>>:$src2) => (SUB32ri8:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src1, (imm:{ *:[i32] })<<P:Predicate_i32immSExt8>>:$src2) 1857 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SUB32ri8, 1858 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 1859 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 1860 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // src2 1861 GIR_EraseFromParent, /*InsnID*/0, 1862 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1863 // GIR_Coverage, 21022, 1864 GIR_Done, 1865 // Label 167: @2049 1866 GIM_Try, /*On fail goto*//*Label 168*/ 2079, // Rule ID 21020 // 1867 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 1868 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 1869 // MIs[1] Operand 1 1870 // No operand predicates 1871 GIM_CheckIsSafeToFold, /*InsnID*/1, 1872 // (sub:{ *:[i32] } GR32:{ *:[i32] }:$src1, (imm:{ *:[i32] }):$src2) => (SUB32ri:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src1, (imm:{ *:[i32] }):$src2) 1873 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SUB32ri, 1874 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 1875 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 1876 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // src2 1877 GIR_EraseFromParent, /*InsnID*/0, 1878 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1879 // GIR_Coverage, 21020, 1880 GIR_Done, 1881 // Label 168: @2079 1882 GIM_Try, /*On fail goto*//*Label 169*/ 2095, // Rule ID 21012 // 1883 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::GR32RegClassID, 1884 // (sub:{ *:[i32] } GR32:{ *:[i32] }:$src1, GR32:{ *:[i32] }:$src2) => (SUB32rr:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src1, GR32:{ *:[i32] }:$src2) 1885 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::SUB32rr, 1886 GIR_AddImplicitDef, /*InsnID*/0, X86::EFLAGS, 1887 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1888 // GIR_Coverage, 21012, 1889 GIR_Done, 1890 // Label 169: @2095 1891 GIM_Reject, 1892 // Label 166: @2096 1893 GIM_Reject, 1894 // Label 145: @2097 1895 GIM_Try, /*On fail goto*//*Label 170*/ 2198, 1896 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 1897 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 1898 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID, 1899 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR64RegClassID, 1900 GIM_Try, /*On fail goto*//*Label 171*/ 2148, // Rule ID 21023 // 1901 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 1902 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 1903 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_i64immSExt8, 1904 // MIs[1] Operand 1 1905 // No operand predicates 1906 GIM_CheckIsSafeToFold, /*InsnID*/1, 1907 // (sub:{ *:[i64] } GR64:{ *:[i64] }:$src1, (imm:{ *:[i64] })<<P:Predicate_i64immSExt8>>:$src2) => (SUB64ri8:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src1, (imm:{ *:[i64] })<<P:Predicate_i64immSExt8>>:$src2) 1908 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SUB64ri8, 1909 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 1910 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 1911 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // src2 1912 GIR_EraseFromParent, /*InsnID*/0, 1913 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1914 // GIR_Coverage, 21023, 1915 GIR_Done, 1916 // Label 171: @2148 1917 GIM_Try, /*On fail goto*//*Label 172*/ 2181, // Rule ID 21024 // 1918 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 1919 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 1920 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_i64immSExt32, 1921 // MIs[1] Operand 1 1922 // No operand predicates 1923 GIM_CheckIsSafeToFold, /*InsnID*/1, 1924 // (sub:{ *:[i64] } GR64:{ *:[i64] }:$src1, (imm:{ *:[i64] })<<P:Predicate_i64immSExt32>>:$src2) => (SUB64ri32:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src1, (imm:{ *:[i64] })<<P:Predicate_i64immSExt32>>:$src2) 1925 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SUB64ri32, 1926 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 1927 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 1928 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // src2 1929 GIR_EraseFromParent, /*InsnID*/0, 1930 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1931 // GIR_Coverage, 21024, 1932 GIR_Done, 1933 // Label 172: @2181 1934 GIM_Try, /*On fail goto*//*Label 173*/ 2197, // Rule ID 21013 // 1935 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::GR64RegClassID, 1936 // (sub:{ *:[i64] } GR64:{ *:[i64] }:$src1, GR64:{ *:[i64] }:$src2) => (SUB64rr:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src1, GR64:{ *:[i64] }:$src2) 1937 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::SUB64rr, 1938 GIR_AddImplicitDef, /*InsnID*/0, X86::EFLAGS, 1939 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1940 // GIR_Coverage, 21013, 1941 GIR_Done, 1942 // Label 173: @2197 1943 GIM_Reject, 1944 // Label 170: @2198 1945 GIM_Reject, 1946 // Label 146: @2199 1947 GIM_Try, /*On fail goto*//*Label 174*/ 2279, 1948 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, 1949 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 1950 GIM_Try, /*On fail goto*//*Label 175*/ 2232, // Rule ID 2298 // 1951 GIM_CheckFeatures, GIFBS_HasAVX_NoVLX, 1952 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 1953 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 1954 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 1955 // (sub:{ *:[v2i64] } VR128:{ *:[v2i64] }:$src1, VR128:{ *:[v2i64] }:$src2) => (VPSUBQrr:{ *:[v2i64] } VR128:{ *:[v2i64] }:$src1, VR128:{ *:[v2i64] }:$src2) 1956 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPSUBQrr, 1957 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1958 // GIR_Coverage, 2298, 1959 GIR_Done, 1960 // Label 175: @2232 1961 GIM_Try, /*On fail goto*//*Label 176*/ 2255, // Rule ID 2300 // 1962 GIM_CheckFeatures, GIFBS_UseSSE2, 1963 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 1964 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 1965 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 1966 // (sub:{ *:[v2i64] } VR128:{ *:[v2i64] }:$src1, VR128:{ *:[v2i64] }:$src2) => (PSUBQrr:{ *:[v2i64] } VR128:{ *:[v2i64] }:$src1, VR128:{ *:[v2i64] }:$src2) 1967 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::PSUBQrr, 1968 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1969 // GIR_Coverage, 2300, 1970 GIR_Done, 1971 // Label 176: @2255 1972 GIM_Try, /*On fail goto*//*Label 177*/ 2278, // Rule ID 4380 // 1973 GIM_CheckFeatures, GIFBS_HasAVX512_HasVLX, 1974 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID, 1975 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID, 1976 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128XRegClassID, 1977 // (sub:{ *:[v2i64] } VR128X:{ *:[v2i64] }:$src1, VR128X:{ *:[v2i64] }:$src2) => (VPSUBQZ128rr:{ *:[v2i64] } VR128X:{ *:[v2i64] }:$src1, VR128X:{ *:[v2i64] }:$src2) 1978 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPSUBQZ128rr, 1979 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1980 // GIR_Coverage, 4380, 1981 GIR_Done, 1982 // Label 177: @2278 1983 GIM_Reject, 1984 // Label 174: @2279 1985 GIM_Reject, 1986 // Label 147: @2280 1987 GIM_Try, /*On fail goto*//*Label 178*/ 2360, 1988 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, 1989 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 1990 GIM_Try, /*On fail goto*//*Label 179*/ 2313, // Rule ID 2292 // 1991 GIM_CheckFeatures, GIFBS_HasAVX_NoVLX, 1992 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 1993 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 1994 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 1995 // (sub:{ *:[v4i32] } VR128:{ *:[v4i32] }:$src1, VR128:{ *:[v4i32] }:$src2) => (VPSUBDrr:{ *:[v4i32] } VR128:{ *:[v4i32] }:$src1, VR128:{ *:[v4i32] }:$src2) 1996 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPSUBDrr, 1997 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1998 // GIR_Coverage, 2292, 1999 GIR_Done, 2000 // Label 179: @2313 2001 GIM_Try, /*On fail goto*//*Label 180*/ 2336, // Rule ID 2294 // 2002 GIM_CheckFeatures, GIFBS_UseSSE2, 2003 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 2004 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 2005 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 2006 // (sub:{ *:[v4i32] } VR128:{ *:[v4i32] }:$src1, VR128:{ *:[v4i32] }:$src2) => (PSUBDrr:{ *:[v4i32] } VR128:{ *:[v4i32] }:$src1, VR128:{ *:[v4i32] }:$src2) 2007 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::PSUBDrr, 2008 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2009 // GIR_Coverage, 2294, 2010 GIR_Done, 2011 // Label 180: @2336 2012 GIM_Try, /*On fail goto*//*Label 181*/ 2359, // Rule ID 4407 // 2013 GIM_CheckFeatures, GIFBS_HasAVX512_HasVLX, 2014 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID, 2015 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID, 2016 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128XRegClassID, 2017 // (sub:{ *:[v4i32] } VR128X:{ *:[v4i32] }:$src1, VR128X:{ *:[v4i32] }:$src2) => (VPSUBDZ128rr:{ *:[v4i32] } VR128X:{ *:[v4i32] }:$src1, VR128X:{ *:[v4i32] }:$src2) 2018 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPSUBDZ128rr, 2019 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2020 // GIR_Coverage, 4407, 2021 GIR_Done, 2022 // Label 181: @2359 2023 GIM_Reject, 2024 // Label 178: @2360 2025 GIM_Reject, 2026 // Label 148: @2361 2027 GIM_Try, /*On fail goto*//*Label 182*/ 2418, 2028 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s64, 2029 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s64, 2030 GIM_Try, /*On fail goto*//*Label 183*/ 2394, // Rule ID 2302 // 2031 GIM_CheckFeatures, GIFBS_HasAVX2_NoVLX, 2032 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID, 2033 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256RegClassID, 2034 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256RegClassID, 2035 // (sub:{ *:[v4i64] } VR256:{ *:[v4i64] }:$src1, VR256:{ *:[v4i64] }:$src2) => (VPSUBQYrr:{ *:[v4i64] } VR256:{ *:[v4i64] }:$src1, VR256:{ *:[v4i64] }:$src2) 2036 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPSUBQYrr, 2037 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2038 // GIR_Coverage, 2302, 2039 GIR_Done, 2040 // Label 183: @2394 2041 GIM_Try, /*On fail goto*//*Label 184*/ 2417, // Rule ID 4371 // 2042 GIM_CheckFeatures, GIFBS_HasAVX512_HasVLX, 2043 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID, 2044 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID, 2045 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256XRegClassID, 2046 // (sub:{ *:[v4i64] } VR256X:{ *:[v4i64] }:$src1, VR256X:{ *:[v4i64] }:$src2) => (VPSUBQZ256rr:{ *:[v4i64] } VR256X:{ *:[v4i64] }:$src1, VR256X:{ *:[v4i64] }:$src2) 2047 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPSUBQZ256rr, 2048 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2049 // GIR_Coverage, 4371, 2050 GIR_Done, 2051 // Label 184: @2417 2052 GIM_Reject, 2053 // Label 182: @2418 2054 GIM_Reject, 2055 // Label 149: @2419 2056 GIM_Try, /*On fail goto*//*Label 185*/ 2499, 2057 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, 2058 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 2059 GIM_Try, /*On fail goto*//*Label 186*/ 2452, // Rule ID 2286 // 2060 GIM_CheckFeatures, GIFBS_HasAVX_NoVLX_Or_NoBWI, 2061 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 2062 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 2063 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 2064 // (sub:{ *:[v8i16] } VR128:{ *:[v8i16] }:$src1, VR128:{ *:[v8i16] }:$src2) => (VPSUBWrr:{ *:[v8i16] } VR128:{ *:[v8i16] }:$src1, VR128:{ *:[v8i16] }:$src2) 2065 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPSUBWrr, 2066 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2067 // GIR_Coverage, 2286, 2068 GIR_Done, 2069 // Label 186: @2452 2070 GIM_Try, /*On fail goto*//*Label 187*/ 2475, // Rule ID 2288 // 2071 GIM_CheckFeatures, GIFBS_UseSSE2, 2072 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 2073 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 2074 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 2075 // (sub:{ *:[v8i16] } VR128:{ *:[v8i16] }:$src1, VR128:{ *:[v8i16] }:$src2) => (PSUBWrr:{ *:[v8i16] } VR128:{ *:[v8i16] }:$src1, VR128:{ *:[v8i16] }:$src2) 2076 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::PSUBWrr, 2077 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2078 // GIR_Coverage, 2288, 2079 GIR_Done, 2080 // Label 187: @2475 2081 GIM_Try, /*On fail goto*//*Label 188*/ 2498, // Rule ID 4428 // 2082 GIM_CheckFeatures, GIFBS_HasBWI_HasVLX, 2083 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID, 2084 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID, 2085 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128XRegClassID, 2086 // (sub:{ *:[v8i16] } VR128X:{ *:[v8i16] }:$src1, VR128X:{ *:[v8i16] }:$src2) => (VPSUBWZ128rr:{ *:[v8i16] } VR128X:{ *:[v8i16] }:$src1, VR128X:{ *:[v8i16] }:$src2) 2087 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPSUBWZ128rr, 2088 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2089 // GIR_Coverage, 4428, 2090 GIR_Done, 2091 // Label 188: @2498 2092 GIM_Reject, 2093 // Label 185: @2499 2094 GIM_Reject, 2095 // Label 150: @2500 2096 GIM_Try, /*On fail goto*//*Label 189*/ 2557, 2097 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s32, 2098 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s32, 2099 GIM_Try, /*On fail goto*//*Label 190*/ 2533, // Rule ID 2296 // 2100 GIM_CheckFeatures, GIFBS_HasAVX2_NoVLX, 2101 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID, 2102 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256RegClassID, 2103 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256RegClassID, 2104 // (sub:{ *:[v8i32] } VR256:{ *:[v8i32] }:$src1, VR256:{ *:[v8i32] }:$src2) => (VPSUBDYrr:{ *:[v8i32] } VR256:{ *:[v8i32] }:$src1, VR256:{ *:[v8i32] }:$src2) 2105 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPSUBDYrr, 2106 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2107 // GIR_Coverage, 2296, 2108 GIR_Done, 2109 // Label 190: @2533 2110 GIM_Try, /*On fail goto*//*Label 191*/ 2556, // Rule ID 4398 // 2111 GIM_CheckFeatures, GIFBS_HasAVX512_HasVLX, 2112 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID, 2113 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID, 2114 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256XRegClassID, 2115 // (sub:{ *:[v8i32] } VR256X:{ *:[v8i32] }:$src1, VR256X:{ *:[v8i32] }:$src2) => (VPSUBDZ256rr:{ *:[v8i32] } VR256X:{ *:[v8i32] }:$src1, VR256X:{ *:[v8i32] }:$src2) 2116 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPSUBDZ256rr, 2117 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2118 // GIR_Coverage, 4398, 2119 GIR_Done, 2120 // Label 191: @2556 2121 GIM_Reject, 2122 // Label 189: @2557 2123 GIM_Reject, 2124 // Label 151: @2558 2125 GIM_Try, /*On fail goto*//*Label 192*/ 2589, // Rule ID 4362 // 2126 GIM_CheckFeatures, GIFBS_HasAVX512, 2127 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s64, 2128 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s64, 2129 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 2130 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR512RegClassID, 2131 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR512RegClassID, 2132 // (sub:{ *:[v8i64] } VR512:{ *:[v8i64] }:$src1, VR512:{ *:[v8i64] }:$src2) => (VPSUBQZrr:{ *:[v8i64] } VR512:{ *:[v8i64] }:$src1, VR512:{ *:[v8i64] }:$src2) 2133 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPSUBQZrr, 2134 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2135 // GIR_Coverage, 4362, 2136 GIR_Done, 2137 // Label 192: @2589 2138 GIM_Reject, 2139 // Label 152: @2590 2140 GIM_Try, /*On fail goto*//*Label 193*/ 2670, 2141 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, 2142 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, 2143 GIM_Try, /*On fail goto*//*Label 194*/ 2623, // Rule ID 2280 // 2144 GIM_CheckFeatures, GIFBS_HasAVX_NoVLX_Or_NoBWI, 2145 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 2146 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 2147 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 2148 // (sub:{ *:[v16i8] } VR128:{ *:[v16i8] }:$src1, VR128:{ *:[v16i8] }:$src2) => (VPSUBBrr:{ *:[v16i8] } VR128:{ *:[v16i8] }:$src1, VR128:{ *:[v16i8] }:$src2) 2149 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPSUBBrr, 2150 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2151 // GIR_Coverage, 2280, 2152 GIR_Done, 2153 // Label 194: @2623 2154 GIM_Try, /*On fail goto*//*Label 195*/ 2646, // Rule ID 2282 // 2155 GIM_CheckFeatures, GIFBS_UseSSE2, 2156 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 2157 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 2158 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 2159 // (sub:{ *:[v16i8] } VR128:{ *:[v16i8] }:$src1, VR128:{ *:[v16i8] }:$src2) => (PSUBBrr:{ *:[v16i8] } VR128:{ *:[v16i8] }:$src1, VR128:{ *:[v16i8] }:$src2) 2160 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::PSUBBrr, 2161 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2162 // GIR_Coverage, 2282, 2163 GIR_Done, 2164 // Label 195: @2646 2165 GIM_Try, /*On fail goto*//*Label 196*/ 2669, // Rule ID 4446 // 2166 GIM_CheckFeatures, GIFBS_HasBWI_HasVLX, 2167 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID, 2168 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID, 2169 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128XRegClassID, 2170 // (sub:{ *:[v16i8] } VR128X:{ *:[v16i8] }:$src1, VR128X:{ *:[v16i8] }:$src2) => (VPSUBBZ128rr:{ *:[v16i8] } VR128X:{ *:[v16i8] }:$src1, VR128X:{ *:[v16i8] }:$src2) 2171 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPSUBBZ128rr, 2172 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2173 // GIR_Coverage, 4446, 2174 GIR_Done, 2175 // Label 196: @2669 2176 GIM_Reject, 2177 // Label 193: @2670 2178 GIM_Reject, 2179 // Label 153: @2671 2180 GIM_Try, /*On fail goto*//*Label 197*/ 2728, 2181 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s16, 2182 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s16, 2183 GIM_Try, /*On fail goto*//*Label 198*/ 2704, // Rule ID 2290 // 2184 GIM_CheckFeatures, GIFBS_HasAVX2_NoVLX_Or_NoBWI, 2185 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID, 2186 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256RegClassID, 2187 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256RegClassID, 2188 // (sub:{ *:[v16i16] } VR256:{ *:[v16i16] }:$src1, VR256:{ *:[v16i16] }:$src2) => (VPSUBWYrr:{ *:[v16i16] } VR256:{ *:[v16i16] }:$src1, VR256:{ *:[v16i16] }:$src2) 2189 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPSUBWYrr, 2190 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2191 // GIR_Coverage, 2290, 2192 GIR_Done, 2193 // Label 198: @2704 2194 GIM_Try, /*On fail goto*//*Label 199*/ 2727, // Rule ID 4422 // 2195 GIM_CheckFeatures, GIFBS_HasBWI_HasVLX, 2196 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID, 2197 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID, 2198 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256XRegClassID, 2199 // (sub:{ *:[v16i16] } VR256X:{ *:[v16i16] }:$src1, VR256X:{ *:[v16i16] }:$src2) => (VPSUBWZ256rr:{ *:[v16i16] } VR256X:{ *:[v16i16] }:$src1, VR256X:{ *:[v16i16] }:$src2) 2200 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPSUBWZ256rr, 2201 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2202 // GIR_Coverage, 4422, 2203 GIR_Done, 2204 // Label 199: @2727 2205 GIM_Reject, 2206 // Label 197: @2728 2207 GIM_Reject, 2208 // Label 154: @2729 2209 GIM_Try, /*On fail goto*//*Label 200*/ 2760, // Rule ID 4389 // 2210 GIM_CheckFeatures, GIFBS_HasAVX512, 2211 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s32, 2212 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s32, 2213 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 2214 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR512RegClassID, 2215 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR512RegClassID, 2216 // (sub:{ *:[v16i32] } VR512:{ *:[v16i32] }:$src1, VR512:{ *:[v16i32] }:$src2) => (VPSUBDZrr:{ *:[v16i32] } VR512:{ *:[v16i32] }:$src1, VR512:{ *:[v16i32] }:$src2) 2217 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPSUBDZrr, 2218 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2219 // GIR_Coverage, 4389, 2220 GIR_Done, 2221 // Label 200: @2760 2222 GIM_Reject, 2223 // Label 155: @2761 2224 GIM_Try, /*On fail goto*//*Label 201*/ 2818, 2225 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v32s8, 2226 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v32s8, 2227 GIM_Try, /*On fail goto*//*Label 202*/ 2794, // Rule ID 2284 // 2228 GIM_CheckFeatures, GIFBS_HasAVX2_NoVLX_Or_NoBWI, 2229 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID, 2230 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256RegClassID, 2231 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256RegClassID, 2232 // (sub:{ *:[v32i8] } VR256:{ *:[v32i8] }:$src1, VR256:{ *:[v32i8] }:$src2) => (VPSUBBYrr:{ *:[v32i8] } VR256:{ *:[v32i8] }:$src1, VR256:{ *:[v32i8] }:$src2) 2233 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPSUBBYrr, 2234 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2235 // GIR_Coverage, 2284, 2236 GIR_Done, 2237 // Label 202: @2794 2238 GIM_Try, /*On fail goto*//*Label 203*/ 2817, // Rule ID 4440 // 2239 GIM_CheckFeatures, GIFBS_HasBWI_HasVLX, 2240 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID, 2241 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID, 2242 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256XRegClassID, 2243 // (sub:{ *:[v32i8] } VR256X:{ *:[v32i8] }:$src1, VR256X:{ *:[v32i8] }:$src2) => (VPSUBBZ256rr:{ *:[v32i8] } VR256X:{ *:[v32i8] }:$src1, VR256X:{ *:[v32i8] }:$src2) 2244 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPSUBBZ256rr, 2245 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2246 // GIR_Coverage, 4440, 2247 GIR_Done, 2248 // Label 203: @2817 2249 GIM_Reject, 2250 // Label 201: @2818 2251 GIM_Reject, 2252 // Label 156: @2819 2253 GIM_Try, /*On fail goto*//*Label 204*/ 2850, // Rule ID 4416 // 2254 GIM_CheckFeatures, GIFBS_HasBWI, 2255 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v32s16, 2256 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v32s16, 2257 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 2258 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR512RegClassID, 2259 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR512RegClassID, 2260 // (sub:{ *:[v32i16] } VR512:{ *:[v32i16] }:$src1, VR512:{ *:[v32i16] }:$src2) => (VPSUBWZrr:{ *:[v32i16] } VR512:{ *:[v32i16] }:$src1, VR512:{ *:[v32i16] }:$src2) 2261 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPSUBWZrr, 2262 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2263 // GIR_Coverage, 4416, 2264 GIR_Done, 2265 // Label 204: @2850 2266 GIM_Reject, 2267 // Label 157: @2851 2268 GIM_Try, /*On fail goto*//*Label 205*/ 2882, // Rule ID 4434 // 2269 GIM_CheckFeatures, GIFBS_HasBWI, 2270 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v64s8, 2271 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v64s8, 2272 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 2273 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR512RegClassID, 2274 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR512RegClassID, 2275 // (sub:{ *:[v64i8] } VR512:{ *:[v64i8] }:$src1, VR512:{ *:[v64i8] }:$src2) => (VPSUBBZrr:{ *:[v64i8] } VR512:{ *:[v64i8] }:$src1, VR512:{ *:[v64i8] }:$src2) 2276 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPSUBBZrr, 2277 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2278 // GIR_Coverage, 4434, 2279 GIR_Done, 2280 // Label 205: @2882 2281 GIM_Reject, 2282 // Label 158: @2883 2283 GIM_Reject, 2284 // Label 2: @2884 2285 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/2, 23, /*)*//*default:*//*Label 218*/ 3953, 2286 /*GILLT_s16*//*Label 206*/ 2911, 2287 /*GILLT_s32*//*Label 207*/ 3010, 2288 /*GILLT_s64*//*Label 208*/ 3109, 0, 0, 0, 2289 /*GILLT_v2s64*//*Label 209*/ 3211, 0, 2290 /*GILLT_v4s32*//*Label 210*/ 3395, 2291 /*GILLT_v4s64*//*Label 211*/ 3476, 0, 2292 /*GILLT_v8s16*//*Label 212*/ 3660, 2293 /*GILLT_v8s32*//*Label 213*/ 3741, 2294 /*GILLT_v8s64*//*Label 214*/ 3799, 0, 0, 2295 /*GILLT_v16s16*//*Label 215*/ 3831, 2296 /*GILLT_v16s32*//*Label 216*/ 3889, 0, 0, 2297 /*GILLT_v32s16*//*Label 217*/ 3921, 2298 // Label 206: @2911 2299 GIM_Try, /*On fail goto*//*Label 219*/ 3009, 2300 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16, 2301 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16, 2302 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR16RegClassID, 2303 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR16RegClassID, 2304 GIM_Try, /*On fail goto*//*Label 220*/ 2962, // Rule ID 21037 // 2305 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 2306 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 2307 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_i16immSExt8, 2308 // MIs[1] Operand 1 2309 // No operand predicates 2310 GIM_CheckIsSafeToFold, /*InsnID*/1, 2311 // (mul:{ *:[i16] } GR16:{ *:[i16] }:$src1, (imm:{ *:[i16] })<<P:Predicate_i16immSExt8>>:$src2) => (IMUL16rri8:{ *:[i16] }:{ *:[i32] } GR16:{ *:[i16] }:$src1, (imm:{ *:[i16] })<<P:Predicate_i16immSExt8>>:$src2) 2312 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::IMUL16rri8, 2313 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 2314 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 2315 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // src2 2316 GIR_EraseFromParent, /*InsnID*/0, 2317 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2318 // GIR_Coverage, 21037, 2319 GIR_Done, 2320 // Label 220: @2962 2321 GIM_Try, /*On fail goto*//*Label 221*/ 2992, // Rule ID 21035 // 2322 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 2323 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 2324 // MIs[1] Operand 1 2325 // No operand predicates 2326 GIM_CheckIsSafeToFold, /*InsnID*/1, 2327 // (mul:{ *:[i16] } GR16:{ *:[i16] }:$src1, (imm:{ *:[i16] }):$src2) => (IMUL16rri:{ *:[i16] }:{ *:[i32] } GR16:{ *:[i16] }:$src1, (imm:{ *:[i16] }):$src2) 2328 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::IMUL16rri, 2329 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 2330 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 2331 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // src2 2332 GIR_EraseFromParent, /*InsnID*/0, 2333 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2334 // GIR_Coverage, 21035, 2335 GIR_Done, 2336 // Label 221: @2992 2337 GIM_Try, /*On fail goto*//*Label 222*/ 3008, // Rule ID 21029 // 2338 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::GR16RegClassID, 2339 // (mul:{ *:[i16] } GR16:{ *:[i16] }:$src1, GR16:{ *:[i16] }:$src2) => (IMUL16rr:{ *:[i16] }:{ *:[i32] } GR16:{ *:[i16] }:$src1, GR16:{ *:[i16] }:$src2) 2340 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::IMUL16rr, 2341 GIR_AddImplicitDef, /*InsnID*/0, X86::EFLAGS, 2342 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2343 // GIR_Coverage, 21029, 2344 GIR_Done, 2345 // Label 222: @3008 2346 GIM_Reject, 2347 // Label 219: @3009 2348 GIM_Reject, 2349 // Label 207: @3010 2350 GIM_Try, /*On fail goto*//*Label 223*/ 3108, 2351 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 2352 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 2353 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID, 2354 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR32RegClassID, 2355 GIM_Try, /*On fail goto*//*Label 224*/ 3061, // Rule ID 21038 // 2356 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 2357 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 2358 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_i32immSExt8, 2359 // MIs[1] Operand 1 2360 // No operand predicates 2361 GIM_CheckIsSafeToFold, /*InsnID*/1, 2362 // (mul:{ *:[i32] } GR32:{ *:[i32] }:$src1, (imm:{ *:[i32] })<<P:Predicate_i32immSExt8>>:$src2) => (IMUL32rri8:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src1, (imm:{ *:[i32] })<<P:Predicate_i32immSExt8>>:$src2) 2363 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::IMUL32rri8, 2364 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 2365 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 2366 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // src2 2367 GIR_EraseFromParent, /*InsnID*/0, 2368 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2369 // GIR_Coverage, 21038, 2370 GIR_Done, 2371 // Label 224: @3061 2372 GIM_Try, /*On fail goto*//*Label 225*/ 3091, // Rule ID 21036 // 2373 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 2374 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 2375 // MIs[1] Operand 1 2376 // No operand predicates 2377 GIM_CheckIsSafeToFold, /*InsnID*/1, 2378 // (mul:{ *:[i32] } GR32:{ *:[i32] }:$src1, (imm:{ *:[i32] }):$src2) => (IMUL32rri:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src1, (imm:{ *:[i32] }):$src2) 2379 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::IMUL32rri, 2380 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 2381 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 2382 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // src2 2383 GIR_EraseFromParent, /*InsnID*/0, 2384 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2385 // GIR_Coverage, 21036, 2386 GIR_Done, 2387 // Label 225: @3091 2388 GIM_Try, /*On fail goto*//*Label 226*/ 3107, // Rule ID 21030 // 2389 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::GR32RegClassID, 2390 // (mul:{ *:[i32] } GR32:{ *:[i32] }:$src1, GR32:{ *:[i32] }:$src2) => (IMUL32rr:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src1, GR32:{ *:[i32] }:$src2) 2391 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::IMUL32rr, 2392 GIR_AddImplicitDef, /*InsnID*/0, X86::EFLAGS, 2393 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2394 // GIR_Coverage, 21030, 2395 GIR_Done, 2396 // Label 226: @3107 2397 GIM_Reject, 2398 // Label 223: @3108 2399 GIM_Reject, 2400 // Label 208: @3109 2401 GIM_Try, /*On fail goto*//*Label 227*/ 3210, 2402 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 2403 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 2404 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID, 2405 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR64RegClassID, 2406 GIM_Try, /*On fail goto*//*Label 228*/ 3160, // Rule ID 21039 // 2407 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 2408 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 2409 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_i64immSExt8, 2410 // MIs[1] Operand 1 2411 // No operand predicates 2412 GIM_CheckIsSafeToFold, /*InsnID*/1, 2413 // (mul:{ *:[i64] } GR64:{ *:[i64] }:$src1, (imm:{ *:[i64] })<<P:Predicate_i64immSExt8>>:$src2) => (IMUL64rri8:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src1, (imm:{ *:[i64] })<<P:Predicate_i64immSExt8>>:$src2) 2414 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::IMUL64rri8, 2415 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 2416 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 2417 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // src2 2418 GIR_EraseFromParent, /*InsnID*/0, 2419 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2420 // GIR_Coverage, 21039, 2421 GIR_Done, 2422 // Label 228: @3160 2423 GIM_Try, /*On fail goto*//*Label 229*/ 3193, // Rule ID 21040 // 2424 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 2425 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 2426 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_i64immSExt32, 2427 // MIs[1] Operand 1 2428 // No operand predicates 2429 GIM_CheckIsSafeToFold, /*InsnID*/1, 2430 // (mul:{ *:[i64] } GR64:{ *:[i64] }:$src1, (imm:{ *:[i64] })<<P:Predicate_i64immSExt32>>:$src2) => (IMUL64rri32:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src1, (imm:{ *:[i64] })<<P:Predicate_i64immSExt32>>:$src2) 2431 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::IMUL64rri32, 2432 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 2433 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 2434 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // src2 2435 GIR_EraseFromParent, /*InsnID*/0, 2436 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2437 // GIR_Coverage, 21040, 2438 GIR_Done, 2439 // Label 229: @3193 2440 GIM_Try, /*On fail goto*//*Label 230*/ 3209, // Rule ID 21031 // 2441 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::GR64RegClassID, 2442 // (mul:{ *:[i64] } GR64:{ *:[i64] }:$src1, GR64:{ *:[i64] }:$src2) => (IMUL64rr:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src1, GR64:{ *:[i64] }:$src2) 2443 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::IMUL64rr, 2444 GIR_AddImplicitDef, /*InsnID*/0, X86::EFLAGS, 2445 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2446 // GIR_Coverage, 21031, 2447 GIR_Done, 2448 // Label 230: @3209 2449 GIM_Reject, 2450 // Label 227: @3210 2451 GIM_Reject, 2452 // Label 209: @3211 2453 GIM_Try, /*On fail goto*//*Label 231*/ 3394, 2454 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, 2455 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 2456 GIM_Try, /*On fail goto*//*Label 232*/ 3244, // Rule ID 4659 // 2457 GIM_CheckFeatures, GIFBS_HasDQI_HasVLX, 2458 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID, 2459 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID, 2460 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128XRegClassID, 2461 // (mul:{ *:[v2i64] } VR128X:{ *:[v2i64] }:$src1, VR128X:{ *:[v2i64] }:$src2) => (VPMULLQZ128rr:{ *:[v2i64] } VR128X:{ *:[v2i64] }:$src1, VR128X:{ *:[v2i64] }:$src2) 2462 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMULLQZ128rr, 2463 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2464 // GIR_Coverage, 4659, 2465 GIR_Done, 2466 // Label 232: @3244 2467 GIM_Try, /*On fail goto*//*Label 233*/ 3393, // Rule ID 18483 // 2468 GIM_CheckFeatures, GIFBS_HasDQI_NoVLX, 2469 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 2470 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID, 2471 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128XRegClassID, 2472 // (mul:{ *:[v2i64] } VR128X:{ *:[v2i64] }:$src1, VR128X:{ *:[v2i64] }:$src2) => (EXTRACT_SUBREG:{ *:[v2i64] } (VPMULLQZrr:{ *:[v64i8] } (INSERT_SUBREG:{ *:[v8i64] } (IMPLICIT_DEF:{ *:[v8i64] }), VR128X:{ *:[v2i64] }:$src1, sub_xmm:{ *:[i32] }), (INSERT_SUBREG:{ *:[v8i64] } (IMPLICIT_DEF:{ *:[v8i64] }), VR128X:{ *:[v2i64] }:$src2, sub_xmm:{ *:[i32] })), sub_xmm:{ *:[i32] }) 2473 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v64s8, 2474 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s64, 2475 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v8s64, 2476 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v8s64, 2477 GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v8s64, 2478 GIR_BuildMI, /*InsnID*/5, /*Opcode*/TargetOpcode::IMPLICIT_DEF, 2479 GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/RegState::Define, 2480 GIR_ConstrainSelectedInstOperands, /*InsnID*/5, 2481 GIR_BuildMI, /*InsnID*/4, /*Opcode*/TargetOpcode::INSERT_SUBREG, 2482 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define, 2483 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/4, /*TempRegFlags*/0, 2484 GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/2, // src2 2485 GIR_AddImm, /*InsnID*/4, /*Imm*/9, 2486 GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, X86::VR512RegClassID, 2487 GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/1, X86::VR512RegClassID, 2488 GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/2, X86::VR128XRegClassID, 2489 GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::IMPLICIT_DEF, 2490 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, 2491 GIR_ConstrainSelectedInstOperands, /*InsnID*/3, 2492 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::INSERT_SUBREG, 2493 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 2494 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/2, /*TempRegFlags*/0, 2495 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src1 2496 GIR_AddImm, /*InsnID*/2, /*Imm*/9, 2497 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, X86::VR512RegClassID, 2498 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, X86::VR512RegClassID, 2499 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, X86::VR128XRegClassID, 2500 GIR_BuildMI, /*InsnID*/1, /*Opcode*/X86::VPMULLQZrr, 2501 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 2502 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, 2503 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/3, /*TempRegFlags*/0, 2504 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 2505 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 2506 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 2507 GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, X86::sub_xmm, 2508 GIR_EraseFromParent, /*InsnID*/0, 2509 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, X86::FR16XRegClassID, 2510 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, X86::VR512RegClassID, 2511 // GIR_Coverage, 18483, 2512 GIR_Done, 2513 // Label 233: @3393 2514 GIM_Reject, 2515 // Label 231: @3394 2516 GIM_Reject, 2517 // Label 210: @3395 2518 GIM_Try, /*On fail goto*//*Label 234*/ 3475, 2519 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, 2520 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 2521 GIM_Try, /*On fail goto*//*Label 235*/ 3428, // Rule ID 2931 // 2522 GIM_CheckFeatures, GIFBS_HasAVX_NoVLX, 2523 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 2524 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 2525 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 2526 // (mul:{ *:[v4i32] } VR128:{ *:[v4i32] }:$src1, VR128:{ *:[v4i32] }:$src2) => (VPMULLDrr:{ *:[v4i32] } VR128:{ *:[v4i32] }:$src1, VR128:{ *:[v4i32] }:$src2) 2527 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMULLDrr, 2528 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2529 // GIR_Coverage, 2931, 2530 GIR_Done, 2531 // Label 235: @3428 2532 GIM_Try, /*On fail goto*//*Label 236*/ 3451, // Rule ID 2939 // 2533 GIM_CheckFeatures, GIFBS_UseSSE41, 2534 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 2535 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 2536 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 2537 // (mul:{ *:[v4i32] } VR128:{ *:[v4i32] }:$src1, VR128:{ *:[v4i32] }:$src2) => (PMULLDrr:{ *:[v4i32] } VR128:{ *:[v4i32] }:$src1, VR128:{ *:[v4i32] }:$src2) 2538 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::PMULLDrr, 2539 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2540 // GIR_Coverage, 2939, 2541 GIR_Done, 2542 // Label 236: @3451 2543 GIM_Try, /*On fail goto*//*Label 237*/ 3474, // Rule ID 4614 // 2544 GIM_CheckFeatures, GIFBS_HasAVX512_HasVLX, 2545 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID, 2546 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID, 2547 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128XRegClassID, 2548 // (mul:{ *:[v4i32] } VR128X:{ *:[v4i32] }:$src1, VR128X:{ *:[v4i32] }:$src2) => (VPMULLDZ128rr:{ *:[v4i32] } VR128X:{ *:[v4i32] }:$src1, VR128X:{ *:[v4i32] }:$src2) 2549 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMULLDZ128rr, 2550 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2551 // GIR_Coverage, 4614, 2552 GIR_Done, 2553 // Label 237: @3474 2554 GIM_Reject, 2555 // Label 234: @3475 2556 GIM_Reject, 2557 // Label 211: @3476 2558 GIM_Try, /*On fail goto*//*Label 238*/ 3659, 2559 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s64, 2560 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s64, 2561 GIM_Try, /*On fail goto*//*Label 239*/ 3509, // Rule ID 4650 // 2562 GIM_CheckFeatures, GIFBS_HasDQI_HasVLX, 2563 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID, 2564 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID, 2565 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256XRegClassID, 2566 // (mul:{ *:[v4i64] } VR256X:{ *:[v4i64] }:$src1, VR256X:{ *:[v4i64] }:$src2) => (VPMULLQZ256rr:{ *:[v4i64] } VR256X:{ *:[v4i64] }:$src1, VR256X:{ *:[v4i64] }:$src2) 2567 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMULLQZ256rr, 2568 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2569 // GIR_Coverage, 4650, 2570 GIR_Done, 2571 // Label 239: @3509 2572 GIM_Try, /*On fail goto*//*Label 240*/ 3658, // Rule ID 18481 // 2573 GIM_CheckFeatures, GIFBS_HasDQI_NoVLX, 2574 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 2575 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID, 2576 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256XRegClassID, 2577 // (mul:{ *:[v4i64] } VR256X:{ *:[v4i64] }:$src1, VR256X:{ *:[v4i64] }:$src2) => (EXTRACT_SUBREG:{ *:[v4i64] } (VPMULLQZrr:{ *:[v64i8] } (INSERT_SUBREG:{ *:[v8i64] } (IMPLICIT_DEF:{ *:[v8i64] }), VR256X:{ *:[v4i64] }:$src1, sub_ymm:{ *:[i32] }), (INSERT_SUBREG:{ *:[v8i64] } (IMPLICIT_DEF:{ *:[v8i64] }), VR256X:{ *:[v4i64] }:$src2, sub_ymm:{ *:[i32] })), sub_ymm:{ *:[i32] }) 2578 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v64s8, 2579 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s64, 2580 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v8s64, 2581 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v8s64, 2582 GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v8s64, 2583 GIR_BuildMI, /*InsnID*/5, /*Opcode*/TargetOpcode::IMPLICIT_DEF, 2584 GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/RegState::Define, 2585 GIR_ConstrainSelectedInstOperands, /*InsnID*/5, 2586 GIR_BuildMI, /*InsnID*/4, /*Opcode*/TargetOpcode::INSERT_SUBREG, 2587 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define, 2588 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/4, /*TempRegFlags*/0, 2589 GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/2, // src2 2590 GIR_AddImm, /*InsnID*/4, /*Imm*/10, 2591 GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, X86::VR512RegClassID, 2592 GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/1, X86::VR512RegClassID, 2593 GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/2, X86::VR256XRegClassID, 2594 GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::IMPLICIT_DEF, 2595 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, 2596 GIR_ConstrainSelectedInstOperands, /*InsnID*/3, 2597 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::INSERT_SUBREG, 2598 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 2599 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/2, /*TempRegFlags*/0, 2600 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src1 2601 GIR_AddImm, /*InsnID*/2, /*Imm*/10, 2602 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, X86::VR512RegClassID, 2603 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, X86::VR512RegClassID, 2604 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, X86::VR256XRegClassID, 2605 GIR_BuildMI, /*InsnID*/1, /*Opcode*/X86::VPMULLQZrr, 2606 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 2607 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, 2608 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/3, /*TempRegFlags*/0, 2609 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 2610 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 2611 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 2612 GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, X86::sub_ymm, 2613 GIR_EraseFromParent, /*InsnID*/0, 2614 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, X86::VR256XRegClassID, 2615 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, X86::VR512RegClassID, 2616 // GIR_Coverage, 18481, 2617 GIR_Done, 2618 // Label 240: @3658 2619 GIM_Reject, 2620 // Label 238: @3659 2621 GIM_Reject, 2622 // Label 212: @3660 2623 GIM_Try, /*On fail goto*//*Label 241*/ 3740, 2624 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, 2625 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 2626 GIM_Try, /*On fail goto*//*Label 242*/ 3693, // Rule ID 2262 // 2627 GIM_CheckFeatures, GIFBS_HasAVX_NoVLX_Or_NoBWI, 2628 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 2629 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 2630 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 2631 // (mul:{ *:[v8i16] } VR128:{ *:[v8i16] }:$src1, VR128:{ *:[v8i16] }:$src2) => (VPMULLWrr:{ *:[v8i16] } VR128:{ *:[v8i16] }:$src1, VR128:{ *:[v8i16] }:$src2) 2632 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMULLWrr, 2633 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2634 // GIR_Coverage, 2262, 2635 GIR_Done, 2636 // Label 242: @3693 2637 GIM_Try, /*On fail goto*//*Label 243*/ 3716, // Rule ID 2264 // 2638 GIM_CheckFeatures, GIFBS_UseSSE2, 2639 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 2640 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 2641 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 2642 // (mul:{ *:[v8i16] } VR128:{ *:[v8i16] }:$src1, VR128:{ *:[v8i16] }:$src2) => (PMULLWrr:{ *:[v8i16] } VR128:{ *:[v8i16] }:$src1, VR128:{ *:[v8i16] }:$src2) 2643 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::PMULLWrr, 2644 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2645 // GIR_Coverage, 2264, 2646 GIR_Done, 2647 // Label 243: @3716 2648 GIM_Try, /*On fail goto*//*Label 244*/ 3739, // Rule ID 4635 // 2649 GIM_CheckFeatures, GIFBS_HasBWI_HasVLX, 2650 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID, 2651 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID, 2652 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128XRegClassID, 2653 // (mul:{ *:[v8i16] } VR128X:{ *:[v8i16] }:$src1, VR128X:{ *:[v8i16] }:$src2) => (VPMULLWZ128rr:{ *:[v8i16] } VR128X:{ *:[v8i16] }:$src1, VR128X:{ *:[v8i16] }:$src2) 2654 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMULLWZ128rr, 2655 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2656 // GIR_Coverage, 4635, 2657 GIR_Done, 2658 // Label 244: @3739 2659 GIM_Reject, 2660 // Label 241: @3740 2661 GIM_Reject, 2662 // Label 213: @3741 2663 GIM_Try, /*On fail goto*//*Label 245*/ 3798, 2664 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s32, 2665 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s32, 2666 GIM_Try, /*On fail goto*//*Label 246*/ 3774, // Rule ID 2935 // 2667 GIM_CheckFeatures, GIFBS_HasAVX2_NoVLX, 2668 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID, 2669 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256RegClassID, 2670 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256RegClassID, 2671 // (mul:{ *:[v8i32] } VR256:{ *:[v8i32] }:$src1, VR256:{ *:[v8i32] }:$src2) => (VPMULLDYrr:{ *:[v8i32] } VR256:{ *:[v8i32] }:$src1, VR256:{ *:[v8i32] }:$src2) 2672 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMULLDYrr, 2673 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2674 // GIR_Coverage, 2935, 2675 GIR_Done, 2676 // Label 246: @3774 2677 GIM_Try, /*On fail goto*//*Label 247*/ 3797, // Rule ID 4605 // 2678 GIM_CheckFeatures, GIFBS_HasAVX512_HasVLX, 2679 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID, 2680 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID, 2681 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256XRegClassID, 2682 // (mul:{ *:[v8i32] } VR256X:{ *:[v8i32] }:$src1, VR256X:{ *:[v8i32] }:$src2) => (VPMULLDZ256rr:{ *:[v8i32] } VR256X:{ *:[v8i32] }:$src1, VR256X:{ *:[v8i32] }:$src2) 2683 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMULLDZ256rr, 2684 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2685 // GIR_Coverage, 4605, 2686 GIR_Done, 2687 // Label 247: @3797 2688 GIM_Reject, 2689 // Label 245: @3798 2690 GIM_Reject, 2691 // Label 214: @3799 2692 GIM_Try, /*On fail goto*//*Label 248*/ 3830, // Rule ID 4641 // 2693 GIM_CheckFeatures, GIFBS_HasDQI, 2694 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s64, 2695 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s64, 2696 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 2697 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR512RegClassID, 2698 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR512RegClassID, 2699 // (mul:{ *:[v8i64] } VR512:{ *:[v8i64] }:$src1, VR512:{ *:[v8i64] }:$src2) => (VPMULLQZrr:{ *:[v8i64] } VR512:{ *:[v8i64] }:$src1, VR512:{ *:[v8i64] }:$src2) 2700 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMULLQZrr, 2701 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2702 // GIR_Coverage, 4641, 2703 GIR_Done, 2704 // Label 248: @3830 2705 GIM_Reject, 2706 // Label 215: @3831 2707 GIM_Try, /*On fail goto*//*Label 249*/ 3888, 2708 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s16, 2709 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s16, 2710 GIM_Try, /*On fail goto*//*Label 250*/ 3864, // Rule ID 2266 // 2711 GIM_CheckFeatures, GIFBS_HasAVX2_NoVLX_Or_NoBWI, 2712 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID, 2713 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256RegClassID, 2714 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256RegClassID, 2715 // (mul:{ *:[v16i16] } VR256:{ *:[v16i16] }:$src1, VR256:{ *:[v16i16] }:$src2) => (VPMULLWYrr:{ *:[v16i16] } VR256:{ *:[v16i16] }:$src1, VR256:{ *:[v16i16] }:$src2) 2716 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMULLWYrr, 2717 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2718 // GIR_Coverage, 2266, 2719 GIR_Done, 2720 // Label 250: @3864 2721 GIM_Try, /*On fail goto*//*Label 251*/ 3887, // Rule ID 4629 // 2722 GIM_CheckFeatures, GIFBS_HasBWI_HasVLX, 2723 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID, 2724 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID, 2725 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256XRegClassID, 2726 // (mul:{ *:[v16i16] } VR256X:{ *:[v16i16] }:$src1, VR256X:{ *:[v16i16] }:$src2) => (VPMULLWZ256rr:{ *:[v16i16] } VR256X:{ *:[v16i16] }:$src1, VR256X:{ *:[v16i16] }:$src2) 2727 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMULLWZ256rr, 2728 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2729 // GIR_Coverage, 4629, 2730 GIR_Done, 2731 // Label 251: @3887 2732 GIM_Reject, 2733 // Label 249: @3888 2734 GIM_Reject, 2735 // Label 216: @3889 2736 GIM_Try, /*On fail goto*//*Label 252*/ 3920, // Rule ID 4596 // 2737 GIM_CheckFeatures, GIFBS_HasAVX512, 2738 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s32, 2739 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s32, 2740 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 2741 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR512RegClassID, 2742 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR512RegClassID, 2743 // (mul:{ *:[v16i32] } VR512:{ *:[v16i32] }:$src1, VR512:{ *:[v16i32] }:$src2) => (VPMULLDZrr:{ *:[v16i32] } VR512:{ *:[v16i32] }:$src1, VR512:{ *:[v16i32] }:$src2) 2744 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMULLDZrr, 2745 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2746 // GIR_Coverage, 4596, 2747 GIR_Done, 2748 // Label 252: @3920 2749 GIM_Reject, 2750 // Label 217: @3921 2751 GIM_Try, /*On fail goto*//*Label 253*/ 3952, // Rule ID 4623 // 2752 GIM_CheckFeatures, GIFBS_HasBWI, 2753 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v32s16, 2754 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v32s16, 2755 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 2756 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR512RegClassID, 2757 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR512RegClassID, 2758 // (mul:{ *:[v32i16] } VR512:{ *:[v32i16] }:$src1, VR512:{ *:[v32i16] }:$src2) => (VPMULLWZrr:{ *:[v32i16] } VR512:{ *:[v32i16] }:$src1, VR512:{ *:[v32i16] }:$src2) 2759 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMULLWZrr, 2760 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2761 // GIR_Coverage, 4623, 2762 GIR_Done, 2763 // Label 253: @3952 2764 GIM_Reject, 2765 // Label 218: @3953 2766 GIM_Reject, 2767 // Label 3: @3954 2768 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 25, /*)*//*default:*//*Label 277*/ 9363, 2769 /*GILLT_s1*//*Label 254*/ 3985, 2770 /*GILLT_s8*//*Label 255*/ 4299, 2771 /*GILLT_s16*//*Label 256*/ 4365, 2772 /*GILLT_s32*//*Label 257*/ 4756, 2773 /*GILLT_s64*//*Label 258*/ 5947, 0, 0, 2774 /*GILLT_v2s1*//*Label 259*/ 7027, 2775 /*GILLT_v2s64*//*Label 260*/ 7341, 2776 /*GILLT_v4s1*//*Label 261*/ 7422, 2777 /*GILLT_v4s32*//*Label 262*/ 7736, 2778 /*GILLT_v4s64*//*Label 263*/ 7817, 2779 /*GILLT_v8s1*//*Label 264*/ 7898, 2780 /*GILLT_v8s16*//*Label 265*/ 8359, 2781 /*GILLT_v8s32*//*Label 266*/ 8440, 2782 /*GILLT_v8s64*//*Label 267*/ 8521, 2783 /*GILLT_v16s1*//*Label 268*/ 8553, 2784 /*GILLT_v16s8*//*Label 269*/ 8710, 2785 /*GILLT_v16s16*//*Label 270*/ 8791, 2786 /*GILLT_v16s32*//*Label 271*/ 8872, 2787 /*GILLT_v32s1*//*Label 272*/ 8904, 2788 /*GILLT_v32s8*//*Label 273*/ 9061, 2789 /*GILLT_v32s16*//*Label 274*/ 9142, 2790 /*GILLT_v64s1*//*Label 275*/ 9174, 2791 /*GILLT_v64s8*//*Label 276*/ 9331, 2792 // Label 254: @3985 2793 GIM_Try, /*On fail goto*//*Label 278*/ 4298, 2794 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s1, 2795 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s1, 2796 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VK1RegClassID, 2797 GIM_Try, /*On fail goto*//*Label 279*/ 4108, // Rule ID 17927 // 2798 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 2799 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, 2800 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s1, 2801 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s1, 2802 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::VK1RegClassID, 2803 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] 2804 GIM_CheckOpcodeIsEither, /*MI*/2, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, 2805 GIM_CheckIsBuildVectorAllOnes, /*MI*/2, 2806 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VK1RegClassID, 2807 GIM_CheckIsSafeToFold, /*InsnID*/1, 2808 GIM_CheckIsSafeToFold, /*InsnID*/2, 2809 // (and:{ *:[v1i1] } (xor:{ *:[v1i1] } VK1:{ *:[v1i1] }:$src1, immAllOnesV:{ *:[v1i1] }), VK1:{ *:[v1i1] }:$src2) => (COPY_TO_REGCLASS:{ *:[v1i1] } (KANDNWrr:{ *:[v16i1] } (COPY_TO_REGCLASS:{ *:[v16i1] } VK1:{ *:[v1i1] }:$src1, VK16:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v16i1] } VK1:{ *:[v1i1] }:$src2, VK16:{ *:[i32] })), VK1:{ *:[i32] }) 2810 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s1, 2811 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s1, 2812 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s1, 2813 GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::COPY, 2814 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, 2815 GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // src2 2816 GIR_ConstrainSelectedInstOperands, /*InsnID*/3, 2817 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY, 2818 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 2819 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, // src1 2820 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 2821 GIR_BuildMI, /*InsnID*/1, /*Opcode*/X86::KANDNWrr, 2822 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 2823 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, 2824 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/2, /*TempRegFlags*/0, 2825 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 2826 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 2827 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 2828 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 2829 GIR_EraseFromParent, /*InsnID*/0, 2830 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, X86::VK1RegClassID, 2831 // GIR_Coverage, 17927, 2832 GIR_Done, 2833 // Label 279: @4108 2834 GIM_Try, /*On fail goto*//*Label 280*/ 4217, // Rule ID 23233 // 2835 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VK1RegClassID, 2836 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 2837 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, 2838 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s1, 2839 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s1, 2840 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::VK1RegClassID, 2841 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] 2842 GIM_CheckOpcodeIsEither, /*MI*/2, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, 2843 GIM_CheckIsBuildVectorAllOnes, /*MI*/2, 2844 GIM_CheckIsSafeToFold, /*InsnID*/1, 2845 GIM_CheckIsSafeToFold, /*InsnID*/2, 2846 // (and:{ *:[v1i1] } VK1:{ *:[v1i1] }:$src2, (xor:{ *:[v1i1] } VK1:{ *:[v1i1] }:$src1, immAllOnesV:{ *:[v1i1] })) => (COPY_TO_REGCLASS:{ *:[v1i1] } (KANDNWrr:{ *:[v16i1] } (COPY_TO_REGCLASS:{ *:[v16i1] } VK1:{ *:[v1i1] }:$src1, VK16:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v16i1] } VK1:{ *:[v1i1] }:$src2, VK16:{ *:[i32] })), VK1:{ *:[i32] }) 2847 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s1, 2848 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s1, 2849 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s1, 2850 GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::COPY, 2851 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, 2852 GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // src2 2853 GIR_ConstrainSelectedInstOperands, /*InsnID*/3, 2854 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY, 2855 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 2856 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, // src1 2857 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 2858 GIR_BuildMI, /*InsnID*/1, /*Opcode*/X86::KANDNWrr, 2859 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 2860 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, 2861 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/2, /*TempRegFlags*/0, 2862 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 2863 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 2864 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 2865 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 2866 GIR_EraseFromParent, /*InsnID*/0, 2867 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, X86::VK1RegClassID, 2868 // GIR_Coverage, 23233, 2869 GIR_Done, 2870 // Label 280: @4217 2871 GIM_Try, /*On fail goto*//*Label 281*/ 4297, // Rule ID 17923 // 2872 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VK1RegClassID, 2873 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VK1RegClassID, 2874 // (and:{ *:[v1i1] } VK1:{ *:[v1i1] }:$src1, VK1:{ *:[v1i1] }:$src2) => (COPY_TO_REGCLASS:{ *:[v1i1] } (KANDWrr:{ *:[v16i1] } (COPY_TO_REGCLASS:{ *:[v16i1] } VK1:{ *:[v1i1] }:$src1, VK16:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v16i1] } VK1:{ *:[v1i1] }:$src2, VK16:{ *:[i32] })), VK1:{ *:[i32] }) 2875 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s1, 2876 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s1, 2877 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s1, 2878 GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::COPY, 2879 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, 2880 GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // src2 2881 GIR_ConstrainSelectedInstOperands, /*InsnID*/3, 2882 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY, 2883 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 2884 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src1 2885 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 2886 GIR_BuildMI, /*InsnID*/1, /*Opcode*/X86::KANDWrr, 2887 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 2888 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, 2889 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/2, /*TempRegFlags*/0, 2890 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 2891 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 2892 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 2893 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 2894 GIR_EraseFromParent, /*InsnID*/0, 2895 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, X86::VK1RegClassID, 2896 // GIR_Coverage, 17923, 2897 GIR_Done, 2898 // Label 281: @4297 2899 GIM_Reject, 2900 // Label 278: @4298 2901 GIM_Reject, 2902 // Label 255: @4299 2903 GIM_Try, /*On fail goto*//*Label 282*/ 4364, 2904 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s8, 2905 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s8, 2906 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR8RegClassID, 2907 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR8RegClassID, 2908 GIM_Try, /*On fail goto*//*Label 283*/ 4347, // Rule ID 15703 // 2909 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 2910 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 2911 // MIs[1] Operand 1 2912 // No operand predicates 2913 GIM_CheckIsSafeToFold, /*InsnID*/1, 2914 // (and:{ *:[i8] } GR8:{ *:[i8] }:$src1, (imm:{ *:[i8] }):$src2) => (AND8ri:{ *:[i8] }:{ *:[i32] } GR8:{ *:[i8] }:$src1, (imm:{ *:[i8] }):$src2) 2915 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::AND8ri, 2916 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 2917 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 2918 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // src2 2919 GIR_EraseFromParent, /*InsnID*/0, 2920 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2921 // GIR_Coverage, 15703, 2922 GIR_Done, 2923 // Label 283: @4347 2924 GIM_Try, /*On fail goto*//*Label 284*/ 4363, // Rule ID 15695 // 2925 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::GR8RegClassID, 2926 // (and:{ *:[i8] } GR8:{ *:[i8] }:$src1, GR8:{ *:[i8] }:$src2) => (AND8rr:{ *:[i8] }:{ *:[i32] } GR8:{ *:[i8] }:$src1, GR8:{ *:[i8] }:$src2) 2927 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::AND8rr, 2928 GIR_AddImplicitDef, /*InsnID*/0, X86::EFLAGS, 2929 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2930 // GIR_Coverage, 15695, 2931 GIR_Done, 2932 // Label 284: @4363 2933 GIM_Reject, 2934 // Label 282: @4364 2935 GIM_Reject, 2936 // Label 256: @4365 2937 GIM_Try, /*On fail goto*//*Label 285*/ 4755, 2938 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16, 2939 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16, 2940 GIM_Try, /*On fail goto*//*Label 286*/ 4475, // Rule ID 23892 // 2941 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR16RegClassID, 2942 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 2943 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ROTL, 2944 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, 2945 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s8, 2946 GIM_CheckConstantInt, /*MI*/1, /*Op*/1, -2, 2947 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/X86::GR8RegClassID, 2948 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::GR16RegClassID, 2949 GIM_CheckIsSafeToFold, /*InsnID*/1, 2950 // (and:{ *:[i16] } (rotl:{ *:[i16] } -2:{ *:[i16] }, GR8:{ *:[i8] }:$src2), GR16:{ *:[i16] }:$src1) => (BTR16rr:{ *:[i16] }:{ *:[i32] } GR16:{ *:[i16] }:$src1, (INSERT_SUBREG:{ *:[i16] } (IMPLICIT_DEF:{ *:[i16] }), GR8:{ *:[i8] }:$src2, sub_8bit:{ *:[i32] })) 2951 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16, 2952 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16, 2953 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, 2954 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 2955 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 2956 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, 2957 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 2958 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, 2959 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // src2 2960 GIR_AddImm, /*InsnID*/1, /*Imm*/1, 2961 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, X86::GR16RegClassID, 2962 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, X86::GR16RegClassID, 2963 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, X86::GR8RegClassID, 2964 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BTR16rr, 2965 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 2966 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 2967 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 2968 GIR_EraseFromParent, /*InsnID*/0, 2969 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2970 // GIR_Coverage, 23892, 2971 GIR_Done, 2972 // Label 286: @4475 2973 GIM_Try, /*On fail goto*//*Label 287*/ 4575, // Rule ID 20977 // 2974 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR16RegClassID, 2975 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR16RegClassID, 2976 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 2977 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ROTL, 2978 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, 2979 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s8, 2980 GIM_CheckConstantInt, /*MI*/1, /*Op*/1, -2, 2981 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/X86::GR8RegClassID, 2982 GIM_CheckIsSafeToFold, /*InsnID*/1, 2983 // (and:{ *:[i16] } GR16:{ *:[i16] }:$src1, (rotl:{ *:[i16] } -2:{ *:[i16] }, GR8:{ *:[i8] }:$src2)) => (BTR16rr:{ *:[i16] }:{ *:[i32] } GR16:{ *:[i16] }:$src1, (INSERT_SUBREG:{ *:[i16] } (IMPLICIT_DEF:{ *:[i16] }), GR8:{ *:[i8] }:$src2, sub_8bit:{ *:[i32] })) 2984 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16, 2985 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16, 2986 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, 2987 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 2988 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 2989 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, 2990 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 2991 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, 2992 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // src2 2993 GIR_AddImm, /*InsnID*/1, /*Imm*/1, 2994 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, X86::GR16RegClassID, 2995 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, X86::GR16RegClassID, 2996 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, X86::GR8RegClassID, 2997 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BTR16rr, 2998 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 2999 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 3000 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 3001 GIR_EraseFromParent, /*InsnID*/0, 3002 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 3003 // GIR_Coverage, 20977, 3004 GIR_Done, 3005 // Label 287: @4575 3006 GIM_Try, /*On fail goto*//*Label 288*/ 4651, // Rule ID 20875 // 3007 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID, 3008 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR16RegClassID, 3009 GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 255, 3010 // (and:{ *:[i16] } GR16:{ *:[i16] }:$src1, 255:{ *:[i16] }) => (EXTRACT_SUBREG:{ *:[i16] } (MOVZX32rr8:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i8] } GR16:{ *:[i16] }:$src1, sub_8bit:{ *:[i32] })), sub_16bit:{ *:[i32] }) 3011 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, 3012 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s8, 3013 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY, 3014 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 3015 GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/1, // src1 3016 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, X86::GR8RegClassID, 3017 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, X86::GR16RegClassID, 3018 GIR_BuildMI, /*InsnID*/1, /*Opcode*/X86::MOVZX32rr8, 3019 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 3020 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, 3021 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 3022 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 3023 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 3024 GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, X86::sub_16bit, 3025 GIR_EraseFromParent, /*InsnID*/0, 3026 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, X86::GR16RegClassID, 3027 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, X86::GR32RegClassID, 3028 // GIR_Coverage, 20875, 3029 GIR_Done, 3030 // Label 288: @4651 3031 GIM_Try, /*On fail goto*//*Label 289*/ 4692, // Rule ID 15706 // 3032 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR16RegClassID, 3033 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR16RegClassID, 3034 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 3035 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 3036 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_i16immSExt8, 3037 // MIs[1] Operand 1 3038 // No operand predicates 3039 GIM_CheckIsSafeToFold, /*InsnID*/1, 3040 // (and:{ *:[i16] } GR16:{ *:[i16] }:$src1, (imm:{ *:[i16] })<<P:Predicate_i16immSExt8>>:$src2) => (AND16ri8:{ *:[i16] }:{ *:[i32] } GR16:{ *:[i16] }:$src1, (imm:{ *:[i16] })<<P:Predicate_i16immSExt8>>:$src2) 3041 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::AND16ri8, 3042 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 3043 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 3044 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // src2 3045 GIR_EraseFromParent, /*InsnID*/0, 3046 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 3047 // GIR_Coverage, 15706, 3048 GIR_Done, 3049 // Label 289: @4692 3050 GIM_Try, /*On fail goto*//*Label 290*/ 4730, // Rule ID 15704 // 3051 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR16RegClassID, 3052 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR16RegClassID, 3053 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 3054 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 3055 // MIs[1] Operand 1 3056 // No operand predicates 3057 GIM_CheckIsSafeToFold, /*InsnID*/1, 3058 // (and:{ *:[i16] } GR16:{ *:[i16] }:$src1, (imm:{ *:[i16] }):$src2) => (AND16ri:{ *:[i16] }:{ *:[i32] } GR16:{ *:[i16] }:$src1, (imm:{ *:[i16] }):$src2) 3059 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::AND16ri, 3060 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 3061 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 3062 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // src2 3063 GIR_EraseFromParent, /*InsnID*/0, 3064 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 3065 // GIR_Coverage, 15704, 3066 GIR_Done, 3067 // Label 290: @4730 3068 GIM_Try, /*On fail goto*//*Label 291*/ 4754, // Rule ID 15696 // 3069 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR16RegClassID, 3070 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR16RegClassID, 3071 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::GR16RegClassID, 3072 // (and:{ *:[i16] } GR16:{ *:[i16] }:$src1, GR16:{ *:[i16] }:$src2) => (AND16rr:{ *:[i16] }:{ *:[i32] } GR16:{ *:[i16] }:$src1, GR16:{ *:[i16] }:$src2) 3073 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::AND16rr, 3074 GIR_AddImplicitDef, /*InsnID*/0, X86::EFLAGS, 3075 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 3076 // GIR_Coverage, 15696, 3077 GIR_Done, 3078 // Label 291: @4754 3079 GIM_Reject, 3080 // Label 285: @4755 3081 GIM_Reject, 3082 // Label 257: @4756 3083 GIM_Try, /*On fail goto*//*Label 292*/ 5946, 3084 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 3085 GIM_Try, /*On fail goto*//*Label 293*/ 4837, // Rule ID 22873 // 3086 GIM_CheckFeatures, GIFBS_HasTBM, 3087 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 3088 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID, 3089 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 3090 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD, 3091 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, 3092 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, 3093 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::GR32RegClassID, 3094 GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 1, 3095 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] 3096 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_XOR, 3097 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, 3098 // MIs[2] src 3099 GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, 3100 GIM_CheckConstantInt, /*MI*/2, /*Op*/2, -1, 3101 GIM_CheckIsSafeToFold, /*InsnID*/1, 3102 GIM_CheckIsSafeToFold, /*InsnID*/2, 3103 // (and:{ *:[i32] } (add:{ *:[i32] } GR32:{ *:[i32] }:$src, 1:{ *:[i32] }), (xor:{ *:[i32] } GR32:{ *:[i32] }:$src, -1:{ *:[i32] })) => (BLCIC32rr:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src) 3104 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLCIC32rr, 3105 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 3106 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src 3107 GIR_EraseFromParent, /*InsnID*/0, 3108 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 3109 // GIR_Coverage, 22873, 3110 GIR_Done, 3111 // Label 293: @4837 3112 GIM_Try, /*On fail goto*//*Label 294*/ 4912, // Rule ID 22885 // 3113 GIM_CheckFeatures, GIFBS_HasTBM, 3114 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 3115 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID, 3116 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 3117 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD, 3118 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, 3119 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, 3120 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::GR32RegClassID, 3121 GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1, 3122 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] 3123 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_XOR, 3124 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, 3125 // MIs[2] src 3126 GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, 3127 GIM_CheckConstantInt, /*MI*/2, /*Op*/2, -1, 3128 GIM_CheckIsSafeToFold, /*InsnID*/1, 3129 GIM_CheckIsSafeToFold, /*InsnID*/2, 3130 // (and:{ *:[i32] } (add:{ *:[i32] } GR32:{ *:[i32] }:$src, -1:{ *:[i32] }), (xor:{ *:[i32] } GR32:{ *:[i32] }:$src, -1:{ *:[i32] })) => (TZMSK32rr:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src) 3131 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::TZMSK32rr, 3132 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 3133 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src 3134 GIR_EraseFromParent, /*InsnID*/0, 3135 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 3136 // GIR_Coverage, 22885, 3137 GIR_Done, 3138 // Label 294: @4912 3139 GIM_Try, /*On fail goto*//*Label 295*/ 4987, // Rule ID 15930 // 3140 GIM_CheckFeatures, GIFBS_HasTBM, 3141 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 3142 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID, 3143 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 3144 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, 3145 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, 3146 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, 3147 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::GR32RegClassID, 3148 GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1, 3149 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] 3150 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ADD, 3151 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, 3152 // MIs[2] src 3153 GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, 3154 GIM_CheckConstantInt, /*MI*/2, /*Op*/2, 1, 3155 GIM_CheckIsSafeToFold, /*InsnID*/1, 3156 GIM_CheckIsSafeToFold, /*InsnID*/2, 3157 // (and:{ *:[i32] } (xor:{ *:[i32] } GR32:{ *:[i32] }:$src, -1:{ *:[i32] }), (add:{ *:[i32] } GR32:{ *:[i32] }:$src, 1:{ *:[i32] })) => (BLCIC32rr:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src) 3158 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLCIC32rr, 3159 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 3160 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src 3161 GIR_EraseFromParent, /*InsnID*/0, 3162 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 3163 // GIR_Coverage, 15930, 3164 GIR_Done, 3165 // Label 295: @4987 3166 GIM_Try, /*On fail goto*//*Label 296*/ 5062, // Rule ID 15942 // 3167 GIM_CheckFeatures, GIFBS_HasTBM, 3168 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 3169 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID, 3170 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 3171 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, 3172 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, 3173 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, 3174 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::GR32RegClassID, 3175 GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1, 3176 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] 3177 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ADD, 3178 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, 3179 // MIs[2] src 3180 GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, 3181 GIM_CheckConstantInt, /*MI*/2, /*Op*/2, -1, 3182 GIM_CheckIsSafeToFold, /*InsnID*/1, 3183 GIM_CheckIsSafeToFold, /*InsnID*/2, 3184 // (and:{ *:[i32] } (xor:{ *:[i32] } GR32:{ *:[i32] }:$src, -1:{ *:[i32] }), (add:{ *:[i32] } GR32:{ *:[i32] }:$src, -1:{ *:[i32] })) => (TZMSK32rr:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src) 3185 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::TZMSK32rr, 3186 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 3187 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src 3188 GIR_EraseFromParent, /*InsnID*/0, 3189 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 3190 // GIR_Coverage, 15942, 3191 GIR_Done, 3192 // Label 296: @5062 3193 GIM_Try, /*On fail goto*//*Label 297*/ 5116, // Rule ID 22855 // 3194 GIM_CheckFeatures, GIFBS_HasBMI, 3195 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID, 3196 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 3197 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD, 3198 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, 3199 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, 3200 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::GR32RegClassID, 3201 GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1, 3202 // MIs[0] src 3203 GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, 3204 GIM_CheckIsSafeToFold, /*InsnID*/1, 3205 // (and:{ *:[i32] } (add:{ *:[i32] } GR32:{ *:[i32] }:$src, -1:{ *:[i32] }), GR32:{ *:[i32] }:$src) => (BLSR32rr:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src) 3206 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLSR32rr, 3207 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 3208 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src 3209 GIR_EraseFromParent, /*InsnID*/0, 3210 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 3211 // GIR_Coverage, 22855, 3212 GIR_Done, 3213 // Label 297: @5116 3214 GIM_Try, /*On fail goto*//*Label 298*/ 5170, // Rule ID 22867 // 3215 GIM_CheckFeatures, GIFBS_HasTBM, 3216 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID, 3217 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 3218 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD, 3219 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, 3220 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, 3221 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::GR32RegClassID, 3222 GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 1, 3223 // MIs[0] src 3224 GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, 3225 GIM_CheckIsSafeToFold, /*InsnID*/1, 3226 // (and:{ *:[i32] } (add:{ *:[i32] } GR32:{ *:[i32] }:$src, 1:{ *:[i32] }), GR32:{ *:[i32] }:$src) => (BLCFILL32rr:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src) 3227 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLCFILL32rr, 3228 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 3229 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src 3230 GIR_EraseFromParent, /*InsnID*/0, 3231 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 3232 // GIR_Coverage, 22867, 3233 GIR_Done, 3234 // Label 298: @5170 3235 GIM_Try, /*On fail goto*//*Label 299*/ 5274, // Rule ID 23898 // 3236 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 3237 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID, 3238 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 3239 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ROTL, 3240 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, 3241 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s8, 3242 GIM_CheckConstantInt, /*MI*/1, /*Op*/1, -2, 3243 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/X86::GR8RegClassID, 3244 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::GR32RegClassID, 3245 GIM_CheckIsSafeToFold, /*InsnID*/1, 3246 // (and:{ *:[i32] } (rotl:{ *:[i32] } -2:{ *:[i32] }, GR8:{ *:[i8] }:$src2), GR32:{ *:[i32] }:$src1) => (BTR32rr:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src1, (INSERT_SUBREG:{ *:[i32] } (IMPLICIT_DEF:{ *:[i32] }), GR8:{ *:[i8] }:$src2, sub_8bit:{ *:[i32] })) 3247 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, 3248 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, 3249 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, 3250 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 3251 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 3252 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, 3253 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 3254 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, 3255 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // src2 3256 GIR_AddImm, /*InsnID*/1, /*Imm*/1, 3257 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID, 3258 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID, 3259 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, X86::GR8RegClassID, 3260 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BTR32rr, 3261 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 3262 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 3263 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 3264 GIR_EraseFromParent, /*InsnID*/0, 3265 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 3266 // GIR_Coverage, 23898, 3267 GIR_Done, 3268 // Label 299: @5274 3269 GIM_Try, /*On fail goto*//*Label 300*/ 5328, // Rule ID 22859 // 3270 GIM_CheckFeatures, GIFBS_HasBMI, 3271 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID, 3272 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 3273 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SUB, 3274 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, 3275 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, 3276 GIM_CheckConstantInt, /*MI*/1, /*Op*/1, 0, 3277 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/X86::GR32RegClassID, 3278 // MIs[0] src 3279 GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, 3280 GIM_CheckIsSafeToFold, /*InsnID*/1, 3281 // (and:{ *:[i32] } (sub:{ *:[i32] } 0:{ *:[i32] }, GR32:{ *:[i32] }:$src), GR32:{ *:[i32] }:$src) => (BLSI32rr:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src) 3282 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLSI32rr, 3283 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 3284 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src 3285 GIR_EraseFromParent, /*InsnID*/0, 3286 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 3287 // GIR_Coverage, 22859, 3288 GIR_Done, 3289 // Label 300: @5328 3290 GIM_Try, /*On fail goto*//*Label 301*/ 5382, // Rule ID 15906 // 3291 GIM_CheckFeatures, GIFBS_HasBMI, 3292 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 3293 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID, 3294 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR32RegClassID, 3295 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 3296 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD, 3297 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, 3298 // MIs[1] src 3299 GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/1, /*OtherMI*/0, /*OtherOpIdx*/1, 3300 GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1, 3301 GIM_CheckIsSafeToFold, /*InsnID*/1, 3302 // (and:{ *:[i32] } GR32:{ *:[i32] }:$src, (add:{ *:[i32] } GR32:{ *:[i32] }:$src, -1:{ *:[i32] })) => (BLSR32rr:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src) 3303 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLSR32rr, 3304 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 3305 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 3306 GIR_EraseFromParent, /*InsnID*/0, 3307 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 3308 // GIR_Coverage, 15906, 3309 GIR_Done, 3310 // Label 301: @5382 3311 GIM_Try, /*On fail goto*//*Label 302*/ 5436, // Rule ID 15924 // 3312 GIM_CheckFeatures, GIFBS_HasTBM, 3313 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 3314 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID, 3315 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR32RegClassID, 3316 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 3317 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD, 3318 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, 3319 // MIs[1] src 3320 GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/1, /*OtherMI*/0, /*OtherOpIdx*/1, 3321 GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 1, 3322 GIM_CheckIsSafeToFold, /*InsnID*/1, 3323 // (and:{ *:[i32] } GR32:{ *:[i32] }:$src, (add:{ *:[i32] } GR32:{ *:[i32] }:$src, 1:{ *:[i32] })) => (BLCFILL32rr:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src) 3324 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLCFILL32rr, 3325 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 3326 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 3327 GIR_EraseFromParent, /*InsnID*/0, 3328 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 3329 // GIR_Coverage, 15924, 3330 GIR_Done, 3331 // Label 302: @5436 3332 GIM_Try, /*On fail goto*//*Label 303*/ 5540, // Rule ID 20983 // 3333 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 3334 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID, 3335 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR32RegClassID, 3336 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 3337 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ROTL, 3338 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, 3339 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s8, 3340 GIM_CheckConstantInt, /*MI*/1, /*Op*/1, -2, 3341 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/X86::GR8RegClassID, 3342 GIM_CheckIsSafeToFold, /*InsnID*/1, 3343 // (and:{ *:[i32] } GR32:{ *:[i32] }:$src1, (rotl:{ *:[i32] } -2:{ *:[i32] }, GR8:{ *:[i8] }:$src2)) => (BTR32rr:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src1, (INSERT_SUBREG:{ *:[i32] } (IMPLICIT_DEF:{ *:[i32] }), GR8:{ *:[i8] }:$src2, sub_8bit:{ *:[i32] })) 3344 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, 3345 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, 3346 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, 3347 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 3348 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 3349 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, 3350 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 3351 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, 3352 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // src2 3353 GIR_AddImm, /*InsnID*/1, /*Imm*/1, 3354 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID, 3355 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID, 3356 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, X86::GR8RegClassID, 3357 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BTR32rr, 3358 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 3359 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 3360 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 3361 GIR_EraseFromParent, /*InsnID*/0, 3362 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 3363 // GIR_Coverage, 20983, 3364 GIR_Done, 3365 // Label 303: @5540 3366 GIM_Try, /*On fail goto*//*Label 304*/ 5594, // Rule ID 15910 // 3367 GIM_CheckFeatures, GIFBS_HasBMI, 3368 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 3369 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID, 3370 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR32RegClassID, 3371 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 3372 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SUB, 3373 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, 3374 GIM_CheckConstantInt, /*MI*/1, /*Op*/1, 0, 3375 // MIs[1] src 3376 GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/2, /*OtherMI*/0, /*OtherOpIdx*/1, 3377 GIM_CheckIsSafeToFold, /*InsnID*/1, 3378 // (and:{ *:[i32] } GR32:{ *:[i32] }:$src, (sub:{ *:[i32] } 0:{ *:[i32] }, GR32:{ *:[i32] }:$src)) => (BLSI32rr:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src) 3379 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLSI32rr, 3380 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 3381 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 3382 GIR_EraseFromParent, /*InsnID*/0, 3383 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 3384 // GIR_Coverage, 15910, 3385 GIR_Done, 3386 // Label 304: @5594 3387 GIM_Try, /*On fail goto*//*Label 305*/ 5651, // Rule ID 20873 // 3388 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 3389 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID, 3390 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR32RegClassID, 3391 GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 65535, 3392 // (and:{ *:[i32] } GR32:{ *:[i32] }:$src1, 65535:{ *:[i32] }) => (MOVZX32rr16:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i16] } GR32:{ *:[i32] }:$src1, sub_16bit:{ *:[i32] })) 3393 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16, 3394 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, 3395 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 3396 GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/4, // src1 3397 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, X86::GR16RegClassID, 3398 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, X86::GR32RegClassID, 3399 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::MOVZX32rr16, 3400 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 3401 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 3402 GIR_EraseFromParent, /*InsnID*/0, 3403 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 3404 // GIR_Coverage, 20873, 3405 GIR_Done, 3406 // Label 305: @5651 3407 GIM_Try, /*On fail goto*//*Label 306*/ 5708, // Rule ID 20874 // 3408 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 3409 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID, 3410 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR32RegClassID, 3411 GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 255, 3412 // (and:{ *:[i32] } GR32:{ *:[i32] }:$src1, 255:{ *:[i32] }) => (MOVZX32rr8:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i8] } GR32:{ *:[i32] }:$src1, sub_8bit:{ *:[i32] })) 3413 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s8, 3414 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, 3415 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 3416 GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/1, // src1 3417 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, X86::GR8RegClassID, 3418 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, X86::GR32RegClassID, 3419 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::MOVZX32rr8, 3420 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 3421 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 3422 GIR_EraseFromParent, /*InsnID*/0, 3423 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 3424 // GIR_Coverage, 20874, 3425 GIR_Done, 3426 // Label 306: @5708 3427 GIM_Try, /*On fail goto*//*Label 307*/ 5753, // Rule ID 15707 // 3428 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 3429 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID, 3430 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR32RegClassID, 3431 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 3432 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 3433 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_i32immSExt8, 3434 // MIs[1] Operand 1 3435 // No operand predicates 3436 GIM_CheckIsSafeToFold, /*InsnID*/1, 3437 // (and:{ *:[i32] } GR32:{ *:[i32] }:$src1, (imm:{ *:[i32] })<<P:Predicate_i32immSExt8>>:$src2) => (AND32ri8:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src1, (imm:{ *:[i32] })<<P:Predicate_i32immSExt8>>:$src2) 3438 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::AND32ri8, 3439 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 3440 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 3441 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // src2 3442 GIR_EraseFromParent, /*InsnID*/0, 3443 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 3444 // GIR_Coverage, 15707, 3445 GIR_Done, 3446 // Label 307: @5753 3447 GIM_Try, /*On fail goto*//*Label 308*/ 5795, // Rule ID 15705 // 3448 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 3449 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID, 3450 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR32RegClassID, 3451 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 3452 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 3453 // MIs[1] Operand 1 3454 // No operand predicates 3455 GIM_CheckIsSafeToFold, /*InsnID*/1, 3456 // (and:{ *:[i32] } GR32:{ *:[i32] }:$src1, (imm:{ *:[i32] }):$src2) => (AND32ri:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src1, (imm:{ *:[i32] }):$src2) 3457 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::AND32ri, 3458 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 3459 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 3460 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // src2 3461 GIR_EraseFromParent, /*InsnID*/0, 3462 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 3463 // GIR_Coverage, 15705, 3464 GIR_Done, 3465 // Label 308: @5795 3466 GIM_Try, /*On fail goto*//*Label 309*/ 5856, // Rule ID 16106 // 3467 GIM_CheckFeatures, GIFBS_HasBMI, 3468 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 3469 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID, 3470 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 3471 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, 3472 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, 3473 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, 3474 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::GR32RegClassID, 3475 GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1, 3476 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::GR32RegClassID, 3477 GIM_CheckIsSafeToFold, /*InsnID*/1, 3478 // (and:{ *:[i32] } (xor:{ *:[i32] } GR32:{ *:[i32] }:$src1, -1:{ *:[i32] }), GR32:{ *:[i32] }:$src2) => (ANDN32rr:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src1, GR32:{ *:[i32] }:$src2) 3479 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::ANDN32rr, 3480 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 3481 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1 3482 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src2 3483 GIR_EraseFromParent, /*InsnID*/0, 3484 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 3485 // GIR_Coverage, 16106, 3486 GIR_Done, 3487 // Label 309: @5856 3488 GIM_Try, /*On fail goto*//*Label 310*/ 5917, // Rule ID 22971 // 3489 GIM_CheckFeatures, GIFBS_HasBMI, 3490 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 3491 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID, 3492 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR32RegClassID, 3493 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 3494 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, 3495 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, 3496 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, 3497 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::GR32RegClassID, 3498 GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1, 3499 GIM_CheckIsSafeToFold, /*InsnID*/1, 3500 // (and:{ *:[i32] } GR32:{ *:[i32] }:$src2, (xor:{ *:[i32] } GR32:{ *:[i32] }:$src1, -1:{ *:[i32] })) => (ANDN32rr:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src1, GR32:{ *:[i32] }:$src2) 3501 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::ANDN32rr, 3502 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 3503 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1 3504 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src2 3505 GIR_EraseFromParent, /*InsnID*/0, 3506 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 3507 // GIR_Coverage, 22971, 3508 GIR_Done, 3509 // Label 310: @5917 3510 GIM_Try, /*On fail goto*//*Label 311*/ 5945, // Rule ID 15697 // 3511 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 3512 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID, 3513 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR32RegClassID, 3514 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::GR32RegClassID, 3515 // (and:{ *:[i32] } GR32:{ *:[i32] }:$src1, GR32:{ *:[i32] }:$src2) => (AND32rr:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src1, GR32:{ *:[i32] }:$src2) 3516 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::AND32rr, 3517 GIR_AddImplicitDef, /*InsnID*/0, X86::EFLAGS, 3518 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 3519 // GIR_Coverage, 15697, 3520 GIR_Done, 3521 // Label 311: @5945 3522 GIM_Reject, 3523 // Label 292: @5946 3524 GIM_Reject, 3525 // Label 258: @5947 3526 GIM_Try, /*On fail goto*//*Label 312*/ 7026, 3527 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 3528 GIM_Try, /*On fail goto*//*Label 313*/ 6028, // Rule ID 22874 // 3529 GIM_CheckFeatures, GIFBS_HasTBM, 3530 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 3531 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID, 3532 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 3533 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD, 3534 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, 3535 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, 3536 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::GR64RegClassID, 3537 GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 1, 3538 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] 3539 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_XOR, 3540 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, 3541 // MIs[2] src 3542 GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, 3543 GIM_CheckConstantInt, /*MI*/2, /*Op*/2, -1, 3544 GIM_CheckIsSafeToFold, /*InsnID*/1, 3545 GIM_CheckIsSafeToFold, /*InsnID*/2, 3546 // (and:{ *:[i64] } (add:{ *:[i64] } GR64:{ *:[i64] }:$src, 1:{ *:[i64] }), (xor:{ *:[i64] } GR64:{ *:[i64] }:$src, -1:{ *:[i64] })) => (BLCIC64rr:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src) 3547 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLCIC64rr, 3548 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 3549 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src 3550 GIR_EraseFromParent, /*InsnID*/0, 3551 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 3552 // GIR_Coverage, 22874, 3553 GIR_Done, 3554 // Label 313: @6028 3555 GIM_Try, /*On fail goto*//*Label 314*/ 6103, // Rule ID 22886 // 3556 GIM_CheckFeatures, GIFBS_HasTBM, 3557 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 3558 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID, 3559 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 3560 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD, 3561 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, 3562 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, 3563 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::GR64RegClassID, 3564 GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1, 3565 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] 3566 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_XOR, 3567 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, 3568 // MIs[2] src 3569 GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, 3570 GIM_CheckConstantInt, /*MI*/2, /*Op*/2, -1, 3571 GIM_CheckIsSafeToFold, /*InsnID*/1, 3572 GIM_CheckIsSafeToFold, /*InsnID*/2, 3573 // (and:{ *:[i64] } (add:{ *:[i64] } GR64:{ *:[i64] }:$src, -1:{ *:[i64] }), (xor:{ *:[i64] } GR64:{ *:[i64] }:$src, -1:{ *:[i64] })) => (TZMSK64rr:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src) 3574 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::TZMSK64rr, 3575 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 3576 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src 3577 GIR_EraseFromParent, /*InsnID*/0, 3578 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 3579 // GIR_Coverage, 22886, 3580 GIR_Done, 3581 // Label 314: @6103 3582 GIM_Try, /*On fail goto*//*Label 315*/ 6178, // Rule ID 15931 // 3583 GIM_CheckFeatures, GIFBS_HasTBM, 3584 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 3585 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID, 3586 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 3587 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, 3588 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, 3589 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, 3590 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::GR64RegClassID, 3591 GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1, 3592 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] 3593 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ADD, 3594 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, 3595 // MIs[2] src 3596 GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, 3597 GIM_CheckConstantInt, /*MI*/2, /*Op*/2, 1, 3598 GIM_CheckIsSafeToFold, /*InsnID*/1, 3599 GIM_CheckIsSafeToFold, /*InsnID*/2, 3600 // (and:{ *:[i64] } (xor:{ *:[i64] } GR64:{ *:[i64] }:$src, -1:{ *:[i64] }), (add:{ *:[i64] } GR64:{ *:[i64] }:$src, 1:{ *:[i64] })) => (BLCIC64rr:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src) 3601 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLCIC64rr, 3602 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 3603 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src 3604 GIR_EraseFromParent, /*InsnID*/0, 3605 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 3606 // GIR_Coverage, 15931, 3607 GIR_Done, 3608 // Label 315: @6178 3609 GIM_Try, /*On fail goto*//*Label 316*/ 6253, // Rule ID 15943 // 3610 GIM_CheckFeatures, GIFBS_HasTBM, 3611 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 3612 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID, 3613 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 3614 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, 3615 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, 3616 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, 3617 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::GR64RegClassID, 3618 GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1, 3619 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] 3620 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ADD, 3621 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, 3622 // MIs[2] src 3623 GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, 3624 GIM_CheckConstantInt, /*MI*/2, /*Op*/2, -1, 3625 GIM_CheckIsSafeToFold, /*InsnID*/1, 3626 GIM_CheckIsSafeToFold, /*InsnID*/2, 3627 // (and:{ *:[i64] } (xor:{ *:[i64] } GR64:{ *:[i64] }:$src, -1:{ *:[i64] }), (add:{ *:[i64] } GR64:{ *:[i64] }:$src, -1:{ *:[i64] })) => (TZMSK64rr:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src) 3628 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::TZMSK64rr, 3629 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 3630 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src 3631 GIR_EraseFromParent, /*InsnID*/0, 3632 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 3633 // GIR_Coverage, 15943, 3634 GIR_Done, 3635 // Label 316: @6253 3636 GIM_Try, /*On fail goto*//*Label 317*/ 6307, // Rule ID 22856 // 3637 GIM_CheckFeatures, GIFBS_HasBMI, 3638 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID, 3639 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 3640 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD, 3641 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, 3642 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, 3643 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::GR64RegClassID, 3644 GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1, 3645 // MIs[0] src 3646 GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, 3647 GIM_CheckIsSafeToFold, /*InsnID*/1, 3648 // (and:{ *:[i64] } (add:{ *:[i64] } GR64:{ *:[i64] }:$src, -1:{ *:[i64] }), GR64:{ *:[i64] }:$src) => (BLSR64rr:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src) 3649 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLSR64rr, 3650 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 3651 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src 3652 GIR_EraseFromParent, /*InsnID*/0, 3653 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 3654 // GIR_Coverage, 22856, 3655 GIR_Done, 3656 // Label 317: @6307 3657 GIM_Try, /*On fail goto*//*Label 318*/ 6361, // Rule ID 22868 // 3658 GIM_CheckFeatures, GIFBS_HasTBM, 3659 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID, 3660 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 3661 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD, 3662 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, 3663 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, 3664 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::GR64RegClassID, 3665 GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 1, 3666 // MIs[0] src 3667 GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, 3668 GIM_CheckIsSafeToFold, /*InsnID*/1, 3669 // (and:{ *:[i64] } (add:{ *:[i64] } GR64:{ *:[i64] }:$src, 1:{ *:[i64] }), GR64:{ *:[i64] }:$src) => (BLCFILL64rr:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src) 3670 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLCFILL64rr, 3671 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 3672 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src 3673 GIR_EraseFromParent, /*InsnID*/0, 3674 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 3675 // GIR_Coverage, 22868, 3676 GIR_Done, 3677 // Label 318: @6361 3678 GIM_Try, /*On fail goto*//*Label 319*/ 6465, // Rule ID 23904 // 3679 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 3680 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID, 3681 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 3682 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ROTL, 3683 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, 3684 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s8, 3685 GIM_CheckConstantInt, /*MI*/1, /*Op*/1, -2, 3686 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/X86::GR8RegClassID, 3687 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::GR64RegClassID, 3688 GIM_CheckIsSafeToFold, /*InsnID*/1, 3689 // (and:{ *:[i64] } (rotl:{ *:[i64] } -2:{ *:[i64] }, GR8:{ *:[i8] }:$src2), GR64:{ *:[i64] }:$src1) => (BTR64rr:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src1, (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), GR8:{ *:[i8] }:$src2, sub_8bit:{ *:[i32] })) 3690 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, 3691 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, 3692 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, 3693 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 3694 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 3695 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, 3696 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 3697 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, 3698 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // src2 3699 GIR_AddImm, /*InsnID*/1, /*Imm*/1, 3700 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, X86::GR64_with_sub_8bitRegClassID, 3701 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, X86::GR64_with_sub_8bitRegClassID, 3702 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, X86::GR8RegClassID, 3703 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BTR64rr, 3704 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 3705 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 3706 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 3707 GIR_EraseFromParent, /*InsnID*/0, 3708 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 3709 // GIR_Coverage, 23904, 3710 GIR_Done, 3711 // Label 319: @6465 3712 GIM_Try, /*On fail goto*//*Label 320*/ 6519, // Rule ID 22860 // 3713 GIM_CheckFeatures, GIFBS_HasBMI, 3714 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID, 3715 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 3716 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SUB, 3717 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, 3718 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, 3719 GIM_CheckConstantInt, /*MI*/1, /*Op*/1, 0, 3720 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/X86::GR64RegClassID, 3721 // MIs[0] src 3722 GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, 3723 GIM_CheckIsSafeToFold, /*InsnID*/1, 3724 // (and:{ *:[i64] } (sub:{ *:[i64] } 0:{ *:[i64] }, GR64:{ *:[i64] }:$src), GR64:{ *:[i64] }:$src) => (BLSI64rr:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src) 3725 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLSI64rr, 3726 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 3727 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src 3728 GIR_EraseFromParent, /*InsnID*/0, 3729 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 3730 // GIR_Coverage, 22860, 3731 GIR_Done, 3732 // Label 320: @6519 3733 GIM_Try, /*On fail goto*//*Label 321*/ 6573, // Rule ID 15907 // 3734 GIM_CheckFeatures, GIFBS_HasBMI, 3735 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 3736 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID, 3737 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR64RegClassID, 3738 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 3739 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD, 3740 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, 3741 // MIs[1] src 3742 GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/1, /*OtherMI*/0, /*OtherOpIdx*/1, 3743 GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1, 3744 GIM_CheckIsSafeToFold, /*InsnID*/1, 3745 // (and:{ *:[i64] } GR64:{ *:[i64] }:$src, (add:{ *:[i64] } GR64:{ *:[i64] }:$src, -1:{ *:[i64] })) => (BLSR64rr:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src) 3746 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLSR64rr, 3747 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 3748 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 3749 GIR_EraseFromParent, /*InsnID*/0, 3750 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 3751 // GIR_Coverage, 15907, 3752 GIR_Done, 3753 // Label 321: @6573 3754 GIM_Try, /*On fail goto*//*Label 322*/ 6627, // Rule ID 15925 // 3755 GIM_CheckFeatures, GIFBS_HasTBM, 3756 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 3757 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID, 3758 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR64RegClassID, 3759 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 3760 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD, 3761 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, 3762 // MIs[1] src 3763 GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/1, /*OtherMI*/0, /*OtherOpIdx*/1, 3764 GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 1, 3765 GIM_CheckIsSafeToFold, /*InsnID*/1, 3766 // (and:{ *:[i64] } GR64:{ *:[i64] }:$src, (add:{ *:[i64] } GR64:{ *:[i64] }:$src, 1:{ *:[i64] })) => (BLCFILL64rr:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src) 3767 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLCFILL64rr, 3768 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 3769 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 3770 GIR_EraseFromParent, /*InsnID*/0, 3771 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 3772 // GIR_Coverage, 15925, 3773 GIR_Done, 3774 // Label 322: @6627 3775 GIM_Try, /*On fail goto*//*Label 323*/ 6731, // Rule ID 20989 // 3776 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 3777 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID, 3778 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR64RegClassID, 3779 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 3780 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ROTL, 3781 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, 3782 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s8, 3783 GIM_CheckConstantInt, /*MI*/1, /*Op*/1, -2, 3784 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/X86::GR8RegClassID, 3785 GIM_CheckIsSafeToFold, /*InsnID*/1, 3786 // (and:{ *:[i64] } GR64:{ *:[i64] }:$src1, (rotl:{ *:[i64] } -2:{ *:[i64] }, GR8:{ *:[i8] }:$src2)) => (BTR64rr:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src1, (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), GR8:{ *:[i8] }:$src2, sub_8bit:{ *:[i32] })) 3787 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, 3788 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, 3789 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, 3790 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 3791 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 3792 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, 3793 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 3794 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, 3795 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // src2 3796 GIR_AddImm, /*InsnID*/1, /*Imm*/1, 3797 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, X86::GR64_with_sub_8bitRegClassID, 3798 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, X86::GR64_with_sub_8bitRegClassID, 3799 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, X86::GR8RegClassID, 3800 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BTR64rr, 3801 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 3802 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 3803 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 3804 GIR_EraseFromParent, /*InsnID*/0, 3805 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 3806 // GIR_Coverage, 20989, 3807 GIR_Done, 3808 // Label 323: @6731 3809 GIM_Try, /*On fail goto*//*Label 324*/ 6785, // Rule ID 15911 // 3810 GIM_CheckFeatures, GIFBS_HasBMI, 3811 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 3812 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID, 3813 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR64RegClassID, 3814 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 3815 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SUB, 3816 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, 3817 GIM_CheckConstantInt, /*MI*/1, /*Op*/1, 0, 3818 // MIs[1] src 3819 GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/2, /*OtherMI*/0, /*OtherOpIdx*/1, 3820 GIM_CheckIsSafeToFold, /*InsnID*/1, 3821 // (and:{ *:[i64] } GR64:{ *:[i64] }:$src, (sub:{ *:[i64] } 0:{ *:[i64] }, GR64:{ *:[i64] }:$src)) => (BLSI64rr:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src) 3822 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLSI64rr, 3823 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 3824 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 3825 GIR_EraseFromParent, /*InsnID*/0, 3826 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 3827 // GIR_Coverage, 15911, 3828 GIR_Done, 3829 // Label 324: @6785 3830 GIM_Try, /*On fail goto*//*Label 325*/ 6830, // Rule ID 15708 // 3831 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 3832 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID, 3833 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR64RegClassID, 3834 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 3835 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 3836 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_i64immSExt8, 3837 // MIs[1] Operand 1 3838 // No operand predicates 3839 GIM_CheckIsSafeToFold, /*InsnID*/1, 3840 // (and:{ *:[i64] } GR64:{ *:[i64] }:$src1, (imm:{ *:[i64] })<<P:Predicate_i64immSExt8>>:$src2) => (AND64ri8:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src1, (imm:{ *:[i64] })<<P:Predicate_i64immSExt8>>:$src2) 3841 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::AND64ri8, 3842 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 3843 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 3844 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // src2 3845 GIR_EraseFromParent, /*InsnID*/0, 3846 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 3847 // GIR_Coverage, 15708, 3848 GIR_Done, 3849 // Label 325: @6830 3850 GIM_Try, /*On fail goto*//*Label 326*/ 6875, // Rule ID 15709 // 3851 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 3852 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID, 3853 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR64RegClassID, 3854 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 3855 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 3856 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_i64immSExt32, 3857 // MIs[1] Operand 1 3858 // No operand predicates 3859 GIM_CheckIsSafeToFold, /*InsnID*/1, 3860 // (and:{ *:[i64] } GR64:{ *:[i64] }:$src1, (imm:{ *:[i64] })<<P:Predicate_i64immSExt32>>:$src2) => (AND64ri32:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src1, (imm:{ *:[i64] })<<P:Predicate_i64immSExt32>>:$src2) 3861 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::AND64ri32, 3862 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 3863 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 3864 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // src2 3865 GIR_EraseFromParent, /*InsnID*/0, 3866 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 3867 // GIR_Coverage, 15709, 3868 GIR_Done, 3869 // Label 326: @6875 3870 GIM_Try, /*On fail goto*//*Label 327*/ 6936, // Rule ID 16107 // 3871 GIM_CheckFeatures, GIFBS_HasBMI, 3872 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 3873 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID, 3874 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 3875 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, 3876 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, 3877 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, 3878 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::GR64RegClassID, 3879 GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1, 3880 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::GR64RegClassID, 3881 GIM_CheckIsSafeToFold, /*InsnID*/1, 3882 // (and:{ *:[i64] } (xor:{ *:[i64] } GR64:{ *:[i64] }:$src1, -1:{ *:[i64] }), GR64:{ *:[i64] }:$src2) => (ANDN64rr:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src1, GR64:{ *:[i64] }:$src2) 3883 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::ANDN64rr, 3884 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 3885 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1 3886 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src2 3887 GIR_EraseFromParent, /*InsnID*/0, 3888 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 3889 // GIR_Coverage, 16107, 3890 GIR_Done, 3891 // Label 327: @6936 3892 GIM_Try, /*On fail goto*//*Label 328*/ 6997, // Rule ID 22972 // 3893 GIM_CheckFeatures, GIFBS_HasBMI, 3894 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 3895 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID, 3896 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR64RegClassID, 3897 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 3898 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, 3899 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, 3900 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, 3901 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::GR64RegClassID, 3902 GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1, 3903 GIM_CheckIsSafeToFold, /*InsnID*/1, 3904 // (and:{ *:[i64] } GR64:{ *:[i64] }:$src2, (xor:{ *:[i64] } GR64:{ *:[i64] }:$src1, -1:{ *:[i64] })) => (ANDN64rr:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src1, GR64:{ *:[i64] }:$src2) 3905 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::ANDN64rr, 3906 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 3907 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1 3908 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src2 3909 GIR_EraseFromParent, /*InsnID*/0, 3910 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 3911 // GIR_Coverage, 22972, 3912 GIR_Done, 3913 // Label 328: @6997 3914 GIM_Try, /*On fail goto*//*Label 329*/ 7025, // Rule ID 15698 // 3915 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 3916 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID, 3917 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR64RegClassID, 3918 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::GR64RegClassID, 3919 // (and:{ *:[i64] } GR64:{ *:[i64] }:$src1, GR64:{ *:[i64] }:$src2) => (AND64rr:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src1, GR64:{ *:[i64] }:$src2) 3920 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::AND64rr, 3921 GIR_AddImplicitDef, /*InsnID*/0, X86::EFLAGS, 3922 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 3923 // GIR_Coverage, 15698, 3924 GIR_Done, 3925 // Label 329: @7025 3926 GIM_Reject, 3927 // Label 312: @7026 3928 GIM_Reject, 3929 // Label 259: @7027 3930 GIM_Try, /*On fail goto*//*Label 330*/ 7340, 3931 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s1, 3932 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s1, 3933 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VK2RegClassID, 3934 GIM_Try, /*On fail goto*//*Label 331*/ 7150, // Rule ID 17928 // 3935 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 3936 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, 3937 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s1, 3938 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s1, 3939 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::VK2RegClassID, 3940 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] 3941 GIM_CheckOpcodeIsEither, /*MI*/2, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, 3942 GIM_CheckIsBuildVectorAllOnes, /*MI*/2, 3943 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VK2RegClassID, 3944 GIM_CheckIsSafeToFold, /*InsnID*/1, 3945 GIM_CheckIsSafeToFold, /*InsnID*/2, 3946 // (and:{ *:[v2i1] } (xor:{ *:[v2i1] } VK2:{ *:[v2i1] }:$src1, immAllOnesV:{ *:[v2i1] }), VK2:{ *:[v2i1] }:$src2) => (COPY_TO_REGCLASS:{ *:[v2i1] } (KANDNWrr:{ *:[v16i1] } (COPY_TO_REGCLASS:{ *:[v16i1] } VK2:{ *:[v2i1] }:$src1, VK16:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v16i1] } VK2:{ *:[v2i1] }:$src2, VK16:{ *:[i32] })), VK2:{ *:[i32] }) 3947 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s1, 3948 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s1, 3949 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s1, 3950 GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::COPY, 3951 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, 3952 GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // src2 3953 GIR_ConstrainSelectedInstOperands, /*InsnID*/3, 3954 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY, 3955 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 3956 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, // src1 3957 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 3958 GIR_BuildMI, /*InsnID*/1, /*Opcode*/X86::KANDNWrr, 3959 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 3960 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, 3961 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/2, /*TempRegFlags*/0, 3962 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 3963 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 3964 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 3965 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 3966 GIR_EraseFromParent, /*InsnID*/0, 3967 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, X86::VK2RegClassID, 3968 // GIR_Coverage, 17928, 3969 GIR_Done, 3970 // Label 331: @7150 3971 GIM_Try, /*On fail goto*//*Label 332*/ 7259, // Rule ID 23234 // 3972 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VK2RegClassID, 3973 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 3974 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, 3975 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s1, 3976 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s1, 3977 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::VK2RegClassID, 3978 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] 3979 GIM_CheckOpcodeIsEither, /*MI*/2, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, 3980 GIM_CheckIsBuildVectorAllOnes, /*MI*/2, 3981 GIM_CheckIsSafeToFold, /*InsnID*/1, 3982 GIM_CheckIsSafeToFold, /*InsnID*/2, 3983 // (and:{ *:[v2i1] } VK2:{ *:[v2i1] }:$src2, (xor:{ *:[v2i1] } VK2:{ *:[v2i1] }:$src1, immAllOnesV:{ *:[v2i1] })) => (COPY_TO_REGCLASS:{ *:[v2i1] } (KANDNWrr:{ *:[v16i1] } (COPY_TO_REGCLASS:{ *:[v16i1] } VK2:{ *:[v2i1] }:$src1, VK16:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v16i1] } VK2:{ *:[v2i1] }:$src2, VK16:{ *:[i32] })), VK2:{ *:[i32] }) 3984 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s1, 3985 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s1, 3986 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s1, 3987 GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::COPY, 3988 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, 3989 GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // src2 3990 GIR_ConstrainSelectedInstOperands, /*InsnID*/3, 3991 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY, 3992 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 3993 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, // src1 3994 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 3995 GIR_BuildMI, /*InsnID*/1, /*Opcode*/X86::KANDNWrr, 3996 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 3997 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, 3998 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/2, /*TempRegFlags*/0, 3999 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 4000 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 4001 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 4002 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 4003 GIR_EraseFromParent, /*InsnID*/0, 4004 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, X86::VK2RegClassID, 4005 // GIR_Coverage, 23234, 4006 GIR_Done, 4007 // Label 332: @7259 4008 GIM_Try, /*On fail goto*//*Label 333*/ 7339, // Rule ID 17924 // 4009 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VK2RegClassID, 4010 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VK2RegClassID, 4011 // (and:{ *:[v2i1] } VK2:{ *:[v2i1] }:$src1, VK2:{ *:[v2i1] }:$src2) => (COPY_TO_REGCLASS:{ *:[v2i1] } (KANDWrr:{ *:[v16i1] } (COPY_TO_REGCLASS:{ *:[v16i1] } VK2:{ *:[v2i1] }:$src1, VK16:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v16i1] } VK2:{ *:[v2i1] }:$src2, VK16:{ *:[i32] })), VK2:{ *:[i32] }) 4012 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s1, 4013 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s1, 4014 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s1, 4015 GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::COPY, 4016 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, 4017 GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // src2 4018 GIR_ConstrainSelectedInstOperands, /*InsnID*/3, 4019 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY, 4020 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 4021 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src1 4022 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 4023 GIR_BuildMI, /*InsnID*/1, /*Opcode*/X86::KANDWrr, 4024 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 4025 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, 4026 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/2, /*TempRegFlags*/0, 4027 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 4028 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 4029 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 4030 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 4031 GIR_EraseFromParent, /*InsnID*/0, 4032 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, X86::VK2RegClassID, 4033 // GIR_Coverage, 17924, 4034 GIR_Done, 4035 // Label 333: @7339 4036 GIM_Reject, 4037 // Label 330: @7340 4038 GIM_Reject, 4039 // Label 260: @7341 4040 GIM_Try, /*On fail goto*//*Label 334*/ 7421, 4041 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, 4042 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 4043 GIM_Try, /*On fail goto*//*Label 335*/ 7374, // Rule ID 1842 // 4044 GIM_CheckFeatures, GIFBS_HasAVX_NoVLX, 4045 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 4046 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 4047 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 4048 // (and:{ *:[v2i64] } VR128:{ *:[v2i64] }:$src1, VR128:{ *:[v2i64] }:$src2) => (VPANDrr:{ *:[v2i64] } VR128:{ *:[v2i64] }:$src1, VR128:{ *:[v2i64] }:$src2) 4049 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPANDrr, 4050 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4051 // GIR_Coverage, 1842, 4052 GIR_Done, 4053 // Label 335: @7374 4054 GIM_Try, /*On fail goto*//*Label 336*/ 7397, // Rule ID 1844 // 4055 GIM_CheckFeatures, GIFBS_UseSSE2, 4056 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 4057 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 4058 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 4059 // (and:{ *:[v2i64] } VR128:{ *:[v2i64] }:$src1, VR128:{ *:[v2i64] }:$src2) => (PANDrr:{ *:[v2i64] } VR128:{ *:[v2i64] }:$src1, VR128:{ *:[v2i64] }:$src2) 4060 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::PANDrr, 4061 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4062 // GIR_Coverage, 1844, 4063 GIR_Done, 4064 // Label 336: @7397 4065 GIM_Try, /*On fail goto*//*Label 337*/ 7420, // Rule ID 5343 // 4066 GIM_CheckFeatures, GIFBS_HasAVX512_HasVLX, 4067 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID, 4068 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID, 4069 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128XRegClassID, 4070 // (and:{ *:[v2i64] } VR128X:{ *:[v2i64] }:$src1, VR128X:{ *:[v2i64] }:$src2) => (VPANDQZ128rr:{ *:[v2i64] } VR128X:{ *:[v2i64] }:$src1, VR128X:{ *:[v2i64] }:$src2) 4071 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPANDQZ128rr, 4072 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4073 // GIR_Coverage, 5343, 4074 GIR_Done, 4075 // Label 337: @7420 4076 GIM_Reject, 4077 // Label 334: @7421 4078 GIM_Reject, 4079 // Label 261: @7422 4080 GIM_Try, /*On fail goto*//*Label 338*/ 7735, 4081 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s1, 4082 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s1, 4083 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VK4RegClassID, 4084 GIM_Try, /*On fail goto*//*Label 339*/ 7545, // Rule ID 17929 // 4085 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 4086 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, 4087 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s1, 4088 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s1, 4089 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::VK4RegClassID, 4090 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] 4091 GIM_CheckOpcodeIsEither, /*MI*/2, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, 4092 GIM_CheckIsBuildVectorAllOnes, /*MI*/2, 4093 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VK4RegClassID, 4094 GIM_CheckIsSafeToFold, /*InsnID*/1, 4095 GIM_CheckIsSafeToFold, /*InsnID*/2, 4096 // (and:{ *:[v4i1] } (xor:{ *:[v4i1] } VK4:{ *:[v4i1] }:$src1, immAllOnesV:{ *:[v4i1] }), VK4:{ *:[v4i1] }:$src2) => (COPY_TO_REGCLASS:{ *:[v4i1] } (KANDNWrr:{ *:[v16i1] } (COPY_TO_REGCLASS:{ *:[v16i1] } VK4:{ *:[v4i1] }:$src1, VK16:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v16i1] } VK4:{ *:[v4i1] }:$src2, VK16:{ *:[i32] })), VK4:{ *:[i32] }) 4097 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s1, 4098 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s1, 4099 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s1, 4100 GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::COPY, 4101 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, 4102 GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // src2 4103 GIR_ConstrainSelectedInstOperands, /*InsnID*/3, 4104 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY, 4105 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 4106 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, // src1 4107 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 4108 GIR_BuildMI, /*InsnID*/1, /*Opcode*/X86::KANDNWrr, 4109 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 4110 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, 4111 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/2, /*TempRegFlags*/0, 4112 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 4113 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 4114 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 4115 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 4116 GIR_EraseFromParent, /*InsnID*/0, 4117 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, X86::VK4RegClassID, 4118 // GIR_Coverage, 17929, 4119 GIR_Done, 4120 // Label 339: @7545 4121 GIM_Try, /*On fail goto*//*Label 340*/ 7654, // Rule ID 23235 // 4122 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VK4RegClassID, 4123 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 4124 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, 4125 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s1, 4126 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s1, 4127 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::VK4RegClassID, 4128 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] 4129 GIM_CheckOpcodeIsEither, /*MI*/2, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, 4130 GIM_CheckIsBuildVectorAllOnes, /*MI*/2, 4131 GIM_CheckIsSafeToFold, /*InsnID*/1, 4132 GIM_CheckIsSafeToFold, /*InsnID*/2, 4133 // (and:{ *:[v4i1] } VK4:{ *:[v4i1] }:$src2, (xor:{ *:[v4i1] } VK4:{ *:[v4i1] }:$src1, immAllOnesV:{ *:[v4i1] })) => (COPY_TO_REGCLASS:{ *:[v4i1] } (KANDNWrr:{ *:[v16i1] } (COPY_TO_REGCLASS:{ *:[v16i1] } VK4:{ *:[v4i1] }:$src1, VK16:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v16i1] } VK4:{ *:[v4i1] }:$src2, VK16:{ *:[i32] })), VK4:{ *:[i32] }) 4134 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s1, 4135 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s1, 4136 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s1, 4137 GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::COPY, 4138 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, 4139 GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // src2 4140 GIR_ConstrainSelectedInstOperands, /*InsnID*/3, 4141 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY, 4142 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 4143 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, // src1 4144 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 4145 GIR_BuildMI, /*InsnID*/1, /*Opcode*/X86::KANDNWrr, 4146 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 4147 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, 4148 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/2, /*TempRegFlags*/0, 4149 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 4150 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 4151 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 4152 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 4153 GIR_EraseFromParent, /*InsnID*/0, 4154 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, X86::VK4RegClassID, 4155 // GIR_Coverage, 23235, 4156 GIR_Done, 4157 // Label 340: @7654 4158 GIM_Try, /*On fail goto*//*Label 341*/ 7734, // Rule ID 17925 // 4159 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VK4RegClassID, 4160 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VK4RegClassID, 4161 // (and:{ *:[v4i1] } VK4:{ *:[v4i1] }:$src1, VK4:{ *:[v4i1] }:$src2) => (COPY_TO_REGCLASS:{ *:[v4i1] } (KANDWrr:{ *:[v16i1] } (COPY_TO_REGCLASS:{ *:[v16i1] } VK4:{ *:[v4i1] }:$src1, VK16:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v16i1] } VK4:{ *:[v4i1] }:$src2, VK16:{ *:[i32] })), VK4:{ *:[i32] }) 4162 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s1, 4163 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s1, 4164 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s1, 4165 GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::COPY, 4166 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, 4167 GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // src2 4168 GIR_ConstrainSelectedInstOperands, /*InsnID*/3, 4169 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY, 4170 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 4171 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src1 4172 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 4173 GIR_BuildMI, /*InsnID*/1, /*Opcode*/X86::KANDWrr, 4174 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 4175 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, 4176 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/2, /*TempRegFlags*/0, 4177 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 4178 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 4179 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 4180 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 4181 GIR_EraseFromParent, /*InsnID*/0, 4182 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, X86::VK4RegClassID, 4183 // GIR_Coverage, 17925, 4184 GIR_Done, 4185 // Label 341: @7734 4186 GIM_Reject, 4187 // Label 338: @7735 4188 GIM_Reject, 4189 // Label 262: @7736 4190 GIM_Try, /*On fail goto*//*Label 342*/ 7816, 4191 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, 4192 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 4193 GIM_Try, /*On fail goto*//*Label 343*/ 7769, // Rule ID 5370 // 4194 GIM_CheckFeatures, GIFBS_HasAVX512_HasVLX, 4195 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID, 4196 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID, 4197 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128XRegClassID, 4198 // (and:{ *:[v4i32] } VR128X:{ *:[v4i32] }:$src1, VR128X:{ *:[v4i32] }:$src2) => (VPANDDZ128rr:{ *:[v4i32] } VR128X:{ *:[v4i32] }:$src1, VR128X:{ *:[v4i32] }:$src2) 4199 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPANDDZ128rr, 4200 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4201 // GIR_Coverage, 5370, 4202 GIR_Done, 4203 // Label 343: @7769 4204 GIM_Try, /*On fail goto*//*Label 344*/ 7792, // Rule ID 16595 // 4205 GIM_CheckFeatures, GIFBS_HasAVX_NoVLX, 4206 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 4207 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 4208 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 4209 // (and:{ *:[v4i32] } VR128:{ *:[v4i32] }:$src1, VR128:{ *:[v4i32] }:$src2) => (VPANDrr:{ *:[v4i32] } VR128:{ *:[v4i32] }:$src1, VR128:{ *:[v4i32] }:$src2) 4210 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPANDrr, 4211 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4212 // GIR_Coverage, 16595, 4213 GIR_Done, 4214 // Label 344: @7792 4215 GIM_Try, /*On fail goto*//*Label 345*/ 7815, // Rule ID 16619 // 4216 GIM_CheckFeatures, GIFBS_UseSSE2, 4217 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 4218 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 4219 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 4220 // (and:{ *:[v4i32] } VR128:{ *:[v4i32] }:$src1, VR128:{ *:[v4i32] }:$src2) => (PANDrr:{ *:[v4i32] } VR128:{ *:[v4i32] }:$src1, VR128:{ *:[v4i32] }:$src2) 4221 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::PANDrr, 4222 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4223 // GIR_Coverage, 16619, 4224 GIR_Done, 4225 // Label 345: @7815 4226 GIM_Reject, 4227 // Label 342: @7816 4228 GIM_Reject, 4229 // Label 263: @7817 4230 GIM_Try, /*On fail goto*//*Label 346*/ 7897, 4231 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s64, 4232 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s64, 4233 GIM_Try, /*On fail goto*//*Label 347*/ 7850, // Rule ID 1846 // 4234 GIM_CheckFeatures, GIFBS_HasAVX2_NoVLX, 4235 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID, 4236 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256RegClassID, 4237 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256RegClassID, 4238 // (and:{ *:[v4i64] } VR256:{ *:[v4i64] }:$src1, VR256:{ *:[v4i64] }:$src2) => (VPANDYrr:{ *:[v4i64] } VR256:{ *:[v4i64] }:$src1, VR256:{ *:[v4i64] }:$src2) 4239 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPANDYrr, 4240 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4241 // GIR_Coverage, 1846, 4242 GIR_Done, 4243 // Label 347: @7850 4244 GIM_Try, /*On fail goto*//*Label 348*/ 7873, // Rule ID 5334 // 4245 GIM_CheckFeatures, GIFBS_HasAVX512_HasVLX, 4246 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID, 4247 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID, 4248 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256XRegClassID, 4249 // (and:{ *:[v4i64] } VR256X:{ *:[v4i64] }:$src1, VR256X:{ *:[v4i64] }:$src2) => (VPANDQZ256rr:{ *:[v4i64] } VR256X:{ *:[v4i64] }:$src1, VR256X:{ *:[v4i64] }:$src2) 4250 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPANDQZ256rr, 4251 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4252 // GIR_Coverage, 5334, 4253 GIR_Done, 4254 // Label 348: @7873 4255 GIM_Try, /*On fail goto*//*Label 349*/ 7896, // Rule ID 16564 // 4256 GIM_CheckFeatures, GIFBS_HasAVX1Only, 4257 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID, 4258 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256RegClassID, 4259 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256RegClassID, 4260 // (and:{ *:[v4i64] } VR256:{ *:[v4i64] }:$src1, VR256:{ *:[v4i64] }:$src2) => (VANDPSYrr:{ *:[v4i64] } VR256:{ *:[v4i64] }:$src1, VR256:{ *:[v4i64] }:$src2) 4261 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VANDPSYrr, 4262 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4263 // GIR_Coverage, 16564, 4264 GIR_Done, 4265 // Label 349: @7896 4266 GIM_Reject, 4267 // Label 346: @7897 4268 GIM_Reject, 4269 // Label 264: @7898 4270 GIM_Try, /*On fail goto*//*Label 350*/ 8358, 4271 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s1, 4272 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s1, 4273 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VK8RegClassID, 4274 GIM_Try, /*On fail goto*//*Label 351*/ 7973, // Rule ID 4070 // 4275 GIM_CheckFeatures, GIFBS_HasDQI, 4276 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 4277 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, 4278 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s1, 4279 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s1, 4280 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::VK8RegClassID, 4281 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] 4282 GIM_CheckOpcodeIsEither, /*MI*/2, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, 4283 GIM_CheckIsBuildVectorAllOnes, /*MI*/2, 4284 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VK8RegClassID, 4285 GIM_CheckIsSafeToFold, /*InsnID*/1, 4286 GIM_CheckIsSafeToFold, /*InsnID*/2, 4287 // (and:{ *:[v8i1] } (xor:{ *:[v8i1] } VK8:{ *:[v8i1] }:$src1, immAllOnesV:{ *:[v8i1] }), VK8:{ *:[v8i1] }:$src2) => (KANDNBrr:{ *:[v8i1] } VK8:{ *:[v8i1] }:$src1, VK8:{ *:[v8i1] }:$src2) 4288 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::KANDNBrr, 4289 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 4290 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1 4291 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src2 4292 GIR_EraseFromParent, /*InsnID*/0, 4293 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4294 // GIR_Coverage, 4070, 4295 GIR_Done, 4296 // Label 351: @7973 4297 GIM_Try, /*On fail goto*//*Label 352*/ 8084, // Rule ID 17926 // 4298 GIM_CheckFeatures, GIFBS_NoDQI, 4299 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 4300 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, 4301 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s1, 4302 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s1, 4303 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::VK8RegClassID, 4304 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] 4305 GIM_CheckOpcodeIsEither, /*MI*/2, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, 4306 GIM_CheckIsBuildVectorAllOnes, /*MI*/2, 4307 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VK8RegClassID, 4308 GIM_CheckIsSafeToFold, /*InsnID*/1, 4309 GIM_CheckIsSafeToFold, /*InsnID*/2, 4310 // (and:{ *:[v8i1] } (xor:{ *:[v8i1] } VK8:{ *:[v8i1] }:$src1, immAllOnesV:{ *:[v8i1] }), VK8:{ *:[v8i1] }:$src2) => (COPY_TO_REGCLASS:{ *:[v8i1] } (KANDNWrr:{ *:[v16i1] } (COPY_TO_REGCLASS:{ *:[v16i1] } VK8:{ *:[v8i1] }:$src1, VK16:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v16i1] } VK8:{ *:[v8i1] }:$src2, VK16:{ *:[i32] })), VK8:{ *:[i32] }) 4311 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s1, 4312 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s1, 4313 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s1, 4314 GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::COPY, 4315 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, 4316 GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // src2 4317 GIR_ConstrainSelectedInstOperands, /*InsnID*/3, 4318 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY, 4319 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 4320 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, // src1 4321 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 4322 GIR_BuildMI, /*InsnID*/1, /*Opcode*/X86::KANDNWrr, 4323 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 4324 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, 4325 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/2, /*TempRegFlags*/0, 4326 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 4327 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 4328 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 4329 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 4330 GIR_EraseFromParent, /*InsnID*/0, 4331 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, X86::VK8RegClassID, 4332 // GIR_Coverage, 17926, 4333 GIR_Done, 4334 // Label 352: @8084 4335 GIM_Try, /*On fail goto*//*Label 353*/ 8145, // Rule ID 21561 // 4336 GIM_CheckFeatures, GIFBS_HasDQI, 4337 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VK8RegClassID, 4338 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 4339 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, 4340 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s1, 4341 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s1, 4342 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::VK8RegClassID, 4343 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] 4344 GIM_CheckOpcodeIsEither, /*MI*/2, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, 4345 GIM_CheckIsBuildVectorAllOnes, /*MI*/2, 4346 GIM_CheckIsSafeToFold, /*InsnID*/1, 4347 GIM_CheckIsSafeToFold, /*InsnID*/2, 4348 // (and:{ *:[v8i1] } VK8:{ *:[v8i1] }:$src2, (xor:{ *:[v8i1] } VK8:{ *:[v8i1] }:$src1, immAllOnesV:{ *:[v8i1] })) => (KANDNBrr:{ *:[v8i1] } VK8:{ *:[v8i1] }:$src1, VK8:{ *:[v8i1] }:$src2) 4349 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::KANDNBrr, 4350 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 4351 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1 4352 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src2 4353 GIR_EraseFromParent, /*InsnID*/0, 4354 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4355 // GIR_Coverage, 21561, 4356 GIR_Done, 4357 // Label 353: @8145 4358 GIM_Try, /*On fail goto*//*Label 354*/ 8256, // Rule ID 23232 // 4359 GIM_CheckFeatures, GIFBS_NoDQI, 4360 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VK8RegClassID, 4361 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 4362 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, 4363 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s1, 4364 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s1, 4365 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::VK8RegClassID, 4366 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] 4367 GIM_CheckOpcodeIsEither, /*MI*/2, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, 4368 GIM_CheckIsBuildVectorAllOnes, /*MI*/2, 4369 GIM_CheckIsSafeToFold, /*InsnID*/1, 4370 GIM_CheckIsSafeToFold, /*InsnID*/2, 4371 // (and:{ *:[v8i1] } VK8:{ *:[v8i1] }:$src2, (xor:{ *:[v8i1] } VK8:{ *:[v8i1] }:$src1, immAllOnesV:{ *:[v8i1] })) => (COPY_TO_REGCLASS:{ *:[v8i1] } (KANDNWrr:{ *:[v16i1] } (COPY_TO_REGCLASS:{ *:[v16i1] } VK8:{ *:[v8i1] }:$src1, VK16:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v16i1] } VK8:{ *:[v8i1] }:$src2, VK16:{ *:[i32] })), VK8:{ *:[i32] }) 4372 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s1, 4373 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s1, 4374 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s1, 4375 GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::COPY, 4376 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, 4377 GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // src2 4378 GIR_ConstrainSelectedInstOperands, /*InsnID*/3, 4379 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY, 4380 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 4381 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, // src1 4382 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 4383 GIR_BuildMI, /*InsnID*/1, /*Opcode*/X86::KANDNWrr, 4384 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 4385 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, 4386 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/2, /*TempRegFlags*/0, 4387 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 4388 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 4389 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 4390 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 4391 GIR_EraseFromParent, /*InsnID*/0, 4392 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, X86::VK8RegClassID, 4393 // GIR_Coverage, 23232, 4394 GIR_Done, 4395 // Label 354: @8256 4396 GIM_Try, /*On fail goto*//*Label 355*/ 8275, // Rule ID 4054 // 4397 GIM_CheckFeatures, GIFBS_HasDQI, 4398 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VK8RegClassID, 4399 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VK8RegClassID, 4400 // (and:{ *:[v8i1] } VK8:{ *:[v8i1] }:$src1, VK8:{ *:[v8i1] }:$src2) => (KANDBrr:{ *:[v8i1] } VK8:{ *:[v8i1] }:$src1, VK8:{ *:[v8i1] }:$src2) 4401 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::KANDBrr, 4402 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4403 // GIR_Coverage, 4054, 4404 GIR_Done, 4405 // Label 355: @8275 4406 GIM_Try, /*On fail goto*//*Label 356*/ 8357, // Rule ID 17922 // 4407 GIM_CheckFeatures, GIFBS_NoDQI, 4408 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VK8RegClassID, 4409 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VK8RegClassID, 4410 // (and:{ *:[v8i1] } VK8:{ *:[v8i1] }:$src1, VK8:{ *:[v8i1] }:$src2) => (COPY_TO_REGCLASS:{ *:[v8i1] } (KANDWrr:{ *:[v16i1] } (COPY_TO_REGCLASS:{ *:[v16i1] } VK8:{ *:[v8i1] }:$src1, VK16:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v16i1] } VK8:{ *:[v8i1] }:$src2, VK16:{ *:[i32] })), VK8:{ *:[i32] }) 4411 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s1, 4412 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s1, 4413 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s1, 4414 GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::COPY, 4415 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, 4416 GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // src2 4417 GIR_ConstrainSelectedInstOperands, /*InsnID*/3, 4418 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY, 4419 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 4420 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src1 4421 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 4422 GIR_BuildMI, /*InsnID*/1, /*Opcode*/X86::KANDWrr, 4423 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 4424 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, 4425 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/2, /*TempRegFlags*/0, 4426 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 4427 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 4428 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 4429 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 4430 GIR_EraseFromParent, /*InsnID*/0, 4431 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, X86::VK8RegClassID, 4432 // GIR_Coverage, 17922, 4433 GIR_Done, 4434 // Label 356: @8357 4435 GIM_Reject, 4436 // Label 350: @8358 4437 GIM_Reject, 4438 // Label 265: @8359 4439 GIM_Try, /*On fail goto*//*Label 357*/ 8439, 4440 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, 4441 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 4442 GIM_Try, /*On fail goto*//*Label 358*/ 8392, // Rule ID 16594 // 4443 GIM_CheckFeatures, GIFBS_HasAVX_NoVLX, 4444 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 4445 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 4446 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 4447 // (and:{ *:[v8i16] } VR128:{ *:[v8i16] }:$src1, VR128:{ *:[v8i16] }:$src2) => (VPANDrr:{ *:[v8i16] } VR128:{ *:[v8i16] }:$src1, VR128:{ *:[v8i16] }:$src2) 4448 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPANDrr, 4449 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4450 // GIR_Coverage, 16594, 4451 GIR_Done, 4452 // Label 358: @8392 4453 GIM_Try, /*On fail goto*//*Label 359*/ 8415, // Rule ID 16618 // 4454 GIM_CheckFeatures, GIFBS_UseSSE2, 4455 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 4456 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 4457 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 4458 // (and:{ *:[v8i16] } VR128:{ *:[v8i16] }:$src1, VR128:{ *:[v8i16] }:$src2) => (PANDrr:{ *:[v8i16] } VR128:{ *:[v8i16] }:$src1, VR128:{ *:[v8i16] }:$src2) 4459 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::PANDrr, 4460 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4461 // GIR_Coverage, 16618, 4462 GIR_Done, 4463 // Label 359: @8415 4464 GIM_Try, /*On fail goto*//*Label 360*/ 8438, // Rule ID 18502 // 4465 GIM_CheckFeatures, GIFBS_HasVLX, 4466 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID, 4467 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID, 4468 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128XRegClassID, 4469 // (and:{ *:[v8i16] } VR128X:{ *:[v8i16] }:$src1, VR128X:{ *:[v8i16] }:$src2) => (VPANDQZ128rr:{ *:[v8i16] } VR128X:{ *:[v8i16] }:$src1, VR128X:{ *:[v8i16] }:$src2) 4470 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPANDQZ128rr, 4471 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4472 // GIR_Coverage, 18502, 4473 GIR_Done, 4474 // Label 360: @8438 4475 GIM_Reject, 4476 // Label 357: @8439 4477 GIM_Reject, 4478 // Label 266: @8440 4479 GIM_Try, /*On fail goto*//*Label 361*/ 8520, 4480 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s32, 4481 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s32, 4482 GIM_Try, /*On fail goto*//*Label 362*/ 8473, // Rule ID 5361 // 4483 GIM_CheckFeatures, GIFBS_HasAVX512_HasVLX, 4484 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID, 4485 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID, 4486 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256XRegClassID, 4487 // (and:{ *:[v8i32] } VR256X:{ *:[v8i32] }:$src1, VR256X:{ *:[v8i32] }:$src2) => (VPANDDZ256rr:{ *:[v8i32] } VR256X:{ *:[v8i32] }:$src1, VR256X:{ *:[v8i32] }:$src2) 4488 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPANDDZ256rr, 4489 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4490 // GIR_Coverage, 5361, 4491 GIR_Done, 4492 // Label 362: @8473 4493 GIM_Try, /*On fail goto*//*Label 363*/ 8496, // Rule ID 16539 // 4494 GIM_CheckFeatures, GIFBS_HasAVX2_NoVLX, 4495 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID, 4496 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256RegClassID, 4497 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256RegClassID, 4498 // (and:{ *:[v8i32] } VR256:{ *:[v8i32] }:$src1, VR256:{ *:[v8i32] }:$src2) => (VPANDYrr:{ *:[v8i32] } VR256:{ *:[v8i32] }:$src1, VR256:{ *:[v8i32] }:$src2) 4499 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPANDYrr, 4500 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4501 // GIR_Coverage, 16539, 4502 GIR_Done, 4503 // Label 363: @8496 4504 GIM_Try, /*On fail goto*//*Label 364*/ 8519, // Rule ID 16563 // 4505 GIM_CheckFeatures, GIFBS_HasAVX1Only, 4506 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID, 4507 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256RegClassID, 4508 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256RegClassID, 4509 // (and:{ *:[v8i32] } VR256:{ *:[v8i32] }:$src1, VR256:{ *:[v8i32] }:$src2) => (VANDPSYrr:{ *:[v8i32] } VR256:{ *:[v8i32] }:$src1, VR256:{ *:[v8i32] }:$src2) 4510 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VANDPSYrr, 4511 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4512 // GIR_Coverage, 16563, 4513 GIR_Done, 4514 // Label 364: @8519 4515 GIM_Reject, 4516 // Label 361: @8520 4517 GIM_Reject, 4518 // Label 267: @8521 4519 GIM_Try, /*On fail goto*//*Label 365*/ 8552, // Rule ID 5325 // 4520 GIM_CheckFeatures, GIFBS_HasAVX512, 4521 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s64, 4522 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s64, 4523 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 4524 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR512RegClassID, 4525 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR512RegClassID, 4526 // (and:{ *:[v8i64] } VR512:{ *:[v8i64] }:$src1, VR512:{ *:[v8i64] }:$src2) => (VPANDQZrr:{ *:[v8i64] } VR512:{ *:[v8i64] }:$src1, VR512:{ *:[v8i64] }:$src2) 4527 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPANDQZrr, 4528 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4529 // GIR_Coverage, 5325, 4530 GIR_Done, 4531 // Label 365: @8552 4532 GIM_Reject, 4533 // Label 268: @8553 4534 GIM_Try, /*On fail goto*//*Label 366*/ 8709, 4535 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s1, 4536 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s1, 4537 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VK16RegClassID, 4538 GIM_Try, /*On fail goto*//*Label 367*/ 8628, // Rule ID 4071 // 4539 GIM_CheckFeatures, GIFBS_HasAVX512, 4540 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 4541 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, 4542 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s1, 4543 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s1, 4544 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::VK16RegClassID, 4545 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] 4546 GIM_CheckOpcodeIsEither, /*MI*/2, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, 4547 GIM_CheckIsBuildVectorAllOnes, /*MI*/2, 4548 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VK16RegClassID, 4549 GIM_CheckIsSafeToFold, /*InsnID*/1, 4550 GIM_CheckIsSafeToFold, /*InsnID*/2, 4551 // (and:{ *:[v16i1] } (xor:{ *:[v16i1] } VK16:{ *:[v16i1] }:$src1, immAllOnesV:{ *:[v16i1] }), VK16:{ *:[v16i1] }:$src2) => (KANDNWrr:{ *:[v16i1] } VK16:{ *:[v16i1] }:$src1, VK16:{ *:[v16i1] }:$src2) 4552 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::KANDNWrr, 4553 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 4554 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1 4555 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src2 4556 GIR_EraseFromParent, /*InsnID*/0, 4557 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4558 // GIR_Coverage, 4071, 4559 GIR_Done, 4560 // Label 367: @8628 4561 GIM_Try, /*On fail goto*//*Label 368*/ 8689, // Rule ID 21562 // 4562 GIM_CheckFeatures, GIFBS_HasAVX512, 4563 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VK16RegClassID, 4564 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 4565 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, 4566 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s1, 4567 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s1, 4568 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::VK16RegClassID, 4569 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] 4570 GIM_CheckOpcodeIsEither, /*MI*/2, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, 4571 GIM_CheckIsBuildVectorAllOnes, /*MI*/2, 4572 GIM_CheckIsSafeToFold, /*InsnID*/1, 4573 GIM_CheckIsSafeToFold, /*InsnID*/2, 4574 // (and:{ *:[v16i1] } VK16:{ *:[v16i1] }:$src2, (xor:{ *:[v16i1] } VK16:{ *:[v16i1] }:$src1, immAllOnesV:{ *:[v16i1] })) => (KANDNWrr:{ *:[v16i1] } VK16:{ *:[v16i1] }:$src1, VK16:{ *:[v16i1] }:$src2) 4575 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::KANDNWrr, 4576 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 4577 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1 4578 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src2 4579 GIR_EraseFromParent, /*InsnID*/0, 4580 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4581 // GIR_Coverage, 21562, 4582 GIR_Done, 4583 // Label 368: @8689 4584 GIM_Try, /*On fail goto*//*Label 369*/ 8708, // Rule ID 4055 // 4585 GIM_CheckFeatures, GIFBS_HasAVX512, 4586 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VK16RegClassID, 4587 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VK16RegClassID, 4588 // (and:{ *:[v16i1] } VK16:{ *:[v16i1] }:$src1, VK16:{ *:[v16i1] }:$src2) => (KANDWrr:{ *:[v16i1] } VK16:{ *:[v16i1] }:$src1, VK16:{ *:[v16i1] }:$src2) 4589 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::KANDWrr, 4590 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4591 // GIR_Coverage, 4055, 4592 GIR_Done, 4593 // Label 369: @8708 4594 GIM_Reject, 4595 // Label 366: @8709 4596 GIM_Reject, 4597 // Label 269: @8710 4598 GIM_Try, /*On fail goto*//*Label 370*/ 8790, 4599 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, 4600 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, 4601 GIM_Try, /*On fail goto*//*Label 371*/ 8743, // Rule ID 16593 // 4602 GIM_CheckFeatures, GIFBS_HasAVX_NoVLX, 4603 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 4604 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 4605 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 4606 // (and:{ *:[v16i8] } VR128:{ *:[v16i8] }:$src1, VR128:{ *:[v16i8] }:$src2) => (VPANDrr:{ *:[v16i8] } VR128:{ *:[v16i8] }:$src1, VR128:{ *:[v16i8] }:$src2) 4607 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPANDrr, 4608 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4609 // GIR_Coverage, 16593, 4610 GIR_Done, 4611 // Label 371: @8743 4612 GIM_Try, /*On fail goto*//*Label 372*/ 8766, // Rule ID 16617 // 4613 GIM_CheckFeatures, GIFBS_UseSSE2, 4614 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 4615 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 4616 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 4617 // (and:{ *:[v16i8] } VR128:{ *:[v16i8] }:$src1, VR128:{ *:[v16i8] }:$src2) => (PANDrr:{ *:[v16i8] } VR128:{ *:[v16i8] }:$src1, VR128:{ *:[v16i8] }:$src2) 4618 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::PANDrr, 4619 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4620 // GIR_Coverage, 16617, 4621 GIR_Done, 4622 // Label 372: @8766 4623 GIM_Try, /*On fail goto*//*Label 373*/ 8789, // Rule ID 18501 // 4624 GIM_CheckFeatures, GIFBS_HasVLX, 4625 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID, 4626 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID, 4627 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128XRegClassID, 4628 // (and:{ *:[v16i8] } VR128X:{ *:[v16i8] }:$src1, VR128X:{ *:[v16i8] }:$src2) => (VPANDQZ128rr:{ *:[v16i8] } VR128X:{ *:[v16i8] }:$src1, VR128X:{ *:[v16i8] }:$src2) 4629 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPANDQZ128rr, 4630 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4631 // GIR_Coverage, 18501, 4632 GIR_Done, 4633 // Label 373: @8789 4634 GIM_Reject, 4635 // Label 370: @8790 4636 GIM_Reject, 4637 // Label 270: @8791 4638 GIM_Try, /*On fail goto*//*Label 374*/ 8871, 4639 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s16, 4640 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s16, 4641 GIM_Try, /*On fail goto*//*Label 375*/ 8824, // Rule ID 16538 // 4642 GIM_CheckFeatures, GIFBS_HasAVX2_NoVLX, 4643 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID, 4644 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256RegClassID, 4645 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256RegClassID, 4646 // (and:{ *:[v16i16] } VR256:{ *:[v16i16] }:$src1, VR256:{ *:[v16i16] }:$src2) => (VPANDYrr:{ *:[v16i16] } VR256:{ *:[v16i16] }:$src1, VR256:{ *:[v16i16] }:$src2) 4647 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPANDYrr, 4648 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4649 // GIR_Coverage, 16538, 4650 GIR_Done, 4651 // Label 375: @8824 4652 GIM_Try, /*On fail goto*//*Label 376*/ 8847, // Rule ID 16562 // 4653 GIM_CheckFeatures, GIFBS_HasAVX1Only, 4654 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID, 4655 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256RegClassID, 4656 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256RegClassID, 4657 // (and:{ *:[v16i16] } VR256:{ *:[v16i16] }:$src1, VR256:{ *:[v16i16] }:$src2) => (VANDPSYrr:{ *:[v16i16] } VR256:{ *:[v16i16] }:$src1, VR256:{ *:[v16i16] }:$src2) 4658 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VANDPSYrr, 4659 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4660 // GIR_Coverage, 16562, 4661 GIR_Done, 4662 // Label 376: @8847 4663 GIM_Try, /*On fail goto*//*Label 377*/ 8870, // Rule ID 18518 // 4664 GIM_CheckFeatures, GIFBS_HasVLX, 4665 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID, 4666 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID, 4667 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256XRegClassID, 4668 // (and:{ *:[v16i16] } VR256X:{ *:[v16i16] }:$src1, VR256X:{ *:[v16i16] }:$src2) => (VPANDQZ256rr:{ *:[v16i16] } VR256X:{ *:[v16i16] }:$src1, VR256X:{ *:[v16i16] }:$src2) 4669 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPANDQZ256rr, 4670 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4671 // GIR_Coverage, 18518, 4672 GIR_Done, 4673 // Label 377: @8870 4674 GIM_Reject, 4675 // Label 374: @8871 4676 GIM_Reject, 4677 // Label 271: @8872 4678 GIM_Try, /*On fail goto*//*Label 378*/ 8903, // Rule ID 5352 // 4679 GIM_CheckFeatures, GIFBS_HasAVX512, 4680 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s32, 4681 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s32, 4682 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 4683 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR512RegClassID, 4684 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR512RegClassID, 4685 // (and:{ *:[v16i32] } VR512:{ *:[v16i32] }:$src1, VR512:{ *:[v16i32] }:$src2) => (VPANDDZrr:{ *:[v16i32] } VR512:{ *:[v16i32] }:$src1, VR512:{ *:[v16i32] }:$src2) 4686 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPANDDZrr, 4687 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4688 // GIR_Coverage, 5352, 4689 GIR_Done, 4690 // Label 378: @8903 4691 GIM_Reject, 4692 // Label 272: @8904 4693 GIM_Try, /*On fail goto*//*Label 379*/ 9060, 4694 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v32s1, 4695 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v32s1, 4696 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VK32RegClassID, 4697 GIM_Try, /*On fail goto*//*Label 380*/ 8979, // Rule ID 4072 // 4698 GIM_CheckFeatures, GIFBS_HasBWI, 4699 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 4700 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, 4701 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v32s1, 4702 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v32s1, 4703 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::VK32RegClassID, 4704 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] 4705 GIM_CheckOpcodeIsEither, /*MI*/2, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, 4706 GIM_CheckIsBuildVectorAllOnes, /*MI*/2, 4707 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VK32RegClassID, 4708 GIM_CheckIsSafeToFold, /*InsnID*/1, 4709 GIM_CheckIsSafeToFold, /*InsnID*/2, 4710 // (and:{ *:[v32i1] } (xor:{ *:[v32i1] } VK32:{ *:[v32i1] }:$src1, immAllOnesV:{ *:[v32i1] }), VK32:{ *:[v32i1] }:$src2) => (KANDNDrr:{ *:[v32i1] } VK32:{ *:[v32i1] }:$src1, VK32:{ *:[v32i1] }:$src2) 4711 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::KANDNDrr, 4712 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 4713 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1 4714 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src2 4715 GIR_EraseFromParent, /*InsnID*/0, 4716 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4717 // GIR_Coverage, 4072, 4718 GIR_Done, 4719 // Label 380: @8979 4720 GIM_Try, /*On fail goto*//*Label 381*/ 9040, // Rule ID 21563 // 4721 GIM_CheckFeatures, GIFBS_HasBWI, 4722 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VK32RegClassID, 4723 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 4724 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, 4725 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v32s1, 4726 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v32s1, 4727 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::VK32RegClassID, 4728 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] 4729 GIM_CheckOpcodeIsEither, /*MI*/2, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, 4730 GIM_CheckIsBuildVectorAllOnes, /*MI*/2, 4731 GIM_CheckIsSafeToFold, /*InsnID*/1, 4732 GIM_CheckIsSafeToFold, /*InsnID*/2, 4733 // (and:{ *:[v32i1] } VK32:{ *:[v32i1] }:$src2, (xor:{ *:[v32i1] } VK32:{ *:[v32i1] }:$src1, immAllOnesV:{ *:[v32i1] })) => (KANDNDrr:{ *:[v32i1] } VK32:{ *:[v32i1] }:$src1, VK32:{ *:[v32i1] }:$src2) 4734 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::KANDNDrr, 4735 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 4736 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1 4737 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src2 4738 GIR_EraseFromParent, /*InsnID*/0, 4739 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4740 // GIR_Coverage, 21563, 4741 GIR_Done, 4742 // Label 381: @9040 4743 GIM_Try, /*On fail goto*//*Label 382*/ 9059, // Rule ID 4056 // 4744 GIM_CheckFeatures, GIFBS_HasBWI, 4745 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VK32RegClassID, 4746 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VK32RegClassID, 4747 // (and:{ *:[v32i1] } VK32:{ *:[v32i1] }:$src1, VK32:{ *:[v32i1] }:$src2) => (KANDDrr:{ *:[v32i1] } VK32:{ *:[v32i1] }:$src1, VK32:{ *:[v32i1] }:$src2) 4748 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::KANDDrr, 4749 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4750 // GIR_Coverage, 4056, 4751 GIR_Done, 4752 // Label 382: @9059 4753 GIM_Reject, 4754 // Label 379: @9060 4755 GIM_Reject, 4756 // Label 273: @9061 4757 GIM_Try, /*On fail goto*//*Label 383*/ 9141, 4758 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v32s8, 4759 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v32s8, 4760 GIM_Try, /*On fail goto*//*Label 384*/ 9094, // Rule ID 16537 // 4761 GIM_CheckFeatures, GIFBS_HasAVX2_NoVLX, 4762 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID, 4763 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256RegClassID, 4764 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256RegClassID, 4765 // (and:{ *:[v32i8] } VR256:{ *:[v32i8] }:$src1, VR256:{ *:[v32i8] }:$src2) => (VPANDYrr:{ *:[v32i8] } VR256:{ *:[v32i8] }:$src1, VR256:{ *:[v32i8] }:$src2) 4766 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPANDYrr, 4767 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4768 // GIR_Coverage, 16537, 4769 GIR_Done, 4770 // Label 384: @9094 4771 GIM_Try, /*On fail goto*//*Label 385*/ 9117, // Rule ID 16561 // 4772 GIM_CheckFeatures, GIFBS_HasAVX1Only, 4773 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID, 4774 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256RegClassID, 4775 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256RegClassID, 4776 // (and:{ *:[v32i8] } VR256:{ *:[v32i8] }:$src1, VR256:{ *:[v32i8] }:$src2) => (VANDPSYrr:{ *:[v32i8] } VR256:{ *:[v32i8] }:$src1, VR256:{ *:[v32i8] }:$src2) 4777 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VANDPSYrr, 4778 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4779 // GIR_Coverage, 16561, 4780 GIR_Done, 4781 // Label 385: @9117 4782 GIM_Try, /*On fail goto*//*Label 386*/ 9140, // Rule ID 18517 // 4783 GIM_CheckFeatures, GIFBS_HasVLX, 4784 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID, 4785 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID, 4786 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256XRegClassID, 4787 // (and:{ *:[v32i8] } VR256X:{ *:[v32i8] }:$src1, VR256X:{ *:[v32i8] }:$src2) => (VPANDQZ256rr:{ *:[v32i8] } VR256X:{ *:[v32i8] }:$src1, VR256X:{ *:[v32i8] }:$src2) 4788 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPANDQZ256rr, 4789 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4790 // GIR_Coverage, 18517, 4791 GIR_Done, 4792 // Label 386: @9140 4793 GIM_Reject, 4794 // Label 383: @9141 4795 GIM_Reject, 4796 // Label 274: @9142 4797 GIM_Try, /*On fail goto*//*Label 387*/ 9173, // Rule ID 18534 // 4798 GIM_CheckFeatures, GIFBS_HasAVX512, 4799 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v32s16, 4800 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v32s16, 4801 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 4802 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR512RegClassID, 4803 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR512RegClassID, 4804 // (and:{ *:[v32i16] } VR512:{ *:[v32i16] }:$src1, VR512:{ *:[v32i16] }:$src2) => (VPANDQZrr:{ *:[v32i16] } VR512:{ *:[v32i16] }:$src1, VR512:{ *:[v32i16] }:$src2) 4805 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPANDQZrr, 4806 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4807 // GIR_Coverage, 18534, 4808 GIR_Done, 4809 // Label 387: @9173 4810 GIM_Reject, 4811 // Label 275: @9174 4812 GIM_Try, /*On fail goto*//*Label 388*/ 9330, 4813 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v64s1, 4814 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v64s1, 4815 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VK64RegClassID, 4816 GIM_Try, /*On fail goto*//*Label 389*/ 9249, // Rule ID 4073 // 4817 GIM_CheckFeatures, GIFBS_HasBWI, 4818 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 4819 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, 4820 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v64s1, 4821 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v64s1, 4822 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::VK64RegClassID, 4823 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] 4824 GIM_CheckOpcodeIsEither, /*MI*/2, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, 4825 GIM_CheckIsBuildVectorAllOnes, /*MI*/2, 4826 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VK64RegClassID, 4827 GIM_CheckIsSafeToFold, /*InsnID*/1, 4828 GIM_CheckIsSafeToFold, /*InsnID*/2, 4829 // (and:{ *:[v64i1] } (xor:{ *:[v64i1] } VK64:{ *:[v64i1] }:$src1, immAllOnesV:{ *:[v64i1] }), VK64:{ *:[v64i1] }:$src2) => (KANDNQrr:{ *:[v64i1] } VK64:{ *:[v64i1] }:$src1, VK64:{ *:[v64i1] }:$src2) 4830 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::KANDNQrr, 4831 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 4832 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1 4833 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src2 4834 GIR_EraseFromParent, /*InsnID*/0, 4835 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4836 // GIR_Coverage, 4073, 4837 GIR_Done, 4838 // Label 389: @9249 4839 GIM_Try, /*On fail goto*//*Label 390*/ 9310, // Rule ID 21564 // 4840 GIM_CheckFeatures, GIFBS_HasBWI, 4841 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VK64RegClassID, 4842 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 4843 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, 4844 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v64s1, 4845 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v64s1, 4846 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::VK64RegClassID, 4847 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] 4848 GIM_CheckOpcodeIsEither, /*MI*/2, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, 4849 GIM_CheckIsBuildVectorAllOnes, /*MI*/2, 4850 GIM_CheckIsSafeToFold, /*InsnID*/1, 4851 GIM_CheckIsSafeToFold, /*InsnID*/2, 4852 // (and:{ *:[v64i1] } VK64:{ *:[v64i1] }:$src2, (xor:{ *:[v64i1] } VK64:{ *:[v64i1] }:$src1, immAllOnesV:{ *:[v64i1] })) => (KANDNQrr:{ *:[v64i1] } VK64:{ *:[v64i1] }:$src1, VK64:{ *:[v64i1] }:$src2) 4853 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::KANDNQrr, 4854 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 4855 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1 4856 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src2 4857 GIR_EraseFromParent, /*InsnID*/0, 4858 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4859 // GIR_Coverage, 21564, 4860 GIR_Done, 4861 // Label 390: @9310 4862 GIM_Try, /*On fail goto*//*Label 391*/ 9329, // Rule ID 4057 // 4863 GIM_CheckFeatures, GIFBS_HasBWI, 4864 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VK64RegClassID, 4865 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VK64RegClassID, 4866 // (and:{ *:[v64i1] } VK64:{ *:[v64i1] }:$src1, VK64:{ *:[v64i1] }:$src2) => (KANDQrr:{ *:[v64i1] } VK64:{ *:[v64i1] }:$src1, VK64:{ *:[v64i1] }:$src2) 4867 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::KANDQrr, 4868 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4869 // GIR_Coverage, 4057, 4870 GIR_Done, 4871 // Label 391: @9329 4872 GIM_Reject, 4873 // Label 388: @9330 4874 GIM_Reject, 4875 // Label 276: @9331 4876 GIM_Try, /*On fail goto*//*Label 392*/ 9362, // Rule ID 18533 // 4877 GIM_CheckFeatures, GIFBS_HasAVX512, 4878 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v64s8, 4879 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v64s8, 4880 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 4881 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR512RegClassID, 4882 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR512RegClassID, 4883 // (and:{ *:[v64i8] } VR512:{ *:[v64i8] }:$src1, VR512:{ *:[v64i8] }:$src2) => (VPANDQZrr:{ *:[v64i8] } VR512:{ *:[v64i8] }:$src1, VR512:{ *:[v64i8] }:$src2) 4884 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPANDQZrr, 4885 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4886 // GIR_Coverage, 18533, 4887 GIR_Done, 4888 // Label 392: @9362 4889 GIM_Reject, 4890 // Label 277: @9363 4891 GIM_Reject, 4892 // Label 4: @9364 4893 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 25, /*)*//*default:*//*Label 416*/ 13233, 4894 /*GILLT_s1*//*Label 393*/ 9395, 4895 /*GILLT_s8*//*Label 394*/ 9488, 4896 /*GILLT_s16*//*Label 395*/ 9554, 4897 /*GILLT_s32*//*Label 396*/ 9853, 4898 /*GILLT_s64*//*Label 397*/ 10958, 0, 0, 4899 /*GILLT_v2s1*//*Label 398*/ 12066, 4900 /*GILLT_v2s64*//*Label 399*/ 12159, 4901 /*GILLT_v4s1*//*Label 400*/ 12240, 4902 /*GILLT_v4s32*//*Label 401*/ 12333, 4903 /*GILLT_v4s64*//*Label 402*/ 12414, 4904 /*GILLT_v8s1*//*Label 403*/ 12495, 4905 /*GILLT_v8s16*//*Label 404*/ 12604, 4906 /*GILLT_v8s32*//*Label 405*/ 12685, 4907 /*GILLT_v8s64*//*Label 406*/ 12766, 4908 /*GILLT_v16s1*//*Label 407*/ 12798, 4909 /*GILLT_v16s8*//*Label 408*/ 12830, 4910 /*GILLT_v16s16*//*Label 409*/ 12911, 4911 /*GILLT_v16s32*//*Label 410*/ 12992, 4912 /*GILLT_v32s1*//*Label 411*/ 13024, 4913 /*GILLT_v32s8*//*Label 412*/ 13056, 4914 /*GILLT_v32s16*//*Label 413*/ 13137, 4915 /*GILLT_v64s1*//*Label 414*/ 13169, 4916 /*GILLT_v64s8*//*Label 415*/ 13201, 4917 // Label 393: @9395 4918 GIM_Try, /*On fail goto*//*Label 417*/ 9487, // Rule ID 17931 // 4919 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s1, 4920 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s1, 4921 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VK1RegClassID, 4922 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VK1RegClassID, 4923 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VK1RegClassID, 4924 // (or:{ *:[v1i1] } VK1:{ *:[v1i1] }:$src1, VK1:{ *:[v1i1] }:$src2) => (COPY_TO_REGCLASS:{ *:[v1i1] } (KORWrr:{ *:[v16i1] } (COPY_TO_REGCLASS:{ *:[v16i1] } VK1:{ *:[v1i1] }:$src1, VK16:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v16i1] } VK1:{ *:[v1i1] }:$src2, VK16:{ *:[i32] })), VK1:{ *:[i32] }) 4925 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s1, 4926 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s1, 4927 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s1, 4928 GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::COPY, 4929 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, 4930 GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // src2 4931 GIR_ConstrainSelectedInstOperands, /*InsnID*/3, 4932 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY, 4933 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 4934 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src1 4935 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 4936 GIR_BuildMI, /*InsnID*/1, /*Opcode*/X86::KORWrr, 4937 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 4938 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, 4939 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/2, /*TempRegFlags*/0, 4940 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 4941 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 4942 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 4943 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 4944 GIR_EraseFromParent, /*InsnID*/0, 4945 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, X86::VK1RegClassID, 4946 // GIR_Coverage, 17931, 4947 GIR_Done, 4948 // Label 417: @9487 4949 GIM_Reject, 4950 // Label 394: @9488 4951 GIM_Try, /*On fail goto*//*Label 418*/ 9553, 4952 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s8, 4953 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s8, 4954 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR8RegClassID, 4955 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR8RegClassID, 4956 GIM_Try, /*On fail goto*//*Label 419*/ 9536, // Rule ID 15673 // 4957 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 4958 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 4959 // MIs[1] Operand 1 4960 // No operand predicates 4961 GIM_CheckIsSafeToFold, /*InsnID*/1, 4962 // (or:{ *:[i8] } GR8:{ *:[i8] }:$src1, (imm:{ *:[i8] }):$src2) => (OR8ri:{ *:[i8] }:{ *:[i32] } GR8:{ *:[i8] }:$src1, (imm:{ *:[i8] }):$src2) 4963 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::OR8ri, 4964 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 4965 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 4966 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // src2 4967 GIR_EraseFromParent, /*InsnID*/0, 4968 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4969 // GIR_Coverage, 15673, 4970 GIR_Done, 4971 // Label 419: @9536 4972 GIM_Try, /*On fail goto*//*Label 420*/ 9552, // Rule ID 21063 // 4973 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::GR8RegClassID, 4974 // (or:{ *:[i8] } GR8:{ *:[i8] }:$src1, GR8:{ *:[i8] }:$src2) => (OR8rr:{ *:[i8] }:{ *:[i32] } GR8:{ *:[i8] }:$src1, GR8:{ *:[i8] }:$src2) 4975 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::OR8rr, 4976 GIR_AddImplicitDef, /*InsnID*/0, X86::EFLAGS, 4977 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4978 // GIR_Coverage, 21063, 4979 GIR_Done, 4980 // Label 420: @9552 4981 GIM_Reject, 4982 // Label 418: @9553 4983 GIM_Reject, 4984 // Label 395: @9554 4985 GIM_Try, /*On fail goto*//*Label 421*/ 9852, 4986 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16, 4987 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16, 4988 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR16RegClassID, 4989 GIM_Try, /*On fail goto*//*Label 422*/ 9664, // Rule ID 23893 // 4990 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 4991 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SHL, 4992 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, 4993 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s8, 4994 GIM_CheckConstantInt, /*MI*/1, /*Op*/1, 1, 4995 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/X86::GR8RegClassID, 4996 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::GR16RegClassID, 4997 GIM_CheckIsSafeToFold, /*InsnID*/1, 4998 // (or:{ *:[i16] } (shl:{ *:[i16] } 1:{ *:[i16] }, GR8:{ *:[i8] }:$src2), GR16:{ *:[i16] }:$src1) => (BTS16rr:{ *:[i16] }:{ *:[i32] } GR16:{ *:[i16] }:$src1, (INSERT_SUBREG:{ *:[i16] } (IMPLICIT_DEF:{ *:[i16] }), GR8:{ *:[i8] }:$src2, sub_8bit:{ *:[i32] })) 4999 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16, 5000 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16, 5001 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, 5002 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 5003 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 5004 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, 5005 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 5006 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, 5007 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // src2 5008 GIR_AddImm, /*InsnID*/1, /*Imm*/1, 5009 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, X86::GR16RegClassID, 5010 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, X86::GR16RegClassID, 5011 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, X86::GR8RegClassID, 5012 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BTS16rr, 5013 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 5014 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 5015 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 5016 GIR_EraseFromParent, /*InsnID*/0, 5017 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5018 // GIR_Coverage, 23893, 5019 GIR_Done, 5020 // Label 422: @9664 5021 GIM_Try, /*On fail goto*//*Label 423*/ 9760, // Rule ID 20978 // 5022 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR16RegClassID, 5023 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 5024 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SHL, 5025 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, 5026 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s8, 5027 GIM_CheckConstantInt, /*MI*/1, /*Op*/1, 1, 5028 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/X86::GR8RegClassID, 5029 GIM_CheckIsSafeToFold, /*InsnID*/1, 5030 // (or:{ *:[i16] } GR16:{ *:[i16] }:$src1, (shl:{ *:[i16] } 1:{ *:[i16] }, GR8:{ *:[i8] }:$src2)) => (BTS16rr:{ *:[i16] }:{ *:[i32] } GR16:{ *:[i16] }:$src1, (INSERT_SUBREG:{ *:[i16] } (IMPLICIT_DEF:{ *:[i16] }), GR8:{ *:[i8] }:$src2, sub_8bit:{ *:[i32] })) 5031 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16, 5032 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16, 5033 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, 5034 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 5035 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 5036 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, 5037 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 5038 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, 5039 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // src2 5040 GIR_AddImm, /*InsnID*/1, /*Imm*/1, 5041 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, X86::GR16RegClassID, 5042 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, X86::GR16RegClassID, 5043 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, X86::GR8RegClassID, 5044 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BTS16rr, 5045 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 5046 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 5047 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 5048 GIR_EraseFromParent, /*InsnID*/0, 5049 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5050 // GIR_Coverage, 20978, 5051 GIR_Done, 5052 // Label 423: @9760 5053 GIM_Try, /*On fail goto*//*Label 424*/ 9797, // Rule ID 15676 // 5054 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR16RegClassID, 5055 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 5056 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 5057 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_i16immSExt8, 5058 // MIs[1] Operand 1 5059 // No operand predicates 5060 GIM_CheckIsSafeToFold, /*InsnID*/1, 5061 // (or:{ *:[i16] } GR16:{ *:[i16] }:$src1, (imm:{ *:[i16] })<<P:Predicate_i16immSExt8>>:$src2) => (OR16ri8:{ *:[i16] }:{ *:[i32] } GR16:{ *:[i16] }:$src1, (imm:{ *:[i16] })<<P:Predicate_i16immSExt8>>:$src2) 5062 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::OR16ri8, 5063 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 5064 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 5065 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // src2 5066 GIR_EraseFromParent, /*InsnID*/0, 5067 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5068 // GIR_Coverage, 15676, 5069 GIR_Done, 5070 // Label 424: @9797 5071 GIM_Try, /*On fail goto*//*Label 425*/ 9831, // Rule ID 15674 // 5072 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR16RegClassID, 5073 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 5074 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 5075 // MIs[1] Operand 1 5076 // No operand predicates 5077 GIM_CheckIsSafeToFold, /*InsnID*/1, 5078 // (or:{ *:[i16] } GR16:{ *:[i16] }:$src1, (imm:{ *:[i16] }):$src2) => (OR16ri:{ *:[i16] }:{ *:[i32] } GR16:{ *:[i16] }:$src1, (imm:{ *:[i16] }):$src2) 5079 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::OR16ri, 5080 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 5081 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 5082 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // src2 5083 GIR_EraseFromParent, /*InsnID*/0, 5084 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5085 // GIR_Coverage, 15674, 5086 GIR_Done, 5087 // Label 425: @9831 5088 GIM_Try, /*On fail goto*//*Label 426*/ 9851, // Rule ID 15666 // 5089 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR16RegClassID, 5090 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::GR16RegClassID, 5091 // (or:{ *:[i16] } GR16:{ *:[i16] }:$src1, GR16:{ *:[i16] }:$src2) => (OR16rr:{ *:[i16] }:{ *:[i32] } GR16:{ *:[i16] }:$src1, GR16:{ *:[i16] }:$src2) 5092 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::OR16rr, 5093 GIR_AddImplicitDef, /*InsnID*/0, X86::EFLAGS, 5094 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5095 // GIR_Coverage, 15666, 5096 GIR_Done, 5097 // Label 426: @9851 5098 GIM_Reject, 5099 // Label 421: @9852 5100 GIM_Reject, 5101 // Label 396: @9853 5102 GIM_Try, /*On fail goto*//*Label 427*/ 10957, 5103 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 5104 GIM_Try, /*On fail goto*//*Label 428*/ 9934, // Rule ID 22881 // 5105 GIM_CheckFeatures, GIFBS_HasTBM, 5106 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 5107 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID, 5108 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 5109 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD, 5110 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, 5111 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, 5112 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::GR32RegClassID, 5113 GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1, 5114 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] 5115 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_XOR, 5116 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, 5117 // MIs[2] src 5118 GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, 5119 GIM_CheckConstantInt, /*MI*/2, /*Op*/2, -1, 5120 GIM_CheckIsSafeToFold, /*InsnID*/1, 5121 GIM_CheckIsSafeToFold, /*InsnID*/2, 5122 // (or:{ *:[i32] } (add:{ *:[i32] } GR32:{ *:[i32] }:$src, -1:{ *:[i32] }), (xor:{ *:[i32] } GR32:{ *:[i32] }:$src, -1:{ *:[i32] })) => (BLSIC32rr:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src) 5123 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLSIC32rr, 5124 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 5125 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src 5126 GIR_EraseFromParent, /*InsnID*/0, 5127 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5128 // GIR_Coverage, 22881, 5129 GIR_Done, 5130 // Label 428: @9934 5131 GIM_Try, /*On fail goto*//*Label 429*/ 10009, // Rule ID 22883 // 5132 GIM_CheckFeatures, GIFBS_HasTBM, 5133 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 5134 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID, 5135 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 5136 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD, 5137 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, 5138 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, 5139 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::GR32RegClassID, 5140 GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 1, 5141 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] 5142 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_XOR, 5143 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, 5144 // MIs[2] src 5145 GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, 5146 GIM_CheckConstantInt, /*MI*/2, /*Op*/2, -1, 5147 GIM_CheckIsSafeToFold, /*InsnID*/1, 5148 GIM_CheckIsSafeToFold, /*InsnID*/2, 5149 // (or:{ *:[i32] } (add:{ *:[i32] } GR32:{ *:[i32] }:$src, 1:{ *:[i32] }), (xor:{ *:[i32] } GR32:{ *:[i32] }:$src, -1:{ *:[i32] })) => (T1MSKC32rr:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src) 5150 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::T1MSKC32rr, 5151 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 5152 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src 5153 GIR_EraseFromParent, /*InsnID*/0, 5154 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5155 // GIR_Coverage, 22883, 5156 GIR_Done, 5157 // Label 429: @10009 5158 GIM_Try, /*On fail goto*//*Label 430*/ 10084, // Rule ID 22869 // 5159 GIM_CheckFeatures, GIFBS_HasTBM, 5160 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID, 5161 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 5162 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, 5163 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, 5164 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, 5165 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] 5166 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ADD, 5167 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, 5168 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, 5169 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/X86::GR32RegClassID, 5170 GIM_CheckConstantInt, /*MI*/2, /*Op*/2, 1, 5171 GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1, 5172 // MIs[0] src 5173 GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, 5174 GIM_CheckIsSafeToFold, /*InsnID*/1, 5175 GIM_CheckIsSafeToFold, /*InsnID*/2, 5176 // (or:{ *:[i32] } (xor:{ *:[i32] } (add:{ *:[i32] } GR32:{ *:[i32] }:$src, 1:{ *:[i32] }), -1:{ *:[i32] }), GR32:{ *:[i32] }:$src) => (BLCI32rr:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src) 5177 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLCI32rr, 5178 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 5179 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src 5180 GIR_EraseFromParent, /*InsnID*/0, 5181 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5182 // GIR_Coverage, 22869, 5183 GIR_Done, 5184 // Label 430: @10084 5185 GIM_Try, /*On fail goto*//*Label 431*/ 10159, // Rule ID 15938 // 5186 GIM_CheckFeatures, GIFBS_HasTBM, 5187 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 5188 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID, 5189 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 5190 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, 5191 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, 5192 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, 5193 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::GR32RegClassID, 5194 GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1, 5195 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] 5196 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ADD, 5197 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, 5198 // MIs[2] src 5199 GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, 5200 GIM_CheckConstantInt, /*MI*/2, /*Op*/2, -1, 5201 GIM_CheckIsSafeToFold, /*InsnID*/1, 5202 GIM_CheckIsSafeToFold, /*InsnID*/2, 5203 // (or:{ *:[i32] } (xor:{ *:[i32] } GR32:{ *:[i32] }:$src, -1:{ *:[i32] }), (add:{ *:[i32] } GR32:{ *:[i32] }:$src, -1:{ *:[i32] })) => (BLSIC32rr:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src) 5204 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLSIC32rr, 5205 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 5206 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src 5207 GIR_EraseFromParent, /*InsnID*/0, 5208 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5209 // GIR_Coverage, 15938, 5210 GIR_Done, 5211 // Label 431: @10159 5212 GIM_Try, /*On fail goto*//*Label 432*/ 10234, // Rule ID 15940 // 5213 GIM_CheckFeatures, GIFBS_HasTBM, 5214 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 5215 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID, 5216 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 5217 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, 5218 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, 5219 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, 5220 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::GR32RegClassID, 5221 GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1, 5222 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] 5223 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ADD, 5224 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, 5225 // MIs[2] src 5226 GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, 5227 GIM_CheckConstantInt, /*MI*/2, /*Op*/2, 1, 5228 GIM_CheckIsSafeToFold, /*InsnID*/1, 5229 GIM_CheckIsSafeToFold, /*InsnID*/2, 5230 // (or:{ *:[i32] } (xor:{ *:[i32] } GR32:{ *:[i32] }:$src, -1:{ *:[i32] }), (add:{ *:[i32] } GR32:{ *:[i32] }:$src, 1:{ *:[i32] })) => (T1MSKC32rr:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src) 5231 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::T1MSKC32rr, 5232 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 5233 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src 5234 GIR_EraseFromParent, /*InsnID*/0, 5235 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5236 // GIR_Coverage, 15940, 5237 GIR_Done, 5238 // Label 432: @10234 5239 GIM_Try, /*On fail goto*//*Label 433*/ 10309, // Rule ID 15926 // 5240 GIM_CheckFeatures, GIFBS_HasTBM, 5241 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 5242 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID, 5243 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR32RegClassID, 5244 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 5245 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, 5246 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, 5247 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, 5248 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] 5249 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ADD, 5250 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, 5251 // MIs[2] src 5252 GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/0, /*OtherOpIdx*/1, 5253 GIM_CheckConstantInt, /*MI*/2, /*Op*/2, 1, 5254 GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1, 5255 GIM_CheckIsSafeToFold, /*InsnID*/1, 5256 GIM_CheckIsSafeToFold, /*InsnID*/2, 5257 // (or:{ *:[i32] } GR32:{ *:[i32] }:$src, (xor:{ *:[i32] } (add:{ *:[i32] } GR32:{ *:[i32] }:$src, 1:{ *:[i32] }), -1:{ *:[i32] })) => (BLCI32rr:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src) 5258 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLCI32rr, 5259 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 5260 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 5261 GIR_EraseFromParent, /*InsnID*/0, 5262 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5263 // GIR_Coverage, 15926, 5264 GIR_Done, 5265 // Label 433: @10309 5266 GIM_Try, /*On fail goto*//*Label 434*/ 10363, // Rule ID 22877 // 5267 GIM_CheckFeatures, GIFBS_HasTBM, 5268 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID, 5269 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 5270 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD, 5271 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, 5272 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, 5273 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::GR32RegClassID, 5274 GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 1, 5275 // MIs[0] src 5276 GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, 5277 GIM_CheckIsSafeToFold, /*InsnID*/1, 5278 // (or:{ *:[i32] } (add:{ *:[i32] } GR32:{ *:[i32] }:$src, 1:{ *:[i32] }), GR32:{ *:[i32] }:$src) => (BLCS32rr:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src) 5279 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLCS32rr, 5280 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 5281 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src 5282 GIR_EraseFromParent, /*InsnID*/0, 5283 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5284 // GIR_Coverage, 22877, 5285 GIR_Done, 5286 // Label 434: @10363 5287 GIM_Try, /*On fail goto*//*Label 435*/ 10417, // Rule ID 22879 // 5288 GIM_CheckFeatures, GIFBS_HasTBM, 5289 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID, 5290 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 5291 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD, 5292 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, 5293 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, 5294 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::GR32RegClassID, 5295 GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1, 5296 // MIs[0] src 5297 GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, 5298 GIM_CheckIsSafeToFold, /*InsnID*/1, 5299 // (or:{ *:[i32] } (add:{ *:[i32] } GR32:{ *:[i32] }:$src, -1:{ *:[i32] }), GR32:{ *:[i32] }:$src) => (BLSFILL32rr:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src) 5300 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLSFILL32rr, 5301 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 5302 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src 5303 GIR_EraseFromParent, /*InsnID*/0, 5304 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5305 // GIR_Coverage, 22879, 5306 GIR_Done, 5307 // Label 435: @10417 5308 GIM_Try, /*On fail goto*//*Label 436*/ 10521, // Rule ID 23899 // 5309 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 5310 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID, 5311 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 5312 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SHL, 5313 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, 5314 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s8, 5315 GIM_CheckConstantInt, /*MI*/1, /*Op*/1, 1, 5316 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/X86::GR8RegClassID, 5317 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::GR32RegClassID, 5318 GIM_CheckIsSafeToFold, /*InsnID*/1, 5319 // (or:{ *:[i32] } (shl:{ *:[i32] } 1:{ *:[i32] }, GR8:{ *:[i8] }:$src2), GR32:{ *:[i32] }:$src1) => (BTS32rr:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src1, (INSERT_SUBREG:{ *:[i32] } (IMPLICIT_DEF:{ *:[i32] }), GR8:{ *:[i8] }:$src2, sub_8bit:{ *:[i32] })) 5320 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, 5321 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, 5322 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, 5323 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 5324 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 5325 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, 5326 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 5327 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, 5328 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // src2 5329 GIR_AddImm, /*InsnID*/1, /*Imm*/1, 5330 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID, 5331 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID, 5332 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, X86::GR8RegClassID, 5333 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BTS32rr, 5334 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 5335 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 5336 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 5337 GIR_EraseFromParent, /*InsnID*/0, 5338 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5339 // GIR_Coverage, 23899, 5340 GIR_Done, 5341 // Label 436: @10521 5342 GIM_Try, /*On fail goto*//*Label 437*/ 10575, // Rule ID 22871 // 5343 GIM_CheckFeatures, GIFBS_HasTBM, 5344 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID, 5345 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 5346 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SUB, 5347 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, 5348 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, 5349 GIM_CheckConstantInt, /*MI*/1, /*Op*/1, -2, 5350 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/X86::GR32RegClassID, 5351 // MIs[0] src 5352 GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, 5353 GIM_CheckIsSafeToFold, /*InsnID*/1, 5354 // (or:{ *:[i32] } (sub:{ *:[i32] } -2:{ *:[i32] }, GR32:{ *:[i32] }:$src), GR32:{ *:[i32] }:$src) => (BLCI32rr:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src) 5355 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLCI32rr, 5356 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 5357 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src 5358 GIR_EraseFromParent, /*InsnID*/0, 5359 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5360 // GIR_Coverage, 22871, 5361 GIR_Done, 5362 // Label 437: @10575 5363 GIM_Try, /*On fail goto*//*Label 438*/ 10629, // Rule ID 15934 // 5364 GIM_CheckFeatures, GIFBS_HasTBM, 5365 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 5366 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID, 5367 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR32RegClassID, 5368 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 5369 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD, 5370 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, 5371 // MIs[1] src 5372 GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/1, /*OtherMI*/0, /*OtherOpIdx*/1, 5373 GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 1, 5374 GIM_CheckIsSafeToFold, /*InsnID*/1, 5375 // (or:{ *:[i32] } GR32:{ *:[i32] }:$src, (add:{ *:[i32] } GR32:{ *:[i32] }:$src, 1:{ *:[i32] })) => (BLCS32rr:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src) 5376 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLCS32rr, 5377 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 5378 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 5379 GIR_EraseFromParent, /*InsnID*/0, 5380 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5381 // GIR_Coverage, 15934, 5382 GIR_Done, 5383 // Label 438: @10629 5384 GIM_Try, /*On fail goto*//*Label 439*/ 10683, // Rule ID 15936 // 5385 GIM_CheckFeatures, GIFBS_HasTBM, 5386 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 5387 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID, 5388 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR32RegClassID, 5389 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 5390 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD, 5391 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, 5392 // MIs[1] src 5393 GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/1, /*OtherMI*/0, /*OtherOpIdx*/1, 5394 GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1, 5395 GIM_CheckIsSafeToFold, /*InsnID*/1, 5396 // (or:{ *:[i32] } GR32:{ *:[i32] }:$src, (add:{ *:[i32] } GR32:{ *:[i32] }:$src, -1:{ *:[i32] })) => (BLSFILL32rr:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src) 5397 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLSFILL32rr, 5398 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 5399 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 5400 GIR_EraseFromParent, /*InsnID*/0, 5401 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5402 // GIR_Coverage, 15936, 5403 GIR_Done, 5404 // Label 439: @10683 5405 GIM_Try, /*On fail goto*//*Label 440*/ 10787, // Rule ID 20984 // 5406 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 5407 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID, 5408 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR32RegClassID, 5409 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 5410 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SHL, 5411 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, 5412 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s8, 5413 GIM_CheckConstantInt, /*MI*/1, /*Op*/1, 1, 5414 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/X86::GR8RegClassID, 5415 GIM_CheckIsSafeToFold, /*InsnID*/1, 5416 // (or:{ *:[i32] } GR32:{ *:[i32] }:$src1, (shl:{ *:[i32] } 1:{ *:[i32] }, GR8:{ *:[i8] }:$src2)) => (BTS32rr:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src1, (INSERT_SUBREG:{ *:[i32] } (IMPLICIT_DEF:{ *:[i32] }), GR8:{ *:[i8] }:$src2, sub_8bit:{ *:[i32] })) 5417 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, 5418 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, 5419 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, 5420 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 5421 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 5422 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, 5423 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 5424 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, 5425 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // src2 5426 GIR_AddImm, /*InsnID*/1, /*Imm*/1, 5427 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID, 5428 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID, 5429 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, X86::GR8RegClassID, 5430 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BTS32rr, 5431 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 5432 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 5433 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 5434 GIR_EraseFromParent, /*InsnID*/0, 5435 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5436 // GIR_Coverage, 20984, 5437 GIR_Done, 5438 // Label 440: @10787 5439 GIM_Try, /*On fail goto*//*Label 441*/ 10841, // Rule ID 15928 // 5440 GIM_CheckFeatures, GIFBS_HasTBM, 5441 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 5442 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID, 5443 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR32RegClassID, 5444 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 5445 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SUB, 5446 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, 5447 GIM_CheckConstantInt, /*MI*/1, /*Op*/1, -2, 5448 // MIs[1] src 5449 GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/2, /*OtherMI*/0, /*OtherOpIdx*/1, 5450 GIM_CheckIsSafeToFold, /*InsnID*/1, 5451 // (or:{ *:[i32] } GR32:{ *:[i32] }:$src, (sub:{ *:[i32] } -2:{ *:[i32] }, GR32:{ *:[i32] }:$src)) => (BLCI32rr:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src) 5452 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLCI32rr, 5453 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 5454 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 5455 GIR_EraseFromParent, /*InsnID*/0, 5456 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5457 // GIR_Coverage, 15928, 5458 GIR_Done, 5459 // Label 441: @10841 5460 GIM_Try, /*On fail goto*//*Label 442*/ 10886, // Rule ID 15677 // 5461 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 5462 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID, 5463 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR32RegClassID, 5464 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 5465 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 5466 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_i32immSExt8, 5467 // MIs[1] Operand 1 5468 // No operand predicates 5469 GIM_CheckIsSafeToFold, /*InsnID*/1, 5470 // (or:{ *:[i32] } GR32:{ *:[i32] }:$src1, (imm:{ *:[i32] })<<P:Predicate_i32immSExt8>>:$src2) => (OR32ri8:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src1, (imm:{ *:[i32] })<<P:Predicate_i32immSExt8>>:$src2) 5471 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::OR32ri8, 5472 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 5473 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 5474 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // src2 5475 GIR_EraseFromParent, /*InsnID*/0, 5476 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5477 // GIR_Coverage, 15677, 5478 GIR_Done, 5479 // Label 442: @10886 5480 GIM_Try, /*On fail goto*//*Label 443*/ 10928, // Rule ID 15675 // 5481 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 5482 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID, 5483 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR32RegClassID, 5484 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 5485 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 5486 // MIs[1] Operand 1 5487 // No operand predicates 5488 GIM_CheckIsSafeToFold, /*InsnID*/1, 5489 // (or:{ *:[i32] } GR32:{ *:[i32] }:$src1, (imm:{ *:[i32] }):$src2) => (OR32ri:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src1, (imm:{ *:[i32] }):$src2) 5490 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::OR32ri, 5491 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 5492 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 5493 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // src2 5494 GIR_EraseFromParent, /*InsnID*/0, 5495 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5496 // GIR_Coverage, 15675, 5497 GIR_Done, 5498 // Label 443: @10928 5499 GIM_Try, /*On fail goto*//*Label 444*/ 10956, // Rule ID 15667 // 5500 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 5501 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID, 5502 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR32RegClassID, 5503 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::GR32RegClassID, 5504 // (or:{ *:[i32] } GR32:{ *:[i32] }:$src1, GR32:{ *:[i32] }:$src2) => (OR32rr:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src1, GR32:{ *:[i32] }:$src2) 5505 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::OR32rr, 5506 GIR_AddImplicitDef, /*InsnID*/0, X86::EFLAGS, 5507 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5508 // GIR_Coverage, 15667, 5509 GIR_Done, 5510 // Label 444: @10956 5511 GIM_Reject, 5512 // Label 427: @10957 5513 GIM_Reject, 5514 // Label 397: @10958 5515 GIM_Try, /*On fail goto*//*Label 445*/ 12065, 5516 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 5517 GIM_Try, /*On fail goto*//*Label 446*/ 11039, // Rule ID 22882 // 5518 GIM_CheckFeatures, GIFBS_HasTBM, 5519 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 5520 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID, 5521 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 5522 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD, 5523 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, 5524 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, 5525 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::GR64RegClassID, 5526 GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1, 5527 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] 5528 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_XOR, 5529 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, 5530 // MIs[2] src 5531 GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, 5532 GIM_CheckConstantInt, /*MI*/2, /*Op*/2, -1, 5533 GIM_CheckIsSafeToFold, /*InsnID*/1, 5534 GIM_CheckIsSafeToFold, /*InsnID*/2, 5535 // (or:{ *:[i64] } (add:{ *:[i64] } GR64:{ *:[i64] }:$src, -1:{ *:[i64] }), (xor:{ *:[i64] } GR64:{ *:[i64] }:$src, -1:{ *:[i64] })) => (BLSIC64rr:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src) 5536 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLSIC64rr, 5537 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 5538 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src 5539 GIR_EraseFromParent, /*InsnID*/0, 5540 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5541 // GIR_Coverage, 22882, 5542 GIR_Done, 5543 // Label 446: @11039 5544 GIM_Try, /*On fail goto*//*Label 447*/ 11114, // Rule ID 22884 // 5545 GIM_CheckFeatures, GIFBS_HasTBM, 5546 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 5547 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID, 5548 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 5549 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD, 5550 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, 5551 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, 5552 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::GR64RegClassID, 5553 GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 1, 5554 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] 5555 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_XOR, 5556 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, 5557 // MIs[2] src 5558 GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, 5559 GIM_CheckConstantInt, /*MI*/2, /*Op*/2, -1, 5560 GIM_CheckIsSafeToFold, /*InsnID*/1, 5561 GIM_CheckIsSafeToFold, /*InsnID*/2, 5562 // (or:{ *:[i64] } (add:{ *:[i64] } GR64:{ *:[i64] }:$src, 1:{ *:[i64] }), (xor:{ *:[i64] } GR64:{ *:[i64] }:$src, -1:{ *:[i64] })) => (T1MSKC64rr:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src) 5563 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::T1MSKC64rr, 5564 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 5565 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src 5566 GIR_EraseFromParent, /*InsnID*/0, 5567 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5568 // GIR_Coverage, 22884, 5569 GIR_Done, 5570 // Label 447: @11114 5571 GIM_Try, /*On fail goto*//*Label 448*/ 11189, // Rule ID 22870 // 5572 GIM_CheckFeatures, GIFBS_HasTBM, 5573 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID, 5574 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 5575 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, 5576 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, 5577 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, 5578 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] 5579 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ADD, 5580 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, 5581 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, 5582 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/X86::GR64RegClassID, 5583 GIM_CheckConstantInt, /*MI*/2, /*Op*/2, 1, 5584 GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1, 5585 // MIs[0] src 5586 GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, 5587 GIM_CheckIsSafeToFold, /*InsnID*/1, 5588 GIM_CheckIsSafeToFold, /*InsnID*/2, 5589 // (or:{ *:[i64] } (xor:{ *:[i64] } (add:{ *:[i64] } GR64:{ *:[i64] }:$src, 1:{ *:[i64] }), -1:{ *:[i64] }), GR64:{ *:[i64] }:$src) => (BLCI64rr:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src) 5590 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLCI64rr, 5591 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 5592 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src 5593 GIR_EraseFromParent, /*InsnID*/0, 5594 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5595 // GIR_Coverage, 22870, 5596 GIR_Done, 5597 // Label 448: @11189 5598 GIM_Try, /*On fail goto*//*Label 449*/ 11264, // Rule ID 15939 // 5599 GIM_CheckFeatures, GIFBS_HasTBM, 5600 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 5601 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID, 5602 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 5603 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, 5604 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, 5605 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, 5606 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::GR64RegClassID, 5607 GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1, 5608 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] 5609 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ADD, 5610 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, 5611 // MIs[2] src 5612 GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, 5613 GIM_CheckConstantInt, /*MI*/2, /*Op*/2, -1, 5614 GIM_CheckIsSafeToFold, /*InsnID*/1, 5615 GIM_CheckIsSafeToFold, /*InsnID*/2, 5616 // (or:{ *:[i64] } (xor:{ *:[i64] } GR64:{ *:[i64] }:$src, -1:{ *:[i64] }), (add:{ *:[i64] } GR64:{ *:[i64] }:$src, -1:{ *:[i64] })) => (BLSIC64rr:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src) 5617 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLSIC64rr, 5618 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 5619 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src 5620 GIR_EraseFromParent, /*InsnID*/0, 5621 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5622 // GIR_Coverage, 15939, 5623 GIR_Done, 5624 // Label 449: @11264 5625 GIM_Try, /*On fail goto*//*Label 450*/ 11339, // Rule ID 15941 // 5626 GIM_CheckFeatures, GIFBS_HasTBM, 5627 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 5628 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID, 5629 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 5630 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, 5631 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, 5632 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, 5633 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::GR64RegClassID, 5634 GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1, 5635 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] 5636 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ADD, 5637 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, 5638 // MIs[2] src 5639 GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, 5640 GIM_CheckConstantInt, /*MI*/2, /*Op*/2, 1, 5641 GIM_CheckIsSafeToFold, /*InsnID*/1, 5642 GIM_CheckIsSafeToFold, /*InsnID*/2, 5643 // (or:{ *:[i64] } (xor:{ *:[i64] } GR64:{ *:[i64] }:$src, -1:{ *:[i64] }), (add:{ *:[i64] } GR64:{ *:[i64] }:$src, 1:{ *:[i64] })) => (T1MSKC64rr:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src) 5644 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::T1MSKC64rr, 5645 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 5646 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src 5647 GIR_EraseFromParent, /*InsnID*/0, 5648 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5649 // GIR_Coverage, 15941, 5650 GIR_Done, 5651 // Label 450: @11339 5652 GIM_Try, /*On fail goto*//*Label 451*/ 11414, // Rule ID 15927 // 5653 GIM_CheckFeatures, GIFBS_HasTBM, 5654 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 5655 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID, 5656 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR64RegClassID, 5657 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 5658 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, 5659 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, 5660 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, 5661 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] 5662 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ADD, 5663 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, 5664 // MIs[2] src 5665 GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/0, /*OtherOpIdx*/1, 5666 GIM_CheckConstantInt, /*MI*/2, /*Op*/2, 1, 5667 GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1, 5668 GIM_CheckIsSafeToFold, /*InsnID*/1, 5669 GIM_CheckIsSafeToFold, /*InsnID*/2, 5670 // (or:{ *:[i64] } GR64:{ *:[i64] }:$src, (xor:{ *:[i64] } (add:{ *:[i64] } GR64:{ *:[i64] }:$src, 1:{ *:[i64] }), -1:{ *:[i64] })) => (BLCI64rr:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src) 5671 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLCI64rr, 5672 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 5673 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 5674 GIR_EraseFromParent, /*InsnID*/0, 5675 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5676 // GIR_Coverage, 15927, 5677 GIR_Done, 5678 // Label 451: @11414 5679 GIM_Try, /*On fail goto*//*Label 452*/ 11468, // Rule ID 22878 // 5680 GIM_CheckFeatures, GIFBS_HasTBM, 5681 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID, 5682 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 5683 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD, 5684 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, 5685 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, 5686 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::GR64RegClassID, 5687 GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 1, 5688 // MIs[0] src 5689 GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, 5690 GIM_CheckIsSafeToFold, /*InsnID*/1, 5691 // (or:{ *:[i64] } (add:{ *:[i64] } GR64:{ *:[i64] }:$src, 1:{ *:[i64] }), GR64:{ *:[i64] }:$src) => (BLCS64rr:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src) 5692 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLCS64rr, 5693 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 5694 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src 5695 GIR_EraseFromParent, /*InsnID*/0, 5696 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5697 // GIR_Coverage, 22878, 5698 GIR_Done, 5699 // Label 452: @11468 5700 GIM_Try, /*On fail goto*//*Label 453*/ 11522, // Rule ID 22880 // 5701 GIM_CheckFeatures, GIFBS_HasTBM, 5702 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID, 5703 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 5704 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD, 5705 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, 5706 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, 5707 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::GR64RegClassID, 5708 GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1, 5709 // MIs[0] src 5710 GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, 5711 GIM_CheckIsSafeToFold, /*InsnID*/1, 5712 // (or:{ *:[i64] } (add:{ *:[i64] } GR64:{ *:[i64] }:$src, -1:{ *:[i64] }), GR64:{ *:[i64] }:$src) => (BLSFILL64rr:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src) 5713 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLSFILL64rr, 5714 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 5715 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src 5716 GIR_EraseFromParent, /*InsnID*/0, 5717 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5718 // GIR_Coverage, 22880, 5719 GIR_Done, 5720 // Label 453: @11522 5721 GIM_Try, /*On fail goto*//*Label 454*/ 11626, // Rule ID 23905 // 5722 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 5723 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID, 5724 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 5725 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SHL, 5726 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, 5727 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s8, 5728 GIM_CheckConstantInt, /*MI*/1, /*Op*/1, 1, 5729 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/X86::GR8RegClassID, 5730 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::GR64RegClassID, 5731 GIM_CheckIsSafeToFold, /*InsnID*/1, 5732 // (or:{ *:[i64] } (shl:{ *:[i64] } 1:{ *:[i64] }, GR8:{ *:[i8] }:$src2), GR64:{ *:[i64] }:$src1) => (BTS64rr:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src1, (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), GR8:{ *:[i8] }:$src2, sub_8bit:{ *:[i32] })) 5733 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, 5734 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, 5735 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, 5736 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 5737 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 5738 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, 5739 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 5740 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, 5741 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // src2 5742 GIR_AddImm, /*InsnID*/1, /*Imm*/1, 5743 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, X86::GR64_with_sub_8bitRegClassID, 5744 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, X86::GR64_with_sub_8bitRegClassID, 5745 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, X86::GR8RegClassID, 5746 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BTS64rr, 5747 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 5748 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 5749 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 5750 GIR_EraseFromParent, /*InsnID*/0, 5751 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5752 // GIR_Coverage, 23905, 5753 GIR_Done, 5754 // Label 454: @11626 5755 GIM_Try, /*On fail goto*//*Label 455*/ 11680, // Rule ID 22872 // 5756 GIM_CheckFeatures, GIFBS_HasTBM, 5757 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID, 5758 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 5759 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SUB, 5760 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, 5761 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, 5762 GIM_CheckConstantInt, /*MI*/1, /*Op*/1, -2, 5763 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/X86::GR64RegClassID, 5764 // MIs[0] src 5765 GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, 5766 GIM_CheckIsSafeToFold, /*InsnID*/1, 5767 // (or:{ *:[i64] } (sub:{ *:[i64] } -2:{ *:[i64] }, GR64:{ *:[i64] }:$src), GR64:{ *:[i64] }:$src) => (BLCI64rr:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src) 5768 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLCI64rr, 5769 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 5770 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src 5771 GIR_EraseFromParent, /*InsnID*/0, 5772 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5773 // GIR_Coverage, 22872, 5774 GIR_Done, 5775 // Label 455: @11680 5776 GIM_Try, /*On fail goto*//*Label 456*/ 11734, // Rule ID 15935 // 5777 GIM_CheckFeatures, GIFBS_HasTBM, 5778 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 5779 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID, 5780 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR64RegClassID, 5781 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 5782 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD, 5783 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, 5784 // MIs[1] src 5785 GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/1, /*OtherMI*/0, /*OtherOpIdx*/1, 5786 GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 1, 5787 GIM_CheckIsSafeToFold, /*InsnID*/1, 5788 // (or:{ *:[i64] } GR64:{ *:[i64] }:$src, (add:{ *:[i64] } GR64:{ *:[i64] }:$src, 1:{ *:[i64] })) => (BLCS64rr:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src) 5789 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLCS64rr, 5790 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 5791 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 5792 GIR_EraseFromParent, /*InsnID*/0, 5793 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5794 // GIR_Coverage, 15935, 5795 GIR_Done, 5796 // Label 456: @11734 5797 GIM_Try, /*On fail goto*//*Label 457*/ 11788, // Rule ID 15937 // 5798 GIM_CheckFeatures, GIFBS_HasTBM, 5799 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 5800 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID, 5801 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR64RegClassID, 5802 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 5803 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD, 5804 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, 5805 // MIs[1] src 5806 GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/1, /*OtherMI*/0, /*OtherOpIdx*/1, 5807 GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1, 5808 GIM_CheckIsSafeToFold, /*InsnID*/1, 5809 // (or:{ *:[i64] } GR64:{ *:[i64] }:$src, (add:{ *:[i64] } GR64:{ *:[i64] }:$src, -1:{ *:[i64] })) => (BLSFILL64rr:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src) 5810 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLSFILL64rr, 5811 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 5812 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 5813 GIR_EraseFromParent, /*InsnID*/0, 5814 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5815 // GIR_Coverage, 15937, 5816 GIR_Done, 5817 // Label 457: @11788 5818 GIM_Try, /*On fail goto*//*Label 458*/ 11892, // Rule ID 20990 // 5819 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 5820 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID, 5821 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR64RegClassID, 5822 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 5823 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SHL, 5824 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, 5825 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s8, 5826 GIM_CheckConstantInt, /*MI*/1, /*Op*/1, 1, 5827 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/X86::GR8RegClassID, 5828 GIM_CheckIsSafeToFold, /*InsnID*/1, 5829 // (or:{ *:[i64] } GR64:{ *:[i64] }:$src1, (shl:{ *:[i64] } 1:{ *:[i64] }, GR8:{ *:[i8] }:$src2)) => (BTS64rr:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src1, (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), GR8:{ *:[i8] }:$src2, sub_8bit:{ *:[i32] })) 5830 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, 5831 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, 5832 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, 5833 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 5834 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 5835 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, 5836 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 5837 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, 5838 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // src2 5839 GIR_AddImm, /*InsnID*/1, /*Imm*/1, 5840 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, X86::GR64_with_sub_8bitRegClassID, 5841 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, X86::GR64_with_sub_8bitRegClassID, 5842 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, X86::GR8RegClassID, 5843 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BTS64rr, 5844 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 5845 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 5846 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 5847 GIR_EraseFromParent, /*InsnID*/0, 5848 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5849 // GIR_Coverage, 20990, 5850 GIR_Done, 5851 // Label 458: @11892 5852 GIM_Try, /*On fail goto*//*Label 459*/ 11946, // Rule ID 15929 // 5853 GIM_CheckFeatures, GIFBS_HasTBM, 5854 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 5855 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID, 5856 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR64RegClassID, 5857 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 5858 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SUB, 5859 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, 5860 GIM_CheckConstantInt, /*MI*/1, /*Op*/1, -2, 5861 // MIs[1] src 5862 GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/2, /*OtherMI*/0, /*OtherOpIdx*/1, 5863 GIM_CheckIsSafeToFold, /*InsnID*/1, 5864 // (or:{ *:[i64] } GR64:{ *:[i64] }:$src, (sub:{ *:[i64] } -2:{ *:[i64] }, GR64:{ *:[i64] }:$src)) => (BLCI64rr:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src) 5865 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLCI64rr, 5866 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 5867 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 5868 GIR_EraseFromParent, /*InsnID*/0, 5869 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5870 // GIR_Coverage, 15929, 5871 GIR_Done, 5872 // Label 459: @11946 5873 GIM_Try, /*On fail goto*//*Label 460*/ 11991, // Rule ID 15678 // 5874 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 5875 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID, 5876 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR64RegClassID, 5877 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 5878 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 5879 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_i64immSExt8, 5880 // MIs[1] Operand 1 5881 // No operand predicates 5882 GIM_CheckIsSafeToFold, /*InsnID*/1, 5883 // (or:{ *:[i64] } GR64:{ *:[i64] }:$src1, (imm:{ *:[i64] })<<P:Predicate_i64immSExt8>>:$src2) => (OR64ri8:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src1, (imm:{ *:[i64] })<<P:Predicate_i64immSExt8>>:$src2) 5884 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::OR64ri8, 5885 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 5886 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 5887 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // src2 5888 GIR_EraseFromParent, /*InsnID*/0, 5889 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5890 // GIR_Coverage, 15678, 5891 GIR_Done, 5892 // Label 460: @11991 5893 GIM_Try, /*On fail goto*//*Label 461*/ 12036, // Rule ID 15679 // 5894 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 5895 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID, 5896 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR64RegClassID, 5897 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 5898 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 5899 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_i64immSExt32, 5900 // MIs[1] Operand 1 5901 // No operand predicates 5902 GIM_CheckIsSafeToFold, /*InsnID*/1, 5903 // (or:{ *:[i64] } GR64:{ *:[i64] }:$src1, (imm:{ *:[i64] })<<P:Predicate_i64immSExt32>>:$src2) => (OR64ri32:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src1, (imm:{ *:[i64] })<<P:Predicate_i64immSExt32>>:$src2) 5904 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::OR64ri32, 5905 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 5906 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 5907 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // src2 5908 GIR_EraseFromParent, /*InsnID*/0, 5909 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5910 // GIR_Coverage, 15679, 5911 GIR_Done, 5912 // Label 461: @12036 5913 GIM_Try, /*On fail goto*//*Label 462*/ 12064, // Rule ID 15668 // 5914 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 5915 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID, 5916 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR64RegClassID, 5917 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::GR64RegClassID, 5918 // (or:{ *:[i64] } GR64:{ *:[i64] }:$src1, GR64:{ *:[i64] }:$src2) => (OR64rr:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src1, GR64:{ *:[i64] }:$src2) 5919 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::OR64rr, 5920 GIR_AddImplicitDef, /*InsnID*/0, X86::EFLAGS, 5921 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5922 // GIR_Coverage, 15668, 5923 GIR_Done, 5924 // Label 462: @12064 5925 GIM_Reject, 5926 // Label 445: @12065 5927 GIM_Reject, 5928 // Label 398: @12066 5929 GIM_Try, /*On fail goto*//*Label 463*/ 12158, // Rule ID 17932 // 5930 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s1, 5931 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s1, 5932 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VK2RegClassID, 5933 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VK2RegClassID, 5934 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VK2RegClassID, 5935 // (or:{ *:[v2i1] } VK2:{ *:[v2i1] }:$src1, VK2:{ *:[v2i1] }:$src2) => (COPY_TO_REGCLASS:{ *:[v2i1] } (KORWrr:{ *:[v16i1] } (COPY_TO_REGCLASS:{ *:[v16i1] } VK2:{ *:[v2i1] }:$src1, VK16:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v16i1] } VK2:{ *:[v2i1] }:$src2, VK16:{ *:[i32] })), VK2:{ *:[i32] }) 5936 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s1, 5937 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s1, 5938 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s1, 5939 GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::COPY, 5940 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, 5941 GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // src2 5942 GIR_ConstrainSelectedInstOperands, /*InsnID*/3, 5943 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY, 5944 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 5945 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src1 5946 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 5947 GIR_BuildMI, /*InsnID*/1, /*Opcode*/X86::KORWrr, 5948 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 5949 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, 5950 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/2, /*TempRegFlags*/0, 5951 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 5952 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 5953 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 5954 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 5955 GIR_EraseFromParent, /*InsnID*/0, 5956 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, X86::VK2RegClassID, 5957 // GIR_Coverage, 17932, 5958 GIR_Done, 5959 // Label 463: @12158 5960 GIM_Reject, 5961 // Label 399: @12159 5962 GIM_Try, /*On fail goto*//*Label 464*/ 12239, 5963 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, 5964 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 5965 GIM_Try, /*On fail goto*//*Label 465*/ 12192, // Rule ID 1848 // 5966 GIM_CheckFeatures, GIFBS_HasAVX_NoVLX, 5967 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 5968 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 5969 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 5970 // (or:{ *:[v2i64] } VR128:{ *:[v2i64] }:$src1, VR128:{ *:[v2i64] }:$src2) => (VPORrr:{ *:[v2i64] } VR128:{ *:[v2i64] }:$src1, VR128:{ *:[v2i64] }:$src2) 5971 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPORrr, 5972 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5973 // GIR_Coverage, 1848, 5974 GIR_Done, 5975 // Label 465: @12192 5976 GIM_Try, /*On fail goto*//*Label 466*/ 12215, // Rule ID 1850 // 5977 GIM_CheckFeatures, GIFBS_UseSSE2, 5978 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 5979 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 5980 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 5981 // (or:{ *:[v2i64] } VR128:{ *:[v2i64] }:$src1, VR128:{ *:[v2i64] }:$src2) => (PORrr:{ *:[v2i64] } VR128:{ *:[v2i64] }:$src1, VR128:{ *:[v2i64] }:$src2) 5982 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::PORrr, 5983 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5984 // GIR_Coverage, 1850, 5985 GIR_Done, 5986 // Label 466: @12215 5987 GIM_Try, /*On fail goto*//*Label 467*/ 12238, // Rule ID 5397 // 5988 GIM_CheckFeatures, GIFBS_HasAVX512_HasVLX, 5989 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID, 5990 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID, 5991 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128XRegClassID, 5992 // (or:{ *:[v2i64] } VR128X:{ *:[v2i64] }:$src1, VR128X:{ *:[v2i64] }:$src2) => (VPORQZ128rr:{ *:[v2i64] } VR128X:{ *:[v2i64] }:$src1, VR128X:{ *:[v2i64] }:$src2) 5993 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPORQZ128rr, 5994 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5995 // GIR_Coverage, 5397, 5996 GIR_Done, 5997 // Label 467: @12238 5998 GIM_Reject, 5999 // Label 464: @12239 6000 GIM_Reject, 6001 // Label 400: @12240 6002 GIM_Try, /*On fail goto*//*Label 468*/ 12332, // Rule ID 17933 // 6003 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s1, 6004 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s1, 6005 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VK4RegClassID, 6006 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VK4RegClassID, 6007 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VK4RegClassID, 6008 // (or:{ *:[v4i1] } VK4:{ *:[v4i1] }:$src1, VK4:{ *:[v4i1] }:$src2) => (COPY_TO_REGCLASS:{ *:[v4i1] } (KORWrr:{ *:[v16i1] } (COPY_TO_REGCLASS:{ *:[v16i1] } VK4:{ *:[v4i1] }:$src1, VK16:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v16i1] } VK4:{ *:[v4i1] }:$src2, VK16:{ *:[i32] })), VK4:{ *:[i32] }) 6009 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s1, 6010 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s1, 6011 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s1, 6012 GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::COPY, 6013 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, 6014 GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // src2 6015 GIR_ConstrainSelectedInstOperands, /*InsnID*/3, 6016 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY, 6017 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 6018 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src1 6019 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 6020 GIR_BuildMI, /*InsnID*/1, /*Opcode*/X86::KORWrr, 6021 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 6022 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, 6023 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/2, /*TempRegFlags*/0, 6024 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 6025 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 6026 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 6027 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 6028 GIR_EraseFromParent, /*InsnID*/0, 6029 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, X86::VK4RegClassID, 6030 // GIR_Coverage, 17933, 6031 GIR_Done, 6032 // Label 468: @12332 6033 GIM_Reject, 6034 // Label 401: @12333 6035 GIM_Try, /*On fail goto*//*Label 469*/ 12413, 6036 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, 6037 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 6038 GIM_Try, /*On fail goto*//*Label 470*/ 12366, // Rule ID 5424 // 6039 GIM_CheckFeatures, GIFBS_HasAVX512_HasVLX, 6040 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID, 6041 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID, 6042 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128XRegClassID, 6043 // (or:{ *:[v4i32] } VR128X:{ *:[v4i32] }:$src1, VR128X:{ *:[v4i32] }:$src2) => (VPORDZ128rr:{ *:[v4i32] } VR128X:{ *:[v4i32] }:$src1, VR128X:{ *:[v4i32] }:$src2) 6044 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPORDZ128rr, 6045 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6046 // GIR_Coverage, 5424, 6047 GIR_Done, 6048 // Label 470: @12366 6049 GIM_Try, /*On fail goto*//*Label 471*/ 12389, // Rule ID 16598 // 6050 GIM_CheckFeatures, GIFBS_HasAVX_NoVLX, 6051 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 6052 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 6053 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 6054 // (or:{ *:[v4i32] } VR128:{ *:[v4i32] }:$src1, VR128:{ *:[v4i32] }:$src2) => (VPORrr:{ *:[v4i32] } VR128:{ *:[v4i32] }:$src1, VR128:{ *:[v4i32] }:$src2) 6055 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPORrr, 6056 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6057 // GIR_Coverage, 16598, 6058 GIR_Done, 6059 // Label 471: @12389 6060 GIM_Try, /*On fail goto*//*Label 472*/ 12412, // Rule ID 16622 // 6061 GIM_CheckFeatures, GIFBS_UseSSE2, 6062 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 6063 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 6064 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 6065 // (or:{ *:[v4i32] } VR128:{ *:[v4i32] }:$src1, VR128:{ *:[v4i32] }:$src2) => (PORrr:{ *:[v4i32] } VR128:{ *:[v4i32] }:$src1, VR128:{ *:[v4i32] }:$src2) 6066 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::PORrr, 6067 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6068 // GIR_Coverage, 16622, 6069 GIR_Done, 6070 // Label 472: @12412 6071 GIM_Reject, 6072 // Label 469: @12413 6073 GIM_Reject, 6074 // Label 402: @12414 6075 GIM_Try, /*On fail goto*//*Label 473*/ 12494, 6076 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s64, 6077 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s64, 6078 GIM_Try, /*On fail goto*//*Label 474*/ 12447, // Rule ID 1852 // 6079 GIM_CheckFeatures, GIFBS_HasAVX2_NoVLX, 6080 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID, 6081 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256RegClassID, 6082 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256RegClassID, 6083 // (or:{ *:[v4i64] } VR256:{ *:[v4i64] }:$src1, VR256:{ *:[v4i64] }:$src2) => (VPORYrr:{ *:[v4i64] } VR256:{ *:[v4i64] }:$src1, VR256:{ *:[v4i64] }:$src2) 6084 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPORYrr, 6085 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6086 // GIR_Coverage, 1852, 6087 GIR_Done, 6088 // Label 474: @12447 6089 GIM_Try, /*On fail goto*//*Label 475*/ 12470, // Rule ID 5388 // 6090 GIM_CheckFeatures, GIFBS_HasAVX512_HasVLX, 6091 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID, 6092 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID, 6093 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256XRegClassID, 6094 // (or:{ *:[v4i64] } VR256X:{ *:[v4i64] }:$src1, VR256X:{ *:[v4i64] }:$src2) => (VPORQZ256rr:{ *:[v4i64] } VR256X:{ *:[v4i64] }:$src1, VR256X:{ *:[v4i64] }:$src2) 6095 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPORQZ256rr, 6096 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6097 // GIR_Coverage, 5388, 6098 GIR_Done, 6099 // Label 475: @12470 6100 GIM_Try, /*On fail goto*//*Label 476*/ 12493, // Rule ID 16568 // 6101 GIM_CheckFeatures, GIFBS_HasAVX1Only, 6102 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID, 6103 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256RegClassID, 6104 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256RegClassID, 6105 // (or:{ *:[v4i64] } VR256:{ *:[v4i64] }:$src1, VR256:{ *:[v4i64] }:$src2) => (VORPSYrr:{ *:[v4i64] } VR256:{ *:[v4i64] }:$src1, VR256:{ *:[v4i64] }:$src2) 6106 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VORPSYrr, 6107 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6108 // GIR_Coverage, 16568, 6109 GIR_Done, 6110 // Label 476: @12493 6111 GIM_Reject, 6112 // Label 473: @12494 6113 GIM_Reject, 6114 // Label 403: @12495 6115 GIM_Try, /*On fail goto*//*Label 477*/ 12603, 6116 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s1, 6117 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s1, 6118 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VK8RegClassID, 6119 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VK8RegClassID, 6120 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VK8RegClassID, 6121 GIM_Try, /*On fail goto*//*Label 478*/ 12528, // Rule ID 4058 // 6122 GIM_CheckFeatures, GIFBS_HasDQI, 6123 // (or:{ *:[v8i1] } VK8:{ *:[v8i1] }:$src1, VK8:{ *:[v8i1] }:$src2) => (KORBrr:{ *:[v8i1] } VK8:{ *:[v8i1] }:$src1, VK8:{ *:[v8i1] }:$src2) 6124 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::KORBrr, 6125 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6126 // GIR_Coverage, 4058, 6127 GIR_Done, 6128 // Label 478: @12528 6129 GIM_Try, /*On fail goto*//*Label 479*/ 12602, // Rule ID 17930 // 6130 GIM_CheckFeatures, GIFBS_NoDQI, 6131 // (or:{ *:[v8i1] } VK8:{ *:[v8i1] }:$src1, VK8:{ *:[v8i1] }:$src2) => (COPY_TO_REGCLASS:{ *:[v8i1] } (KORWrr:{ *:[v16i1] } (COPY_TO_REGCLASS:{ *:[v16i1] } VK8:{ *:[v8i1] }:$src1, VK16:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v16i1] } VK8:{ *:[v8i1] }:$src2, VK16:{ *:[i32] })), VK8:{ *:[i32] }) 6132 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s1, 6133 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s1, 6134 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s1, 6135 GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::COPY, 6136 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, 6137 GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // src2 6138 GIR_ConstrainSelectedInstOperands, /*InsnID*/3, 6139 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY, 6140 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 6141 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src1 6142 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 6143 GIR_BuildMI, /*InsnID*/1, /*Opcode*/X86::KORWrr, 6144 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 6145 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, 6146 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/2, /*TempRegFlags*/0, 6147 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 6148 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 6149 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 6150 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 6151 GIR_EraseFromParent, /*InsnID*/0, 6152 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, X86::VK8RegClassID, 6153 // GIR_Coverage, 17930, 6154 GIR_Done, 6155 // Label 479: @12602 6156 GIM_Reject, 6157 // Label 477: @12603 6158 GIM_Reject, 6159 // Label 404: @12604 6160 GIM_Try, /*On fail goto*//*Label 480*/ 12684, 6161 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, 6162 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 6163 GIM_Try, /*On fail goto*//*Label 481*/ 12637, // Rule ID 16597 // 6164 GIM_CheckFeatures, GIFBS_HasAVX_NoVLX, 6165 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 6166 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 6167 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 6168 // (or:{ *:[v8i16] } VR128:{ *:[v8i16] }:$src1, VR128:{ *:[v8i16] }:$src2) => (VPORrr:{ *:[v8i16] } VR128:{ *:[v8i16] }:$src1, VR128:{ *:[v8i16] }:$src2) 6169 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPORrr, 6170 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6171 // GIR_Coverage, 16597, 6172 GIR_Done, 6173 // Label 481: @12637 6174 GIM_Try, /*On fail goto*//*Label 482*/ 12660, // Rule ID 16621 // 6175 GIM_CheckFeatures, GIFBS_UseSSE2, 6176 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 6177 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 6178 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 6179 // (or:{ *:[v8i16] } VR128:{ *:[v8i16] }:$src1, VR128:{ *:[v8i16] }:$src2) => (PORrr:{ *:[v8i16] } VR128:{ *:[v8i16] }:$src1, VR128:{ *:[v8i16] }:$src2) 6180 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::PORrr, 6181 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6182 // GIR_Coverage, 16621, 6183 GIR_Done, 6184 // Label 482: @12660 6185 GIM_Try, /*On fail goto*//*Label 483*/ 12683, // Rule ID 18504 // 6186 GIM_CheckFeatures, GIFBS_HasVLX, 6187 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID, 6188 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID, 6189 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128XRegClassID, 6190 // (or:{ *:[v8i16] } VR128X:{ *:[v8i16] }:$src1, VR128X:{ *:[v8i16] }:$src2) => (VPORQZ128rr:{ *:[v8i16] } VR128X:{ *:[v8i16] }:$src1, VR128X:{ *:[v8i16] }:$src2) 6191 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPORQZ128rr, 6192 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6193 // GIR_Coverage, 18504, 6194 GIR_Done, 6195 // Label 483: @12683 6196 GIM_Reject, 6197 // Label 480: @12684 6198 GIM_Reject, 6199 // Label 405: @12685 6200 GIM_Try, /*On fail goto*//*Label 484*/ 12765, 6201 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s32, 6202 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s32, 6203 GIM_Try, /*On fail goto*//*Label 485*/ 12718, // Rule ID 5415 // 6204 GIM_CheckFeatures, GIFBS_HasAVX512_HasVLX, 6205 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID, 6206 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID, 6207 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256XRegClassID, 6208 // (or:{ *:[v8i32] } VR256X:{ *:[v8i32] }:$src1, VR256X:{ *:[v8i32] }:$src2) => (VPORDZ256rr:{ *:[v8i32] } VR256X:{ *:[v8i32] }:$src1, VR256X:{ *:[v8i32] }:$src2) 6209 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPORDZ256rr, 6210 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6211 // GIR_Coverage, 5415, 6212 GIR_Done, 6213 // Label 485: @12718 6214 GIM_Try, /*On fail goto*//*Label 486*/ 12741, // Rule ID 16542 // 6215 GIM_CheckFeatures, GIFBS_HasAVX2_NoVLX, 6216 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID, 6217 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256RegClassID, 6218 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256RegClassID, 6219 // (or:{ *:[v8i32] } VR256:{ *:[v8i32] }:$src1, VR256:{ *:[v8i32] }:$src2) => (VPORYrr:{ *:[v8i32] } VR256:{ *:[v8i32] }:$src1, VR256:{ *:[v8i32] }:$src2) 6220 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPORYrr, 6221 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6222 // GIR_Coverage, 16542, 6223 GIR_Done, 6224 // Label 486: @12741 6225 GIM_Try, /*On fail goto*//*Label 487*/ 12764, // Rule ID 16567 // 6226 GIM_CheckFeatures, GIFBS_HasAVX1Only, 6227 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID, 6228 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256RegClassID, 6229 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256RegClassID, 6230 // (or:{ *:[v8i32] } VR256:{ *:[v8i32] }:$src1, VR256:{ *:[v8i32] }:$src2) => (VORPSYrr:{ *:[v8i32] } VR256:{ *:[v8i32] }:$src1, VR256:{ *:[v8i32] }:$src2) 6231 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VORPSYrr, 6232 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6233 // GIR_Coverage, 16567, 6234 GIR_Done, 6235 // Label 487: @12764 6236 GIM_Reject, 6237 // Label 484: @12765 6238 GIM_Reject, 6239 // Label 406: @12766 6240 GIM_Try, /*On fail goto*//*Label 488*/ 12797, // Rule ID 5379 // 6241 GIM_CheckFeatures, GIFBS_HasAVX512, 6242 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s64, 6243 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s64, 6244 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 6245 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR512RegClassID, 6246 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR512RegClassID, 6247 // (or:{ *:[v8i64] } VR512:{ *:[v8i64] }:$src1, VR512:{ *:[v8i64] }:$src2) => (VPORQZrr:{ *:[v8i64] } VR512:{ *:[v8i64] }:$src1, VR512:{ *:[v8i64] }:$src2) 6248 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPORQZrr, 6249 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6250 // GIR_Coverage, 5379, 6251 GIR_Done, 6252 // Label 488: @12797 6253 GIM_Reject, 6254 // Label 407: @12798 6255 GIM_Try, /*On fail goto*//*Label 489*/ 12829, // Rule ID 4059 // 6256 GIM_CheckFeatures, GIFBS_HasAVX512, 6257 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s1, 6258 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s1, 6259 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VK16RegClassID, 6260 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VK16RegClassID, 6261 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VK16RegClassID, 6262 // (or:{ *:[v16i1] } VK16:{ *:[v16i1] }:$src1, VK16:{ *:[v16i1] }:$src2) => (KORWrr:{ *:[v16i1] } VK16:{ *:[v16i1] }:$src1, VK16:{ *:[v16i1] }:$src2) 6263 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::KORWrr, 6264 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6265 // GIR_Coverage, 4059, 6266 GIR_Done, 6267 // Label 489: @12829 6268 GIM_Reject, 6269 // Label 408: @12830 6270 GIM_Try, /*On fail goto*//*Label 490*/ 12910, 6271 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, 6272 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, 6273 GIM_Try, /*On fail goto*//*Label 491*/ 12863, // Rule ID 16596 // 6274 GIM_CheckFeatures, GIFBS_HasAVX_NoVLX, 6275 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 6276 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 6277 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 6278 // (or:{ *:[v16i8] } VR128:{ *:[v16i8] }:$src1, VR128:{ *:[v16i8] }:$src2) => (VPORrr:{ *:[v16i8] } VR128:{ *:[v16i8] }:$src1, VR128:{ *:[v16i8] }:$src2) 6279 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPORrr, 6280 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6281 // GIR_Coverage, 16596, 6282 GIR_Done, 6283 // Label 491: @12863 6284 GIM_Try, /*On fail goto*//*Label 492*/ 12886, // Rule ID 16620 // 6285 GIM_CheckFeatures, GIFBS_UseSSE2, 6286 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 6287 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 6288 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 6289 // (or:{ *:[v16i8] } VR128:{ *:[v16i8] }:$src1, VR128:{ *:[v16i8] }:$src2) => (PORrr:{ *:[v16i8] } VR128:{ *:[v16i8] }:$src1, VR128:{ *:[v16i8] }:$src2) 6290 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::PORrr, 6291 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6292 // GIR_Coverage, 16620, 6293 GIR_Done, 6294 // Label 492: @12886 6295 GIM_Try, /*On fail goto*//*Label 493*/ 12909, // Rule ID 18503 // 6296 GIM_CheckFeatures, GIFBS_HasVLX, 6297 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID, 6298 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID, 6299 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128XRegClassID, 6300 // (or:{ *:[v16i8] } VR128X:{ *:[v16i8] }:$src1, VR128X:{ *:[v16i8] }:$src2) => (VPORQZ128rr:{ *:[v16i8] } VR128X:{ *:[v16i8] }:$src1, VR128X:{ *:[v16i8] }:$src2) 6301 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPORQZ128rr, 6302 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6303 // GIR_Coverage, 18503, 6304 GIR_Done, 6305 // Label 493: @12909 6306 GIM_Reject, 6307 // Label 490: @12910 6308 GIM_Reject, 6309 // Label 409: @12911 6310 GIM_Try, /*On fail goto*//*Label 494*/ 12991, 6311 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s16, 6312 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s16, 6313 GIM_Try, /*On fail goto*//*Label 495*/ 12944, // Rule ID 16541 // 6314 GIM_CheckFeatures, GIFBS_HasAVX2_NoVLX, 6315 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID, 6316 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256RegClassID, 6317 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256RegClassID, 6318 // (or:{ *:[v16i16] } VR256:{ *:[v16i16] }:$src1, VR256:{ *:[v16i16] }:$src2) => (VPORYrr:{ *:[v16i16] } VR256:{ *:[v16i16] }:$src1, VR256:{ *:[v16i16] }:$src2) 6319 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPORYrr, 6320 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6321 // GIR_Coverage, 16541, 6322 GIR_Done, 6323 // Label 495: @12944 6324 GIM_Try, /*On fail goto*//*Label 496*/ 12967, // Rule ID 16566 // 6325 GIM_CheckFeatures, GIFBS_HasAVX1Only, 6326 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID, 6327 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256RegClassID, 6328 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256RegClassID, 6329 // (or:{ *:[v16i16] } VR256:{ *:[v16i16] }:$src1, VR256:{ *:[v16i16] }:$src2) => (VORPSYrr:{ *:[v16i16] } VR256:{ *:[v16i16] }:$src1, VR256:{ *:[v16i16] }:$src2) 6330 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VORPSYrr, 6331 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6332 // GIR_Coverage, 16566, 6333 GIR_Done, 6334 // Label 496: @12967 6335 GIM_Try, /*On fail goto*//*Label 497*/ 12990, // Rule ID 18520 // 6336 GIM_CheckFeatures, GIFBS_HasVLX, 6337 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID, 6338 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID, 6339 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256XRegClassID, 6340 // (or:{ *:[v16i16] } VR256X:{ *:[v16i16] }:$src1, VR256X:{ *:[v16i16] }:$src2) => (VPORQZ256rr:{ *:[v16i16] } VR256X:{ *:[v16i16] }:$src1, VR256X:{ *:[v16i16] }:$src2) 6341 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPORQZ256rr, 6342 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6343 // GIR_Coverage, 18520, 6344 GIR_Done, 6345 // Label 497: @12990 6346 GIM_Reject, 6347 // Label 494: @12991 6348 GIM_Reject, 6349 // Label 410: @12992 6350 GIM_Try, /*On fail goto*//*Label 498*/ 13023, // Rule ID 5406 // 6351 GIM_CheckFeatures, GIFBS_HasAVX512, 6352 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s32, 6353 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s32, 6354 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 6355 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR512RegClassID, 6356 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR512RegClassID, 6357 // (or:{ *:[v16i32] } VR512:{ *:[v16i32] }:$src1, VR512:{ *:[v16i32] }:$src2) => (VPORDZrr:{ *:[v16i32] } VR512:{ *:[v16i32] }:$src1, VR512:{ *:[v16i32] }:$src2) 6358 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPORDZrr, 6359 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6360 // GIR_Coverage, 5406, 6361 GIR_Done, 6362 // Label 498: @13023 6363 GIM_Reject, 6364 // Label 411: @13024 6365 GIM_Try, /*On fail goto*//*Label 499*/ 13055, // Rule ID 4060 // 6366 GIM_CheckFeatures, GIFBS_HasBWI, 6367 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v32s1, 6368 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v32s1, 6369 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VK32RegClassID, 6370 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VK32RegClassID, 6371 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VK32RegClassID, 6372 // (or:{ *:[v32i1] } VK32:{ *:[v32i1] }:$src1, VK32:{ *:[v32i1] }:$src2) => (KORDrr:{ *:[v32i1] } VK32:{ *:[v32i1] }:$src1, VK32:{ *:[v32i1] }:$src2) 6373 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::KORDrr, 6374 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6375 // GIR_Coverage, 4060, 6376 GIR_Done, 6377 // Label 499: @13055 6378 GIM_Reject, 6379 // Label 412: @13056 6380 GIM_Try, /*On fail goto*//*Label 500*/ 13136, 6381 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v32s8, 6382 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v32s8, 6383 GIM_Try, /*On fail goto*//*Label 501*/ 13089, // Rule ID 16540 // 6384 GIM_CheckFeatures, GIFBS_HasAVX2_NoVLX, 6385 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID, 6386 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256RegClassID, 6387 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256RegClassID, 6388 // (or:{ *:[v32i8] } VR256:{ *:[v32i8] }:$src1, VR256:{ *:[v32i8] }:$src2) => (VPORYrr:{ *:[v32i8] } VR256:{ *:[v32i8] }:$src1, VR256:{ *:[v32i8] }:$src2) 6389 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPORYrr, 6390 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6391 // GIR_Coverage, 16540, 6392 GIR_Done, 6393 // Label 501: @13089 6394 GIM_Try, /*On fail goto*//*Label 502*/ 13112, // Rule ID 16565 // 6395 GIM_CheckFeatures, GIFBS_HasAVX1Only, 6396 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID, 6397 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256RegClassID, 6398 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256RegClassID, 6399 // (or:{ *:[v32i8] } VR256:{ *:[v32i8] }:$src1, VR256:{ *:[v32i8] }:$src2) => (VORPSYrr:{ *:[v32i8] } VR256:{ *:[v32i8] }:$src1, VR256:{ *:[v32i8] }:$src2) 6400 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VORPSYrr, 6401 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6402 // GIR_Coverage, 16565, 6403 GIR_Done, 6404 // Label 502: @13112 6405 GIM_Try, /*On fail goto*//*Label 503*/ 13135, // Rule ID 18519 // 6406 GIM_CheckFeatures, GIFBS_HasVLX, 6407 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID, 6408 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID, 6409 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256XRegClassID, 6410 // (or:{ *:[v32i8] } VR256X:{ *:[v32i8] }:$src1, VR256X:{ *:[v32i8] }:$src2) => (VPORQZ256rr:{ *:[v32i8] } VR256X:{ *:[v32i8] }:$src1, VR256X:{ *:[v32i8] }:$src2) 6411 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPORQZ256rr, 6412 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6413 // GIR_Coverage, 18519, 6414 GIR_Done, 6415 // Label 503: @13135 6416 GIM_Reject, 6417 // Label 500: @13136 6418 GIM_Reject, 6419 // Label 413: @13137 6420 GIM_Try, /*On fail goto*//*Label 504*/ 13168, // Rule ID 18536 // 6421 GIM_CheckFeatures, GIFBS_HasAVX512, 6422 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v32s16, 6423 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v32s16, 6424 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 6425 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR512RegClassID, 6426 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR512RegClassID, 6427 // (or:{ *:[v32i16] } VR512:{ *:[v32i16] }:$src1, VR512:{ *:[v32i16] }:$src2) => (VPORQZrr:{ *:[v32i16] } VR512:{ *:[v32i16] }:$src1, VR512:{ *:[v32i16] }:$src2) 6428 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPORQZrr, 6429 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6430 // GIR_Coverage, 18536, 6431 GIR_Done, 6432 // Label 504: @13168 6433 GIM_Reject, 6434 // Label 414: @13169 6435 GIM_Try, /*On fail goto*//*Label 505*/ 13200, // Rule ID 4061 // 6436 GIM_CheckFeatures, GIFBS_HasBWI, 6437 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v64s1, 6438 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v64s1, 6439 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VK64RegClassID, 6440 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VK64RegClassID, 6441 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VK64RegClassID, 6442 // (or:{ *:[v64i1] } VK64:{ *:[v64i1] }:$src1, VK64:{ *:[v64i1] }:$src2) => (KORQrr:{ *:[v64i1] } VK64:{ *:[v64i1] }:$src1, VK64:{ *:[v64i1] }:$src2) 6443 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::KORQrr, 6444 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6445 // GIR_Coverage, 4061, 6446 GIR_Done, 6447 // Label 505: @13200 6448 GIM_Reject, 6449 // Label 415: @13201 6450 GIM_Try, /*On fail goto*//*Label 506*/ 13232, // Rule ID 18535 // 6451 GIM_CheckFeatures, GIFBS_HasAVX512, 6452 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v64s8, 6453 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v64s8, 6454 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 6455 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR512RegClassID, 6456 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR512RegClassID, 6457 // (or:{ *:[v64i8] } VR512:{ *:[v64i8] }:$src1, VR512:{ *:[v64i8] }:$src2) => (VPORQZrr:{ *:[v64i8] } VR512:{ *:[v64i8] }:$src1, VR512:{ *:[v64i8] }:$src2) 6458 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPORQZrr, 6459 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6460 // GIR_Coverage, 18535, 6461 GIR_Done, 6462 // Label 506: @13232 6463 GIM_Reject, 6464 // Label 416: @13233 6465 GIM_Reject, 6466 // Label 5: @13234 6467 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 25, /*)*//*default:*//*Label 530*/ 20964, 6468 /*GILLT_s1*//*Label 507*/ 13265, 6469 /*GILLT_s8*//*Label 508*/ 13772, 6470 /*GILLT_s16*//*Label 509*/ 13885, 6471 /*GILLT_s32*//*Label 510*/ 14239, 6472 /*GILLT_s64*//*Label 511*/ 14857, 0, 0, 6473 /*GILLT_v2s1*//*Label 512*/ 15441, 6474 /*GILLT_v2s64*//*Label 513*/ 15932, 6475 /*GILLT_v4s1*//*Label 514*/ 16273, 6476 /*GILLT_v4s32*//*Label 515*/ 16764, 6477 /*GILLT_v4s64*//*Label 516*/ 17105, 6478 /*GILLT_v8s1*//*Label 517*/ 17446, 6479 /*GILLT_v8s16*//*Label 518*/ 18185, 6480 /*GILLT_v8s32*//*Label 519*/ 18526, 6481 /*GILLT_v8s64*//*Label 520*/ 18867, 6482 /*GILLT_v16s1*//*Label 521*/ 18945, 6483 /*GILLT_v16s8*//*Label 522*/ 19199, 6484 /*GILLT_v16s16*//*Label 523*/ 19540, 6485 /*GILLT_v16s32*//*Label 524*/ 19881, 6486 /*GILLT_v32s1*//*Label 525*/ 19959, 6487 /*GILLT_v32s8*//*Label 526*/ 20213, 6488 /*GILLT_v32s16*//*Label 527*/ 20554, 6489 /*GILLT_v64s1*//*Label 528*/ 20632, 6490 /*GILLT_v64s8*//*Label 529*/ 20886, 6491 // Label 507: @13265 6492 GIM_Try, /*On fail goto*//*Label 531*/ 13771, 6493 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s1, 6494 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s1, 6495 GIM_Try, /*On fail goto*//*Label 532*/ 13388, // Rule ID 23238 // 6496 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VK1RegClassID, 6497 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 6498 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, 6499 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s1, 6500 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s1, 6501 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::VK1RegClassID, 6502 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] 6503 GIM_CheckOpcodeIsEither, /*MI*/2, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, 6504 GIM_CheckIsBuildVectorAllOnes, /*MI*/2, 6505 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VK1RegClassID, 6506 GIM_CheckIsSafeToFold, /*InsnID*/1, 6507 GIM_CheckIsSafeToFold, /*InsnID*/2, 6508 // (xor:{ *:[v1i1] } (xor:{ *:[v1i1] } VK1:{ *:[v1i1] }:$src1, immAllOnesV:{ *:[v1i1] }), VK1:{ *:[v1i1] }:$src2) => (COPY_TO_REGCLASS:{ *:[v1i1] } (KXNORWrr:{ *:[v16i1] } (COPY_TO_REGCLASS:{ *:[v16i1] } VK1:{ *:[v1i1] }:$src1, VK16:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v16i1] } VK1:{ *:[v1i1] }:$src2, VK16:{ *:[i32] })), VK1:{ *:[i32] }) 6509 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s1, 6510 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s1, 6511 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s1, 6512 GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::COPY, 6513 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, 6514 GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // src2 6515 GIR_ConstrainSelectedInstOperands, /*InsnID*/3, 6516 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY, 6517 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 6518 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, // src1 6519 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 6520 GIR_BuildMI, /*InsnID*/1, /*Opcode*/X86::KXNORWrr, 6521 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 6522 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, 6523 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/2, /*TempRegFlags*/0, 6524 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 6525 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 6526 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 6527 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 6528 GIR_EraseFromParent, /*InsnID*/0, 6529 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, X86::VK1RegClassID, 6530 // GIR_Coverage, 23238, 6531 GIR_Done, 6532 // Label 532: @13388 6533 GIM_Try, /*On fail goto*//*Label 533*/ 13501, // Rule ID 17935 // 6534 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VK1RegClassID, 6535 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 6536 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, 6537 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s1, 6538 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s1, 6539 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::VK1RegClassID, 6540 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/X86::VK1RegClassID, 6541 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] 6542 GIM_CheckOpcodeIsEither, /*MI*/2, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, 6543 GIM_CheckIsBuildVectorAllOnes, /*MI*/2, 6544 GIM_CheckIsSafeToFold, /*InsnID*/1, 6545 GIM_CheckIsSafeToFold, /*InsnID*/2, 6546 // (xor:{ *:[v1i1] } (xor:{ *:[v1i1] } VK1:{ *:[v1i1] }:$src1, VK1:{ *:[v1i1] }:$src2), immAllOnesV:{ *:[v1i1] }) => (COPY_TO_REGCLASS:{ *:[v1i1] } (KXNORWrr:{ *:[v16i1] } (COPY_TO_REGCLASS:{ *:[v16i1] } VK1:{ *:[v1i1] }:$src1, VK16:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v16i1] } VK1:{ *:[v1i1] }:$src2, VK16:{ *:[i32] })), VK1:{ *:[i32] }) 6547 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s1, 6548 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s1, 6549 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s1, 6550 GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::COPY, 6551 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, 6552 GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/1, /*OpIdx*/2, // src2 6553 GIR_ConstrainSelectedInstOperands, /*InsnID*/3, 6554 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY, 6555 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 6556 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, // src1 6557 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 6558 GIR_BuildMI, /*InsnID*/1, /*Opcode*/X86::KXNORWrr, 6559 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 6560 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, 6561 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/2, /*TempRegFlags*/0, 6562 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 6563 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 6564 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 6565 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 6566 GIR_EraseFromParent, /*InsnID*/0, 6567 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, X86::VK1RegClassID, 6568 // GIR_Coverage, 17935, 6569 GIR_Done, 6570 // Label 533: @13501 6571 GIM_Try, /*On fail goto*//*Label 534*/ 13614, // Rule ID 23239 // 6572 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VK1RegClassID, 6573 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VK1RegClassID, 6574 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 6575 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, 6576 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s1, 6577 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s1, 6578 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::VK1RegClassID, 6579 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] 6580 GIM_CheckOpcodeIsEither, /*MI*/2, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, 6581 GIM_CheckIsBuildVectorAllOnes, /*MI*/2, 6582 GIM_CheckIsSafeToFold, /*InsnID*/1, 6583 GIM_CheckIsSafeToFold, /*InsnID*/2, 6584 // (xor:{ *:[v1i1] } VK1:{ *:[v1i1] }:$src2, (xor:{ *:[v1i1] } VK1:{ *:[v1i1] }:$src1, immAllOnesV:{ *:[v1i1] })) => (COPY_TO_REGCLASS:{ *:[v1i1] } (KXNORWrr:{ *:[v16i1] } (COPY_TO_REGCLASS:{ *:[v16i1] } VK1:{ *:[v1i1] }:$src1, VK16:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v16i1] } VK1:{ *:[v1i1] }:$src2, VK16:{ *:[i32] })), VK1:{ *:[i32] }) 6585 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s1, 6586 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s1, 6587 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s1, 6588 GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::COPY, 6589 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, 6590 GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // src2 6591 GIR_ConstrainSelectedInstOperands, /*InsnID*/3, 6592 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY, 6593 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 6594 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, // src1 6595 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 6596 GIR_BuildMI, /*InsnID*/1, /*Opcode*/X86::KXNORWrr, 6597 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 6598 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, 6599 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/2, /*TempRegFlags*/0, 6600 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 6601 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 6602 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 6603 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 6604 GIR_EraseFromParent, /*InsnID*/0, 6605 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, X86::VK1RegClassID, 6606 // GIR_Coverage, 23239, 6607 GIR_Done, 6608 // Label 534: @13614 6609 GIM_Try, /*On fail goto*//*Label 535*/ 13686, // Rule ID 17921 // 6610 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VK2RegClassID, 6611 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VK1RegClassID, 6612 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 6613 GIM_CheckOpcodeIsEither, /*MI*/1, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, 6614 GIM_CheckIsBuildVectorAllOnes, /*MI*/1, 6615 GIM_CheckIsSafeToFold, /*InsnID*/1, 6616 // (xor:{ *:[v1i1] } VK1:{ *:[v1i1] }:$src, immAllOnesV:{ *:[v1i1] }) => (COPY_TO_REGCLASS:{ *:[v1i1] } (KNOTWrr:{ *:[v16i1] } (COPY_TO_REGCLASS:{ *:[v16i1] } VK1:{ *:[v1i1] }:$src, VK16:{ *:[i32] })), VK2:{ *:[i32] }) 6617 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s1, 6618 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s1, 6619 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY, 6620 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 6621 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src 6622 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 6623 GIR_BuildMI, /*InsnID*/1, /*Opcode*/X86::KNOTWrr, 6624 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 6625 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, 6626 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 6627 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 6628 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 6629 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 6630 GIR_EraseFromParent, /*InsnID*/0, 6631 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, X86::VK2RegClassID, 6632 // GIR_Coverage, 17921, 6633 GIR_Done, 6634 // Label 535: @13686 6635 GIM_Try, /*On fail goto*//*Label 536*/ 13770, // Rule ID 17939 // 6636 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VK1RegClassID, 6637 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VK1RegClassID, 6638 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VK1RegClassID, 6639 // (xor:{ *:[v1i1] } VK1:{ *:[v1i1] }:$src1, VK1:{ *:[v1i1] }:$src2) => (COPY_TO_REGCLASS:{ *:[v1i1] } (KXORWrr:{ *:[v16i1] } (COPY_TO_REGCLASS:{ *:[v16i1] } VK1:{ *:[v1i1] }:$src1, VK16:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v16i1] } VK1:{ *:[v1i1] }:$src2, VK16:{ *:[i32] })), VK1:{ *:[i32] }) 6640 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s1, 6641 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s1, 6642 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s1, 6643 GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::COPY, 6644 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, 6645 GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // src2 6646 GIR_ConstrainSelectedInstOperands, /*InsnID*/3, 6647 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY, 6648 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 6649 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src1 6650 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 6651 GIR_BuildMI, /*InsnID*/1, /*Opcode*/X86::KXORWrr, 6652 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 6653 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, 6654 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/2, /*TempRegFlags*/0, 6655 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 6656 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 6657 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 6658 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 6659 GIR_EraseFromParent, /*InsnID*/0, 6660 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, X86::VK1RegClassID, 6661 // GIR_Coverage, 17939, 6662 GIR_Done, 6663 // Label 536: @13770 6664 GIM_Reject, 6665 // Label 531: @13771 6666 GIM_Reject, 6667 // Label 508: @13772 6668 GIM_Try, /*On fail goto*//*Label 537*/ 13884, 6669 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s8, 6670 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s8, 6671 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR8RegClassID, 6672 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR8RegClassID, 6673 GIM_Try, /*On fail goto*//*Label 538*/ 13815, // Rule ID 20856 // 6674 GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -128, 6675 // (xor:{ *:[i8] } GR8:{ *:[i8] }:$src1, -128:{ *:[i8] }) => (ADD8ri:{ *:[i8] }:{ *:[i32] } GR8:{ *:[i8] }:$src1, -128:{ *:[i8] }) 6676 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::ADD8ri, 6677 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 6678 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 6679 GIR_AddImm, /*InsnID*/0, /*Imm*/-128, 6680 GIR_EraseFromParent, /*InsnID*/0, 6681 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6682 // GIR_Coverage, 20856, 6683 GIR_Done, 6684 // Label 538: @13815 6685 GIM_Try, /*On fail goto*//*Label 539*/ 13837, // Rule ID 165 // 6686 GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1, 6687 // (xor:{ *:[i8] } GR8:{ *:[i8] }:$src1, -1:{ *:[i8] }) => (NOT8r:{ *:[i8] } GR8:{ *:[i8] }:$src1) 6688 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::NOT8r, 6689 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 6690 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 6691 GIR_EraseFromParent, /*InsnID*/0, 6692 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6693 // GIR_Coverage, 165, 6694 GIR_Done, 6695 // Label 539: @13837 6696 GIM_Try, /*On fail goto*//*Label 540*/ 13867, // Rule ID 15688 // 6697 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 6698 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 6699 // MIs[1] Operand 1 6700 // No operand predicates 6701 GIM_CheckIsSafeToFold, /*InsnID*/1, 6702 // (xor:{ *:[i8] } GR8:{ *:[i8] }:$src1, (imm:{ *:[i8] }):$src2) => (XOR8ri:{ *:[i8] }:{ *:[i32] } GR8:{ *:[i8] }:$src1, (imm:{ *:[i8] }):$src2) 6703 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::XOR8ri, 6704 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 6705 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 6706 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // src2 6707 GIR_EraseFromParent, /*InsnID*/0, 6708 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6709 // GIR_Coverage, 15688, 6710 GIR_Done, 6711 // Label 540: @13867 6712 GIM_Try, /*On fail goto*//*Label 541*/ 13883, // Rule ID 15680 // 6713 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::GR8RegClassID, 6714 // (xor:{ *:[i8] } GR8:{ *:[i8] }:$src1, GR8:{ *:[i8] }:$src2) => (XOR8rr:{ *:[i8] }:{ *:[i32] } GR8:{ *:[i8] }:$src1, GR8:{ *:[i8] }:$src2) 6715 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::XOR8rr, 6716 GIR_AddImplicitDef, /*InsnID*/0, X86::EFLAGS, 6717 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6718 // GIR_Coverage, 15680, 6719 GIR_Done, 6720 // Label 541: @13883 6721 GIM_Reject, 6722 // Label 537: @13884 6723 GIM_Reject, 6724 // Label 509: @13885 6725 GIM_Try, /*On fail goto*//*Label 542*/ 14238, 6726 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16, 6727 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16, 6728 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR16RegClassID, 6729 GIM_Try, /*On fail goto*//*Label 543*/ 13928, // Rule ID 20857 // 6730 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR16RegClassID, 6731 GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -32768, 6732 // (xor:{ *:[i16] } GR16:{ *:[i16] }:$src1, -32768:{ *:[i16] }) => (ADD16ri:{ *:[i16] }:{ *:[i32] } GR16:{ *:[i16] }:$src1, -32768:{ *:[i16] }) 6733 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::ADD16ri, 6734 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 6735 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 6736 GIR_AddImm, /*InsnID*/0, /*Imm*/-32768, 6737 GIR_EraseFromParent, /*InsnID*/0, 6738 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6739 // GIR_Coverage, 20857, 6740 GIR_Done, 6741 // Label 543: @13928 6742 GIM_Try, /*On fail goto*//*Label 544*/ 14024, // Rule ID 23894 // 6743 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 6744 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SHL, 6745 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, 6746 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s8, 6747 GIM_CheckConstantInt, /*MI*/1, /*Op*/1, 1, 6748 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/X86::GR8RegClassID, 6749 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::GR16RegClassID, 6750 GIM_CheckIsSafeToFold, /*InsnID*/1, 6751 // (xor:{ *:[i16] } (shl:{ *:[i16] } 1:{ *:[i16] }, GR8:{ *:[i8] }:$src2), GR16:{ *:[i16] }:$src1) => (BTC16rr:{ *:[i16] }:{ *:[i32] } GR16:{ *:[i16] }:$src1, (INSERT_SUBREG:{ *:[i16] } (IMPLICIT_DEF:{ *:[i16] }), GR8:{ *:[i8] }:$src2, sub_8bit:{ *:[i32] })) 6752 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16, 6753 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16, 6754 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, 6755 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 6756 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 6757 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, 6758 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 6759 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, 6760 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // src2 6761 GIR_AddImm, /*InsnID*/1, /*Imm*/1, 6762 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, X86::GR16RegClassID, 6763 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, X86::GR16RegClassID, 6764 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, X86::GR8RegClassID, 6765 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BTC16rr, 6766 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 6767 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 6768 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 6769 GIR_EraseFromParent, /*InsnID*/0, 6770 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6771 // GIR_Coverage, 23894, 6772 GIR_Done, 6773 // Label 544: @14024 6774 GIM_Try, /*On fail goto*//*Label 545*/ 14120, // Rule ID 20979 // 6775 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR16RegClassID, 6776 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 6777 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SHL, 6778 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, 6779 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s8, 6780 GIM_CheckConstantInt, /*MI*/1, /*Op*/1, 1, 6781 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/X86::GR8RegClassID, 6782 GIM_CheckIsSafeToFold, /*InsnID*/1, 6783 // (xor:{ *:[i16] } GR16:{ *:[i16] }:$src1, (shl:{ *:[i16] } 1:{ *:[i16] }, GR8:{ *:[i8] }:$src2)) => (BTC16rr:{ *:[i16] }:{ *:[i32] } GR16:{ *:[i16] }:$src1, (INSERT_SUBREG:{ *:[i16] } (IMPLICIT_DEF:{ *:[i16] }), GR8:{ *:[i8] }:$src2, sub_8bit:{ *:[i32] })) 6784 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16, 6785 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16, 6786 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, 6787 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 6788 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 6789 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, 6790 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 6791 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, 6792 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // src2 6793 GIR_AddImm, /*InsnID*/1, /*Imm*/1, 6794 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, X86::GR16RegClassID, 6795 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, X86::GR16RegClassID, 6796 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, X86::GR8RegClassID, 6797 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BTC16rr, 6798 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 6799 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 6800 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 6801 GIR_EraseFromParent, /*InsnID*/0, 6802 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6803 // GIR_Coverage, 20979, 6804 GIR_Done, 6805 // Label 545: @14120 6806 GIM_Try, /*On fail goto*//*Label 546*/ 14146, // Rule ID 166 // 6807 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR16RegClassID, 6808 GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1, 6809 // (xor:{ *:[i16] } GR16:{ *:[i16] }:$src1, -1:{ *:[i16] }) => (NOT16r:{ *:[i16] } GR16:{ *:[i16] }:$src1) 6810 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::NOT16r, 6811 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 6812 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 6813 GIR_EraseFromParent, /*InsnID*/0, 6814 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6815 // GIR_Coverage, 166, 6816 GIR_Done, 6817 // Label 546: @14146 6818 GIM_Try, /*On fail goto*//*Label 547*/ 14183, // Rule ID 15691 // 6819 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR16RegClassID, 6820 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 6821 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 6822 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_i16immSExt8, 6823 // MIs[1] Operand 1 6824 // No operand predicates 6825 GIM_CheckIsSafeToFold, /*InsnID*/1, 6826 // (xor:{ *:[i16] } GR16:{ *:[i16] }:$src1, (imm:{ *:[i16] })<<P:Predicate_i16immSExt8>>:$src2) => (XOR16ri8:{ *:[i16] }:{ *:[i32] } GR16:{ *:[i16] }:$src1, (imm:{ *:[i16] })<<P:Predicate_i16immSExt8>>:$src2) 6827 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::XOR16ri8, 6828 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 6829 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 6830 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // src2 6831 GIR_EraseFromParent, /*InsnID*/0, 6832 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6833 // GIR_Coverage, 15691, 6834 GIR_Done, 6835 // Label 547: @14183 6836 GIM_Try, /*On fail goto*//*Label 548*/ 14217, // Rule ID 15689 // 6837 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR16RegClassID, 6838 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 6839 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 6840 // MIs[1] Operand 1 6841 // No operand predicates 6842 GIM_CheckIsSafeToFold, /*InsnID*/1, 6843 // (xor:{ *:[i16] } GR16:{ *:[i16] }:$src1, (imm:{ *:[i16] }):$src2) => (XOR16ri:{ *:[i16] }:{ *:[i32] } GR16:{ *:[i16] }:$src1, (imm:{ *:[i16] }):$src2) 6844 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::XOR16ri, 6845 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 6846 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 6847 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // src2 6848 GIR_EraseFromParent, /*InsnID*/0, 6849 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6850 // GIR_Coverage, 15689, 6851 GIR_Done, 6852 // Label 548: @14217 6853 GIM_Try, /*On fail goto*//*Label 549*/ 14237, // Rule ID 15681 // 6854 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR16RegClassID, 6855 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::GR16RegClassID, 6856 // (xor:{ *:[i16] } GR16:{ *:[i16] }:$src1, GR16:{ *:[i16] }:$src2) => (XOR16rr:{ *:[i16] }:{ *:[i32] } GR16:{ *:[i16] }:$src1, GR16:{ *:[i16] }:$src2) 6857 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::XOR16rr, 6858 GIR_AddImplicitDef, /*InsnID*/0, X86::EFLAGS, 6859 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6860 // GIR_Coverage, 15681, 6861 GIR_Done, 6862 // Label 549: @14237 6863 GIM_Reject, 6864 // Label 542: @14238 6865 GIM_Reject, 6866 // Label 510: @14239 6867 GIM_Try, /*On fail goto*//*Label 550*/ 14856, 6868 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 6869 GIM_Try, /*On fail goto*//*Label 551*/ 14282, // Rule ID 20858 // 6870 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 6871 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID, 6872 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR32RegClassID, 6873 GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -2147483648, 6874 // (xor:{ *:[i32] } GR32:{ *:[i32] }:$src1, -2147483648:{ *:[i32] }) => (ADD32ri:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src1, -2147483648:{ *:[i32] }) 6875 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::ADD32ri, 6876 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 6877 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 6878 GIR_AddImm, /*InsnID*/0, /*Imm*/-2147483648, 6879 GIR_EraseFromParent, /*InsnID*/0, 6880 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6881 // GIR_Coverage, 20858, 6882 GIR_Done, 6883 // Label 551: @14282 6884 GIM_Try, /*On fail goto*//*Label 552*/ 14336, // Rule ID 22857 // 6885 GIM_CheckFeatures, GIFBS_HasBMI, 6886 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID, 6887 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 6888 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD, 6889 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, 6890 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, 6891 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::GR32RegClassID, 6892 GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1, 6893 // MIs[0] src 6894 GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, 6895 GIM_CheckIsSafeToFold, /*InsnID*/1, 6896 // (xor:{ *:[i32] } (add:{ *:[i32] } GR32:{ *:[i32] }:$src, -1:{ *:[i32] }), GR32:{ *:[i32] }:$src) => (BLSMSK32rr:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src) 6897 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLSMSK32rr, 6898 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 6899 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src 6900 GIR_EraseFromParent, /*InsnID*/0, 6901 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6902 // GIR_Coverage, 22857, 6903 GIR_Done, 6904 // Label 552: @14336 6905 GIM_Try, /*On fail goto*//*Label 553*/ 14390, // Rule ID 22875 // 6906 GIM_CheckFeatures, GIFBS_HasTBM, 6907 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID, 6908 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 6909 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD, 6910 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, 6911 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, 6912 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::GR32RegClassID, 6913 GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 1, 6914 // MIs[0] src 6915 GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, 6916 GIM_CheckIsSafeToFold, /*InsnID*/1, 6917 // (xor:{ *:[i32] } (add:{ *:[i32] } GR32:{ *:[i32] }:$src, 1:{ *:[i32] }), GR32:{ *:[i32] }:$src) => (BLCMSK32rr:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src) 6918 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLCMSK32rr, 6919 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 6920 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src 6921 GIR_EraseFromParent, /*InsnID*/0, 6922 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6923 // GIR_Coverage, 22875, 6924 GIR_Done, 6925 // Label 553: @14390 6926 GIM_Try, /*On fail goto*//*Label 554*/ 14494, // Rule ID 23900 // 6927 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 6928 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID, 6929 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 6930 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SHL, 6931 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, 6932 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s8, 6933 GIM_CheckConstantInt, /*MI*/1, /*Op*/1, 1, 6934 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/X86::GR8RegClassID, 6935 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::GR32RegClassID, 6936 GIM_CheckIsSafeToFold, /*InsnID*/1, 6937 // (xor:{ *:[i32] } (shl:{ *:[i32] } 1:{ *:[i32] }, GR8:{ *:[i8] }:$src2), GR32:{ *:[i32] }:$src1) => (BTC32rr:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src1, (INSERT_SUBREG:{ *:[i32] } (IMPLICIT_DEF:{ *:[i32] }), GR8:{ *:[i8] }:$src2, sub_8bit:{ *:[i32] })) 6938 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, 6939 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, 6940 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, 6941 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 6942 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 6943 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, 6944 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 6945 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, 6946 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // src2 6947 GIR_AddImm, /*InsnID*/1, /*Imm*/1, 6948 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID, 6949 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID, 6950 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, X86::GR8RegClassID, 6951 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BTC32rr, 6952 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 6953 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 6954 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 6955 GIR_EraseFromParent, /*InsnID*/0, 6956 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6957 // GIR_Coverage, 23900, 6958 GIR_Done, 6959 // Label 554: @14494 6960 GIM_Try, /*On fail goto*//*Label 555*/ 14548, // Rule ID 15908 // 6961 GIM_CheckFeatures, GIFBS_HasBMI, 6962 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 6963 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID, 6964 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR32RegClassID, 6965 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 6966 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD, 6967 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, 6968 // MIs[1] src 6969 GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/1, /*OtherMI*/0, /*OtherOpIdx*/1, 6970 GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1, 6971 GIM_CheckIsSafeToFold, /*InsnID*/1, 6972 // (xor:{ *:[i32] } GR32:{ *:[i32] }:$src, (add:{ *:[i32] } GR32:{ *:[i32] }:$src, -1:{ *:[i32] })) => (BLSMSK32rr:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src) 6973 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLSMSK32rr, 6974 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 6975 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 6976 GIR_EraseFromParent, /*InsnID*/0, 6977 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6978 // GIR_Coverage, 15908, 6979 GIR_Done, 6980 // Label 555: @14548 6981 GIM_Try, /*On fail goto*//*Label 556*/ 14602, // Rule ID 15932 // 6982 GIM_CheckFeatures, GIFBS_HasTBM, 6983 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 6984 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID, 6985 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR32RegClassID, 6986 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 6987 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD, 6988 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, 6989 // MIs[1] src 6990 GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/1, /*OtherMI*/0, /*OtherOpIdx*/1, 6991 GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 1, 6992 GIM_CheckIsSafeToFold, /*InsnID*/1, 6993 // (xor:{ *:[i32] } GR32:{ *:[i32] }:$src, (add:{ *:[i32] } GR32:{ *:[i32] }:$src, 1:{ *:[i32] })) => (BLCMSK32rr:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src) 6994 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLCMSK32rr, 6995 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 6996 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 6997 GIR_EraseFromParent, /*InsnID*/0, 6998 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6999 // GIR_Coverage, 15932, 7000 GIR_Done, 7001 // Label 556: @14602 7002 GIM_Try, /*On fail goto*//*Label 557*/ 14706, // Rule ID 20985 // 7003 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 7004 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID, 7005 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR32RegClassID, 7006 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 7007 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SHL, 7008 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, 7009 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s8, 7010 GIM_CheckConstantInt, /*MI*/1, /*Op*/1, 1, 7011 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/X86::GR8RegClassID, 7012 GIM_CheckIsSafeToFold, /*InsnID*/1, 7013 // (xor:{ *:[i32] } GR32:{ *:[i32] }:$src1, (shl:{ *:[i32] } 1:{ *:[i32] }, GR8:{ *:[i8] }:$src2)) => (BTC32rr:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src1, (INSERT_SUBREG:{ *:[i32] } (IMPLICIT_DEF:{ *:[i32] }), GR8:{ *:[i8] }:$src2, sub_8bit:{ *:[i32] })) 7014 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, 7015 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, 7016 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, 7017 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 7018 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 7019 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, 7020 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 7021 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, 7022 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // src2 7023 GIR_AddImm, /*InsnID*/1, /*Imm*/1, 7024 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID, 7025 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID, 7026 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, X86::GR8RegClassID, 7027 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BTC32rr, 7028 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 7029 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 7030 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 7031 GIR_EraseFromParent, /*InsnID*/0, 7032 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7033 // GIR_Coverage, 20985, 7034 GIR_Done, 7035 // Label 557: @14706 7036 GIM_Try, /*On fail goto*//*Label 558*/ 14740, // Rule ID 167 // 7037 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 7038 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID, 7039 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR32RegClassID, 7040 GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1, 7041 // (xor:{ *:[i32] } GR32:{ *:[i32] }:$src1, -1:{ *:[i32] }) => (NOT32r:{ *:[i32] } GR32:{ *:[i32] }:$src1) 7042 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::NOT32r, 7043 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 7044 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 7045 GIR_EraseFromParent, /*InsnID*/0, 7046 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7047 // GIR_Coverage, 167, 7048 GIR_Done, 7049 // Label 558: @14740 7050 GIM_Try, /*On fail goto*//*Label 559*/ 14785, // Rule ID 15692 // 7051 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 7052 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID, 7053 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR32RegClassID, 7054 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 7055 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 7056 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_i32immSExt8, 7057 // MIs[1] Operand 1 7058 // No operand predicates 7059 GIM_CheckIsSafeToFold, /*InsnID*/1, 7060 // (xor:{ *:[i32] } GR32:{ *:[i32] }:$src1, (imm:{ *:[i32] })<<P:Predicate_i32immSExt8>>:$src2) => (XOR32ri8:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src1, (imm:{ *:[i32] })<<P:Predicate_i32immSExt8>>:$src2) 7061 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::XOR32ri8, 7062 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 7063 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 7064 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // src2 7065 GIR_EraseFromParent, /*InsnID*/0, 7066 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7067 // GIR_Coverage, 15692, 7068 GIR_Done, 7069 // Label 559: @14785 7070 GIM_Try, /*On fail goto*//*Label 560*/ 14827, // Rule ID 15690 // 7071 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 7072 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID, 7073 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR32RegClassID, 7074 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 7075 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 7076 // MIs[1] Operand 1 7077 // No operand predicates 7078 GIM_CheckIsSafeToFold, /*InsnID*/1, 7079 // (xor:{ *:[i32] } GR32:{ *:[i32] }:$src1, (imm:{ *:[i32] }):$src2) => (XOR32ri:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src1, (imm:{ *:[i32] }):$src2) 7080 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::XOR32ri, 7081 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 7082 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 7083 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // src2 7084 GIR_EraseFromParent, /*InsnID*/0, 7085 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7086 // GIR_Coverage, 15690, 7087 GIR_Done, 7088 // Label 560: @14827 7089 GIM_Try, /*On fail goto*//*Label 561*/ 14855, // Rule ID 15682 // 7090 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 7091 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID, 7092 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR32RegClassID, 7093 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::GR32RegClassID, 7094 // (xor:{ *:[i32] } GR32:{ *:[i32] }:$src1, GR32:{ *:[i32] }:$src2) => (XOR32rr:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src1, GR32:{ *:[i32] }:$src2) 7095 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::XOR32rr, 7096 GIR_AddImplicitDef, /*InsnID*/0, X86::EFLAGS, 7097 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7098 // GIR_Coverage, 15682, 7099 GIR_Done, 7100 // Label 561: @14855 7101 GIM_Reject, 7102 // Label 550: @14856 7103 GIM_Reject, 7104 // Label 511: @14857 7105 GIM_Try, /*On fail goto*//*Label 562*/ 15440, 7106 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 7107 GIM_Try, /*On fail goto*//*Label 563*/ 14917, // Rule ID 22858 // 7108 GIM_CheckFeatures, GIFBS_HasBMI, 7109 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID, 7110 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 7111 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD, 7112 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, 7113 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, 7114 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::GR64RegClassID, 7115 GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1, 7116 // MIs[0] src 7117 GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, 7118 GIM_CheckIsSafeToFold, /*InsnID*/1, 7119 // (xor:{ *:[i64] } (add:{ *:[i64] } GR64:{ *:[i64] }:$src, -1:{ *:[i64] }), GR64:{ *:[i64] }:$src) => (BLSMSK64rr:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src) 7120 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLSMSK64rr, 7121 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 7122 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src 7123 GIR_EraseFromParent, /*InsnID*/0, 7124 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7125 // GIR_Coverage, 22858, 7126 GIR_Done, 7127 // Label 563: @14917 7128 GIM_Try, /*On fail goto*//*Label 564*/ 14971, // Rule ID 22876 // 7129 GIM_CheckFeatures, GIFBS_HasTBM, 7130 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID, 7131 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 7132 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD, 7133 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, 7134 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, 7135 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::GR64RegClassID, 7136 GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 1, 7137 // MIs[0] src 7138 GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, 7139 GIM_CheckIsSafeToFold, /*InsnID*/1, 7140 // (xor:{ *:[i64] } (add:{ *:[i64] } GR64:{ *:[i64] }:$src, 1:{ *:[i64] }), GR64:{ *:[i64] }:$src) => (BLCMSK64rr:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src) 7141 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLCMSK64rr, 7142 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 7143 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src 7144 GIR_EraseFromParent, /*InsnID*/0, 7145 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7146 // GIR_Coverage, 22876, 7147 GIR_Done, 7148 // Label 564: @14971 7149 GIM_Try, /*On fail goto*//*Label 565*/ 15075, // Rule ID 23906 // 7150 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 7151 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID, 7152 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 7153 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SHL, 7154 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, 7155 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s8, 7156 GIM_CheckConstantInt, /*MI*/1, /*Op*/1, 1, 7157 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/X86::GR8RegClassID, 7158 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::GR64RegClassID, 7159 GIM_CheckIsSafeToFold, /*InsnID*/1, 7160 // (xor:{ *:[i64] } (shl:{ *:[i64] } 1:{ *:[i64] }, GR8:{ *:[i8] }:$src2), GR64:{ *:[i64] }:$src1) => (BTC64rr:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src1, (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), GR8:{ *:[i8] }:$src2, sub_8bit:{ *:[i32] })) 7161 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, 7162 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, 7163 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, 7164 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 7165 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 7166 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, 7167 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 7168 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, 7169 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // src2 7170 GIR_AddImm, /*InsnID*/1, /*Imm*/1, 7171 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, X86::GR64_with_sub_8bitRegClassID, 7172 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, X86::GR64_with_sub_8bitRegClassID, 7173 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, X86::GR8RegClassID, 7174 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BTC64rr, 7175 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 7176 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 7177 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 7178 GIR_EraseFromParent, /*InsnID*/0, 7179 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7180 // GIR_Coverage, 23906, 7181 GIR_Done, 7182 // Label 565: @15075 7183 GIM_Try, /*On fail goto*//*Label 566*/ 15129, // Rule ID 15909 // 7184 GIM_CheckFeatures, GIFBS_HasBMI, 7185 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 7186 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID, 7187 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR64RegClassID, 7188 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 7189 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD, 7190 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, 7191 // MIs[1] src 7192 GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/1, /*OtherMI*/0, /*OtherOpIdx*/1, 7193 GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1, 7194 GIM_CheckIsSafeToFold, /*InsnID*/1, 7195 // (xor:{ *:[i64] } GR64:{ *:[i64] }:$src, (add:{ *:[i64] } GR64:{ *:[i64] }:$src, -1:{ *:[i64] })) => (BLSMSK64rr:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src) 7196 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLSMSK64rr, 7197 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 7198 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 7199 GIR_EraseFromParent, /*InsnID*/0, 7200 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7201 // GIR_Coverage, 15909, 7202 GIR_Done, 7203 // Label 566: @15129 7204 GIM_Try, /*On fail goto*//*Label 567*/ 15183, // Rule ID 15933 // 7205 GIM_CheckFeatures, GIFBS_HasTBM, 7206 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 7207 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID, 7208 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR64RegClassID, 7209 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 7210 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD, 7211 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, 7212 // MIs[1] src 7213 GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/1, /*OtherMI*/0, /*OtherOpIdx*/1, 7214 GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 1, 7215 GIM_CheckIsSafeToFold, /*InsnID*/1, 7216 // (xor:{ *:[i64] } GR64:{ *:[i64] }:$src, (add:{ *:[i64] } GR64:{ *:[i64] }:$src, 1:{ *:[i64] })) => (BLCMSK64rr:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src) 7217 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLCMSK64rr, 7218 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 7219 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 7220 GIR_EraseFromParent, /*InsnID*/0, 7221 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7222 // GIR_Coverage, 15933, 7223 GIR_Done, 7224 // Label 567: @15183 7225 GIM_Try, /*On fail goto*//*Label 568*/ 15287, // Rule ID 20991 // 7226 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 7227 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID, 7228 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR64RegClassID, 7229 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 7230 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SHL, 7231 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, 7232 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s8, 7233 GIM_CheckConstantInt, /*MI*/1, /*Op*/1, 1, 7234 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/X86::GR8RegClassID, 7235 GIM_CheckIsSafeToFold, /*InsnID*/1, 7236 // (xor:{ *:[i64] } GR64:{ *:[i64] }:$src1, (shl:{ *:[i64] } 1:{ *:[i64] }, GR8:{ *:[i8] }:$src2)) => (BTC64rr:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src1, (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), GR8:{ *:[i8] }:$src2, sub_8bit:{ *:[i32] })) 7237 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, 7238 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, 7239 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, 7240 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 7241 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 7242 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, 7243 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 7244 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, 7245 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // src2 7246 GIR_AddImm, /*InsnID*/1, /*Imm*/1, 7247 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, X86::GR64_with_sub_8bitRegClassID, 7248 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, X86::GR64_with_sub_8bitRegClassID, 7249 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, X86::GR8RegClassID, 7250 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BTC64rr, 7251 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 7252 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 7253 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 7254 GIR_EraseFromParent, /*InsnID*/0, 7255 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7256 // GIR_Coverage, 20991, 7257 GIR_Done, 7258 // Label 568: @15287 7259 GIM_Try, /*On fail goto*//*Label 569*/ 15321, // Rule ID 168 // 7260 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 7261 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID, 7262 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR64RegClassID, 7263 GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1, 7264 // (xor:{ *:[i64] } GR64:{ *:[i64] }:$src1, -1:{ *:[i64] }) => (NOT64r:{ *:[i64] } GR64:{ *:[i64] }:$src1) 7265 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::NOT64r, 7266 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 7267 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 7268 GIR_EraseFromParent, /*InsnID*/0, 7269 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7270 // GIR_Coverage, 168, 7271 GIR_Done, 7272 // Label 569: @15321 7273 GIM_Try, /*On fail goto*//*Label 570*/ 15366, // Rule ID 15693 // 7274 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 7275 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID, 7276 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR64RegClassID, 7277 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 7278 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 7279 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_i64immSExt8, 7280 // MIs[1] Operand 1 7281 // No operand predicates 7282 GIM_CheckIsSafeToFold, /*InsnID*/1, 7283 // (xor:{ *:[i64] } GR64:{ *:[i64] }:$src1, (imm:{ *:[i64] })<<P:Predicate_i64immSExt8>>:$src2) => (XOR64ri8:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src1, (imm:{ *:[i64] })<<P:Predicate_i64immSExt8>>:$src2) 7284 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::XOR64ri8, 7285 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 7286 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 7287 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // src2 7288 GIR_EraseFromParent, /*InsnID*/0, 7289 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7290 // GIR_Coverage, 15693, 7291 GIR_Done, 7292 // Label 570: @15366 7293 GIM_Try, /*On fail goto*//*Label 571*/ 15411, // Rule ID 15694 // 7294 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 7295 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID, 7296 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR64RegClassID, 7297 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 7298 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 7299 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_i64immSExt32, 7300 // MIs[1] Operand 1 7301 // No operand predicates 7302 GIM_CheckIsSafeToFold, /*InsnID*/1, 7303 // (xor:{ *:[i64] } GR64:{ *:[i64] }:$src1, (imm:{ *:[i64] })<<P:Predicate_i64immSExt32>>:$src2) => (XOR64ri32:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src1, (imm:{ *:[i64] })<<P:Predicate_i64immSExt32>>:$src2) 7304 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::XOR64ri32, 7305 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 7306 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 7307 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // src2 7308 GIR_EraseFromParent, /*InsnID*/0, 7309 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7310 // GIR_Coverage, 15694, 7311 GIR_Done, 7312 // Label 571: @15411 7313 GIM_Try, /*On fail goto*//*Label 572*/ 15439, // Rule ID 15683 // 7314 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 7315 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID, 7316 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR64RegClassID, 7317 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::GR64RegClassID, 7318 // (xor:{ *:[i64] } GR64:{ *:[i64] }:$src1, GR64:{ *:[i64] }:$src2) => (XOR64rr:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src1, GR64:{ *:[i64] }:$src2) 7319 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::XOR64rr, 7320 GIR_AddImplicitDef, /*InsnID*/0, X86::EFLAGS, 7321 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7322 // GIR_Coverage, 15683, 7323 GIR_Done, 7324 // Label 572: @15439 7325 GIM_Reject, 7326 // Label 562: @15440 7327 GIM_Reject, 7328 // Label 512: @15441 7329 GIM_Try, /*On fail goto*//*Label 573*/ 15931, 7330 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s1, 7331 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s1, 7332 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VK2RegClassID, 7333 GIM_Try, /*On fail goto*//*Label 574*/ 15564, // Rule ID 23240 // 7334 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 7335 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, 7336 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s1, 7337 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s1, 7338 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::VK2RegClassID, 7339 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] 7340 GIM_CheckOpcodeIsEither, /*MI*/2, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, 7341 GIM_CheckIsBuildVectorAllOnes, /*MI*/2, 7342 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VK2RegClassID, 7343 GIM_CheckIsSafeToFold, /*InsnID*/1, 7344 GIM_CheckIsSafeToFold, /*InsnID*/2, 7345 // (xor:{ *:[v2i1] } (xor:{ *:[v2i1] } VK2:{ *:[v2i1] }:$src1, immAllOnesV:{ *:[v2i1] }), VK2:{ *:[v2i1] }:$src2) => (COPY_TO_REGCLASS:{ *:[v2i1] } (KXNORWrr:{ *:[v16i1] } (COPY_TO_REGCLASS:{ *:[v16i1] } VK2:{ *:[v2i1] }:$src1, VK16:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v16i1] } VK2:{ *:[v2i1] }:$src2, VK16:{ *:[i32] })), VK2:{ *:[i32] }) 7346 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s1, 7347 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s1, 7348 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s1, 7349 GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::COPY, 7350 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, 7351 GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // src2 7352 GIR_ConstrainSelectedInstOperands, /*InsnID*/3, 7353 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY, 7354 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 7355 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, // src1 7356 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 7357 GIR_BuildMI, /*InsnID*/1, /*Opcode*/X86::KXNORWrr, 7358 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 7359 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, 7360 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/2, /*TempRegFlags*/0, 7361 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 7362 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 7363 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 7364 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 7365 GIR_EraseFromParent, /*InsnID*/0, 7366 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, X86::VK2RegClassID, 7367 // GIR_Coverage, 23240, 7368 GIR_Done, 7369 // Label 574: @15564 7370 GIM_Try, /*On fail goto*//*Label 575*/ 15673, // Rule ID 17936 // 7371 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 7372 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, 7373 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s1, 7374 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s1, 7375 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::VK2RegClassID, 7376 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/X86::VK2RegClassID, 7377 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] 7378 GIM_CheckOpcodeIsEither, /*MI*/2, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, 7379 GIM_CheckIsBuildVectorAllOnes, /*MI*/2, 7380 GIM_CheckIsSafeToFold, /*InsnID*/1, 7381 GIM_CheckIsSafeToFold, /*InsnID*/2, 7382 // (xor:{ *:[v2i1] } (xor:{ *:[v2i1] } VK2:{ *:[v2i1] }:$src1, VK2:{ *:[v2i1] }:$src2), immAllOnesV:{ *:[v2i1] }) => (COPY_TO_REGCLASS:{ *:[v2i1] } (KXNORWrr:{ *:[v16i1] } (COPY_TO_REGCLASS:{ *:[v16i1] } VK2:{ *:[v2i1] }:$src1, VK16:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v16i1] } VK2:{ *:[v2i1] }:$src2, VK16:{ *:[i32] })), VK2:{ *:[i32] }) 7383 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s1, 7384 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s1, 7385 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s1, 7386 GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::COPY, 7387 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, 7388 GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/1, /*OpIdx*/2, // src2 7389 GIR_ConstrainSelectedInstOperands, /*InsnID*/3, 7390 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY, 7391 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 7392 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, // src1 7393 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 7394 GIR_BuildMI, /*InsnID*/1, /*Opcode*/X86::KXNORWrr, 7395 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 7396 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, 7397 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/2, /*TempRegFlags*/0, 7398 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 7399 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 7400 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 7401 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 7402 GIR_EraseFromParent, /*InsnID*/0, 7403 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, X86::VK2RegClassID, 7404 // GIR_Coverage, 17936, 7405 GIR_Done, 7406 // Label 575: @15673 7407 GIM_Try, /*On fail goto*//*Label 576*/ 15782, // Rule ID 23241 // 7408 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VK2RegClassID, 7409 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 7410 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, 7411 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s1, 7412 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s1, 7413 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::VK2RegClassID, 7414 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] 7415 GIM_CheckOpcodeIsEither, /*MI*/2, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, 7416 GIM_CheckIsBuildVectorAllOnes, /*MI*/2, 7417 GIM_CheckIsSafeToFold, /*InsnID*/1, 7418 GIM_CheckIsSafeToFold, /*InsnID*/2, 7419 // (xor:{ *:[v2i1] } VK2:{ *:[v2i1] }:$src2, (xor:{ *:[v2i1] } VK2:{ *:[v2i1] }:$src1, immAllOnesV:{ *:[v2i1] })) => (COPY_TO_REGCLASS:{ *:[v2i1] } (KXNORWrr:{ *:[v16i1] } (COPY_TO_REGCLASS:{ *:[v16i1] } VK2:{ *:[v2i1] }:$src1, VK16:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v16i1] } VK2:{ *:[v2i1] }:$src2, VK16:{ *:[i32] })), VK2:{ *:[i32] }) 7420 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s1, 7421 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s1, 7422 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s1, 7423 GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::COPY, 7424 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, 7425 GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // src2 7426 GIR_ConstrainSelectedInstOperands, /*InsnID*/3, 7427 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY, 7428 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 7429 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, // src1 7430 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 7431 GIR_BuildMI, /*InsnID*/1, /*Opcode*/X86::KXNORWrr, 7432 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 7433 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, 7434 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/2, /*TempRegFlags*/0, 7435 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 7436 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 7437 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 7438 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 7439 GIR_EraseFromParent, /*InsnID*/0, 7440 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, X86::VK2RegClassID, 7441 // GIR_Coverage, 23241, 7442 GIR_Done, 7443 // Label 576: @15782 7444 GIM_Try, /*On fail goto*//*Label 577*/ 15850, // Rule ID 17920 // 7445 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VK2RegClassID, 7446 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 7447 GIM_CheckOpcodeIsEither, /*MI*/1, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, 7448 GIM_CheckIsBuildVectorAllOnes, /*MI*/1, 7449 GIM_CheckIsSafeToFold, /*InsnID*/1, 7450 // (xor:{ *:[v2i1] } VK2:{ *:[v2i1] }:$src, immAllOnesV:{ *:[v2i1] }) => (COPY_TO_REGCLASS:{ *:[v2i1] } (KNOTWrr:{ *:[v16i1] } (COPY_TO_REGCLASS:{ *:[v16i1] } VK2:{ *:[v2i1] }:$src, VK16:{ *:[i32] })), VK2:{ *:[i32] }) 7451 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s1, 7452 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s1, 7453 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY, 7454 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 7455 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src 7456 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 7457 GIR_BuildMI, /*InsnID*/1, /*Opcode*/X86::KNOTWrr, 7458 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 7459 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, 7460 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 7461 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 7462 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 7463 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 7464 GIR_EraseFromParent, /*InsnID*/0, 7465 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, X86::VK2RegClassID, 7466 // GIR_Coverage, 17920, 7467 GIR_Done, 7468 // Label 577: @15850 7469 GIM_Try, /*On fail goto*//*Label 578*/ 15930, // Rule ID 17940 // 7470 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VK2RegClassID, 7471 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VK2RegClassID, 7472 // (xor:{ *:[v2i1] } VK2:{ *:[v2i1] }:$src1, VK2:{ *:[v2i1] }:$src2) => (COPY_TO_REGCLASS:{ *:[v2i1] } (KXORWrr:{ *:[v16i1] } (COPY_TO_REGCLASS:{ *:[v16i1] } VK2:{ *:[v2i1] }:$src1, VK16:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v16i1] } VK2:{ *:[v2i1] }:$src2, VK16:{ *:[i32] })), VK2:{ *:[i32] }) 7473 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s1, 7474 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s1, 7475 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s1, 7476 GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::COPY, 7477 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, 7478 GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // src2 7479 GIR_ConstrainSelectedInstOperands, /*InsnID*/3, 7480 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY, 7481 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 7482 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src1 7483 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 7484 GIR_BuildMI, /*InsnID*/1, /*Opcode*/X86::KXORWrr, 7485 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 7486 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, 7487 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/2, /*TempRegFlags*/0, 7488 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 7489 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 7490 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 7491 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 7492 GIR_EraseFromParent, /*InsnID*/0, 7493 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, X86::VK2RegClassID, 7494 // GIR_Coverage, 17940, 7495 GIR_Done, 7496 // Label 578: @15930 7497 GIM_Reject, 7498 // Label 573: @15931 7499 GIM_Reject, 7500 // Label 513: @15932 7501 GIM_Try, /*On fail goto*//*Label 579*/ 16272, 7502 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, 7503 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 7504 GIM_Try, /*On fail goto*//*Label 580*/ 16151, // Rule ID 20365 // 7505 GIM_CheckFeatures, GIFBS_HasAVX512_NoVLX, 7506 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 7507 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID, 7508 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 7509 GIM_CheckOpcodeIsEither, /*MI*/1, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, 7510 GIM_CheckIsBuildVectorAllOnes, /*MI*/1, 7511 GIM_CheckIsSafeToFold, /*InsnID*/1, 7512 // (xor:{ *:[v2i64] } VR128X:{ *:[v2i64] }:$src, immAllOnesV:{ *:[v2i64] }) => (EXTRACT_SUBREG:{ *:[v2i64] } (VPTERNLOGQZrri:{ *:[v64i8] } (INSERT_SUBREG:{ *:[v8i64] } (IMPLICIT_DEF:{ *:[v8i64] }), VR128X:{ *:[v2i64] }:$src, sub_xmm:{ *:[i32] }), (INSERT_SUBREG:{ *:[v8i64] } (IMPLICIT_DEF:{ *:[v8i64] }), VR128X:{ *:[v2i64] }:$src, sub_xmm:{ *:[i32] }), (INSERT_SUBREG:{ *:[v8i64] } (IMPLICIT_DEF:{ *:[v8i64] }), VR128X:{ *:[v2i64] }:$src, sub_xmm:{ *:[i32] }), 15:{ *:[i8] }), sub_xmm:{ *:[i32] }) 7513 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v64s8, 7514 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s64, 7515 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v8s64, 7516 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v8s64, 7517 GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v8s64, 7518 GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v8s64, 7519 GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_v8s64, 7520 GIR_BuildMI, /*InsnID*/7, /*Opcode*/TargetOpcode::IMPLICIT_DEF, 7521 GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/RegState::Define, 7522 GIR_ConstrainSelectedInstOperands, /*InsnID*/7, 7523 GIR_BuildMI, /*InsnID*/6, /*Opcode*/TargetOpcode::INSERT_SUBREG, 7524 GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/RegState::Define, 7525 GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/6, /*TempRegFlags*/0, 7526 GIR_Copy, /*NewInsnID*/6, /*OldInsnID*/0, /*OpIdx*/1, // src 7527 GIR_AddImm, /*InsnID*/6, /*Imm*/9, 7528 GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, X86::VR512RegClassID, 7529 GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, X86::VR512RegClassID, 7530 GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/2, X86::VR128XRegClassID, 7531 GIR_BuildMI, /*InsnID*/5, /*Opcode*/TargetOpcode::IMPLICIT_DEF, 7532 GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/RegState::Define, 7533 GIR_ConstrainSelectedInstOperands, /*InsnID*/5, 7534 GIR_BuildMI, /*InsnID*/4, /*Opcode*/TargetOpcode::INSERT_SUBREG, 7535 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define, 7536 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/4, /*TempRegFlags*/0, 7537 GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/1, // src 7538 GIR_AddImm, /*InsnID*/4, /*Imm*/9, 7539 GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, X86::VR512RegClassID, 7540 GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/1, X86::VR512RegClassID, 7541 GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/2, X86::VR128XRegClassID, 7542 GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::IMPLICIT_DEF, 7543 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, 7544 GIR_ConstrainSelectedInstOperands, /*InsnID*/3, 7545 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::INSERT_SUBREG, 7546 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 7547 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/2, /*TempRegFlags*/0, 7548 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src 7549 GIR_AddImm, /*InsnID*/2, /*Imm*/9, 7550 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, X86::VR512RegClassID, 7551 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, X86::VR512RegClassID, 7552 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, X86::VR128XRegClassID, 7553 GIR_BuildMI, /*InsnID*/1, /*Opcode*/X86::VPTERNLOGQZrri, 7554 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 7555 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, 7556 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/3, /*TempRegFlags*/0, 7557 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/5, /*TempRegFlags*/0, 7558 GIR_AddImm, /*InsnID*/1, /*Imm*/15, 7559 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 7560 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 7561 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 7562 GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, X86::sub_xmm, 7563 GIR_EraseFromParent, /*InsnID*/0, 7564 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, X86::FR16XRegClassID, 7565 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, X86::VR512RegClassID, 7566 // GIR_Coverage, 20365, 7567 GIR_Done, 7568 // Label 580: @16151 7569 GIM_Try, /*On fail goto*//*Label 581*/ 16202, // Rule ID 20373 // 7570 GIM_CheckFeatures, GIFBS_HasVLX, 7571 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID, 7572 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID, 7573 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 7574 GIM_CheckOpcodeIsEither, /*MI*/1, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, 7575 GIM_CheckIsBuildVectorAllOnes, /*MI*/1, 7576 GIM_CheckIsSafeToFold, /*InsnID*/1, 7577 // (xor:{ *:[v2i64] } VR128X:{ *:[v2i64] }:$src, immAllOnesV:{ *:[v2i64] }) => (VPTERNLOGQZ128rri:{ *:[v2i64] } VR128X:{ *:[v2i64] }:$src, VR128X:{ *:[v2i64] }:$src, VR128X:{ *:[v2i64] }:$src, 15:{ *:[i8] }) 7578 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VPTERNLOGQZ128rri, 7579 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 7580 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 7581 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 7582 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 7583 GIR_AddImm, /*InsnID*/0, /*Imm*/15, 7584 GIR_EraseFromParent, /*InsnID*/0, 7585 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7586 // GIR_Coverage, 20373, 7587 GIR_Done, 7588 // Label 581: @16202 7589 GIM_Try, /*On fail goto*//*Label 582*/ 16225, // Rule ID 1854 // 7590 GIM_CheckFeatures, GIFBS_HasAVX_NoVLX, 7591 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 7592 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 7593 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 7594 // (xor:{ *:[v2i64] } VR128:{ *:[v2i64] }:$src1, VR128:{ *:[v2i64] }:$src2) => (VPXORrr:{ *:[v2i64] } VR128:{ *:[v2i64] }:$src1, VR128:{ *:[v2i64] }:$src2) 7595 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPXORrr, 7596 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7597 // GIR_Coverage, 1854, 7598 GIR_Done, 7599 // Label 582: @16225 7600 GIM_Try, /*On fail goto*//*Label 583*/ 16248, // Rule ID 1856 // 7601 GIM_CheckFeatures, GIFBS_UseSSE2, 7602 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 7603 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 7604 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 7605 // (xor:{ *:[v2i64] } VR128:{ *:[v2i64] }:$src1, VR128:{ *:[v2i64] }:$src2) => (PXORrr:{ *:[v2i64] } VR128:{ *:[v2i64] }:$src1, VR128:{ *:[v2i64] }:$src2) 7606 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::PXORrr, 7607 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7608 // GIR_Coverage, 1856, 7609 GIR_Done, 7610 // Label 583: @16248 7611 GIM_Try, /*On fail goto*//*Label 584*/ 16271, // Rule ID 5451 // 7612 GIM_CheckFeatures, GIFBS_HasAVX512_HasVLX, 7613 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID, 7614 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID, 7615 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128XRegClassID, 7616 // (xor:{ *:[v2i64] } VR128X:{ *:[v2i64] }:$src1, VR128X:{ *:[v2i64] }:$src2) => (VPXORQZ128rr:{ *:[v2i64] } VR128X:{ *:[v2i64] }:$src1, VR128X:{ *:[v2i64] }:$src2) 7617 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPXORQZ128rr, 7618 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7619 // GIR_Coverage, 5451, 7620 GIR_Done, 7621 // Label 584: @16271 7622 GIM_Reject, 7623 // Label 579: @16272 7624 GIM_Reject, 7625 // Label 514: @16273 7626 GIM_Try, /*On fail goto*//*Label 585*/ 16763, 7627 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s1, 7628 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s1, 7629 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VK4RegClassID, 7630 GIM_Try, /*On fail goto*//*Label 586*/ 16396, // Rule ID 23242 // 7631 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 7632 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, 7633 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s1, 7634 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s1, 7635 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::VK4RegClassID, 7636 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] 7637 GIM_CheckOpcodeIsEither, /*MI*/2, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, 7638 GIM_CheckIsBuildVectorAllOnes, /*MI*/2, 7639 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VK4RegClassID, 7640 GIM_CheckIsSafeToFold, /*InsnID*/1, 7641 GIM_CheckIsSafeToFold, /*InsnID*/2, 7642 // (xor:{ *:[v4i1] } (xor:{ *:[v4i1] } VK4:{ *:[v4i1] }:$src1, immAllOnesV:{ *:[v4i1] }), VK4:{ *:[v4i1] }:$src2) => (COPY_TO_REGCLASS:{ *:[v4i1] } (KXNORWrr:{ *:[v16i1] } (COPY_TO_REGCLASS:{ *:[v16i1] } VK4:{ *:[v4i1] }:$src1, VK16:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v16i1] } VK4:{ *:[v4i1] }:$src2, VK16:{ *:[i32] })), VK4:{ *:[i32] }) 7643 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s1, 7644 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s1, 7645 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s1, 7646 GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::COPY, 7647 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, 7648 GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // src2 7649 GIR_ConstrainSelectedInstOperands, /*InsnID*/3, 7650 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY, 7651 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 7652 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, // src1 7653 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 7654 GIR_BuildMI, /*InsnID*/1, /*Opcode*/X86::KXNORWrr, 7655 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 7656 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, 7657 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/2, /*TempRegFlags*/0, 7658 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 7659 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 7660 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 7661 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 7662 GIR_EraseFromParent, /*InsnID*/0, 7663 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, X86::VK4RegClassID, 7664 // GIR_Coverage, 23242, 7665 GIR_Done, 7666 // Label 586: @16396 7667 GIM_Try, /*On fail goto*//*Label 587*/ 16505, // Rule ID 17937 // 7668 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 7669 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, 7670 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s1, 7671 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s1, 7672 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::VK4RegClassID, 7673 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/X86::VK4RegClassID, 7674 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] 7675 GIM_CheckOpcodeIsEither, /*MI*/2, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, 7676 GIM_CheckIsBuildVectorAllOnes, /*MI*/2, 7677 GIM_CheckIsSafeToFold, /*InsnID*/1, 7678 GIM_CheckIsSafeToFold, /*InsnID*/2, 7679 // (xor:{ *:[v4i1] } (xor:{ *:[v4i1] } VK4:{ *:[v4i1] }:$src1, VK4:{ *:[v4i1] }:$src2), immAllOnesV:{ *:[v4i1] }) => (COPY_TO_REGCLASS:{ *:[v4i1] } (KXNORWrr:{ *:[v16i1] } (COPY_TO_REGCLASS:{ *:[v16i1] } VK4:{ *:[v4i1] }:$src1, VK16:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v16i1] } VK4:{ *:[v4i1] }:$src2, VK16:{ *:[i32] })), VK4:{ *:[i32] }) 7680 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s1, 7681 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s1, 7682 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s1, 7683 GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::COPY, 7684 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, 7685 GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/1, /*OpIdx*/2, // src2 7686 GIR_ConstrainSelectedInstOperands, /*InsnID*/3, 7687 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY, 7688 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 7689 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, // src1 7690 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 7691 GIR_BuildMI, /*InsnID*/1, /*Opcode*/X86::KXNORWrr, 7692 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 7693 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, 7694 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/2, /*TempRegFlags*/0, 7695 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 7696 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 7697 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 7698 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 7699 GIR_EraseFromParent, /*InsnID*/0, 7700 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, X86::VK4RegClassID, 7701 // GIR_Coverage, 17937, 7702 GIR_Done, 7703 // Label 587: @16505 7704 GIM_Try, /*On fail goto*//*Label 588*/ 16614, // Rule ID 23243 // 7705 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VK4RegClassID, 7706 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 7707 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, 7708 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s1, 7709 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s1, 7710 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::VK4RegClassID, 7711 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] 7712 GIM_CheckOpcodeIsEither, /*MI*/2, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, 7713 GIM_CheckIsBuildVectorAllOnes, /*MI*/2, 7714 GIM_CheckIsSafeToFold, /*InsnID*/1, 7715 GIM_CheckIsSafeToFold, /*InsnID*/2, 7716 // (xor:{ *:[v4i1] } VK4:{ *:[v4i1] }:$src2, (xor:{ *:[v4i1] } VK4:{ *:[v4i1] }:$src1, immAllOnesV:{ *:[v4i1] })) => (COPY_TO_REGCLASS:{ *:[v4i1] } (KXNORWrr:{ *:[v16i1] } (COPY_TO_REGCLASS:{ *:[v16i1] } VK4:{ *:[v4i1] }:$src1, VK16:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v16i1] } VK4:{ *:[v4i1] }:$src2, VK16:{ *:[i32] })), VK4:{ *:[i32] }) 7717 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s1, 7718 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s1, 7719 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s1, 7720 GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::COPY, 7721 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, 7722 GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // src2 7723 GIR_ConstrainSelectedInstOperands, /*InsnID*/3, 7724 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY, 7725 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 7726 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, // src1 7727 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 7728 GIR_BuildMI, /*InsnID*/1, /*Opcode*/X86::KXNORWrr, 7729 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 7730 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, 7731 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/2, /*TempRegFlags*/0, 7732 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 7733 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 7734 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 7735 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 7736 GIR_EraseFromParent, /*InsnID*/0, 7737 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, X86::VK4RegClassID, 7738 // GIR_Coverage, 23243, 7739 GIR_Done, 7740 // Label 588: @16614 7741 GIM_Try, /*On fail goto*//*Label 589*/ 16682, // Rule ID 17919 // 7742 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VK4RegClassID, 7743 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 7744 GIM_CheckOpcodeIsEither, /*MI*/1, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, 7745 GIM_CheckIsBuildVectorAllOnes, /*MI*/1, 7746 GIM_CheckIsSafeToFold, /*InsnID*/1, 7747 // (xor:{ *:[v4i1] } VK4:{ *:[v4i1] }:$src, immAllOnesV:{ *:[v4i1] }) => (COPY_TO_REGCLASS:{ *:[v4i1] } (KNOTWrr:{ *:[v16i1] } (COPY_TO_REGCLASS:{ *:[v16i1] } VK4:{ *:[v4i1] }:$src, VK16:{ *:[i32] })), VK4:{ *:[i32] }) 7748 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s1, 7749 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s1, 7750 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY, 7751 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 7752 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src 7753 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 7754 GIR_BuildMI, /*InsnID*/1, /*Opcode*/X86::KNOTWrr, 7755 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 7756 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, 7757 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 7758 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 7759 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 7760 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 7761 GIR_EraseFromParent, /*InsnID*/0, 7762 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, X86::VK4RegClassID, 7763 // GIR_Coverage, 17919, 7764 GIR_Done, 7765 // Label 589: @16682 7766 GIM_Try, /*On fail goto*//*Label 590*/ 16762, // Rule ID 17941 // 7767 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VK4RegClassID, 7768 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VK4RegClassID, 7769 // (xor:{ *:[v4i1] } VK4:{ *:[v4i1] }:$src1, VK4:{ *:[v4i1] }:$src2) => (COPY_TO_REGCLASS:{ *:[v4i1] } (KXORWrr:{ *:[v16i1] } (COPY_TO_REGCLASS:{ *:[v16i1] } VK4:{ *:[v4i1] }:$src1, VK16:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v16i1] } VK4:{ *:[v4i1] }:$src2, VK16:{ *:[i32] })), VK4:{ *:[i32] }) 7770 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s1, 7771 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s1, 7772 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s1, 7773 GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::COPY, 7774 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, 7775 GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // src2 7776 GIR_ConstrainSelectedInstOperands, /*InsnID*/3, 7777 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY, 7778 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 7779 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src1 7780 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 7781 GIR_BuildMI, /*InsnID*/1, /*Opcode*/X86::KXORWrr, 7782 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 7783 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, 7784 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/2, /*TempRegFlags*/0, 7785 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 7786 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 7787 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 7788 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 7789 GIR_EraseFromParent, /*InsnID*/0, 7790 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, X86::VK4RegClassID, 7791 // GIR_Coverage, 17941, 7792 GIR_Done, 7793 // Label 590: @16762 7794 GIM_Reject, 7795 // Label 585: @16763 7796 GIM_Reject, 7797 // Label 515: @16764 7798 GIM_Try, /*On fail goto*//*Label 591*/ 17104, 7799 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, 7800 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 7801 GIM_Try, /*On fail goto*//*Label 592*/ 16983, // Rule ID 20364 // 7802 GIM_CheckFeatures, GIFBS_HasAVX512_NoVLX, 7803 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 7804 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID, 7805 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 7806 GIM_CheckOpcodeIsEither, /*MI*/1, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, 7807 GIM_CheckIsBuildVectorAllOnes, /*MI*/1, 7808 GIM_CheckIsSafeToFold, /*InsnID*/1, 7809 // (xor:{ *:[v4i32] } VR128X:{ *:[v4i32] }:$src, immAllOnesV:{ *:[v4i32] }) => (EXTRACT_SUBREG:{ *:[v4i32] } (VPTERNLOGQZrri:{ *:[v64i8] } (INSERT_SUBREG:{ *:[v8i64] } (IMPLICIT_DEF:{ *:[v8i64] }), VR128X:{ *:[v4i32] }:$src, sub_xmm:{ *:[i32] }), (INSERT_SUBREG:{ *:[v8i64] } (IMPLICIT_DEF:{ *:[v8i64] }), VR128X:{ *:[v4i32] }:$src, sub_xmm:{ *:[i32] }), (INSERT_SUBREG:{ *:[v8i64] } (IMPLICIT_DEF:{ *:[v8i64] }), VR128X:{ *:[v4i32] }:$src, sub_xmm:{ *:[i32] }), 15:{ *:[i8] }), sub_xmm:{ *:[i32] }) 7810 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v64s8, 7811 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s64, 7812 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v8s64, 7813 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v8s64, 7814 GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v8s64, 7815 GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v8s64, 7816 GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_v8s64, 7817 GIR_BuildMI, /*InsnID*/7, /*Opcode*/TargetOpcode::IMPLICIT_DEF, 7818 GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/RegState::Define, 7819 GIR_ConstrainSelectedInstOperands, /*InsnID*/7, 7820 GIR_BuildMI, /*InsnID*/6, /*Opcode*/TargetOpcode::INSERT_SUBREG, 7821 GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/RegState::Define, 7822 GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/6, /*TempRegFlags*/0, 7823 GIR_Copy, /*NewInsnID*/6, /*OldInsnID*/0, /*OpIdx*/1, // src 7824 GIR_AddImm, /*InsnID*/6, /*Imm*/9, 7825 GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, X86::VR512RegClassID, 7826 GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, X86::VR512RegClassID, 7827 GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/2, X86::VR128XRegClassID, 7828 GIR_BuildMI, /*InsnID*/5, /*Opcode*/TargetOpcode::IMPLICIT_DEF, 7829 GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/RegState::Define, 7830 GIR_ConstrainSelectedInstOperands, /*InsnID*/5, 7831 GIR_BuildMI, /*InsnID*/4, /*Opcode*/TargetOpcode::INSERT_SUBREG, 7832 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define, 7833 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/4, /*TempRegFlags*/0, 7834 GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/1, // src 7835 GIR_AddImm, /*InsnID*/4, /*Imm*/9, 7836 GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, X86::VR512RegClassID, 7837 GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/1, X86::VR512RegClassID, 7838 GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/2, X86::VR128XRegClassID, 7839 GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::IMPLICIT_DEF, 7840 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, 7841 GIR_ConstrainSelectedInstOperands, /*InsnID*/3, 7842 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::INSERT_SUBREG, 7843 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 7844 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/2, /*TempRegFlags*/0, 7845 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src 7846 GIR_AddImm, /*InsnID*/2, /*Imm*/9, 7847 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, X86::VR512RegClassID, 7848 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, X86::VR512RegClassID, 7849 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, X86::VR128XRegClassID, 7850 GIR_BuildMI, /*InsnID*/1, /*Opcode*/X86::VPTERNLOGQZrri, 7851 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 7852 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, 7853 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/3, /*TempRegFlags*/0, 7854 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/5, /*TempRegFlags*/0, 7855 GIR_AddImm, /*InsnID*/1, /*Imm*/15, 7856 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 7857 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 7858 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 7859 GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, X86::sub_xmm, 7860 GIR_EraseFromParent, /*InsnID*/0, 7861 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, X86::FR16XRegClassID, 7862 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, X86::VR512RegClassID, 7863 // GIR_Coverage, 20364, 7864 GIR_Done, 7865 // Label 592: @16983 7866 GIM_Try, /*On fail goto*//*Label 593*/ 17034, // Rule ID 20372 // 7867 GIM_CheckFeatures, GIFBS_HasVLX, 7868 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID, 7869 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID, 7870 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 7871 GIM_CheckOpcodeIsEither, /*MI*/1, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, 7872 GIM_CheckIsBuildVectorAllOnes, /*MI*/1, 7873 GIM_CheckIsSafeToFold, /*InsnID*/1, 7874 // (xor:{ *:[v4i32] } VR128X:{ *:[v4i32] }:$src, immAllOnesV:{ *:[v4i32] }) => (VPTERNLOGQZ128rri:{ *:[v4i32] } VR128X:{ *:[v4i32] }:$src, VR128X:{ *:[v4i32] }:$src, VR128X:{ *:[v4i32] }:$src, 15:{ *:[i8] }) 7875 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VPTERNLOGQZ128rri, 7876 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 7877 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 7878 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 7879 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 7880 GIR_AddImm, /*InsnID*/0, /*Imm*/15, 7881 GIR_EraseFromParent, /*InsnID*/0, 7882 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7883 // GIR_Coverage, 20372, 7884 GIR_Done, 7885 // Label 593: @17034 7886 GIM_Try, /*On fail goto*//*Label 594*/ 17057, // Rule ID 5478 // 7887 GIM_CheckFeatures, GIFBS_HasAVX512_HasVLX, 7888 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID, 7889 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID, 7890 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128XRegClassID, 7891 // (xor:{ *:[v4i32] } VR128X:{ *:[v4i32] }:$src1, VR128X:{ *:[v4i32] }:$src2) => (VPXORDZ128rr:{ *:[v4i32] } VR128X:{ *:[v4i32] }:$src1, VR128X:{ *:[v4i32] }:$src2) 7892 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPXORDZ128rr, 7893 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7894 // GIR_Coverage, 5478, 7895 GIR_Done, 7896 // Label 594: @17057 7897 GIM_Try, /*On fail goto*//*Label 595*/ 17080, // Rule ID 16601 // 7898 GIM_CheckFeatures, GIFBS_HasAVX_NoVLX, 7899 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 7900 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 7901 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 7902 // (xor:{ *:[v4i32] } VR128:{ *:[v4i32] }:$src1, VR128:{ *:[v4i32] }:$src2) => (VPXORrr:{ *:[v4i32] } VR128:{ *:[v4i32] }:$src1, VR128:{ *:[v4i32] }:$src2) 7903 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPXORrr, 7904 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7905 // GIR_Coverage, 16601, 7906 GIR_Done, 7907 // Label 595: @17080 7908 GIM_Try, /*On fail goto*//*Label 596*/ 17103, // Rule ID 16625 // 7909 GIM_CheckFeatures, GIFBS_UseSSE2, 7910 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 7911 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 7912 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 7913 // (xor:{ *:[v4i32] } VR128:{ *:[v4i32] }:$src1, VR128:{ *:[v4i32] }:$src2) => (PXORrr:{ *:[v4i32] } VR128:{ *:[v4i32] }:$src1, VR128:{ *:[v4i32] }:$src2) 7914 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::PXORrr, 7915 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7916 // GIR_Coverage, 16625, 7917 GIR_Done, 7918 // Label 596: @17103 7919 GIM_Reject, 7920 // Label 591: @17104 7921 GIM_Reject, 7922 // Label 516: @17105 7923 GIM_Try, /*On fail goto*//*Label 597*/ 17445, 7924 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s64, 7925 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s64, 7926 GIM_Try, /*On fail goto*//*Label 598*/ 17324, // Rule ID 20369 // 7927 GIM_CheckFeatures, GIFBS_HasAVX512_NoVLX, 7928 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 7929 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID, 7930 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 7931 GIM_CheckOpcodeIsEither, /*MI*/1, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, 7932 GIM_CheckIsBuildVectorAllOnes, /*MI*/1, 7933 GIM_CheckIsSafeToFold, /*InsnID*/1, 7934 // (xor:{ *:[v4i64] } VR256X:{ *:[v4i64] }:$src, immAllOnesV:{ *:[v4i64] }) => (EXTRACT_SUBREG:{ *:[v4i64] } (VPTERNLOGQZrri:{ *:[v64i8] } (INSERT_SUBREG:{ *:[v8i64] } (IMPLICIT_DEF:{ *:[v8i64] }), VR256X:{ *:[v4i64] }:$src, sub_ymm:{ *:[i32] }), (INSERT_SUBREG:{ *:[v8i64] } (IMPLICIT_DEF:{ *:[v8i64] }), VR256X:{ *:[v4i64] }:$src, sub_ymm:{ *:[i32] }), (INSERT_SUBREG:{ *:[v8i64] } (IMPLICIT_DEF:{ *:[v8i64] }), VR256X:{ *:[v4i64] }:$src, sub_ymm:{ *:[i32] }), 15:{ *:[i8] }), sub_ymm:{ *:[i32] }) 7935 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v64s8, 7936 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s64, 7937 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v8s64, 7938 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v8s64, 7939 GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v8s64, 7940 GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v8s64, 7941 GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_v8s64, 7942 GIR_BuildMI, /*InsnID*/7, /*Opcode*/TargetOpcode::IMPLICIT_DEF, 7943 GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/RegState::Define, 7944 GIR_ConstrainSelectedInstOperands, /*InsnID*/7, 7945 GIR_BuildMI, /*InsnID*/6, /*Opcode*/TargetOpcode::INSERT_SUBREG, 7946 GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/RegState::Define, 7947 GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/6, /*TempRegFlags*/0, 7948 GIR_Copy, /*NewInsnID*/6, /*OldInsnID*/0, /*OpIdx*/1, // src 7949 GIR_AddImm, /*InsnID*/6, /*Imm*/10, 7950 GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, X86::VR512RegClassID, 7951 GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, X86::VR512RegClassID, 7952 GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/2, X86::VR256XRegClassID, 7953 GIR_BuildMI, /*InsnID*/5, /*Opcode*/TargetOpcode::IMPLICIT_DEF, 7954 GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/RegState::Define, 7955 GIR_ConstrainSelectedInstOperands, /*InsnID*/5, 7956 GIR_BuildMI, /*InsnID*/4, /*Opcode*/TargetOpcode::INSERT_SUBREG, 7957 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define, 7958 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/4, /*TempRegFlags*/0, 7959 GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/1, // src 7960 GIR_AddImm, /*InsnID*/4, /*Imm*/10, 7961 GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, X86::VR512RegClassID, 7962 GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/1, X86::VR512RegClassID, 7963 GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/2, X86::VR256XRegClassID, 7964 GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::IMPLICIT_DEF, 7965 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, 7966 GIR_ConstrainSelectedInstOperands, /*InsnID*/3, 7967 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::INSERT_SUBREG, 7968 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 7969 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/2, /*TempRegFlags*/0, 7970 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src 7971 GIR_AddImm, /*InsnID*/2, /*Imm*/10, 7972 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, X86::VR512RegClassID, 7973 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, X86::VR512RegClassID, 7974 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, X86::VR256XRegClassID, 7975 GIR_BuildMI, /*InsnID*/1, /*Opcode*/X86::VPTERNLOGQZrri, 7976 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 7977 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, 7978 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/3, /*TempRegFlags*/0, 7979 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/5, /*TempRegFlags*/0, 7980 GIR_AddImm, /*InsnID*/1, /*Imm*/15, 7981 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 7982 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 7983 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 7984 GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, X86::sub_ymm, 7985 GIR_EraseFromParent, /*InsnID*/0, 7986 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, X86::VR256XRegClassID, 7987 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, X86::VR512RegClassID, 7988 // GIR_Coverage, 20369, 7989 GIR_Done, 7990 // Label 598: @17324 7991 GIM_Try, /*On fail goto*//*Label 599*/ 17375, // Rule ID 20377 // 7992 GIM_CheckFeatures, GIFBS_HasVLX, 7993 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID, 7994 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID, 7995 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 7996 GIM_CheckOpcodeIsEither, /*MI*/1, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, 7997 GIM_CheckIsBuildVectorAllOnes, /*MI*/1, 7998 GIM_CheckIsSafeToFold, /*InsnID*/1, 7999 // (xor:{ *:[v4i64] } VR256X:{ *:[v4i64] }:$src, immAllOnesV:{ *:[v4i64] }) => (VPTERNLOGQZ256rri:{ *:[v4i64] } VR256X:{ *:[v4i64] }:$src, VR256X:{ *:[v4i64] }:$src, VR256X:{ *:[v4i64] }:$src, 15:{ *:[i8] }) 8000 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VPTERNLOGQZ256rri, 8001 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 8002 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 8003 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 8004 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 8005 GIR_AddImm, /*InsnID*/0, /*Imm*/15, 8006 GIR_EraseFromParent, /*InsnID*/0, 8007 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8008 // GIR_Coverage, 20377, 8009 GIR_Done, 8010 // Label 599: @17375 8011 GIM_Try, /*On fail goto*//*Label 600*/ 17398, // Rule ID 1858 // 8012 GIM_CheckFeatures, GIFBS_HasAVX2_NoVLX, 8013 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID, 8014 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256RegClassID, 8015 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256RegClassID, 8016 // (xor:{ *:[v4i64] } VR256:{ *:[v4i64] }:$src1, VR256:{ *:[v4i64] }:$src2) => (VPXORYrr:{ *:[v4i64] } VR256:{ *:[v4i64] }:$src1, VR256:{ *:[v4i64] }:$src2) 8017 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPXORYrr, 8018 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8019 // GIR_Coverage, 1858, 8020 GIR_Done, 8021 // Label 600: @17398 8022 GIM_Try, /*On fail goto*//*Label 601*/ 17421, // Rule ID 5442 // 8023 GIM_CheckFeatures, GIFBS_HasAVX512_HasVLX, 8024 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID, 8025 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID, 8026 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256XRegClassID, 8027 // (xor:{ *:[v4i64] } VR256X:{ *:[v4i64] }:$src1, VR256X:{ *:[v4i64] }:$src2) => (VPXORQZ256rr:{ *:[v4i64] } VR256X:{ *:[v4i64] }:$src1, VR256X:{ *:[v4i64] }:$src2) 8028 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPXORQZ256rr, 8029 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8030 // GIR_Coverage, 5442, 8031 GIR_Done, 8032 // Label 601: @17421 8033 GIM_Try, /*On fail goto*//*Label 602*/ 17444, // Rule ID 16572 // 8034 GIM_CheckFeatures, GIFBS_HasAVX1Only, 8035 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID, 8036 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256RegClassID, 8037 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256RegClassID, 8038 // (xor:{ *:[v4i64] } VR256:{ *:[v4i64] }:$src1, VR256:{ *:[v4i64] }:$src2) => (VXORPSYrr:{ *:[v4i64] } VR256:{ *:[v4i64] }:$src1, VR256:{ *:[v4i64] }:$src2) 8039 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VXORPSYrr, 8040 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8041 // GIR_Coverage, 16572, 8042 GIR_Done, 8043 // Label 602: @17444 8044 GIM_Reject, 8045 // Label 597: @17445 8046 GIM_Reject, 8047 // Label 517: @17446 8048 GIM_Try, /*On fail goto*//*Label 603*/ 18184, 8049 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s1, 8050 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s1, 8051 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VK8RegClassID, 8052 GIM_Try, /*On fail goto*//*Label 604*/ 17521, // Rule ID 21553 // 8053 GIM_CheckFeatures, GIFBS_HasDQI, 8054 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 8055 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, 8056 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s1, 8057 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s1, 8058 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::VK8RegClassID, 8059 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] 8060 GIM_CheckOpcodeIsEither, /*MI*/2, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, 8061 GIM_CheckIsBuildVectorAllOnes, /*MI*/2, 8062 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VK8RegClassID, 8063 GIM_CheckIsSafeToFold, /*InsnID*/1, 8064 GIM_CheckIsSafeToFold, /*InsnID*/2, 8065 // (xor:{ *:[v8i1] } (xor:{ *:[v8i1] } VK8:{ *:[v8i1] }:$src1, immAllOnesV:{ *:[v8i1] }), VK8:{ *:[v8i1] }:$src2) => (KXNORBrr:{ *:[v8i1] } VK8:{ *:[v8i1] }:$src1, VK8:{ *:[v8i1] }:$src2) 8066 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::KXNORBrr, 8067 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 8068 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1 8069 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src2 8070 GIR_EraseFromParent, /*InsnID*/0, 8071 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8072 // GIR_Coverage, 21553, 8073 GIR_Done, 8074 // Label 604: @17521 8075 GIM_Try, /*On fail goto*//*Label 605*/ 17632, // Rule ID 23236 // 8076 GIM_CheckFeatures, GIFBS_NoDQI, 8077 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 8078 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, 8079 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s1, 8080 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s1, 8081 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::VK8RegClassID, 8082 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] 8083 GIM_CheckOpcodeIsEither, /*MI*/2, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, 8084 GIM_CheckIsBuildVectorAllOnes, /*MI*/2, 8085 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VK8RegClassID, 8086 GIM_CheckIsSafeToFold, /*InsnID*/1, 8087 GIM_CheckIsSafeToFold, /*InsnID*/2, 8088 // (xor:{ *:[v8i1] } (xor:{ *:[v8i1] } VK8:{ *:[v8i1] }:$src1, immAllOnesV:{ *:[v8i1] }), VK8:{ *:[v8i1] }:$src2) => (COPY_TO_REGCLASS:{ *:[v8i1] } (KXNORWrr:{ *:[v16i1] } (COPY_TO_REGCLASS:{ *:[v16i1] } VK8:{ *:[v8i1] }:$src1, VK16:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v16i1] } VK8:{ *:[v8i1] }:$src2, VK16:{ *:[i32] })), VK8:{ *:[i32] }) 8089 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s1, 8090 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s1, 8091 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s1, 8092 GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::COPY, 8093 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, 8094 GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // src2 8095 GIR_ConstrainSelectedInstOperands, /*InsnID*/3, 8096 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY, 8097 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 8098 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, // src1 8099 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 8100 GIR_BuildMI, /*InsnID*/1, /*Opcode*/X86::KXNORWrr, 8101 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 8102 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, 8103 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/2, /*TempRegFlags*/0, 8104 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 8105 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 8106 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 8107 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 8108 GIR_EraseFromParent, /*InsnID*/0, 8109 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, X86::VK8RegClassID, 8110 // GIR_Coverage, 23236, 8111 GIR_Done, 8112 // Label 605: @17632 8113 GIM_Try, /*On fail goto*//*Label 606*/ 17693, // Rule ID 4062 // 8114 GIM_CheckFeatures, GIFBS_HasDQI, 8115 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 8116 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, 8117 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s1, 8118 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s1, 8119 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::VK8RegClassID, 8120 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/X86::VK8RegClassID, 8121 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] 8122 GIM_CheckOpcodeIsEither, /*MI*/2, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, 8123 GIM_CheckIsBuildVectorAllOnes, /*MI*/2, 8124 GIM_CheckIsSafeToFold, /*InsnID*/1, 8125 GIM_CheckIsSafeToFold, /*InsnID*/2, 8126 // (xor:{ *:[v8i1] } (xor:{ *:[v8i1] } VK8:{ *:[v8i1] }:$src1, VK8:{ *:[v8i1] }:$src2), immAllOnesV:{ *:[v8i1] }) => (KXNORBrr:{ *:[v8i1] } VK8:{ *:[v8i1] }:$src1, VK8:{ *:[v8i1] }:$src2) 8127 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::KXNORBrr, 8128 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 8129 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1 8130 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src2 8131 GIR_EraseFromParent, /*InsnID*/0, 8132 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8133 // GIR_Coverage, 4062, 8134 GIR_Done, 8135 // Label 606: @17693 8136 GIM_Try, /*On fail goto*//*Label 607*/ 17804, // Rule ID 17934 // 8137 GIM_CheckFeatures, GIFBS_NoDQI, 8138 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 8139 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, 8140 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s1, 8141 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s1, 8142 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::VK8RegClassID, 8143 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/X86::VK8RegClassID, 8144 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] 8145 GIM_CheckOpcodeIsEither, /*MI*/2, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, 8146 GIM_CheckIsBuildVectorAllOnes, /*MI*/2, 8147 GIM_CheckIsSafeToFold, /*InsnID*/1, 8148 GIM_CheckIsSafeToFold, /*InsnID*/2, 8149 // (xor:{ *:[v8i1] } (xor:{ *:[v8i1] } VK8:{ *:[v8i1] }:$src1, VK8:{ *:[v8i1] }:$src2), immAllOnesV:{ *:[v8i1] }) => (COPY_TO_REGCLASS:{ *:[v8i1] } (KXNORWrr:{ *:[v16i1] } (COPY_TO_REGCLASS:{ *:[v16i1] } VK8:{ *:[v8i1] }:$src1, VK16:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v16i1] } VK8:{ *:[v8i1] }:$src2, VK16:{ *:[i32] })), VK8:{ *:[i32] }) 8150 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s1, 8151 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s1, 8152 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s1, 8153 GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::COPY, 8154 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, 8155 GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/1, /*OpIdx*/2, // src2 8156 GIR_ConstrainSelectedInstOperands, /*InsnID*/3, 8157 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY, 8158 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 8159 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, // src1 8160 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 8161 GIR_BuildMI, /*InsnID*/1, /*Opcode*/X86::KXNORWrr, 8162 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 8163 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, 8164 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/2, /*TempRegFlags*/0, 8165 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 8166 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 8167 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 8168 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 8169 GIR_EraseFromParent, /*InsnID*/0, 8170 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, X86::VK8RegClassID, 8171 // GIR_Coverage, 17934, 8172 GIR_Done, 8173 // Label 607: @17804 8174 GIM_Try, /*On fail goto*//*Label 608*/ 17865, // Rule ID 21554 // 8175 GIM_CheckFeatures, GIFBS_HasDQI, 8176 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VK8RegClassID, 8177 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 8178 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, 8179 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s1, 8180 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s1, 8181 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::VK8RegClassID, 8182 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] 8183 GIM_CheckOpcodeIsEither, /*MI*/2, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, 8184 GIM_CheckIsBuildVectorAllOnes, /*MI*/2, 8185 GIM_CheckIsSafeToFold, /*InsnID*/1, 8186 GIM_CheckIsSafeToFold, /*InsnID*/2, 8187 // (xor:{ *:[v8i1] } VK8:{ *:[v8i1] }:$src2, (xor:{ *:[v8i1] } VK8:{ *:[v8i1] }:$src1, immAllOnesV:{ *:[v8i1] })) => (KXNORBrr:{ *:[v8i1] } VK8:{ *:[v8i1] }:$src1, VK8:{ *:[v8i1] }:$src2) 8188 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::KXNORBrr, 8189 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 8190 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1 8191 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src2 8192 GIR_EraseFromParent, /*InsnID*/0, 8193 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8194 // GIR_Coverage, 21554, 8195 GIR_Done, 8196 // Label 608: @17865 8197 GIM_Try, /*On fail goto*//*Label 609*/ 17976, // Rule ID 23237 // 8198 GIM_CheckFeatures, GIFBS_NoDQI, 8199 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VK8RegClassID, 8200 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 8201 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, 8202 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s1, 8203 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s1, 8204 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::VK8RegClassID, 8205 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] 8206 GIM_CheckOpcodeIsEither, /*MI*/2, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, 8207 GIM_CheckIsBuildVectorAllOnes, /*MI*/2, 8208 GIM_CheckIsSafeToFold, /*InsnID*/1, 8209 GIM_CheckIsSafeToFold, /*InsnID*/2, 8210 // (xor:{ *:[v8i1] } VK8:{ *:[v8i1] }:$src2, (xor:{ *:[v8i1] } VK8:{ *:[v8i1] }:$src1, immAllOnesV:{ *:[v8i1] })) => (COPY_TO_REGCLASS:{ *:[v8i1] } (KXNORWrr:{ *:[v16i1] } (COPY_TO_REGCLASS:{ *:[v16i1] } VK8:{ *:[v8i1] }:$src1, VK16:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v16i1] } VK8:{ *:[v8i1] }:$src2, VK16:{ *:[i32] })), VK8:{ *:[i32] }) 8211 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s1, 8212 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s1, 8213 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s1, 8214 GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::COPY, 8215 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, 8216 GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // src2 8217 GIR_ConstrainSelectedInstOperands, /*InsnID*/3, 8218 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY, 8219 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 8220 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, // src1 8221 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 8222 GIR_BuildMI, /*InsnID*/1, /*Opcode*/X86::KXNORWrr, 8223 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 8224 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, 8225 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/2, /*TempRegFlags*/0, 8226 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 8227 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 8228 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 8229 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 8230 GIR_EraseFromParent, /*InsnID*/0, 8231 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, X86::VK8RegClassID, 8232 // GIR_Coverage, 23237, 8233 GIR_Done, 8234 // Label 609: @17976 8235 GIM_Try, /*On fail goto*//*Label 610*/ 18012, // Rule ID 4050 // 8236 GIM_CheckFeatures, GIFBS_HasDQI, 8237 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VK8RegClassID, 8238 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 8239 GIM_CheckOpcodeIsEither, /*MI*/1, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, 8240 GIM_CheckIsBuildVectorAllOnes, /*MI*/1, 8241 GIM_CheckIsSafeToFold, /*InsnID*/1, 8242 // (xor:{ *:[v8i1] } VK8:{ *:[v8i1] }:$src, immAllOnesV:{ *:[v8i1] }) => (KNOTBrr:{ *:[v8i1] } VK8:{ *:[v8i1] }:$src) 8243 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::KNOTBrr, 8244 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 8245 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 8246 GIR_EraseFromParent, /*InsnID*/0, 8247 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8248 // GIR_Coverage, 4050, 8249 GIR_Done, 8250 // Label 610: @18012 8251 GIM_Try, /*On fail goto*//*Label 611*/ 18082, // Rule ID 17918 // 8252 GIM_CheckFeatures, GIFBS_HasAVX512_NoDQI, 8253 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VK8RegClassID, 8254 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 8255 GIM_CheckOpcodeIsEither, /*MI*/1, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, 8256 GIM_CheckIsBuildVectorAllOnes, /*MI*/1, 8257 GIM_CheckIsSafeToFold, /*InsnID*/1, 8258 // (xor:{ *:[v8i1] } VK8:{ *:[v8i1] }:$src, immAllOnesV:{ *:[v8i1] }) => (COPY_TO_REGCLASS:{ *:[v8i1] } (KNOTWrr:{ *:[v16i1] } (COPY_TO_REGCLASS:{ *:[v16i1] } VK8:{ *:[v8i1] }:$src, VK16:{ *:[i32] })), VK8:{ *:[i32] }) 8259 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s1, 8260 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s1, 8261 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY, 8262 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 8263 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src 8264 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 8265 GIR_BuildMI, /*InsnID*/1, /*Opcode*/X86::KNOTWrr, 8266 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 8267 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, 8268 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 8269 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 8270 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 8271 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 8272 GIR_EraseFromParent, /*InsnID*/0, 8273 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, X86::VK8RegClassID, 8274 // GIR_Coverage, 17918, 8275 GIR_Done, 8276 // Label 611: @18082 8277 GIM_Try, /*On fail goto*//*Label 612*/ 18101, // Rule ID 4066 // 8278 GIM_CheckFeatures, GIFBS_HasDQI, 8279 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VK8RegClassID, 8280 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VK8RegClassID, 8281 // (xor:{ *:[v8i1] } VK8:{ *:[v8i1] }:$src1, VK8:{ *:[v8i1] }:$src2) => (KXORBrr:{ *:[v8i1] } VK8:{ *:[v8i1] }:$src1, VK8:{ *:[v8i1] }:$src2) 8282 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::KXORBrr, 8283 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8284 // GIR_Coverage, 4066, 8285 GIR_Done, 8286 // Label 612: @18101 8287 GIM_Try, /*On fail goto*//*Label 613*/ 18183, // Rule ID 17938 // 8288 GIM_CheckFeatures, GIFBS_NoDQI, 8289 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VK8RegClassID, 8290 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VK8RegClassID, 8291 // (xor:{ *:[v8i1] } VK8:{ *:[v8i1] }:$src1, VK8:{ *:[v8i1] }:$src2) => (COPY_TO_REGCLASS:{ *:[v8i1] } (KXORWrr:{ *:[v16i1] } (COPY_TO_REGCLASS:{ *:[v16i1] } VK8:{ *:[v8i1] }:$src1, VK16:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v16i1] } VK8:{ *:[v8i1] }:$src2, VK16:{ *:[i32] })), VK8:{ *:[i32] }) 8292 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s1, 8293 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s1, 8294 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s1, 8295 GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::COPY, 8296 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, 8297 GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // src2 8298 GIR_ConstrainSelectedInstOperands, /*InsnID*/3, 8299 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY, 8300 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 8301 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src1 8302 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 8303 GIR_BuildMI, /*InsnID*/1, /*Opcode*/X86::KXORWrr, 8304 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 8305 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, 8306 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/2, /*TempRegFlags*/0, 8307 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 8308 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 8309 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 8310 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 8311 GIR_EraseFromParent, /*InsnID*/0, 8312 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, X86::VK8RegClassID, 8313 // GIR_Coverage, 17938, 8314 GIR_Done, 8315 // Label 613: @18183 8316 GIM_Reject, 8317 // Label 603: @18184 8318 GIM_Reject, 8319 // Label 518: @18185 8320 GIM_Try, /*On fail goto*//*Label 614*/ 18525, 8321 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, 8322 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 8323 GIM_Try, /*On fail goto*//*Label 615*/ 18404, // Rule ID 20363 // 8324 GIM_CheckFeatures, GIFBS_HasAVX512_NoVLX, 8325 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 8326 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID, 8327 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 8328 GIM_CheckOpcodeIsEither, /*MI*/1, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, 8329 GIM_CheckIsBuildVectorAllOnes, /*MI*/1, 8330 GIM_CheckIsSafeToFold, /*InsnID*/1, 8331 // (xor:{ *:[v8i16] } VR128X:{ *:[v8i16] }:$src, immAllOnesV:{ *:[v8i16] }) => (EXTRACT_SUBREG:{ *:[v8i16] } (VPTERNLOGQZrri:{ *:[v64i8] } (INSERT_SUBREG:{ *:[v8i64] } (IMPLICIT_DEF:{ *:[v8i64] }), VR128X:{ *:[v8i16] }:$src, sub_xmm:{ *:[i32] }), (INSERT_SUBREG:{ *:[v8i64] } (IMPLICIT_DEF:{ *:[v8i64] }), VR128X:{ *:[v8i16] }:$src, sub_xmm:{ *:[i32] }), (INSERT_SUBREG:{ *:[v8i64] } (IMPLICIT_DEF:{ *:[v8i64] }), VR128X:{ *:[v8i16] }:$src, sub_xmm:{ *:[i32] }), 15:{ *:[i8] }), sub_xmm:{ *:[i32] }) 8332 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v64s8, 8333 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s64, 8334 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v8s64, 8335 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v8s64, 8336 GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v8s64, 8337 GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v8s64, 8338 GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_v8s64, 8339 GIR_BuildMI, /*InsnID*/7, /*Opcode*/TargetOpcode::IMPLICIT_DEF, 8340 GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/RegState::Define, 8341 GIR_ConstrainSelectedInstOperands, /*InsnID*/7, 8342 GIR_BuildMI, /*InsnID*/6, /*Opcode*/TargetOpcode::INSERT_SUBREG, 8343 GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/RegState::Define, 8344 GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/6, /*TempRegFlags*/0, 8345 GIR_Copy, /*NewInsnID*/6, /*OldInsnID*/0, /*OpIdx*/1, // src 8346 GIR_AddImm, /*InsnID*/6, /*Imm*/9, 8347 GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, X86::VR512RegClassID, 8348 GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, X86::VR512RegClassID, 8349 GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/2, X86::VR128XRegClassID, 8350 GIR_BuildMI, /*InsnID*/5, /*Opcode*/TargetOpcode::IMPLICIT_DEF, 8351 GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/RegState::Define, 8352 GIR_ConstrainSelectedInstOperands, /*InsnID*/5, 8353 GIR_BuildMI, /*InsnID*/4, /*Opcode*/TargetOpcode::INSERT_SUBREG, 8354 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define, 8355 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/4, /*TempRegFlags*/0, 8356 GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/1, // src 8357 GIR_AddImm, /*InsnID*/4, /*Imm*/9, 8358 GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, X86::VR512RegClassID, 8359 GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/1, X86::VR512RegClassID, 8360 GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/2, X86::VR128XRegClassID, 8361 GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::IMPLICIT_DEF, 8362 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, 8363 GIR_ConstrainSelectedInstOperands, /*InsnID*/3, 8364 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::INSERT_SUBREG, 8365 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 8366 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/2, /*TempRegFlags*/0, 8367 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src 8368 GIR_AddImm, /*InsnID*/2, /*Imm*/9, 8369 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, X86::VR512RegClassID, 8370 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, X86::VR512RegClassID, 8371 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, X86::VR128XRegClassID, 8372 GIR_BuildMI, /*InsnID*/1, /*Opcode*/X86::VPTERNLOGQZrri, 8373 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 8374 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, 8375 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/3, /*TempRegFlags*/0, 8376 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/5, /*TempRegFlags*/0, 8377 GIR_AddImm, /*InsnID*/1, /*Imm*/15, 8378 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 8379 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 8380 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 8381 GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, X86::sub_xmm, 8382 GIR_EraseFromParent, /*InsnID*/0, 8383 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, X86::FR16XRegClassID, 8384 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, X86::VR512RegClassID, 8385 // GIR_Coverage, 20363, 8386 GIR_Done, 8387 // Label 615: @18404 8388 GIM_Try, /*On fail goto*//*Label 616*/ 18455, // Rule ID 20371 // 8389 GIM_CheckFeatures, GIFBS_HasVLX, 8390 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID, 8391 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID, 8392 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 8393 GIM_CheckOpcodeIsEither, /*MI*/1, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, 8394 GIM_CheckIsBuildVectorAllOnes, /*MI*/1, 8395 GIM_CheckIsSafeToFold, /*InsnID*/1, 8396 // (xor:{ *:[v8i16] } VR128X:{ *:[v8i16] }:$src, immAllOnesV:{ *:[v8i16] }) => (VPTERNLOGQZ128rri:{ *:[v8i16] } VR128X:{ *:[v8i16] }:$src, VR128X:{ *:[v8i16] }:$src, VR128X:{ *:[v8i16] }:$src, 15:{ *:[i8] }) 8397 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VPTERNLOGQZ128rri, 8398 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 8399 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 8400 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 8401 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 8402 GIR_AddImm, /*InsnID*/0, /*Imm*/15, 8403 GIR_EraseFromParent, /*InsnID*/0, 8404 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8405 // GIR_Coverage, 20371, 8406 GIR_Done, 8407 // Label 616: @18455 8408 GIM_Try, /*On fail goto*//*Label 617*/ 18478, // Rule ID 16600 // 8409 GIM_CheckFeatures, GIFBS_HasAVX_NoVLX, 8410 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 8411 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 8412 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 8413 // (xor:{ *:[v8i16] } VR128:{ *:[v8i16] }:$src1, VR128:{ *:[v8i16] }:$src2) => (VPXORrr:{ *:[v8i16] } VR128:{ *:[v8i16] }:$src1, VR128:{ *:[v8i16] }:$src2) 8414 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPXORrr, 8415 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8416 // GIR_Coverage, 16600, 8417 GIR_Done, 8418 // Label 617: @18478 8419 GIM_Try, /*On fail goto*//*Label 618*/ 18501, // Rule ID 16624 // 8420 GIM_CheckFeatures, GIFBS_UseSSE2, 8421 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 8422 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 8423 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 8424 // (xor:{ *:[v8i16] } VR128:{ *:[v8i16] }:$src1, VR128:{ *:[v8i16] }:$src2) => (PXORrr:{ *:[v8i16] } VR128:{ *:[v8i16] }:$src1, VR128:{ *:[v8i16] }:$src2) 8425 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::PXORrr, 8426 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8427 // GIR_Coverage, 16624, 8428 GIR_Done, 8429 // Label 618: @18501 8430 GIM_Try, /*On fail goto*//*Label 619*/ 18524, // Rule ID 18506 // 8431 GIM_CheckFeatures, GIFBS_HasVLX, 8432 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID, 8433 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID, 8434 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128XRegClassID, 8435 // (xor:{ *:[v8i16] } VR128X:{ *:[v8i16] }:$src1, VR128X:{ *:[v8i16] }:$src2) => (VPXORQZ128rr:{ *:[v8i16] } VR128X:{ *:[v8i16] }:$src1, VR128X:{ *:[v8i16] }:$src2) 8436 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPXORQZ128rr, 8437 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8438 // GIR_Coverage, 18506, 8439 GIR_Done, 8440 // Label 619: @18524 8441 GIM_Reject, 8442 // Label 614: @18525 8443 GIM_Reject, 8444 // Label 519: @18526 8445 GIM_Try, /*On fail goto*//*Label 620*/ 18866, 8446 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s32, 8447 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s32, 8448 GIM_Try, /*On fail goto*//*Label 621*/ 18745, // Rule ID 20368 // 8449 GIM_CheckFeatures, GIFBS_HasAVX512_NoVLX, 8450 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 8451 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID, 8452 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 8453 GIM_CheckOpcodeIsEither, /*MI*/1, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, 8454 GIM_CheckIsBuildVectorAllOnes, /*MI*/1, 8455 GIM_CheckIsSafeToFold, /*InsnID*/1, 8456 // (xor:{ *:[v8i32] } VR256X:{ *:[v8i32] }:$src, immAllOnesV:{ *:[v8i32] }) => (EXTRACT_SUBREG:{ *:[v8i32] } (VPTERNLOGQZrri:{ *:[v64i8] } (INSERT_SUBREG:{ *:[v8i64] } (IMPLICIT_DEF:{ *:[v8i64] }), VR256X:{ *:[v8i32] }:$src, sub_ymm:{ *:[i32] }), (INSERT_SUBREG:{ *:[v8i64] } (IMPLICIT_DEF:{ *:[v8i64] }), VR256X:{ *:[v8i32] }:$src, sub_ymm:{ *:[i32] }), (INSERT_SUBREG:{ *:[v8i64] } (IMPLICIT_DEF:{ *:[v8i64] }), VR256X:{ *:[v8i32] }:$src, sub_ymm:{ *:[i32] }), 15:{ *:[i8] }), sub_ymm:{ *:[i32] }) 8457 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v64s8, 8458 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s64, 8459 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v8s64, 8460 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v8s64, 8461 GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v8s64, 8462 GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v8s64, 8463 GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_v8s64, 8464 GIR_BuildMI, /*InsnID*/7, /*Opcode*/TargetOpcode::IMPLICIT_DEF, 8465 GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/RegState::Define, 8466 GIR_ConstrainSelectedInstOperands, /*InsnID*/7, 8467 GIR_BuildMI, /*InsnID*/6, /*Opcode*/TargetOpcode::INSERT_SUBREG, 8468 GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/RegState::Define, 8469 GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/6, /*TempRegFlags*/0, 8470 GIR_Copy, /*NewInsnID*/6, /*OldInsnID*/0, /*OpIdx*/1, // src 8471 GIR_AddImm, /*InsnID*/6, /*Imm*/10, 8472 GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, X86::VR512RegClassID, 8473 GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, X86::VR512RegClassID, 8474 GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/2, X86::VR256XRegClassID, 8475 GIR_BuildMI, /*InsnID*/5, /*Opcode*/TargetOpcode::IMPLICIT_DEF, 8476 GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/RegState::Define, 8477 GIR_ConstrainSelectedInstOperands, /*InsnID*/5, 8478 GIR_BuildMI, /*InsnID*/4, /*Opcode*/TargetOpcode::INSERT_SUBREG, 8479 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define, 8480 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/4, /*TempRegFlags*/0, 8481 GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/1, // src 8482 GIR_AddImm, /*InsnID*/4, /*Imm*/10, 8483 GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, X86::VR512RegClassID, 8484 GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/1, X86::VR512RegClassID, 8485 GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/2, X86::VR256XRegClassID, 8486 GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::IMPLICIT_DEF, 8487 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, 8488 GIR_ConstrainSelectedInstOperands, /*InsnID*/3, 8489 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::INSERT_SUBREG, 8490 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 8491 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/2, /*TempRegFlags*/0, 8492 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src 8493 GIR_AddImm, /*InsnID*/2, /*Imm*/10, 8494 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, X86::VR512RegClassID, 8495 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, X86::VR512RegClassID, 8496 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, X86::VR256XRegClassID, 8497 GIR_BuildMI, /*InsnID*/1, /*Opcode*/X86::VPTERNLOGQZrri, 8498 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 8499 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, 8500 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/3, /*TempRegFlags*/0, 8501 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/5, /*TempRegFlags*/0, 8502 GIR_AddImm, /*InsnID*/1, /*Imm*/15, 8503 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 8504 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 8505 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 8506 GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, X86::sub_ymm, 8507 GIR_EraseFromParent, /*InsnID*/0, 8508 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, X86::VR256XRegClassID, 8509 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, X86::VR512RegClassID, 8510 // GIR_Coverage, 20368, 8511 GIR_Done, 8512 // Label 621: @18745 8513 GIM_Try, /*On fail goto*//*Label 622*/ 18796, // Rule ID 20376 // 8514 GIM_CheckFeatures, GIFBS_HasVLX, 8515 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID, 8516 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID, 8517 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 8518 GIM_CheckOpcodeIsEither, /*MI*/1, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, 8519 GIM_CheckIsBuildVectorAllOnes, /*MI*/1, 8520 GIM_CheckIsSafeToFold, /*InsnID*/1, 8521 // (xor:{ *:[v8i32] } VR256X:{ *:[v8i32] }:$src, immAllOnesV:{ *:[v8i32] }) => (VPTERNLOGQZ256rri:{ *:[v8i32] } VR256X:{ *:[v8i32] }:$src, VR256X:{ *:[v8i32] }:$src, VR256X:{ *:[v8i32] }:$src, 15:{ *:[i8] }) 8522 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VPTERNLOGQZ256rri, 8523 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 8524 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 8525 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 8526 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 8527 GIR_AddImm, /*InsnID*/0, /*Imm*/15, 8528 GIR_EraseFromParent, /*InsnID*/0, 8529 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8530 // GIR_Coverage, 20376, 8531 GIR_Done, 8532 // Label 622: @18796 8533 GIM_Try, /*On fail goto*//*Label 623*/ 18819, // Rule ID 5469 // 8534 GIM_CheckFeatures, GIFBS_HasAVX512_HasVLX, 8535 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID, 8536 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID, 8537 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256XRegClassID, 8538 // (xor:{ *:[v8i32] } VR256X:{ *:[v8i32] }:$src1, VR256X:{ *:[v8i32] }:$src2) => (VPXORDZ256rr:{ *:[v8i32] } VR256X:{ *:[v8i32] }:$src1, VR256X:{ *:[v8i32] }:$src2) 8539 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPXORDZ256rr, 8540 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8541 // GIR_Coverage, 5469, 8542 GIR_Done, 8543 // Label 623: @18819 8544 GIM_Try, /*On fail goto*//*Label 624*/ 18842, // Rule ID 16545 // 8545 GIM_CheckFeatures, GIFBS_HasAVX2_NoVLX, 8546 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID, 8547 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256RegClassID, 8548 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256RegClassID, 8549 // (xor:{ *:[v8i32] } VR256:{ *:[v8i32] }:$src1, VR256:{ *:[v8i32] }:$src2) => (VPXORYrr:{ *:[v8i32] } VR256:{ *:[v8i32] }:$src1, VR256:{ *:[v8i32] }:$src2) 8550 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPXORYrr, 8551 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8552 // GIR_Coverage, 16545, 8553 GIR_Done, 8554 // Label 624: @18842 8555 GIM_Try, /*On fail goto*//*Label 625*/ 18865, // Rule ID 16571 // 8556 GIM_CheckFeatures, GIFBS_HasAVX1Only, 8557 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID, 8558 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256RegClassID, 8559 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256RegClassID, 8560 // (xor:{ *:[v8i32] } VR256:{ *:[v8i32] }:$src1, VR256:{ *:[v8i32] }:$src2) => (VXORPSYrr:{ *:[v8i32] } VR256:{ *:[v8i32] }:$src1, VR256:{ *:[v8i32] }:$src2) 8561 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VXORPSYrr, 8562 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8563 // GIR_Coverage, 16571, 8564 GIR_Done, 8565 // Label 625: @18865 8566 GIM_Reject, 8567 // Label 620: @18866 8568 GIM_Reject, 8569 // Label 520: @18867 8570 GIM_Try, /*On fail goto*//*Label 626*/ 18944, 8571 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s64, 8572 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s64, 8573 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 8574 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR512RegClassID, 8575 GIM_Try, /*On fail goto*//*Label 627*/ 18928, // Rule ID 20361 // 8576 GIM_CheckFeatures, GIFBS_HasAVX512, 8577 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 8578 GIM_CheckOpcodeIsEither, /*MI*/1, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, 8579 GIM_CheckIsBuildVectorAllOnes, /*MI*/1, 8580 GIM_CheckIsSafeToFold, /*InsnID*/1, 8581 // (xor:{ *:[v8i64] } VR512:{ *:[v8i64] }:$src, immAllOnesV:{ *:[v8i64] }) => (VPTERNLOGQZrri:{ *:[v8i64] } VR512:{ *:[v8i64] }:$src, VR512:{ *:[v8i64] }:$src, VR512:{ *:[v8i64] }:$src, 15:{ *:[i8] }) 8582 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VPTERNLOGQZrri, 8583 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 8584 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 8585 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 8586 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 8587 GIR_AddImm, /*InsnID*/0, /*Imm*/15, 8588 GIR_EraseFromParent, /*InsnID*/0, 8589 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8590 // GIR_Coverage, 20361, 8591 GIR_Done, 8592 // Label 627: @18928 8593 GIM_Try, /*On fail goto*//*Label 628*/ 18943, // Rule ID 5433 // 8594 GIM_CheckFeatures, GIFBS_HasAVX512, 8595 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR512RegClassID, 8596 // (xor:{ *:[v8i64] } VR512:{ *:[v8i64] }:$src1, VR512:{ *:[v8i64] }:$src2) => (VPXORQZrr:{ *:[v8i64] } VR512:{ *:[v8i64] }:$src1, VR512:{ *:[v8i64] }:$src2) 8597 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPXORQZrr, 8598 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8599 // GIR_Coverage, 5433, 8600 GIR_Done, 8601 // Label 628: @18943 8602 GIM_Reject, 8603 // Label 626: @18944 8604 GIM_Reject, 8605 // Label 521: @18945 8606 GIM_Try, /*On fail goto*//*Label 629*/ 19198, 8607 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s1, 8608 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s1, 8609 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VK16RegClassID, 8610 GIM_Try, /*On fail goto*//*Label 630*/ 19020, // Rule ID 21555 // 8611 GIM_CheckFeatures, GIFBS_HasAVX512, 8612 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 8613 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, 8614 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s1, 8615 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s1, 8616 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::VK16RegClassID, 8617 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] 8618 GIM_CheckOpcodeIsEither, /*MI*/2, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, 8619 GIM_CheckIsBuildVectorAllOnes, /*MI*/2, 8620 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VK16RegClassID, 8621 GIM_CheckIsSafeToFold, /*InsnID*/1, 8622 GIM_CheckIsSafeToFold, /*InsnID*/2, 8623 // (xor:{ *:[v16i1] } (xor:{ *:[v16i1] } VK16:{ *:[v16i1] }:$src1, immAllOnesV:{ *:[v16i1] }), VK16:{ *:[v16i1] }:$src2) => (KXNORWrr:{ *:[v16i1] } VK16:{ *:[v16i1] }:$src1, VK16:{ *:[v16i1] }:$src2) 8624 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::KXNORWrr, 8625 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 8626 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1 8627 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src2 8628 GIR_EraseFromParent, /*InsnID*/0, 8629 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8630 // GIR_Coverage, 21555, 8631 GIR_Done, 8632 // Label 630: @19020 8633 GIM_Try, /*On fail goto*//*Label 631*/ 19081, // Rule ID 4063 // 8634 GIM_CheckFeatures, GIFBS_HasAVX512, 8635 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 8636 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, 8637 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s1, 8638 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s1, 8639 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::VK16RegClassID, 8640 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/X86::VK16RegClassID, 8641 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] 8642 GIM_CheckOpcodeIsEither, /*MI*/2, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, 8643 GIM_CheckIsBuildVectorAllOnes, /*MI*/2, 8644 GIM_CheckIsSafeToFold, /*InsnID*/1, 8645 GIM_CheckIsSafeToFold, /*InsnID*/2, 8646 // (xor:{ *:[v16i1] } (xor:{ *:[v16i1] } VK16:{ *:[v16i1] }:$src1, VK16:{ *:[v16i1] }:$src2), immAllOnesV:{ *:[v16i1] }) => (KXNORWrr:{ *:[v16i1] } VK16:{ *:[v16i1] }:$src1, VK16:{ *:[v16i1] }:$src2) 8647 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::KXNORWrr, 8648 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 8649 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1 8650 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src2 8651 GIR_EraseFromParent, /*InsnID*/0, 8652 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8653 // GIR_Coverage, 4063, 8654 GIR_Done, 8655 // Label 631: @19081 8656 GIM_Try, /*On fail goto*//*Label 632*/ 19142, // Rule ID 21556 // 8657 GIM_CheckFeatures, GIFBS_HasAVX512, 8658 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VK16RegClassID, 8659 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 8660 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, 8661 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s1, 8662 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s1, 8663 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::VK16RegClassID, 8664 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] 8665 GIM_CheckOpcodeIsEither, /*MI*/2, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, 8666 GIM_CheckIsBuildVectorAllOnes, /*MI*/2, 8667 GIM_CheckIsSafeToFold, /*InsnID*/1, 8668 GIM_CheckIsSafeToFold, /*InsnID*/2, 8669 // (xor:{ *:[v16i1] } VK16:{ *:[v16i1] }:$src2, (xor:{ *:[v16i1] } VK16:{ *:[v16i1] }:$src1, immAllOnesV:{ *:[v16i1] })) => (KXNORWrr:{ *:[v16i1] } VK16:{ *:[v16i1] }:$src1, VK16:{ *:[v16i1] }:$src2) 8670 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::KXNORWrr, 8671 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 8672 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1 8673 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src2 8674 GIR_EraseFromParent, /*InsnID*/0, 8675 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8676 // GIR_Coverage, 21556, 8677 GIR_Done, 8678 // Label 632: @19142 8679 GIM_Try, /*On fail goto*//*Label 633*/ 19178, // Rule ID 4051 // 8680 GIM_CheckFeatures, GIFBS_HasAVX512, 8681 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VK16RegClassID, 8682 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 8683 GIM_CheckOpcodeIsEither, /*MI*/1, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, 8684 GIM_CheckIsBuildVectorAllOnes, /*MI*/1, 8685 GIM_CheckIsSafeToFold, /*InsnID*/1, 8686 // (xor:{ *:[v16i1] } VK16:{ *:[v16i1] }:$src, immAllOnesV:{ *:[v16i1] }) => (KNOTWrr:{ *:[v16i1] } VK16:{ *:[v16i1] }:$src) 8687 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::KNOTWrr, 8688 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 8689 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 8690 GIR_EraseFromParent, /*InsnID*/0, 8691 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8692 // GIR_Coverage, 4051, 8693 GIR_Done, 8694 // Label 633: @19178 8695 GIM_Try, /*On fail goto*//*Label 634*/ 19197, // Rule ID 4067 // 8696 GIM_CheckFeatures, GIFBS_HasAVX512, 8697 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VK16RegClassID, 8698 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VK16RegClassID, 8699 // (xor:{ *:[v16i1] } VK16:{ *:[v16i1] }:$src1, VK16:{ *:[v16i1] }:$src2) => (KXORWrr:{ *:[v16i1] } VK16:{ *:[v16i1] }:$src1, VK16:{ *:[v16i1] }:$src2) 8700 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::KXORWrr, 8701 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8702 // GIR_Coverage, 4067, 8703 GIR_Done, 8704 // Label 634: @19197 8705 GIM_Reject, 8706 // Label 629: @19198 8707 GIM_Reject, 8708 // Label 522: @19199 8709 GIM_Try, /*On fail goto*//*Label 635*/ 19539, 8710 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, 8711 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, 8712 GIM_Try, /*On fail goto*//*Label 636*/ 19418, // Rule ID 20362 // 8713 GIM_CheckFeatures, GIFBS_HasAVX512_NoVLX, 8714 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 8715 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID, 8716 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 8717 GIM_CheckOpcodeIsEither, /*MI*/1, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, 8718 GIM_CheckIsBuildVectorAllOnes, /*MI*/1, 8719 GIM_CheckIsSafeToFold, /*InsnID*/1, 8720 // (xor:{ *:[v16i8] } VR128X:{ *:[v16i8] }:$src, immAllOnesV:{ *:[v16i8] }) => (EXTRACT_SUBREG:{ *:[v16i8] } (VPTERNLOGQZrri:{ *:[v64i8] } (INSERT_SUBREG:{ *:[v8i64] } (IMPLICIT_DEF:{ *:[v8i64] }), VR128X:{ *:[v16i8] }:$src, sub_xmm:{ *:[i32] }), (INSERT_SUBREG:{ *:[v8i64] } (IMPLICIT_DEF:{ *:[v8i64] }), VR128X:{ *:[v16i8] }:$src, sub_xmm:{ *:[i32] }), (INSERT_SUBREG:{ *:[v8i64] } (IMPLICIT_DEF:{ *:[v8i64] }), VR128X:{ *:[v16i8] }:$src, sub_xmm:{ *:[i32] }), 15:{ *:[i8] }), sub_xmm:{ *:[i32] }) 8721 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v64s8, 8722 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s64, 8723 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v8s64, 8724 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v8s64, 8725 GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v8s64, 8726 GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v8s64, 8727 GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_v8s64, 8728 GIR_BuildMI, /*InsnID*/7, /*Opcode*/TargetOpcode::IMPLICIT_DEF, 8729 GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/RegState::Define, 8730 GIR_ConstrainSelectedInstOperands, /*InsnID*/7, 8731 GIR_BuildMI, /*InsnID*/6, /*Opcode*/TargetOpcode::INSERT_SUBREG, 8732 GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/RegState::Define, 8733 GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/6, /*TempRegFlags*/0, 8734 GIR_Copy, /*NewInsnID*/6, /*OldInsnID*/0, /*OpIdx*/1, // src 8735 GIR_AddImm, /*InsnID*/6, /*Imm*/9, 8736 GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, X86::VR512RegClassID, 8737 GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, X86::VR512RegClassID, 8738 GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/2, X86::VR128XRegClassID, 8739 GIR_BuildMI, /*InsnID*/5, /*Opcode*/TargetOpcode::IMPLICIT_DEF, 8740 GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/RegState::Define, 8741 GIR_ConstrainSelectedInstOperands, /*InsnID*/5, 8742 GIR_BuildMI, /*InsnID*/4, /*Opcode*/TargetOpcode::INSERT_SUBREG, 8743 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define, 8744 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/4, /*TempRegFlags*/0, 8745 GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/1, // src 8746 GIR_AddImm, /*InsnID*/4, /*Imm*/9, 8747 GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, X86::VR512RegClassID, 8748 GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/1, X86::VR512RegClassID, 8749 GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/2, X86::VR128XRegClassID, 8750 GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::IMPLICIT_DEF, 8751 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, 8752 GIR_ConstrainSelectedInstOperands, /*InsnID*/3, 8753 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::INSERT_SUBREG, 8754 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 8755 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/2, /*TempRegFlags*/0, 8756 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src 8757 GIR_AddImm, /*InsnID*/2, /*Imm*/9, 8758 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, X86::VR512RegClassID, 8759 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, X86::VR512RegClassID, 8760 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, X86::VR128XRegClassID, 8761 GIR_BuildMI, /*InsnID*/1, /*Opcode*/X86::VPTERNLOGQZrri, 8762 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 8763 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, 8764 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/3, /*TempRegFlags*/0, 8765 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/5, /*TempRegFlags*/0, 8766 GIR_AddImm, /*InsnID*/1, /*Imm*/15, 8767 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 8768 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 8769 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 8770 GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, X86::sub_xmm, 8771 GIR_EraseFromParent, /*InsnID*/0, 8772 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, X86::FR16XRegClassID, 8773 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, X86::VR512RegClassID, 8774 // GIR_Coverage, 20362, 8775 GIR_Done, 8776 // Label 636: @19418 8777 GIM_Try, /*On fail goto*//*Label 637*/ 19469, // Rule ID 20370 // 8778 GIM_CheckFeatures, GIFBS_HasVLX, 8779 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID, 8780 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID, 8781 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 8782 GIM_CheckOpcodeIsEither, /*MI*/1, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, 8783 GIM_CheckIsBuildVectorAllOnes, /*MI*/1, 8784 GIM_CheckIsSafeToFold, /*InsnID*/1, 8785 // (xor:{ *:[v16i8] } VR128X:{ *:[v16i8] }:$src, immAllOnesV:{ *:[v16i8] }) => (VPTERNLOGQZ128rri:{ *:[v16i8] } VR128X:{ *:[v16i8] }:$src, VR128X:{ *:[v16i8] }:$src, VR128X:{ *:[v16i8] }:$src, 15:{ *:[i8] }) 8786 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VPTERNLOGQZ128rri, 8787 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 8788 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 8789 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 8790 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 8791 GIR_AddImm, /*InsnID*/0, /*Imm*/15, 8792 GIR_EraseFromParent, /*InsnID*/0, 8793 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8794 // GIR_Coverage, 20370, 8795 GIR_Done, 8796 // Label 637: @19469 8797 GIM_Try, /*On fail goto*//*Label 638*/ 19492, // Rule ID 16599 // 8798 GIM_CheckFeatures, GIFBS_HasAVX_NoVLX, 8799 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 8800 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 8801 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 8802 // (xor:{ *:[v16i8] } VR128:{ *:[v16i8] }:$src1, VR128:{ *:[v16i8] }:$src2) => (VPXORrr:{ *:[v16i8] } VR128:{ *:[v16i8] }:$src1, VR128:{ *:[v16i8] }:$src2) 8803 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPXORrr, 8804 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8805 // GIR_Coverage, 16599, 8806 GIR_Done, 8807 // Label 638: @19492 8808 GIM_Try, /*On fail goto*//*Label 639*/ 19515, // Rule ID 16623 // 8809 GIM_CheckFeatures, GIFBS_UseSSE2, 8810 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 8811 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 8812 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 8813 // (xor:{ *:[v16i8] } VR128:{ *:[v16i8] }:$src1, VR128:{ *:[v16i8] }:$src2) => (PXORrr:{ *:[v16i8] } VR128:{ *:[v16i8] }:$src1, VR128:{ *:[v16i8] }:$src2) 8814 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::PXORrr, 8815 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8816 // GIR_Coverage, 16623, 8817 GIR_Done, 8818 // Label 639: @19515 8819 GIM_Try, /*On fail goto*//*Label 640*/ 19538, // Rule ID 18505 // 8820 GIM_CheckFeatures, GIFBS_HasVLX, 8821 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID, 8822 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID, 8823 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128XRegClassID, 8824 // (xor:{ *:[v16i8] } VR128X:{ *:[v16i8] }:$src1, VR128X:{ *:[v16i8] }:$src2) => (VPXORQZ128rr:{ *:[v16i8] } VR128X:{ *:[v16i8] }:$src1, VR128X:{ *:[v16i8] }:$src2) 8825 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPXORQZ128rr, 8826 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8827 // GIR_Coverage, 18505, 8828 GIR_Done, 8829 // Label 640: @19538 8830 GIM_Reject, 8831 // Label 635: @19539 8832 GIM_Reject, 8833 // Label 523: @19540 8834 GIM_Try, /*On fail goto*//*Label 641*/ 19880, 8835 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s16, 8836 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s16, 8837 GIM_Try, /*On fail goto*//*Label 642*/ 19759, // Rule ID 20367 // 8838 GIM_CheckFeatures, GIFBS_HasAVX512_NoVLX, 8839 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 8840 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID, 8841 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 8842 GIM_CheckOpcodeIsEither, /*MI*/1, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, 8843 GIM_CheckIsBuildVectorAllOnes, /*MI*/1, 8844 GIM_CheckIsSafeToFold, /*InsnID*/1, 8845 // (xor:{ *:[v16i16] } VR256X:{ *:[v16i16] }:$src, immAllOnesV:{ *:[v16i16] }) => (EXTRACT_SUBREG:{ *:[v16i16] } (VPTERNLOGQZrri:{ *:[v64i8] } (INSERT_SUBREG:{ *:[v8i64] } (IMPLICIT_DEF:{ *:[v8i64] }), VR256X:{ *:[v16i16] }:$src, sub_ymm:{ *:[i32] }), (INSERT_SUBREG:{ *:[v8i64] } (IMPLICIT_DEF:{ *:[v8i64] }), VR256X:{ *:[v16i16] }:$src, sub_ymm:{ *:[i32] }), (INSERT_SUBREG:{ *:[v8i64] } (IMPLICIT_DEF:{ *:[v8i64] }), VR256X:{ *:[v16i16] }:$src, sub_ymm:{ *:[i32] }), 15:{ *:[i8] }), sub_ymm:{ *:[i32] }) 8846 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v64s8, 8847 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s64, 8848 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v8s64, 8849 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v8s64, 8850 GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v8s64, 8851 GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v8s64, 8852 GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_v8s64, 8853 GIR_BuildMI, /*InsnID*/7, /*Opcode*/TargetOpcode::IMPLICIT_DEF, 8854 GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/RegState::Define, 8855 GIR_ConstrainSelectedInstOperands, /*InsnID*/7, 8856 GIR_BuildMI, /*InsnID*/6, /*Opcode*/TargetOpcode::INSERT_SUBREG, 8857 GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/RegState::Define, 8858 GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/6, /*TempRegFlags*/0, 8859 GIR_Copy, /*NewInsnID*/6, /*OldInsnID*/0, /*OpIdx*/1, // src 8860 GIR_AddImm, /*InsnID*/6, /*Imm*/10, 8861 GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, X86::VR512RegClassID, 8862 GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, X86::VR512RegClassID, 8863 GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/2, X86::VR256XRegClassID, 8864 GIR_BuildMI, /*InsnID*/5, /*Opcode*/TargetOpcode::IMPLICIT_DEF, 8865 GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/RegState::Define, 8866 GIR_ConstrainSelectedInstOperands, /*InsnID*/5, 8867 GIR_BuildMI, /*InsnID*/4, /*Opcode*/TargetOpcode::INSERT_SUBREG, 8868 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define, 8869 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/4, /*TempRegFlags*/0, 8870 GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/1, // src 8871 GIR_AddImm, /*InsnID*/4, /*Imm*/10, 8872 GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, X86::VR512RegClassID, 8873 GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/1, X86::VR512RegClassID, 8874 GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/2, X86::VR256XRegClassID, 8875 GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::IMPLICIT_DEF, 8876 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, 8877 GIR_ConstrainSelectedInstOperands, /*InsnID*/3, 8878 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::INSERT_SUBREG, 8879 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 8880 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/2, /*TempRegFlags*/0, 8881 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src 8882 GIR_AddImm, /*InsnID*/2, /*Imm*/10, 8883 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, X86::VR512RegClassID, 8884 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, X86::VR512RegClassID, 8885 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, X86::VR256XRegClassID, 8886 GIR_BuildMI, /*InsnID*/1, /*Opcode*/X86::VPTERNLOGQZrri, 8887 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 8888 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, 8889 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/3, /*TempRegFlags*/0, 8890 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/5, /*TempRegFlags*/0, 8891 GIR_AddImm, /*InsnID*/1, /*Imm*/15, 8892 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 8893 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 8894 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 8895 GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, X86::sub_ymm, 8896 GIR_EraseFromParent, /*InsnID*/0, 8897 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, X86::VR256XRegClassID, 8898 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, X86::VR512RegClassID, 8899 // GIR_Coverage, 20367, 8900 GIR_Done, 8901 // Label 642: @19759 8902 GIM_Try, /*On fail goto*//*Label 643*/ 19810, // Rule ID 20375 // 8903 GIM_CheckFeatures, GIFBS_HasVLX, 8904 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID, 8905 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID, 8906 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 8907 GIM_CheckOpcodeIsEither, /*MI*/1, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, 8908 GIM_CheckIsBuildVectorAllOnes, /*MI*/1, 8909 GIM_CheckIsSafeToFold, /*InsnID*/1, 8910 // (xor:{ *:[v16i16] } VR256X:{ *:[v16i16] }:$src, immAllOnesV:{ *:[v16i16] }) => (VPTERNLOGQZ256rri:{ *:[v16i16] } VR256X:{ *:[v16i16] }:$src, VR256X:{ *:[v16i16] }:$src, VR256X:{ *:[v16i16] }:$src, 15:{ *:[i8] }) 8911 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VPTERNLOGQZ256rri, 8912 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 8913 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 8914 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 8915 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 8916 GIR_AddImm, /*InsnID*/0, /*Imm*/15, 8917 GIR_EraseFromParent, /*InsnID*/0, 8918 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8919 // GIR_Coverage, 20375, 8920 GIR_Done, 8921 // Label 643: @19810 8922 GIM_Try, /*On fail goto*//*Label 644*/ 19833, // Rule ID 16544 // 8923 GIM_CheckFeatures, GIFBS_HasAVX2_NoVLX, 8924 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID, 8925 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256RegClassID, 8926 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256RegClassID, 8927 // (xor:{ *:[v16i16] } VR256:{ *:[v16i16] }:$src1, VR256:{ *:[v16i16] }:$src2) => (VPXORYrr:{ *:[v16i16] } VR256:{ *:[v16i16] }:$src1, VR256:{ *:[v16i16] }:$src2) 8928 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPXORYrr, 8929 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8930 // GIR_Coverage, 16544, 8931 GIR_Done, 8932 // Label 644: @19833 8933 GIM_Try, /*On fail goto*//*Label 645*/ 19856, // Rule ID 16570 // 8934 GIM_CheckFeatures, GIFBS_HasAVX1Only, 8935 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID, 8936 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256RegClassID, 8937 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256RegClassID, 8938 // (xor:{ *:[v16i16] } VR256:{ *:[v16i16] }:$src1, VR256:{ *:[v16i16] }:$src2) => (VXORPSYrr:{ *:[v16i16] } VR256:{ *:[v16i16] }:$src1, VR256:{ *:[v16i16] }:$src2) 8939 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VXORPSYrr, 8940 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8941 // GIR_Coverage, 16570, 8942 GIR_Done, 8943 // Label 645: @19856 8944 GIM_Try, /*On fail goto*//*Label 646*/ 19879, // Rule ID 18522 // 8945 GIM_CheckFeatures, GIFBS_HasVLX, 8946 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID, 8947 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID, 8948 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256XRegClassID, 8949 // (xor:{ *:[v16i16] } VR256X:{ *:[v16i16] }:$src1, VR256X:{ *:[v16i16] }:$src2) => (VPXORQZ256rr:{ *:[v16i16] } VR256X:{ *:[v16i16] }:$src1, VR256X:{ *:[v16i16] }:$src2) 8950 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPXORQZ256rr, 8951 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8952 // GIR_Coverage, 18522, 8953 GIR_Done, 8954 // Label 646: @19879 8955 GIM_Reject, 8956 // Label 641: @19880 8957 GIM_Reject, 8958 // Label 524: @19881 8959 GIM_Try, /*On fail goto*//*Label 647*/ 19958, 8960 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s32, 8961 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s32, 8962 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 8963 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR512RegClassID, 8964 GIM_Try, /*On fail goto*//*Label 648*/ 19942, // Rule ID 20360 // 8965 GIM_CheckFeatures, GIFBS_HasAVX512, 8966 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 8967 GIM_CheckOpcodeIsEither, /*MI*/1, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, 8968 GIM_CheckIsBuildVectorAllOnes, /*MI*/1, 8969 GIM_CheckIsSafeToFold, /*InsnID*/1, 8970 // (xor:{ *:[v16i32] } VR512:{ *:[v16i32] }:$src, immAllOnesV:{ *:[v16i32] }) => (VPTERNLOGQZrri:{ *:[v16i32] } VR512:{ *:[v16i32] }:$src, VR512:{ *:[v16i32] }:$src, VR512:{ *:[v16i32] }:$src, 15:{ *:[i8] }) 8971 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VPTERNLOGQZrri, 8972 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 8973 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 8974 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 8975 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 8976 GIR_AddImm, /*InsnID*/0, /*Imm*/15, 8977 GIR_EraseFromParent, /*InsnID*/0, 8978 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8979 // GIR_Coverage, 20360, 8980 GIR_Done, 8981 // Label 648: @19942 8982 GIM_Try, /*On fail goto*//*Label 649*/ 19957, // Rule ID 5460 // 8983 GIM_CheckFeatures, GIFBS_HasAVX512, 8984 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR512RegClassID, 8985 // (xor:{ *:[v16i32] } VR512:{ *:[v16i32] }:$src1, VR512:{ *:[v16i32] }:$src2) => (VPXORDZrr:{ *:[v16i32] } VR512:{ *:[v16i32] }:$src1, VR512:{ *:[v16i32] }:$src2) 8986 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPXORDZrr, 8987 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8988 // GIR_Coverage, 5460, 8989 GIR_Done, 8990 // Label 649: @19957 8991 GIM_Reject, 8992 // Label 647: @19958 8993 GIM_Reject, 8994 // Label 525: @19959 8995 GIM_Try, /*On fail goto*//*Label 650*/ 20212, 8996 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v32s1, 8997 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v32s1, 8998 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VK32RegClassID, 8999 GIM_Try, /*On fail goto*//*Label 651*/ 20034, // Rule ID 21557 // 9000 GIM_CheckFeatures, GIFBS_HasBWI, 9001 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 9002 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, 9003 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v32s1, 9004 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v32s1, 9005 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::VK32RegClassID, 9006 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] 9007 GIM_CheckOpcodeIsEither, /*MI*/2, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, 9008 GIM_CheckIsBuildVectorAllOnes, /*MI*/2, 9009 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VK32RegClassID, 9010 GIM_CheckIsSafeToFold, /*InsnID*/1, 9011 GIM_CheckIsSafeToFold, /*InsnID*/2, 9012 // (xor:{ *:[v32i1] } (xor:{ *:[v32i1] } VK32:{ *:[v32i1] }:$src1, immAllOnesV:{ *:[v32i1] }), VK32:{ *:[v32i1] }:$src2) => (KXNORDrr:{ *:[v32i1] } VK32:{ *:[v32i1] }:$src1, VK32:{ *:[v32i1] }:$src2) 9013 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::KXNORDrr, 9014 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 9015 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1 9016 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src2 9017 GIR_EraseFromParent, /*InsnID*/0, 9018 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9019 // GIR_Coverage, 21557, 9020 GIR_Done, 9021 // Label 651: @20034 9022 GIM_Try, /*On fail goto*//*Label 652*/ 20095, // Rule ID 4064 // 9023 GIM_CheckFeatures, GIFBS_HasBWI, 9024 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 9025 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, 9026 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v32s1, 9027 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v32s1, 9028 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::VK32RegClassID, 9029 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/X86::VK32RegClassID, 9030 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] 9031 GIM_CheckOpcodeIsEither, /*MI*/2, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, 9032 GIM_CheckIsBuildVectorAllOnes, /*MI*/2, 9033 GIM_CheckIsSafeToFold, /*InsnID*/1, 9034 GIM_CheckIsSafeToFold, /*InsnID*/2, 9035 // (xor:{ *:[v32i1] } (xor:{ *:[v32i1] } VK32:{ *:[v32i1] }:$src1, VK32:{ *:[v32i1] }:$src2), immAllOnesV:{ *:[v32i1] }) => (KXNORDrr:{ *:[v32i1] } VK32:{ *:[v32i1] }:$src1, VK32:{ *:[v32i1] }:$src2) 9036 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::KXNORDrr, 9037 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 9038 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1 9039 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src2 9040 GIR_EraseFromParent, /*InsnID*/0, 9041 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9042 // GIR_Coverage, 4064, 9043 GIR_Done, 9044 // Label 652: @20095 9045 GIM_Try, /*On fail goto*//*Label 653*/ 20156, // Rule ID 21558 // 9046 GIM_CheckFeatures, GIFBS_HasBWI, 9047 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VK32RegClassID, 9048 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 9049 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, 9050 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v32s1, 9051 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v32s1, 9052 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::VK32RegClassID, 9053 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] 9054 GIM_CheckOpcodeIsEither, /*MI*/2, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, 9055 GIM_CheckIsBuildVectorAllOnes, /*MI*/2, 9056 GIM_CheckIsSafeToFold, /*InsnID*/1, 9057 GIM_CheckIsSafeToFold, /*InsnID*/2, 9058 // (xor:{ *:[v32i1] } VK32:{ *:[v32i1] }:$src2, (xor:{ *:[v32i1] } VK32:{ *:[v32i1] }:$src1, immAllOnesV:{ *:[v32i1] })) => (KXNORDrr:{ *:[v32i1] } VK32:{ *:[v32i1] }:$src1, VK32:{ *:[v32i1] }:$src2) 9059 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::KXNORDrr, 9060 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 9061 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1 9062 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src2 9063 GIR_EraseFromParent, /*InsnID*/0, 9064 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9065 // GIR_Coverage, 21558, 9066 GIR_Done, 9067 // Label 653: @20156 9068 GIM_Try, /*On fail goto*//*Label 654*/ 20192, // Rule ID 4052 // 9069 GIM_CheckFeatures, GIFBS_HasBWI, 9070 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VK32RegClassID, 9071 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 9072 GIM_CheckOpcodeIsEither, /*MI*/1, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, 9073 GIM_CheckIsBuildVectorAllOnes, /*MI*/1, 9074 GIM_CheckIsSafeToFold, /*InsnID*/1, 9075 // (xor:{ *:[v32i1] } VK32:{ *:[v32i1] }:$src, immAllOnesV:{ *:[v32i1] }) => (KNOTDrr:{ *:[v32i1] } VK32:{ *:[v32i1] }:$src) 9076 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::KNOTDrr, 9077 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 9078 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 9079 GIR_EraseFromParent, /*InsnID*/0, 9080 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9081 // GIR_Coverage, 4052, 9082 GIR_Done, 9083 // Label 654: @20192 9084 GIM_Try, /*On fail goto*//*Label 655*/ 20211, // Rule ID 4068 // 9085 GIM_CheckFeatures, GIFBS_HasBWI, 9086 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VK32RegClassID, 9087 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VK32RegClassID, 9088 // (xor:{ *:[v32i1] } VK32:{ *:[v32i1] }:$src1, VK32:{ *:[v32i1] }:$src2) => (KXORDrr:{ *:[v32i1] } VK32:{ *:[v32i1] }:$src1, VK32:{ *:[v32i1] }:$src2) 9089 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::KXORDrr, 9090 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9091 // GIR_Coverage, 4068, 9092 GIR_Done, 9093 // Label 655: @20211 9094 GIM_Reject, 9095 // Label 650: @20212 9096 GIM_Reject, 9097 // Label 526: @20213 9098 GIM_Try, /*On fail goto*//*Label 656*/ 20553, 9099 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v32s8, 9100 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v32s8, 9101 GIM_Try, /*On fail goto*//*Label 657*/ 20432, // Rule ID 20366 // 9102 GIM_CheckFeatures, GIFBS_HasAVX512_NoVLX, 9103 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 9104 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID, 9105 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 9106 GIM_CheckOpcodeIsEither, /*MI*/1, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, 9107 GIM_CheckIsBuildVectorAllOnes, /*MI*/1, 9108 GIM_CheckIsSafeToFold, /*InsnID*/1, 9109 // (xor:{ *:[v32i8] } VR256X:{ *:[v32i8] }:$src, immAllOnesV:{ *:[v32i8] }) => (EXTRACT_SUBREG:{ *:[v32i8] } (VPTERNLOGQZrri:{ *:[v64i8] } (INSERT_SUBREG:{ *:[v8i64] } (IMPLICIT_DEF:{ *:[v8i64] }), VR256X:{ *:[v32i8] }:$src, sub_ymm:{ *:[i32] }), (INSERT_SUBREG:{ *:[v8i64] } (IMPLICIT_DEF:{ *:[v8i64] }), VR256X:{ *:[v32i8] }:$src, sub_ymm:{ *:[i32] }), (INSERT_SUBREG:{ *:[v8i64] } (IMPLICIT_DEF:{ *:[v8i64] }), VR256X:{ *:[v32i8] }:$src, sub_ymm:{ *:[i32] }), 15:{ *:[i8] }), sub_ymm:{ *:[i32] }) 9110 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v64s8, 9111 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s64, 9112 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v8s64, 9113 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v8s64, 9114 GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v8s64, 9115 GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v8s64, 9116 GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_v8s64, 9117 GIR_BuildMI, /*InsnID*/7, /*Opcode*/TargetOpcode::IMPLICIT_DEF, 9118 GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/RegState::Define, 9119 GIR_ConstrainSelectedInstOperands, /*InsnID*/7, 9120 GIR_BuildMI, /*InsnID*/6, /*Opcode*/TargetOpcode::INSERT_SUBREG, 9121 GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/RegState::Define, 9122 GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/6, /*TempRegFlags*/0, 9123 GIR_Copy, /*NewInsnID*/6, /*OldInsnID*/0, /*OpIdx*/1, // src 9124 GIR_AddImm, /*InsnID*/6, /*Imm*/10, 9125 GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, X86::VR512RegClassID, 9126 GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, X86::VR512RegClassID, 9127 GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/2, X86::VR256XRegClassID, 9128 GIR_BuildMI, /*InsnID*/5, /*Opcode*/TargetOpcode::IMPLICIT_DEF, 9129 GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/RegState::Define, 9130 GIR_ConstrainSelectedInstOperands, /*InsnID*/5, 9131 GIR_BuildMI, /*InsnID*/4, /*Opcode*/TargetOpcode::INSERT_SUBREG, 9132 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define, 9133 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/4, /*TempRegFlags*/0, 9134 GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/1, // src 9135 GIR_AddImm, /*InsnID*/4, /*Imm*/10, 9136 GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, X86::VR512RegClassID, 9137 GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/1, X86::VR512RegClassID, 9138 GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/2, X86::VR256XRegClassID, 9139 GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::IMPLICIT_DEF, 9140 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, 9141 GIR_ConstrainSelectedInstOperands, /*InsnID*/3, 9142 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::INSERT_SUBREG, 9143 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 9144 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/2, /*TempRegFlags*/0, 9145 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src 9146 GIR_AddImm, /*InsnID*/2, /*Imm*/10, 9147 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, X86::VR512RegClassID, 9148 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, X86::VR512RegClassID, 9149 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, X86::VR256XRegClassID, 9150 GIR_BuildMI, /*InsnID*/1, /*Opcode*/X86::VPTERNLOGQZrri, 9151 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 9152 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, 9153 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/3, /*TempRegFlags*/0, 9154 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/5, /*TempRegFlags*/0, 9155 GIR_AddImm, /*InsnID*/1, /*Imm*/15, 9156 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 9157 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 9158 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 9159 GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, X86::sub_ymm, 9160 GIR_EraseFromParent, /*InsnID*/0, 9161 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, X86::VR256XRegClassID, 9162 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, X86::VR512RegClassID, 9163 // GIR_Coverage, 20366, 9164 GIR_Done, 9165 // Label 657: @20432 9166 GIM_Try, /*On fail goto*//*Label 658*/ 20483, // Rule ID 20374 // 9167 GIM_CheckFeatures, GIFBS_HasVLX, 9168 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID, 9169 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID, 9170 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 9171 GIM_CheckOpcodeIsEither, /*MI*/1, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, 9172 GIM_CheckIsBuildVectorAllOnes, /*MI*/1, 9173 GIM_CheckIsSafeToFold, /*InsnID*/1, 9174 // (xor:{ *:[v32i8] } VR256X:{ *:[v32i8] }:$src, immAllOnesV:{ *:[v32i8] }) => (VPTERNLOGQZ256rri:{ *:[v32i8] } VR256X:{ *:[v32i8] }:$src, VR256X:{ *:[v32i8] }:$src, VR256X:{ *:[v32i8] }:$src, 15:{ *:[i8] }) 9175 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VPTERNLOGQZ256rri, 9176 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 9177 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 9178 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 9179 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 9180 GIR_AddImm, /*InsnID*/0, /*Imm*/15, 9181 GIR_EraseFromParent, /*InsnID*/0, 9182 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9183 // GIR_Coverage, 20374, 9184 GIR_Done, 9185 // Label 658: @20483 9186 GIM_Try, /*On fail goto*//*Label 659*/ 20506, // Rule ID 16543 // 9187 GIM_CheckFeatures, GIFBS_HasAVX2_NoVLX, 9188 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID, 9189 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256RegClassID, 9190 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256RegClassID, 9191 // (xor:{ *:[v32i8] } VR256:{ *:[v32i8] }:$src1, VR256:{ *:[v32i8] }:$src2) => (VPXORYrr:{ *:[v32i8] } VR256:{ *:[v32i8] }:$src1, VR256:{ *:[v32i8] }:$src2) 9192 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPXORYrr, 9193 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9194 // GIR_Coverage, 16543, 9195 GIR_Done, 9196 // Label 659: @20506 9197 GIM_Try, /*On fail goto*//*Label 660*/ 20529, // Rule ID 16569 // 9198 GIM_CheckFeatures, GIFBS_HasAVX1Only, 9199 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID, 9200 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256RegClassID, 9201 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256RegClassID, 9202 // (xor:{ *:[v32i8] } VR256:{ *:[v32i8] }:$src1, VR256:{ *:[v32i8] }:$src2) => (VXORPSYrr:{ *:[v32i8] } VR256:{ *:[v32i8] }:$src1, VR256:{ *:[v32i8] }:$src2) 9203 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VXORPSYrr, 9204 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9205 // GIR_Coverage, 16569, 9206 GIR_Done, 9207 // Label 660: @20529 9208 GIM_Try, /*On fail goto*//*Label 661*/ 20552, // Rule ID 18521 // 9209 GIM_CheckFeatures, GIFBS_HasVLX, 9210 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID, 9211 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID, 9212 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256XRegClassID, 9213 // (xor:{ *:[v32i8] } VR256X:{ *:[v32i8] }:$src1, VR256X:{ *:[v32i8] }:$src2) => (VPXORQZ256rr:{ *:[v32i8] } VR256X:{ *:[v32i8] }:$src1, VR256X:{ *:[v32i8] }:$src2) 9214 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPXORQZ256rr, 9215 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9216 // GIR_Coverage, 18521, 9217 GIR_Done, 9218 // Label 661: @20552 9219 GIM_Reject, 9220 // Label 656: @20553 9221 GIM_Reject, 9222 // Label 527: @20554 9223 GIM_Try, /*On fail goto*//*Label 662*/ 20631, 9224 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v32s16, 9225 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v32s16, 9226 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 9227 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR512RegClassID, 9228 GIM_Try, /*On fail goto*//*Label 663*/ 20615, // Rule ID 20359 // 9229 GIM_CheckFeatures, GIFBS_HasAVX512, 9230 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 9231 GIM_CheckOpcodeIsEither, /*MI*/1, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, 9232 GIM_CheckIsBuildVectorAllOnes, /*MI*/1, 9233 GIM_CheckIsSafeToFold, /*InsnID*/1, 9234 // (xor:{ *:[v32i16] } VR512:{ *:[v32i16] }:$src, immAllOnesV:{ *:[v32i16] }) => (VPTERNLOGQZrri:{ *:[v32i16] } VR512:{ *:[v32i16] }:$src, VR512:{ *:[v32i16] }:$src, VR512:{ *:[v32i16] }:$src, 15:{ *:[i8] }) 9235 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VPTERNLOGQZrri, 9236 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 9237 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 9238 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 9239 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 9240 GIR_AddImm, /*InsnID*/0, /*Imm*/15, 9241 GIR_EraseFromParent, /*InsnID*/0, 9242 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9243 // GIR_Coverage, 20359, 9244 GIR_Done, 9245 // Label 663: @20615 9246 GIM_Try, /*On fail goto*//*Label 664*/ 20630, // Rule ID 18538 // 9247 GIM_CheckFeatures, GIFBS_HasAVX512, 9248 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR512RegClassID, 9249 // (xor:{ *:[v32i16] } VR512:{ *:[v32i16] }:$src1, VR512:{ *:[v32i16] }:$src2) => (VPXORQZrr:{ *:[v32i16] } VR512:{ *:[v32i16] }:$src1, VR512:{ *:[v32i16] }:$src2) 9250 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPXORQZrr, 9251 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9252 // GIR_Coverage, 18538, 9253 GIR_Done, 9254 // Label 664: @20630 9255 GIM_Reject, 9256 // Label 662: @20631 9257 GIM_Reject, 9258 // Label 528: @20632 9259 GIM_Try, /*On fail goto*//*Label 665*/ 20885, 9260 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v64s1, 9261 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v64s1, 9262 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VK64RegClassID, 9263 GIM_Try, /*On fail goto*//*Label 666*/ 20707, // Rule ID 21559 // 9264 GIM_CheckFeatures, GIFBS_HasBWI, 9265 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 9266 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, 9267 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v64s1, 9268 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v64s1, 9269 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::VK64RegClassID, 9270 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] 9271 GIM_CheckOpcodeIsEither, /*MI*/2, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, 9272 GIM_CheckIsBuildVectorAllOnes, /*MI*/2, 9273 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VK64RegClassID, 9274 GIM_CheckIsSafeToFold, /*InsnID*/1, 9275 GIM_CheckIsSafeToFold, /*InsnID*/2, 9276 // (xor:{ *:[v64i1] } (xor:{ *:[v64i1] } VK64:{ *:[v64i1] }:$src1, immAllOnesV:{ *:[v64i1] }), VK64:{ *:[v64i1] }:$src2) => (KXNORQrr:{ *:[v64i1] } VK64:{ *:[v64i1] }:$src1, VK64:{ *:[v64i1] }:$src2) 9277 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::KXNORQrr, 9278 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 9279 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1 9280 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src2 9281 GIR_EraseFromParent, /*InsnID*/0, 9282 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9283 // GIR_Coverage, 21559, 9284 GIR_Done, 9285 // Label 666: @20707 9286 GIM_Try, /*On fail goto*//*Label 667*/ 20768, // Rule ID 4065 // 9287 GIM_CheckFeatures, GIFBS_HasBWI, 9288 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 9289 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, 9290 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v64s1, 9291 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v64s1, 9292 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::VK64RegClassID, 9293 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/X86::VK64RegClassID, 9294 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] 9295 GIM_CheckOpcodeIsEither, /*MI*/2, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, 9296 GIM_CheckIsBuildVectorAllOnes, /*MI*/2, 9297 GIM_CheckIsSafeToFold, /*InsnID*/1, 9298 GIM_CheckIsSafeToFold, /*InsnID*/2, 9299 // (xor:{ *:[v64i1] } (xor:{ *:[v64i1] } VK64:{ *:[v64i1] }:$src1, VK64:{ *:[v64i1] }:$src2), immAllOnesV:{ *:[v64i1] }) => (KXNORQrr:{ *:[v64i1] } VK64:{ *:[v64i1] }:$src1, VK64:{ *:[v64i1] }:$src2) 9300 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::KXNORQrr, 9301 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 9302 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1 9303 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src2 9304 GIR_EraseFromParent, /*InsnID*/0, 9305 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9306 // GIR_Coverage, 4065, 9307 GIR_Done, 9308 // Label 667: @20768 9309 GIM_Try, /*On fail goto*//*Label 668*/ 20829, // Rule ID 21560 // 9310 GIM_CheckFeatures, GIFBS_HasBWI, 9311 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VK64RegClassID, 9312 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 9313 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, 9314 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v64s1, 9315 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v64s1, 9316 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::VK64RegClassID, 9317 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] 9318 GIM_CheckOpcodeIsEither, /*MI*/2, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, 9319 GIM_CheckIsBuildVectorAllOnes, /*MI*/2, 9320 GIM_CheckIsSafeToFold, /*InsnID*/1, 9321 GIM_CheckIsSafeToFold, /*InsnID*/2, 9322 // (xor:{ *:[v64i1] } VK64:{ *:[v64i1] }:$src2, (xor:{ *:[v64i1] } VK64:{ *:[v64i1] }:$src1, immAllOnesV:{ *:[v64i1] })) => (KXNORQrr:{ *:[v64i1] } VK64:{ *:[v64i1] }:$src1, VK64:{ *:[v64i1] }:$src2) 9323 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::KXNORQrr, 9324 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 9325 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1 9326 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src2 9327 GIR_EraseFromParent, /*InsnID*/0, 9328 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9329 // GIR_Coverage, 21560, 9330 GIR_Done, 9331 // Label 668: @20829 9332 GIM_Try, /*On fail goto*//*Label 669*/ 20865, // Rule ID 4053 // 9333 GIM_CheckFeatures, GIFBS_HasBWI, 9334 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VK64RegClassID, 9335 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 9336 GIM_CheckOpcodeIsEither, /*MI*/1, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, 9337 GIM_CheckIsBuildVectorAllOnes, /*MI*/1, 9338 GIM_CheckIsSafeToFold, /*InsnID*/1, 9339 // (xor:{ *:[v64i1] } VK64:{ *:[v64i1] }:$src, immAllOnesV:{ *:[v64i1] }) => (KNOTQrr:{ *:[v64i1] } VK64:{ *:[v64i1] }:$src) 9340 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::KNOTQrr, 9341 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 9342 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 9343 GIR_EraseFromParent, /*InsnID*/0, 9344 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9345 // GIR_Coverage, 4053, 9346 GIR_Done, 9347 // Label 669: @20865 9348 GIM_Try, /*On fail goto*//*Label 670*/ 20884, // Rule ID 4069 // 9349 GIM_CheckFeatures, GIFBS_HasBWI, 9350 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VK64RegClassID, 9351 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VK64RegClassID, 9352 // (xor:{ *:[v64i1] } VK64:{ *:[v64i1] }:$src1, VK64:{ *:[v64i1] }:$src2) => (KXORQrr:{ *:[v64i1] } VK64:{ *:[v64i1] }:$src1, VK64:{ *:[v64i1] }:$src2) 9353 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::KXORQrr, 9354 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9355 // GIR_Coverage, 4069, 9356 GIR_Done, 9357 // Label 670: @20884 9358 GIM_Reject, 9359 // Label 665: @20885 9360 GIM_Reject, 9361 // Label 529: @20886 9362 GIM_Try, /*On fail goto*//*Label 671*/ 20963, 9363 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v64s8, 9364 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v64s8, 9365 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 9366 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR512RegClassID, 9367 GIM_Try, /*On fail goto*//*Label 672*/ 20947, // Rule ID 20358 // 9368 GIM_CheckFeatures, GIFBS_HasAVX512, 9369 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 9370 GIM_CheckOpcodeIsEither, /*MI*/1, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, 9371 GIM_CheckIsBuildVectorAllOnes, /*MI*/1, 9372 GIM_CheckIsSafeToFold, /*InsnID*/1, 9373 // (xor:{ *:[v64i8] } VR512:{ *:[v64i8] }:$src, immAllOnesV:{ *:[v64i8] }) => (VPTERNLOGQZrri:{ *:[v64i8] } VR512:{ *:[v64i8] }:$src, VR512:{ *:[v64i8] }:$src, VR512:{ *:[v64i8] }:$src, 15:{ *:[i8] }) 9374 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VPTERNLOGQZrri, 9375 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 9376 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 9377 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 9378 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 9379 GIR_AddImm, /*InsnID*/0, /*Imm*/15, 9380 GIR_EraseFromParent, /*InsnID*/0, 9381 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9382 // GIR_Coverage, 20358, 9383 GIR_Done, 9384 // Label 672: @20947 9385 GIM_Try, /*On fail goto*//*Label 673*/ 20962, // Rule ID 18537 // 9386 GIM_CheckFeatures, GIFBS_HasAVX512, 9387 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR512RegClassID, 9388 // (xor:{ *:[v64i8] } VR512:{ *:[v64i8] }:$src1, VR512:{ *:[v64i8] }:$src2) => (VPXORQZrr:{ *:[v64i8] } VR512:{ *:[v64i8] }:$src1, VR512:{ *:[v64i8] }:$src2) 9389 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPXORQZrr, 9390 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9391 // GIR_Coverage, 18537, 9392 GIR_Done, 9393 // Label 673: @20962 9394 GIM_Reject, 9395 // Label 671: @20963 9396 GIM_Reject, 9397 // Label 530: @20964 9398 GIM_Reject, 9399 // Label 6: @20965 9400 GIM_Try, /*On fail goto*//*Label 674*/ 21120, 9401 GIM_CheckNumOperands, /*MI*/0, /*Expected*/3, 9402 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/16, 24, /*)*//*default:*//*Label 678*/ 21119, 9403 /*GILLT_v16s1*//*Label 675*/ 20984, 0, 0, 0, 9404 /*GILLT_v32s1*//*Label 676*/ 21029, 0, 0, 9405 /*GILLT_v64s1*//*Label 677*/ 21074, 9406 // Label 675: @20984 9407 GIM_Try, /*On fail goto*//*Label 679*/ 21028, // Rule ID 17942 // 9408 GIM_CheckFeatures, GIFBS_HasAVX512, 9409 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s1, 9410 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s1, 9411 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VK16RegClassID, 9412 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VK8RegClassID, 9413 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VK8RegClassID, 9414 // (concat_vectors:{ *:[v16i1] } VK8:{ *:[v8i1] }:$src1, VK8:{ *:[v8i1] }:$src2) => (KUNPCKBWrr:{ *:[v16i1] } VK8:{ *:[v8i1] }:$src2, VK8:{ *:[v8i1] }:$src1) 9415 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::KUNPCKBWrr, 9416 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 9417 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src2 9418 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 9419 GIR_EraseFromParent, /*InsnID*/0, 9420 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9421 // GIR_Coverage, 17942, 9422 GIR_Done, 9423 // Label 679: @21028 9424 GIM_Reject, 9425 // Label 676: @21029 9426 GIM_Try, /*On fail goto*//*Label 680*/ 21073, // Rule ID 17943 // 9427 GIM_CheckFeatures, GIFBS_HasBWI, 9428 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s1, 9429 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s1, 9430 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VK32RegClassID, 9431 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VK16RegClassID, 9432 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VK16RegClassID, 9433 // (concat_vectors:{ *:[v32i1] } VK16:{ *:[v16i1] }:$src1, VK16:{ *:[v16i1] }:$src2) => (KUNPCKWDrr:{ *:[v32i1] } VK16:{ *:[v16i1] }:$src2, VK16:{ *:[v16i1] }:$src1) 9434 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::KUNPCKWDrr, 9435 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 9436 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src2 9437 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 9438 GIR_EraseFromParent, /*InsnID*/0, 9439 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9440 // GIR_Coverage, 17943, 9441 GIR_Done, 9442 // Label 680: @21073 9443 GIM_Reject, 9444 // Label 677: @21074 9445 GIM_Try, /*On fail goto*//*Label 681*/ 21118, // Rule ID 17944 // 9446 GIM_CheckFeatures, GIFBS_HasBWI, 9447 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v32s1, 9448 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v32s1, 9449 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VK64RegClassID, 9450 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VK32RegClassID, 9451 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VK32RegClassID, 9452 // (concat_vectors:{ *:[v64i1] } VK32:{ *:[v32i1] }:$src1, VK32:{ *:[v32i1] }:$src2) => (KUNPCKDQrr:{ *:[v64i1] } VK32:{ *:[v32i1] }:$src2, VK32:{ *:[v32i1] }:$src1) 9453 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::KUNPCKDQrr, 9454 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 9455 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src2 9456 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 9457 GIR_EraseFromParent, /*InsnID*/0, 9458 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9459 // GIR_Coverage, 17944, 9460 GIR_Done, 9461 // Label 681: @21118 9462 GIM_Reject, 9463 // Label 678: @21119 9464 GIM_Reject, 9465 // Label 674: @21120 9466 GIM_Reject, 9467 // Label 7: @21121 9468 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 24, /*)*//*default:*//*Label 690*/ 22666, 9469 /*GILLT_s8*//*Label 682*/ 21150, 9470 /*GILLT_s16*//*Label 683*/ 21204, 9471 /*GILLT_s32*//*Label 684*/ 21964, 9472 /*GILLT_s64*//*Label 685*/ 22172, 0, 0, 0, 0, 0, 0, 0, 9473 /*GILLT_v8s1*//*Label 686*/ 22380, 0, 0, 0, 9474 /*GILLT_v16s1*//*Label 687*/ 22458, 0, 0, 0, 9475 /*GILLT_v32s1*//*Label 688*/ 22536, 0, 0, 9476 /*GILLT_v64s1*//*Label 689*/ 22601, 9477 // Label 682: @21150 9478 GIM_Try, /*On fail goto*//*Label 691*/ 21203, // Rule ID 17873 // 9479 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s1, 9480 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID, 9481 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VK8RegClassID, 9482 // (bitconvert:{ *:[i8] } VK8:{ *:[v8i1] }:$src) => (EXTRACT_SUBREG:{ *:[i8] } (COPY_TO_REGCLASS:{ *:[i32] } VK8:{ *:[v8i1] }:$src, GR32:{ *:[i32] }), sub_8bit:{ *:[i32] }) 9483 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, 9484 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, 9485 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 9486 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src 9487 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 9488 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 9489 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 9490 GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, X86::sub_8bit, 9491 GIR_EraseFromParent, /*InsnID*/0, 9492 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, X86::GR8RegClassID, 9493 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, X86::GR32RegClassID, 9494 // GIR_Coverage, 17873, 9495 GIR_Done, 9496 // Label 691: @21203 9497 GIM_Reject, 9498 // Label 683: @21204 9499 GIM_Try, /*On fail goto*//*Label 692*/ 21257, // Rule ID 17870 // 9500 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s1, 9501 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID, 9502 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VK16RegClassID, 9503 // (bitconvert:{ *:[i16] } VK16:{ *:[v16i1] }:$src) => (EXTRACT_SUBREG:{ *:[i16] } (COPY_TO_REGCLASS:{ *:[i32] } VK16:{ *:[v16i1] }:$src, GR32:{ *:[i32] }), sub_16bit:{ *:[i32] }) 9504 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, 9505 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, 9506 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 9507 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src 9508 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 9509 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 9510 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 9511 GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, X86::sub_16bit, 9512 GIR_EraseFromParent, /*InsnID*/0, 9513 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, X86::GR16RegClassID, 9514 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, X86::GR32RegClassID, 9515 // GIR_Coverage, 17870, 9516 GIR_Done, 9517 // Label 692: @21257 9518 GIM_Try, /*On fail goto*//*Label 693*/ 21352, // Rule ID 20554 // 9519 GIM_CheckFeatures, GIFBS_HasFP16, 9520 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16, 9521 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::FR16XRegClassID, 9522 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR16RegClassID, 9523 // (bitconvert:{ *:[f16] } GR16:{ *:[i16] }:$src) => (COPY_TO_REGCLASS:{ *:[f16] } (VMOVW2SHrr:{ *:[f128] } (INSERT_SUBREG:{ *:[i32] } (IMPLICIT_DEF:{ *:[i32] }), GR16:{ *:[i16] }:$src, sub_16bit:{ *:[i32] })), FR16X:{ *:[i32] }) 9524 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, 9525 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, 9526 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32, 9527 GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::IMPLICIT_DEF, 9528 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, 9529 GIR_ConstrainSelectedInstOperands, /*InsnID*/3, 9530 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::INSERT_SUBREG, 9531 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 9532 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/2, /*TempRegFlags*/0, 9533 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src 9534 GIR_AddImm, /*InsnID*/2, /*Imm*/4, 9535 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, X86::LOW32_ADDR_ACCESS_RBPRegClassID, 9536 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, X86::LOW32_ADDR_ACCESS_RBPRegClassID, 9537 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, X86::GR16RegClassID, 9538 GIR_BuildMI, /*InsnID*/1, /*Opcode*/X86::VMOVW2SHrr, 9539 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 9540 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, 9541 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 9542 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 9543 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 9544 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 9545 GIR_EraseFromParent, /*InsnID*/0, 9546 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, X86::FR16XRegClassID, 9547 // GIR_Coverage, 20554, 9548 GIR_Done, 9549 // Label 693: @21352 9550 GIM_Try, /*On fail goto*//*Label 694*/ 21423, // Rule ID 20567 // 9551 GIM_CheckFeatures, GIFBS_HasFP16, 9552 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16, 9553 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID, 9554 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::FR16XRegClassID, 9555 // (bitconvert:{ *:[i16] } FR16X:{ *:[f16] }:$src) => (EXTRACT_SUBREG:{ *:[i16] } (VMOVSH2Wrr:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[f128] } FR16X:{ *:[f16] }:$src, VR128X:{ *:[i32] })), sub_16bit:{ *:[i32] }) 9556 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, 9557 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, 9558 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY, 9559 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 9560 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src 9561 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 9562 GIR_BuildMI, /*InsnID*/1, /*Opcode*/X86::VMOVSH2Wrr, 9563 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 9564 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, 9565 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 9566 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 9567 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 9568 GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, X86::sub_16bit, 9569 GIR_EraseFromParent, /*InsnID*/0, 9570 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, X86::GR16RegClassID, 9571 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, X86::GR32RegClassID, 9572 // GIR_Coverage, 20567, 9573 GIR_Done, 9574 // Label 694: @21423 9575 GIM_Try, /*On fail goto*//*Label 695*/ 21493, // Rule ID 16787 // 9576 GIM_CheckFeatures, GIFBS_HasAVX_NoBWI, 9577 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16, 9578 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID, 9579 // (bitconvert:{ *:[i16] } f16:{ *:[f16] }:$src) => (EXTRACT_SUBREG:{ *:[i16] } (VPEXTRWrr:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[v8i16] } FR16:{ *:[f16] }:$src, VR128:{ *:[i32] }), 0:{ *:[i8] }), sub_16bit:{ *:[i32] }) 9580 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, 9581 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16, 9582 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY, 9583 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 9584 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src 9585 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 9586 GIR_BuildMI, /*InsnID*/1, /*Opcode*/X86::VPEXTRWrr, 9587 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 9588 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, 9589 GIR_AddImm, /*InsnID*/1, /*Imm*/0, 9590 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 9591 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 9592 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 9593 GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, X86::sub_16bit, 9594 GIR_EraseFromParent, /*InsnID*/0, 9595 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, X86::GR16RegClassID, 9596 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, X86::GR32RegClassID, 9597 // GIR_Coverage, 16787, 9598 GIR_Done, 9599 // Label 695: @21493 9600 GIM_Try, /*On fail goto*//*Label 696*/ 21603, // Rule ID 16788 // 9601 GIM_CheckFeatures, GIFBS_HasAVX_NoBWI, 9602 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16, 9603 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::FR16RegClassID, 9604 // (bitconvert:{ *:[f16] } i16:{ *:[i16] }:$src) => (COPY_TO_REGCLASS:{ *:[f16] } (VPINSRWrr:{ *:[f128] } (IMPLICIT_DEF:{ *:[v8i16] }), (INSERT_SUBREG:{ *:[i32] } (IMPLICIT_DEF:{ *:[i32] }), GR16:{ *:[i16] }:$src, sub_16bit:{ *:[i32] }), 0:{ *:[i8] }), FR16:{ *:[i32] }) 9605 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, 9606 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16, 9607 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32, 9608 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32, 9609 GIR_BuildMI, /*InsnID*/4, /*Opcode*/TargetOpcode::IMPLICIT_DEF, 9610 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define, 9611 GIR_ConstrainSelectedInstOperands, /*InsnID*/4, 9612 GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::INSERT_SUBREG, 9613 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, 9614 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/3, /*TempRegFlags*/0, 9615 GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // src 9616 GIR_AddImm, /*InsnID*/3, /*Imm*/4, 9617 GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, X86::LOW32_ADDR_ACCESS_RBPRegClassID, 9618 GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, X86::LOW32_ADDR_ACCESS_RBPRegClassID, 9619 GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, X86::GR16RegClassID, 9620 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, 9621 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 9622 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 9623 GIR_BuildMI, /*InsnID*/1, /*Opcode*/X86::VPINSRWrr, 9624 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 9625 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, 9626 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/2, /*TempRegFlags*/0, 9627 GIR_AddImm, /*InsnID*/1, /*Imm*/0, 9628 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 9629 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 9630 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 9631 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 9632 GIR_EraseFromParent, /*InsnID*/0, 9633 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, X86::FR16RegClassID, 9634 // GIR_Coverage, 16788, 9635 GIR_Done, 9636 // Label 696: @21603 9637 GIM_Try, /*On fail goto*//*Label 697*/ 21673, // Rule ID 16784 // 9638 GIM_CheckFeatures, GIFBS_UseSSE2, 9639 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16, 9640 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID, 9641 // (bitconvert:{ *:[i16] } f16:{ *:[f16] }:$src) => (EXTRACT_SUBREG:{ *:[i16] } (PEXTRWrr:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[v8i16] } FR16:{ *:[f16] }:$src, VR128:{ *:[i32] }), 0:{ *:[i8] }), sub_16bit:{ *:[i32] }) 9642 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, 9643 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16, 9644 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY, 9645 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 9646 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src 9647 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 9648 GIR_BuildMI, /*InsnID*/1, /*Opcode*/X86::PEXTRWrr, 9649 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 9650 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, 9651 GIR_AddImm, /*InsnID*/1, /*Imm*/0, 9652 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 9653 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 9654 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 9655 GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, X86::sub_16bit, 9656 GIR_EraseFromParent, /*InsnID*/0, 9657 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, X86::GR16RegClassID, 9658 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, X86::GR32RegClassID, 9659 // GIR_Coverage, 16784, 9660 GIR_Done, 9661 // Label 697: @21673 9662 GIM_Try, /*On fail goto*//*Label 698*/ 21783, // Rule ID 16785 // 9663 GIM_CheckFeatures, GIFBS_UseSSE2, 9664 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16, 9665 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::FR16RegClassID, 9666 // (bitconvert:{ *:[f16] } i16:{ *:[i16] }:$src) => (COPY_TO_REGCLASS:{ *:[f16] } (PINSRWrr:{ *:[f128] } (IMPLICIT_DEF:{ *:[v8i16] }), (INSERT_SUBREG:{ *:[i32] } (IMPLICIT_DEF:{ *:[i32] }), GR16:{ *:[i16] }:$src, sub_16bit:{ *:[i32] }), 0:{ *:[i8] }), FR16:{ *:[i32] }) 9667 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, 9668 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16, 9669 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32, 9670 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32, 9671 GIR_BuildMI, /*InsnID*/4, /*Opcode*/TargetOpcode::IMPLICIT_DEF, 9672 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define, 9673 GIR_ConstrainSelectedInstOperands, /*InsnID*/4, 9674 GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::INSERT_SUBREG, 9675 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, 9676 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/3, /*TempRegFlags*/0, 9677 GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // src 9678 GIR_AddImm, /*InsnID*/3, /*Imm*/4, 9679 GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, X86::LOW32_ADDR_ACCESS_RBPRegClassID, 9680 GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, X86::LOW32_ADDR_ACCESS_RBPRegClassID, 9681 GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, X86::GR16RegClassID, 9682 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, 9683 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 9684 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 9685 GIR_BuildMI, /*InsnID*/1, /*Opcode*/X86::PINSRWrr, 9686 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 9687 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, 9688 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/2, /*TempRegFlags*/0, 9689 GIR_AddImm, /*InsnID*/1, /*Imm*/0, 9690 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 9691 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 9692 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 9693 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 9694 GIR_EraseFromParent, /*InsnID*/0, 9695 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, X86::FR16RegClassID, 9696 // GIR_Coverage, 16785, 9697 GIR_Done, 9698 // Label 698: @21783 9699 GIM_Try, /*On fail goto*//*Label 699*/ 21853, // Rule ID 20260 // 9700 GIM_CheckFeatures, GIFBS_HasBWI, 9701 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16, 9702 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID, 9703 // (bitconvert:{ *:[i16] } f16:{ *:[f16] }:$src) => (EXTRACT_SUBREG:{ *:[i16] } (VPEXTRWZrr:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[v8i16] } FR16X:{ *:[f16] }:$src, VR128X:{ *:[i32] }), 0:{ *:[i8] }), sub_16bit:{ *:[i32] }) 9704 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, 9705 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16, 9706 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY, 9707 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 9708 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src 9709 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 9710 GIR_BuildMI, /*InsnID*/1, /*Opcode*/X86::VPEXTRWZrr, 9711 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 9712 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, 9713 GIR_AddImm, /*InsnID*/1, /*Imm*/0, 9714 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 9715 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 9716 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 9717 GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, X86::sub_16bit, 9718 GIR_EraseFromParent, /*InsnID*/0, 9719 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, X86::GR16RegClassID, 9720 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, X86::GR32RegClassID, 9721 // GIR_Coverage, 20260, 9722 GIR_Done, 9723 // Label 699: @21853 9724 GIM_Try, /*On fail goto*//*Label 700*/ 21963, // Rule ID 20261 // 9725 GIM_CheckFeatures, GIFBS_HasBWI, 9726 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16, 9727 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::FR16XRegClassID, 9728 // (bitconvert:{ *:[f16] } i16:{ *:[i16] }:$src) => (COPY_TO_REGCLASS:{ *:[f16] } (VPINSRWZrr:{ *:[f128] } (IMPLICIT_DEF:{ *:[v8i16] }), (INSERT_SUBREG:{ *:[i32] } (IMPLICIT_DEF:{ *:[i32] }), GR16:{ *:[i16] }:$src, sub_16bit:{ *:[i32] }), 0:{ *:[i8] }), FR16X:{ *:[i32] }) 9729 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, 9730 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16, 9731 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32, 9732 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32, 9733 GIR_BuildMI, /*InsnID*/4, /*Opcode*/TargetOpcode::IMPLICIT_DEF, 9734 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define, 9735 GIR_ConstrainSelectedInstOperands, /*InsnID*/4, 9736 GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::INSERT_SUBREG, 9737 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, 9738 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/3, /*TempRegFlags*/0, 9739 GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // src 9740 GIR_AddImm, /*InsnID*/3, /*Imm*/4, 9741 GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, X86::LOW32_ADDR_ACCESS_RBPRegClassID, 9742 GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, X86::LOW32_ADDR_ACCESS_RBPRegClassID, 9743 GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, X86::GR16RegClassID, 9744 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, 9745 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 9746 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 9747 GIR_BuildMI, /*InsnID*/1, /*Opcode*/X86::VPINSRWZrr, 9748 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 9749 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, 9750 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/2, /*TempRegFlags*/0, 9751 GIR_AddImm, /*InsnID*/1, /*Imm*/0, 9752 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 9753 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 9754 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 9755 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 9756 GIR_EraseFromParent, /*InsnID*/0, 9757 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, X86::FR16XRegClassID, 9758 // GIR_Coverage, 20261, 9759 GIR_Done, 9760 // Label 700: @21963 9761 GIM_Reject, 9762 // Label 684: @21964 9763 GIM_Try, /*On fail goto*//*Label 701*/ 21987, // Rule ID 2607 // 9764 GIM_CheckFeatures, GIFBS_UseAVX, 9765 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 9766 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::FR32RegClassID, 9767 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR32RegClassID, 9768 // (bitconvert:{ *:[f32] } GR32:{ *:[i32] }:$src) => (VMOVDI2SSrr:{ *:[f32] } GR32:{ *:[i32] }:$src) 9769 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VMOVDI2SSrr, 9770 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9771 // GIR_Coverage, 2607, 9772 GIR_Done, 9773 // Label 701: @21987 9774 GIM_Try, /*On fail goto*//*Label 702*/ 22010, // Rule ID 2608 // 9775 GIM_CheckFeatures, GIFBS_UseSSE2, 9776 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 9777 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::FR32RegClassID, 9778 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR32RegClassID, 9779 // (bitconvert:{ *:[f32] } GR32:{ *:[i32] }:$src) => (MOVDI2SSrr:{ *:[f32] } GR32:{ *:[i32] }:$src) 9780 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::MOVDI2SSrr, 9781 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9782 // GIR_Coverage, 2608, 9783 GIR_Done, 9784 // Label 702: @22010 9785 GIM_Try, /*On fail goto*//*Label 703*/ 22033, // Rule ID 2617 // 9786 GIM_CheckFeatures, GIFBS_UseAVX, 9787 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 9788 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID, 9789 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::FR32RegClassID, 9790 // (bitconvert:{ *:[i32] } FR32:{ *:[f32] }:$src) => (VMOVSS2DIrr:{ *:[i32] } FR32:{ *:[f32] }:$src) 9791 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VMOVSS2DIrr, 9792 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9793 // GIR_Coverage, 2617, 9794 GIR_Done, 9795 // Label 703: @22033 9796 GIM_Try, /*On fail goto*//*Label 704*/ 22056, // Rule ID 2618 // 9797 GIM_CheckFeatures, GIFBS_UseSSE2, 9798 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 9799 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID, 9800 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::FR32RegClassID, 9801 // (bitconvert:{ *:[i32] } FR32:{ *:[f32] }:$src) => (MOVSS2DIrr:{ *:[i32] } FR32:{ *:[f32] }:$src) 9802 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::MOVSS2DIrr, 9803 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9804 // GIR_Coverage, 2618, 9805 GIR_Done, 9806 // Label 704: @22056 9807 GIM_Try, /*On fail goto*//*Label 705*/ 22079, // Rule ID 4237 // 9808 GIM_CheckFeatures, GIFBS_HasAVX512, 9809 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 9810 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::FR32XRegClassID, 9811 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR32RegClassID, 9812 // (bitconvert:{ *:[f32] } GR32:{ *:[i32] }:$src) => (VMOVDI2SSZrr:{ *:[f32] } GR32:{ *:[i32] }:$src) 9813 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VMOVDI2SSZrr, 9814 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9815 // GIR_Coverage, 4237, 9816 GIR_Done, 9817 // Label 705: @22079 9818 GIM_Try, /*On fail goto*//*Label 706*/ 22102, // Rule ID 4242 // 9819 GIM_CheckFeatures, GIFBS_HasAVX512, 9820 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 9821 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID, 9822 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::FR32XRegClassID, 9823 // (bitconvert:{ *:[i32] } FR32X:{ *:[f32] }:$src) => (VMOVSS2DIZrr:{ *:[i32] } FR32X:{ *:[f32] }:$src) 9824 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VMOVSS2DIZrr, 9825 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9826 // GIR_Coverage, 4242, 9827 GIR_Done, 9828 // Label 706: @22102 9829 GIM_Try, /*On fail goto*//*Label 707*/ 22125, // Rule ID 17881 // 9830 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v32s1, 9831 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID, 9832 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VK32RegClassID, 9833 // (bitconvert:{ *:[i32] } VK32:{ *:[v32i1] }:$src) => (COPY_TO_REGCLASS:{ *:[i32] } VK32:{ *:[v32i1] }:$src, GR32:{ *:[i32] }) 9834 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, 9835 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, X86::GR32RegClassID, 9836 // GIR_Coverage, 17881, 9837 GIR_Done, 9838 // Label 707: @22125 9839 GIM_Try, /*On fail goto*//*Label 708*/ 22171, // Rule ID 18361 // 9840 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v32s1, 9841 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::FR32XRegClassID, 9842 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VK32RegClassID, 9843 // (bitconvert:{ *:[f32] } VK32:{ *:[v32i1] }:$src) => (VMOVDI2SSZrr:{ *:[f32] } (KMOVDrk:{ *:[i32] } VK32:{ *:[v32i1] }:$src)) 9844 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, 9845 GIR_BuildMI, /*InsnID*/1, /*Opcode*/X86::KMOVDrk, 9846 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 9847 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src 9848 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 9849 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VMOVDI2SSZrr, 9850 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 9851 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 9852 GIR_EraseFromParent, /*InsnID*/0, 9853 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9854 // GIR_Coverage, 18361, 9855 GIR_Done, 9856 // Label 708: @22171 9857 GIM_Reject, 9858 // Label 685: @22172 9859 GIM_Try, /*On fail goto*//*Label 709*/ 22195, // Rule ID 2602 // 9860 GIM_CheckFeatures, GIFBS_UseAVX, 9861 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 9862 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::FR64RegClassID, 9863 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR64RegClassID, 9864 // (bitconvert:{ *:[f64] } GR64:{ *:[i64] }:$src) => (VMOV64toSDrr:{ *:[f64] } GR64:{ *:[i64] }:$src) 9865 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VMOV64toSDrr, 9866 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9867 // GIR_Coverage, 2602, 9868 GIR_Done, 9869 // Label 709: @22195 9870 GIM_Try, /*On fail goto*//*Label 710*/ 22218, // Rule ID 2606 // 9871 GIM_CheckFeatures, GIFBS_UseSSE2, 9872 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 9873 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::FR64RegClassID, 9874 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR64RegClassID, 9875 // (bitconvert:{ *:[f64] } GR64:{ *:[i64] }:$src) => (MOV64toSDrr:{ *:[f64] } GR64:{ *:[i64] }:$src) 9876 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::MOV64toSDrr, 9877 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9878 // GIR_Coverage, 2606, 9879 GIR_Done, 9880 // Label 710: @22218 9881 GIM_Try, /*On fail goto*//*Label 711*/ 22241, // Rule ID 2615 // 9882 GIM_CheckFeatures, GIFBS_UseAVX, 9883 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 9884 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID, 9885 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::FR64RegClassID, 9886 // (bitconvert:{ *:[i64] } FR64:{ *:[f64] }:$src) => (VMOVSDto64rr:{ *:[i64] } FR64:{ *:[f64] }:$src) 9887 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VMOVSDto64rr, 9888 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9889 // GIR_Coverage, 2615, 9890 GIR_Done, 9891 // Label 711: @22241 9892 GIM_Try, /*On fail goto*//*Label 712*/ 22264, // Rule ID 2616 // 9893 GIM_CheckFeatures, GIFBS_UseSSE2, 9894 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 9895 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID, 9896 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::FR64RegClassID, 9897 // (bitconvert:{ *:[i64] } FR64:{ *:[f64] }:$src) => (MOVSDto64rr:{ *:[i64] } FR64:{ *:[f64] }:$src) 9898 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::MOVSDto64rr, 9899 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9900 // GIR_Coverage, 2616, 9901 GIR_Done, 9902 // Label 712: @22264 9903 GIM_Try, /*On fail goto*//*Label 713*/ 22287, // Rule ID 4235 // 9904 GIM_CheckFeatures, GIFBS_HasAVX512, 9905 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 9906 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::FR64XRegClassID, 9907 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR64RegClassID, 9908 // (bitconvert:{ *:[f64] } GR64:{ *:[i64] }:$src) => (VMOV64toSDZrr:{ *:[f64] } GR64:{ *:[i64] }:$src) 9909 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VMOV64toSDZrr, 9910 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9911 // GIR_Coverage, 4235, 9912 GIR_Done, 9913 // Label 713: @22287 9914 GIM_Try, /*On fail goto*//*Label 714*/ 22310, // Rule ID 4236 // 9915 GIM_CheckFeatures, GIFBS_HasAVX512, 9916 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 9917 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID, 9918 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::FR64XRegClassID, 9919 // (bitconvert:{ *:[i64] } FR64X:{ *:[f64] }:$src) => (VMOVSDto64Zrr:{ *:[i64] } FR64X:{ *:[f64] }:$src) 9920 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VMOVSDto64Zrr, 9921 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9922 // GIR_Coverage, 4236, 9923 GIR_Done, 9924 // Label 714: @22310 9925 GIM_Try, /*On fail goto*//*Label 715*/ 22333, // Rule ID 17883 // 9926 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v64s1, 9927 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID, 9928 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VK64RegClassID, 9929 // (bitconvert:{ *:[i64] } VK64:{ *:[v64i1] }:$src) => (COPY_TO_REGCLASS:{ *:[i64] } VK64:{ *:[v64i1] }:$src, GR64:{ *:[i32] }) 9930 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, 9931 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, X86::GR64RegClassID, 9932 // GIR_Coverage, 17883, 9933 GIR_Done, 9934 // Label 715: @22333 9935 GIM_Try, /*On fail goto*//*Label 716*/ 22379, // Rule ID 18363 // 9936 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v64s1, 9937 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::FR64XRegClassID, 9938 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VK64RegClassID, 9939 // (bitconvert:{ *:[f64] } VK64:{ *:[v64i1] }:$src) => (VMOV64toSDZrr:{ *:[f64] } (KMOVQrk:{ *:[i64] } VK64:{ *:[v64i1] }:$src)) 9940 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, 9941 GIR_BuildMI, /*InsnID*/1, /*Opcode*/X86::KMOVQrk, 9942 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 9943 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src 9944 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 9945 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VMOV64toSDZrr, 9946 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 9947 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 9948 GIR_EraseFromParent, /*InsnID*/0, 9949 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9950 // GIR_Coverage, 18363, 9951 GIR_Done, 9952 // Label 716: @22379 9953 GIM_Reject, 9954 // Label 686: @22380 9955 GIM_Try, /*On fail goto*//*Label 717*/ 22457, // Rule ID 17872 // 9956 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s8, 9957 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VK8RegClassID, 9958 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR8RegClassID, 9959 // (bitconvert:{ *:[v8i1] } GR8:{ *:[i8] }:$src) => (COPY_TO_REGCLASS:{ *:[v8i1] } (INSERT_SUBREG:{ *:[i32] } (IMPLICIT_DEF:{ *:[i32] }), GR8:{ *:[i8] }:$src, sub_8bit:{ *:[i32] }), VK8:{ *:[i32] }) 9960 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, 9961 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, 9962 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, 9963 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 9964 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 9965 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, 9966 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 9967 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, 9968 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src 9969 GIR_AddImm, /*InsnID*/1, /*Imm*/1, 9970 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID, 9971 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID, 9972 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, X86::GR8RegClassID, 9973 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 9974 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 9975 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 9976 GIR_EraseFromParent, /*InsnID*/0, 9977 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, X86::VK8RegClassID, 9978 // GIR_Coverage, 17872, 9979 GIR_Done, 9980 // Label 717: @22457 9981 GIM_Reject, 9982 // Label 687: @22458 9983 GIM_Try, /*On fail goto*//*Label 718*/ 22535, // Rule ID 17869 // 9984 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16, 9985 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VK16RegClassID, 9986 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR16RegClassID, 9987 // (bitconvert:{ *:[v16i1] } GR16:{ *:[i16] }:$src) => (COPY_TO_REGCLASS:{ *:[v16i1] } (INSERT_SUBREG:{ *:[i32] } (IMPLICIT_DEF:{ *:[i32] }), GR16:{ *:[i16] }:$src, sub_16bit:{ *:[i32] }), VK16:{ *:[i32] }) 9988 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, 9989 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, 9990 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, 9991 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 9992 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 9993 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, 9994 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 9995 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, 9996 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src 9997 GIR_AddImm, /*InsnID*/1, /*Imm*/4, 9998 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, X86::LOW32_ADDR_ACCESS_RBPRegClassID, 9999 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, X86::LOW32_ADDR_ACCESS_RBPRegClassID, 10000 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, X86::GR16RegClassID, 10001 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 10002 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 10003 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 10004 GIR_EraseFromParent, /*InsnID*/0, 10005 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, X86::VK16RegClassID, 10006 // GIR_Coverage, 17869, 10007 GIR_Done, 10008 // Label 718: @22535 10009 GIM_Reject, 10010 // Label 688: @22536 10011 GIM_Try, /*On fail goto*//*Label 719*/ 22600, 10012 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 10013 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VK32RegClassID, 10014 GIM_Try, /*On fail goto*//*Label 720*/ 22561, // Rule ID 17880 // 10015 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR32RegClassID, 10016 // (bitconvert:{ *:[v32i1] } GR32:{ *:[i32] }:$src) => (COPY_TO_REGCLASS:{ *:[v32i1] } GR32:{ *:[i32] }:$src, VK32:{ *:[i32] }) 10017 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, 10018 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, X86::VK32RegClassID, 10019 // GIR_Coverage, 17880, 10020 GIR_Done, 10021 // Label 720: @22561 10022 GIM_Try, /*On fail goto*//*Label 721*/ 22599, // Rule ID 18360 // 10023 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::FR32XRegClassID, 10024 // (bitconvert:{ *:[v32i1] } FR32X:{ *:[f32] }:$src) => (KMOVDkr:{ *:[v32i1] } (VMOVSS2DIZrr:{ *:[i32] } FR32X:{ *:[f32] }:$src)) 10025 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, 10026 GIR_BuildMI, /*InsnID*/1, /*Opcode*/X86::VMOVSS2DIZrr, 10027 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 10028 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src 10029 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 10030 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::KMOVDkr, 10031 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 10032 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 10033 GIR_EraseFromParent, /*InsnID*/0, 10034 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10035 // GIR_Coverage, 18360, 10036 GIR_Done, 10037 // Label 721: @22599 10038 GIM_Reject, 10039 // Label 719: @22600 10040 GIM_Reject, 10041 // Label 689: @22601 10042 GIM_Try, /*On fail goto*//*Label 722*/ 22665, 10043 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 10044 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VK64RegClassID, 10045 GIM_Try, /*On fail goto*//*Label 723*/ 22626, // Rule ID 17882 // 10046 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR64RegClassID, 10047 // (bitconvert:{ *:[v64i1] } GR64:{ *:[i64] }:$src) => (COPY_TO_REGCLASS:{ *:[v64i1] } GR64:{ *:[i64] }:$src, VK64:{ *:[i32] }) 10048 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, 10049 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, X86::VK64RegClassID, 10050 // GIR_Coverage, 17882, 10051 GIR_Done, 10052 // Label 723: @22626 10053 GIM_Try, /*On fail goto*//*Label 724*/ 22664, // Rule ID 18362 // 10054 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::FR64XRegClassID, 10055 // (bitconvert:{ *:[v64i1] } FR64X:{ *:[f64] }:$src) => (KMOVQkr:{ *:[v64i1] } (VMOVSDto64Zrr:{ *:[i64] } FR64X:{ *:[f64] }:$src)) 10056 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, 10057 GIR_BuildMI, /*InsnID*/1, /*Opcode*/X86::VMOVSDto64Zrr, 10058 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 10059 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src 10060 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 10061 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::KMOVQkr, 10062 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 10063 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 10064 GIR_EraseFromParent, /*InsnID*/0, 10065 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10066 // GIR_Coverage, 18362, 10067 GIR_Done, 10068 // Label 724: @22664 10069 GIM_Reject, 10070 // Label 722: @22665 10071 GIM_Reject, 10072 // Label 690: @22666 10073 GIM_Reject, 10074 // Label 8: @22667 10075 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/3, 5, /*)*//*default:*//*Label 727*/ 22989, 10076 /*GILLT_s32*//*Label 725*/ 22675, 10077 /*GILLT_s64*//*Label 726*/ 22832, 10078 // Label 725: @22675 10079 GIM_Try, /*On fail goto*//*Label 728*/ 22701, // Rule ID 1487 // 10080 GIM_CheckFeatures, GIFBS_UseAVX, 10081 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 10082 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID, 10083 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::FR32RegClassID, 10084 // (lrint:{ *:[i32] } FR32:{ *:[f32] }:$src) => (VCVTSS2SIrr:{ *:[i32] } FR32:{ *:[f32] }:$src) 10085 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VCVTSS2SIrr, 10086 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 10087 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10088 // GIR_Coverage, 1487, 10089 GIR_Done, 10090 // Label 728: @22701 10091 GIM_Try, /*On fail goto*//*Label 729*/ 22727, // Rule ID 1491 // 10092 GIM_CheckFeatures, GIFBS_UseAVX, 10093 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 10094 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID, 10095 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::FR64RegClassID, 10096 // (lrint:{ *:[i32] } FR64:{ *:[f64] }:$src) => (VCVTSD2SIrr:{ *:[i32] } FR64:{ *:[f64] }:$src) 10097 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VCVTSD2SIrr, 10098 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 10099 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10100 // GIR_Coverage, 1491, 10101 GIR_Done, 10102 // Label 729: @22727 10103 GIM_Try, /*On fail goto*//*Label 730*/ 22753, // Rule ID 1511 // 10104 GIM_CheckFeatures, GIFBS_UseSSE1, 10105 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 10106 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID, 10107 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::FR32RegClassID, 10108 // (lrint:{ *:[i32] } FR32:{ *:[f32] }:$src) => (CVTSS2SIrr:{ *:[i32] } FR32:{ *:[f32] }:$src) 10109 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::CVTSS2SIrr, 10110 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 10111 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10112 // GIR_Coverage, 1511, 10113 GIR_Done, 10114 // Label 730: @22753 10115 GIM_Try, /*On fail goto*//*Label 731*/ 22779, // Rule ID 1515 // 10116 GIM_CheckFeatures, GIFBS_UseSSE2, 10117 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 10118 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID, 10119 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::FR64RegClassID, 10120 // (lrint:{ *:[i32] } FR64:{ *:[f64] }:$src) => (CVTSD2SIrr:{ *:[i32] } FR64:{ *:[f64] }:$src) 10121 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::CVTSD2SIrr, 10122 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 10123 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10124 // GIR_Coverage, 1515, 10125 GIR_Done, 10126 // Label 731: @22779 10127 GIM_Try, /*On fail goto*//*Label 732*/ 22805, // Rule ID 9925 // 10128 GIM_CheckFeatures, GIFBS_HasAVX512, 10129 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 10130 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID, 10131 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::FR32XRegClassID, 10132 // (lrint:{ *:[i32] } FR32X:{ *:[f32] }:$src) => (VCVTSS2SIZrr:{ *:[i32] } FR32X:{ *:[f32] }:$src) 10133 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VCVTSS2SIZrr, 10134 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 10135 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10136 // GIR_Coverage, 9925, 10137 GIR_Done, 10138 // Label 732: @22805 10139 GIM_Try, /*On fail goto*//*Label 733*/ 22831, // Rule ID 9929 // 10140 GIM_CheckFeatures, GIFBS_HasAVX512, 10141 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 10142 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID, 10143 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::FR64XRegClassID, 10144 // (lrint:{ *:[i32] } FR64X:{ *:[f64] }:$src) => (VCVTSD2SIZrr:{ *:[i32] } FR64X:{ *:[f64] }:$src) 10145 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VCVTSD2SIZrr, 10146 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 10147 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10148 // GIR_Coverage, 9929, 10149 GIR_Done, 10150 // Label 733: @22831 10151 GIM_Reject, 10152 // Label 726: @22832 10153 GIM_Try, /*On fail goto*//*Label 734*/ 22858, // Rule ID 16444 // 10154 GIM_CheckFeatures, GIFBS_UseAVX, 10155 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 10156 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID, 10157 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::FR32RegClassID, 10158 // (lrint:{ *:[i64] } FR32:{ *:[f32] }:$src) => (VCVTSS2SI64rr:{ *:[i64] } FR32:{ *:[f32] }:$src) 10159 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VCVTSS2SI64rr, 10160 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 10161 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10162 // GIR_Coverage, 16444, 10163 GIR_Done, 10164 // Label 734: @22858 10165 GIM_Try, /*On fail goto*//*Label 735*/ 22884, // Rule ID 16446 // 10166 GIM_CheckFeatures, GIFBS_UseAVX, 10167 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 10168 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID, 10169 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::FR64RegClassID, 10170 // (lrint:{ *:[i64] } FR64:{ *:[f64] }:$src) => (VCVTSD2SI64rr:{ *:[i64] } FR64:{ *:[f64] }:$src) 10171 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VCVTSD2SI64rr, 10172 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 10173 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10174 // GIR_Coverage, 16446, 10175 GIR_Done, 10176 // Label 735: @22884 10177 GIM_Try, /*On fail goto*//*Label 736*/ 22910, // Rule ID 16448 // 10178 GIM_CheckFeatures, GIFBS_UseSSE1, 10179 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 10180 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID, 10181 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::FR32RegClassID, 10182 // (lrint:{ *:[i64] } FR32:{ *:[f32] }:$src) => (CVTSS2SI64rr:{ *:[i64] } FR32:{ *:[f32] }:$src) 10183 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::CVTSS2SI64rr, 10184 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 10185 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10186 // GIR_Coverage, 16448, 10187 GIR_Done, 10188 // Label 736: @22910 10189 GIM_Try, /*On fail goto*//*Label 737*/ 22936, // Rule ID 16450 // 10190 GIM_CheckFeatures, GIFBS_UseSSE2, 10191 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 10192 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID, 10193 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::FR64RegClassID, 10194 // (lrint:{ *:[i64] } FR64:{ *:[f64] }:$src) => (CVTSD2SI64rr:{ *:[i64] } FR64:{ *:[f64] }:$src) 10195 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::CVTSD2SI64rr, 10196 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 10197 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10198 // GIR_Coverage, 16450, 10199 GIR_Done, 10200 // Label 737: @22936 10201 GIM_Try, /*On fail goto*//*Label 738*/ 22962, // Rule ID 19644 // 10202 GIM_CheckFeatures, GIFBS_HasAVX512, 10203 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 10204 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID, 10205 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::FR32RegClassID, 10206 // (lrint:{ *:[i64] } FR32:{ *:[f32] }:$src) => (VCVTSS2SI64Zrr:{ *:[i64] } FR32:{ *:[f32] }:$src) 10207 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VCVTSS2SI64Zrr, 10208 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 10209 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10210 // GIR_Coverage, 19644, 10211 GIR_Done, 10212 // Label 738: @22962 10213 GIM_Try, /*On fail goto*//*Label 739*/ 22988, // Rule ID 19646 // 10214 GIM_CheckFeatures, GIFBS_HasAVX512, 10215 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 10216 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID, 10217 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::FR64RegClassID, 10218 // (lrint:{ *:[i64] } FR64:{ *:[f64] }:$src) => (VCVTSD2SI64Zrr:{ *:[i64] } FR64:{ *:[f64] }:$src) 10219 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VCVTSD2SI64Zrr, 10220 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 10221 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10222 // GIR_Coverage, 19646, 10223 GIR_Done, 10224 // Label 739: @22988 10225 GIM_Reject, 10226 // Label 727: @22989 10227 GIM_Reject, 10228 // Label 9: @22990 10229 GIM_Try, /*On fail goto*//*Label 740*/ 24252, 10230 GIM_CheckNumOperands, /*MI*/0, /*Expected*/3, 10231 GIM_Try, /*On fail goto*//*Label 741*/ 23035, // Rule ID 1261 // 10232 GIM_CheckFeatures, GIFBS_HasXOP, 10233 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_xop_vphsubwd, 10234 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 10235 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 10236 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 10237 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 10238 // (intrinsic_wo_chain:{ *:[v4i32] } 11287:{ *:[iPTR] }, VR128:{ *:[v8i16] }:$src) => (VPHSUBWDrr:{ *:[v4i32] } VR128:{ *:[v8i16] }:$src) 10239 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VPHSUBWDrr, 10240 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 10241 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src 10242 GIR_EraseFromParent, /*InsnID*/0, 10243 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10244 // GIR_Coverage, 1261, 10245 GIR_Done, 10246 // Label 741: @23035 10247 GIM_Try, /*On fail goto*//*Label 742*/ 23075, // Rule ID 1263 // 10248 GIM_CheckFeatures, GIFBS_HasXOP, 10249 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_xop_vphsubdq, 10250 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 10251 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 10252 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 10253 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 10254 // (intrinsic_wo_chain:{ *:[v2i64] } 11286:{ *:[iPTR] }, VR128:{ *:[v4i32] }:$src) => (VPHSUBDQrr:{ *:[v2i64] } VR128:{ *:[v4i32] }:$src) 10255 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VPHSUBDQrr, 10256 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 10257 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src 10258 GIR_EraseFromParent, /*InsnID*/0, 10259 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10260 // GIR_Coverage, 1263, 10261 GIR_Done, 10262 // Label 742: @23075 10263 GIM_Try, /*On fail goto*//*Label 743*/ 23115, // Rule ID 1265 // 10264 GIM_CheckFeatures, GIFBS_HasXOP, 10265 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_xop_vphsubbw, 10266 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, 10267 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, 10268 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 10269 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 10270 // (intrinsic_wo_chain:{ *:[v8i16] } 11285:{ *:[iPTR] }, VR128:{ *:[v16i8] }:$src) => (VPHSUBBWrr:{ *:[v8i16] } VR128:{ *:[v16i8] }:$src) 10271 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VPHSUBBWrr, 10272 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 10273 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src 10274 GIR_EraseFromParent, /*InsnID*/0, 10275 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10276 // GIR_Coverage, 1265, 10277 GIR_Done, 10278 // Label 743: @23115 10279 GIM_Try, /*On fail goto*//*Label 744*/ 23155, // Rule ID 1267 // 10280 GIM_CheckFeatures, GIFBS_HasXOP, 10281 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_xop_vphaddwq, 10282 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 10283 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 10284 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 10285 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 10286 // (intrinsic_wo_chain:{ *:[v2i64] } 11284:{ *:[iPTR] }, VR128:{ *:[v8i16] }:$src) => (VPHADDWQrr:{ *:[v2i64] } VR128:{ *:[v8i16] }:$src) 10287 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VPHADDWQrr, 10288 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 10289 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src 10290 GIR_EraseFromParent, /*InsnID*/0, 10291 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10292 // GIR_Coverage, 1267, 10293 GIR_Done, 10294 // Label 744: @23155 10295 GIM_Try, /*On fail goto*//*Label 745*/ 23195, // Rule ID 1269 // 10296 GIM_CheckFeatures, GIFBS_HasXOP, 10297 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_xop_vphaddwd, 10298 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 10299 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 10300 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 10301 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 10302 // (intrinsic_wo_chain:{ *:[v4i32] } 11283:{ *:[iPTR] }, VR128:{ *:[v8i16] }:$src) => (VPHADDWDrr:{ *:[v4i32] } VR128:{ *:[v8i16] }:$src) 10303 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VPHADDWDrr, 10304 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 10305 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src 10306 GIR_EraseFromParent, /*InsnID*/0, 10307 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10308 // GIR_Coverage, 1269, 10309 GIR_Done, 10310 // Label 745: @23195 10311 GIM_Try, /*On fail goto*//*Label 746*/ 23235, // Rule ID 1271 // 10312 GIM_CheckFeatures, GIFBS_HasXOP, 10313 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_xop_vphadduwq, 10314 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 10315 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 10316 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 10317 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 10318 // (intrinsic_wo_chain:{ *:[v2i64] } 11282:{ *:[iPTR] }, VR128:{ *:[v8i16] }:$src) => (VPHADDUWQrr:{ *:[v2i64] } VR128:{ *:[v8i16] }:$src) 10319 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VPHADDUWQrr, 10320 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 10321 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src 10322 GIR_EraseFromParent, /*InsnID*/0, 10323 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10324 // GIR_Coverage, 1271, 10325 GIR_Done, 10326 // Label 746: @23235 10327 GIM_Try, /*On fail goto*//*Label 747*/ 23275, // Rule ID 1273 // 10328 GIM_CheckFeatures, GIFBS_HasXOP, 10329 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_xop_vphadduwd, 10330 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 10331 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 10332 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 10333 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 10334 // (intrinsic_wo_chain:{ *:[v4i32] } 11281:{ *:[iPTR] }, VR128:{ *:[v8i16] }:$src) => (VPHADDUWDrr:{ *:[v4i32] } VR128:{ *:[v8i16] }:$src) 10335 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VPHADDUWDrr, 10336 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 10337 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src 10338 GIR_EraseFromParent, /*InsnID*/0, 10339 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10340 // GIR_Coverage, 1273, 10341 GIR_Done, 10342 // Label 747: @23275 10343 GIM_Try, /*On fail goto*//*Label 748*/ 23315, // Rule ID 1275 // 10344 GIM_CheckFeatures, GIFBS_HasXOP, 10345 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_xop_vphaddudq, 10346 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 10347 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 10348 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 10349 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 10350 // (intrinsic_wo_chain:{ *:[v2i64] } 11280:{ *:[iPTR] }, VR128:{ *:[v4i32] }:$src) => (VPHADDUDQrr:{ *:[v2i64] } VR128:{ *:[v4i32] }:$src) 10351 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VPHADDUDQrr, 10352 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 10353 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src 10354 GIR_EraseFromParent, /*InsnID*/0, 10355 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10356 // GIR_Coverage, 1275, 10357 GIR_Done, 10358 // Label 748: @23315 10359 GIM_Try, /*On fail goto*//*Label 749*/ 23355, // Rule ID 1277 // 10360 GIM_CheckFeatures, GIFBS_HasXOP, 10361 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_xop_vphaddubw, 10362 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, 10363 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, 10364 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 10365 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 10366 // (intrinsic_wo_chain:{ *:[v8i16] } 11279:{ *:[iPTR] }, VR128:{ *:[v16i8] }:$src) => (VPHADDUBWrr:{ *:[v8i16] } VR128:{ *:[v16i8] }:$src) 10367 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VPHADDUBWrr, 10368 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 10369 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src 10370 GIR_EraseFromParent, /*InsnID*/0, 10371 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10372 // GIR_Coverage, 1277, 10373 GIR_Done, 10374 // Label 749: @23355 10375 GIM_Try, /*On fail goto*//*Label 750*/ 23395, // Rule ID 1279 // 10376 GIM_CheckFeatures, GIFBS_HasXOP, 10377 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_xop_vphaddubq, 10378 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 10379 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, 10380 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 10381 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 10382 // (intrinsic_wo_chain:{ *:[v2i64] } 11278:{ *:[iPTR] }, VR128:{ *:[v16i8] }:$src) => (VPHADDUBQrr:{ *:[v2i64] } VR128:{ *:[v16i8] }:$src) 10383 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VPHADDUBQrr, 10384 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 10385 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src 10386 GIR_EraseFromParent, /*InsnID*/0, 10387 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10388 // GIR_Coverage, 1279, 10389 GIR_Done, 10390 // Label 750: @23395 10391 GIM_Try, /*On fail goto*//*Label 751*/ 23435, // Rule ID 1281 // 10392 GIM_CheckFeatures, GIFBS_HasXOP, 10393 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_xop_vphaddubd, 10394 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 10395 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, 10396 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 10397 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 10398 // (intrinsic_wo_chain:{ *:[v4i32] } 11277:{ *:[iPTR] }, VR128:{ *:[v16i8] }:$src) => (VPHADDUBDrr:{ *:[v4i32] } VR128:{ *:[v16i8] }:$src) 10399 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VPHADDUBDrr, 10400 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 10401 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src 10402 GIR_EraseFromParent, /*InsnID*/0, 10403 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10404 // GIR_Coverage, 1281, 10405 GIR_Done, 10406 // Label 751: @23435 10407 GIM_Try, /*On fail goto*//*Label 752*/ 23475, // Rule ID 1283 // 10408 GIM_CheckFeatures, GIFBS_HasXOP, 10409 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_xop_vphadddq, 10410 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 10411 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 10412 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 10413 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 10414 // (intrinsic_wo_chain:{ *:[v2i64] } 11276:{ *:[iPTR] }, VR128:{ *:[v4i32] }:$src) => (VPHADDDQrr:{ *:[v2i64] } VR128:{ *:[v4i32] }:$src) 10415 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VPHADDDQrr, 10416 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 10417 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src 10418 GIR_EraseFromParent, /*InsnID*/0, 10419 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10420 // GIR_Coverage, 1283, 10421 GIR_Done, 10422 // Label 752: @23475 10423 GIM_Try, /*On fail goto*//*Label 753*/ 23515, // Rule ID 1285 // 10424 GIM_CheckFeatures, GIFBS_HasXOP, 10425 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_xop_vphaddbw, 10426 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, 10427 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, 10428 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 10429 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 10430 // (intrinsic_wo_chain:{ *:[v8i16] } 11275:{ *:[iPTR] }, VR128:{ *:[v16i8] }:$src) => (VPHADDBWrr:{ *:[v8i16] } VR128:{ *:[v16i8] }:$src) 10431 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VPHADDBWrr, 10432 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 10433 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src 10434 GIR_EraseFromParent, /*InsnID*/0, 10435 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10436 // GIR_Coverage, 1285, 10437 GIR_Done, 10438 // Label 753: @23515 10439 GIM_Try, /*On fail goto*//*Label 754*/ 23555, // Rule ID 1287 // 10440 GIM_CheckFeatures, GIFBS_HasXOP, 10441 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_xop_vphaddbq, 10442 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 10443 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, 10444 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 10445 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 10446 // (intrinsic_wo_chain:{ *:[v2i64] } 11274:{ *:[iPTR] }, VR128:{ *:[v16i8] }:$src) => (VPHADDBQrr:{ *:[v2i64] } VR128:{ *:[v16i8] }:$src) 10447 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VPHADDBQrr, 10448 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 10449 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src 10450 GIR_EraseFromParent, /*InsnID*/0, 10451 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10452 // GIR_Coverage, 1287, 10453 GIR_Done, 10454 // Label 754: @23555 10455 GIM_Try, /*On fail goto*//*Label 755*/ 23595, // Rule ID 1289 // 10456 GIM_CheckFeatures, GIFBS_HasXOP, 10457 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_xop_vphaddbd, 10458 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 10459 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, 10460 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 10461 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 10462 // (intrinsic_wo_chain:{ *:[v4i32] } 11273:{ *:[iPTR] }, VR128:{ *:[v16i8] }:$src) => (VPHADDBDrr:{ *:[v4i32] } VR128:{ *:[v16i8] }:$src) 10463 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VPHADDBDrr, 10464 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 10465 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src 10466 GIR_EraseFromParent, /*InsnID*/0, 10467 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10468 // GIR_Coverage, 1289, 10469 GIR_Done, 10470 // Label 755: @23595 10471 GIM_Try, /*On fail goto*//*Label 756*/ 23635, // Rule ID 1291 // 10472 GIM_CheckFeatures, GIFBS_HasXOP, 10473 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_xop_vfrcz_ss, 10474 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 10475 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 10476 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 10477 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 10478 // (intrinsic_wo_chain:{ *:[v4f32] } 11268:{ *:[iPTR] }, VR128:{ *:[v4f32] }:$src) => (VFRCZSSrr:{ *:[v4f32] } VR128:{ *:[v4f32] }:$src) 10479 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VFRCZSSrr, 10480 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 10481 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src 10482 GIR_EraseFromParent, /*InsnID*/0, 10483 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10484 // GIR_Coverage, 1291, 10485 GIR_Done, 10486 // Label 756: @23635 10487 GIM_Try, /*On fail goto*//*Label 757*/ 23675, // Rule ID 1295 // 10488 GIM_CheckFeatures, GIFBS_HasXOP, 10489 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_xop_vfrcz_ps, 10490 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 10491 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 10492 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 10493 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 10494 // (intrinsic_wo_chain:{ *:[v4f32] } 11265:{ *:[iPTR] }, VR128:{ *:[v4f32] }:$src) => (VFRCZPSrr:{ *:[v4f32] } VR128:{ *:[v4f32] }:$src) 10495 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VFRCZPSrr, 10496 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 10497 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src 10498 GIR_EraseFromParent, /*InsnID*/0, 10499 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10500 // GIR_Coverage, 1295, 10501 GIR_Done, 10502 // Label 757: @23675 10503 GIM_Try, /*On fail goto*//*Label 758*/ 23715, // Rule ID 1297 // 10504 GIM_CheckFeatures, GIFBS_HasXOP, 10505 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_xop_vfrcz_ps_256, 10506 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s32, 10507 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s32, 10508 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID, 10509 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256RegClassID, 10510 // (intrinsic_wo_chain:{ *:[v8f32] } 11266:{ *:[iPTR] }, VR256:{ *:[v8f32] }:$src) => (VFRCZPSYrr:{ *:[v8f32] } VR256:{ *:[v8f32] }:$src) 10511 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VFRCZPSYrr, 10512 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 10513 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src 10514 GIR_EraseFromParent, /*InsnID*/0, 10515 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10516 // GIR_Coverage, 1297, 10517 GIR_Done, 10518 // Label 758: @23715 10519 GIM_Try, /*On fail goto*//*Label 759*/ 23755, // Rule ID 1299 // 10520 GIM_CheckFeatures, GIFBS_HasXOP, 10521 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_xop_vfrcz_sd, 10522 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 10523 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 10524 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 10525 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 10526 // (intrinsic_wo_chain:{ *:[v2f64] } 11267:{ *:[iPTR] }, VR128:{ *:[v2f64] }:$src) => (VFRCZSDrr:{ *:[v2f64] } VR128:{ *:[v2f64] }:$src) 10527 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VFRCZSDrr, 10528 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 10529 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src 10530 GIR_EraseFromParent, /*InsnID*/0, 10531 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10532 // GIR_Coverage, 1299, 10533 GIR_Done, 10534 // Label 759: @23755 10535 GIM_Try, /*On fail goto*//*Label 760*/ 23795, // Rule ID 1303 // 10536 GIM_CheckFeatures, GIFBS_HasXOP, 10537 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_xop_vfrcz_pd, 10538 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 10539 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 10540 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 10541 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 10542 // (intrinsic_wo_chain:{ *:[v2f64] } 11263:{ *:[iPTR] }, VR128:{ *:[v2f64] }:$src) => (VFRCZPDrr:{ *:[v2f64] } VR128:{ *:[v2f64] }:$src) 10543 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VFRCZPDrr, 10544 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 10545 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src 10546 GIR_EraseFromParent, /*InsnID*/0, 10547 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10548 // GIR_Coverage, 1303, 10549 GIR_Done, 10550 // Label 760: @23795 10551 GIM_Try, /*On fail goto*//*Label 761*/ 23835, // Rule ID 1305 // 10552 GIM_CheckFeatures, GIFBS_HasXOP, 10553 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_xop_vfrcz_pd_256, 10554 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s64, 10555 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s64, 10556 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID, 10557 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256RegClassID, 10558 // (intrinsic_wo_chain:{ *:[v4f64] } 11264:{ *:[iPTR] }, VR256:{ *:[v4f64] }:$src) => (VFRCZPDYrr:{ *:[v4f64] } VR256:{ *:[v4f64] }:$src) 10559 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VFRCZPDYrr, 10560 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 10561 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src 10562 GIR_EraseFromParent, /*InsnID*/0, 10563 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10564 // GIR_Coverage, 1305, 10565 GIR_Done, 10566 // Label 761: @23835 10567 GIM_Try, /*On fail goto*//*Label 762*/ 23875, // Rule ID 3047 // 10568 GIM_CheckFeatures, GIFBS_HasAES_HasAVX, 10569 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_aesni_aesimc, 10570 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 10571 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 10572 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 10573 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 10574 // (intrinsic_wo_chain:{ *:[v2i64] } 9957:{ *:[iPTR] }, VR128:{ *:[v2i64] }:$src1) => (VAESIMCrr:{ *:[v2i64] } VR128:{ *:[v2i64] }:$src1) 10575 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VAESIMCrr, 10576 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 10577 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 10578 GIR_EraseFromParent, /*InsnID*/0, 10579 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10580 // GIR_Coverage, 3047, 10581 GIR_Done, 10582 // Label 762: @23875 10583 GIM_Try, /*On fail goto*//*Label 763*/ 23915, // Rule ID 3049 // 10584 GIM_CheckFeatures, GIFBS_HasAES_NoAVX, 10585 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_aesni_aesimc, 10586 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 10587 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 10588 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 10589 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 10590 // (intrinsic_wo_chain:{ *:[v2i64] } 9957:{ *:[iPTR] }, VR128:{ *:[v2i64] }:$src1) => (AESIMCrr:{ *:[v2i64] } VR128:{ *:[v2i64] }:$src1) 10591 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::AESIMCrr, 10592 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 10593 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 10594 GIR_EraseFromParent, /*InsnID*/0, 10595 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10596 // GIR_Coverage, 3049, 10597 GIR_Done, 10598 // Label 763: @23915 10599 GIM_Try, /*On fail goto*//*Label 764*/ 23955, // Rule ID 3239 // 10600 GIM_CheckFeatures, GIFBS_HasAVXNECONVERT, 10601 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_vcvtneps2bf16128, 10602 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, 10603 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 10604 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 10605 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 10606 // (intrinsic_wo_chain:{ *:[v8bf16] } 11235:{ *:[iPTR] }, VR128:{ *:[v4f32] }:$src) => (VCVTNEPS2BF16rr:{ *:[v8bf16] } VR128:{ *:[v4f32] }:$src) 10607 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VCVTNEPS2BF16rr, 10608 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 10609 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src 10610 GIR_EraseFromParent, /*InsnID*/0, 10611 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10612 // GIR_Coverage, 3239, 10613 GIR_Done, 10614 // Label 764: @23955 10615 GIM_Try, /*On fail goto*//*Label 765*/ 23995, // Rule ID 3241 // 10616 GIM_CheckFeatures, GIFBS_HasAVXNECONVERT, 10617 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_vcvtneps2bf16256, 10618 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, 10619 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s32, 10620 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 10621 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256RegClassID, 10622 // (intrinsic_wo_chain:{ *:[v8bf16] } 11236:{ *:[iPTR] }, VR256:{ *:[v8f32] }:$src) => (VCVTNEPS2BF16Yrr:{ *:[v8bf16] } VR256:{ *:[v8f32] }:$src) 10623 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VCVTNEPS2BF16Yrr, 10624 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 10625 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src 10626 GIR_EraseFromParent, /*InsnID*/0, 10627 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10628 // GIR_Coverage, 3241, 10629 GIR_Done, 10630 // Label 765: @23995 10631 GIM_Try, /*On fail goto*//*Label 766*/ 24039, // Rule ID 16713 // 10632 GIM_CheckFeatures, GIFBS_UseSSE1, 10633 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_sse_rsqrt_ss, 10634 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 10635 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 10636 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 10637 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 10638 // (intrinsic_wo_chain:{ *:[v4f32] } 11049:{ *:[iPTR] }, VR128:{ *:[v4f32] }:$src) => (RSQRTSSr_Int:{ *:[v4f32] } VR128:{ *:[v4f32] }:$src, VR128:{ *:[v4f32] }:$src) 10639 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::RSQRTSSr_Int, 10640 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 10641 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src 10642 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src 10643 GIR_EraseFromParent, /*InsnID*/0, 10644 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10645 // GIR_Coverage, 16713, 10646 GIR_Done, 10647 // Label 766: @24039 10648 GIM_Try, /*On fail goto*//*Label 767*/ 24083, // Rule ID 16717 // 10649 GIM_CheckFeatures, GIFBS_HasAVX, 10650 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_sse_rsqrt_ss, 10651 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 10652 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 10653 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 10654 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 10655 // (intrinsic_wo_chain:{ *:[v4f32] } 11049:{ *:[iPTR] }, VR128:{ *:[v4f32] }:$src) => (VRSQRTSSr_Int:{ *:[v4f32] } VR128:{ *:[v4f32] }:$src, VR128:{ *:[v4f32] }:$src) 10656 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VRSQRTSSr_Int, 10657 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 10658 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src 10659 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src 10660 GIR_EraseFromParent, /*InsnID*/0, 10661 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10662 // GIR_Coverage, 16717, 10663 GIR_Done, 10664 // Label 767: @24083 10665 GIM_Try, /*On fail goto*//*Label 768*/ 24127, // Rule ID 16733 // 10666 GIM_CheckFeatures, GIFBS_UseSSE1, 10667 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_sse_rcp_ss, 10668 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 10669 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 10670 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 10671 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 10672 // (intrinsic_wo_chain:{ *:[v4f32] } 11047:{ *:[iPTR] }, VR128:{ *:[v4f32] }:$src) => (RCPSSr_Int:{ *:[v4f32] } VR128:{ *:[v4f32] }:$src, VR128:{ *:[v4f32] }:$src) 10673 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::RCPSSr_Int, 10674 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 10675 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src 10676 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src 10677 GIR_EraseFromParent, /*InsnID*/0, 10678 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10679 // GIR_Coverage, 16733, 10680 GIR_Done, 10681 // Label 768: @24127 10682 GIM_Try, /*On fail goto*//*Label 769*/ 24171, // Rule ID 16737 // 10683 GIM_CheckFeatures, GIFBS_HasAVX, 10684 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_sse_rcp_ss, 10685 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 10686 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 10687 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 10688 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 10689 // (intrinsic_wo_chain:{ *:[v4f32] } 11047:{ *:[iPTR] }, VR128:{ *:[v4f32] }:$src) => (VRCPSSr_Int:{ *:[v4f32] } VR128:{ *:[v4f32] }:$src, VR128:{ *:[v4f32] }:$src) 10690 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VRCPSSr_Int, 10691 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 10692 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src 10693 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src 10694 GIR_EraseFromParent, /*InsnID*/0, 10695 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10696 // GIR_Coverage, 16737, 10697 GIR_Done, 10698 // Label 769: @24171 10699 GIM_Try, /*On fail goto*//*Label 770*/ 24211, // Rule ID 20550 // 10700 GIM_CheckFeatures, GIFBS_HasBF16_HasVLX, 10701 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_vcvtneps2bf16128, 10702 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, 10703 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 10704 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID, 10705 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128XRegClassID, 10706 // (intrinsic_wo_chain:{ *:[v8bf16] } 11235:{ *:[iPTR] }, VR128X:{ *:[v4f32] }:$src) => (VCVTNEPS2BF16Z128rr:{ *:[v8bf16] } VR128X:{ *:[v4f32] }:$src) 10707 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VCVTNEPS2BF16Z128rr, 10708 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 10709 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src 10710 GIR_EraseFromParent, /*InsnID*/0, 10711 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10712 // GIR_Coverage, 20550, 10713 GIR_Done, 10714 // Label 770: @24211 10715 GIM_Try, /*On fail goto*//*Label 771*/ 24251, // Rule ID 20552 // 10716 GIM_CheckFeatures, GIFBS_HasBF16_HasVLX, 10717 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_vcvtneps2bf16256, 10718 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, 10719 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s32, 10720 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID, 10721 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256XRegClassID, 10722 // (intrinsic_wo_chain:{ *:[v8bf16] } 11236:{ *:[iPTR] }, VR256X:{ *:[v8f32] }:$src) => (VCVTNEPS2BF16Z256rr:{ *:[v8bf16] } VR256X:{ *:[v8f32] }:$src) 10723 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VCVTNEPS2BF16Z256rr, 10724 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 10725 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src 10726 GIR_EraseFromParent, /*InsnID*/0, 10727 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10728 // GIR_Coverage, 20552, 10729 GIR_Done, 10730 // Label 771: @24251 10731 GIM_Reject, 10732 // Label 740: @24252 10733 GIM_Try, /*On fail goto*//*Label 772*/ 26952, 10734 GIM_CheckNumOperands, /*MI*/0, /*Expected*/4, 10735 GIM_Try, /*On fail goto*//*Label 773*/ 24304, // Rule ID 3051 // 10736 GIM_CheckFeatures, GIFBS_HasAES_HasAVX, 10737 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_aesni_aeskeygenassist, 10738 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 10739 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 10740 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 10741 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 10742 // MIs[0] src2 10743 GIM_CheckIsImm, /*MI*/0, /*Op*/3, 10744 // (intrinsic_wo_chain:{ *:[v2i64] } 9958:{ *:[iPTR] }, VR128:{ *:[v2i64] }:$src1, (timm:{ *:[i8] }):$src2) => (VAESKEYGENASSIST128rr:{ *:[v2i64] } VR128:{ *:[v2i64] }:$src1, (timm:{ *:[i8] }):$src2) 10745 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VAESKEYGENASSIST128rr, 10746 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 10747 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 10748 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src2 10749 GIR_EraseFromParent, /*InsnID*/0, 10750 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10751 // GIR_Coverage, 3051, 10752 GIR_Done, 10753 // Label 773: @24304 10754 GIM_Try, /*On fail goto*//*Label 774*/ 24351, // Rule ID 3053 // 10755 GIM_CheckFeatures, GIFBS_HasAES_NoAVX, 10756 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_aesni_aeskeygenassist, 10757 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 10758 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 10759 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 10760 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 10761 // MIs[0] src2 10762 GIM_CheckIsImm, /*MI*/0, /*Op*/3, 10763 // (intrinsic_wo_chain:{ *:[v2i64] } 9958:{ *:[iPTR] }, VR128:{ *:[v2i64] }:$src1, (timm:{ *:[i8] }):$src2) => (AESKEYGENASSIST128rr:{ *:[v2i64] } VR128:{ *:[v2i64] }:$src1, (timm:{ *:[i8] }):$src2) 10764 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::AESKEYGENASSIST128rr, 10765 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 10766 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 10767 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src2 10768 GIR_EraseFromParent, /*InsnID*/0, 10769 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10770 // GIR_Coverage, 3053, 10771 GIR_Done, 10772 // Label 774: @24351 10773 GIM_Try, /*On fail goto*//*Label 775*/ 24403, // Rule ID 2714 // 10774 GIM_CheckFeatures, GIFBS_HasAVX, 10775 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_ssse3_psign_b_128, 10776 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, 10777 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, 10778 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, 10779 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 10780 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 10781 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::VR128RegClassID, 10782 // (intrinsic_wo_chain:{ *:[v16i8] } 11187:{ *:[iPTR] }, VR128:{ *:[v16i8] }:$src1, VR128:{ *:[v16i8] }:$src2) => (VPSIGNBrr:{ *:[v16i8] } VR128:{ *:[v16i8] }:$src1, VR128:{ *:[v16i8] }:$src2) 10783 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VPSIGNBrr, 10784 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 10785 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 10786 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src2 10787 GIR_EraseFromParent, /*InsnID*/0, 10788 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10789 // GIR_Coverage, 2714, 10790 GIR_Done, 10791 // Label 775: @24403 10792 GIM_Try, /*On fail goto*//*Label 776*/ 24455, // Rule ID 2716 // 10793 GIM_CheckFeatures, GIFBS_HasAVX, 10794 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_ssse3_psign_w_128, 10795 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, 10796 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 10797 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, 10798 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 10799 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 10800 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::VR128RegClassID, 10801 // (intrinsic_wo_chain:{ *:[v8i16] } 11191:{ *:[iPTR] }, VR128:{ *:[v8i16] }:$src1, VR128:{ *:[v8i16] }:$src2) => (VPSIGNWrr:{ *:[v8i16] } VR128:{ *:[v8i16] }:$src1, VR128:{ *:[v8i16] }:$src2) 10802 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VPSIGNWrr, 10803 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 10804 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 10805 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src2 10806 GIR_EraseFromParent, /*InsnID*/0, 10807 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10808 // GIR_Coverage, 2716, 10809 GIR_Done, 10810 // Label 776: @24455 10811 GIM_Try, /*On fail goto*//*Label 777*/ 24507, // Rule ID 2718 // 10812 GIM_CheckFeatures, GIFBS_HasAVX, 10813 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_ssse3_psign_d_128, 10814 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 10815 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 10816 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, 10817 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 10818 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 10819 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::VR128RegClassID, 10820 // (intrinsic_wo_chain:{ *:[v4i32] } 11189:{ *:[iPTR] }, VR128:{ *:[v4i32] }:$src1, VR128:{ *:[v4i32] }:$src2) => (VPSIGNDrr:{ *:[v4i32] } VR128:{ *:[v4i32] }:$src1, VR128:{ *:[v4i32] }:$src2) 10821 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VPSIGNDrr, 10822 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 10823 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 10824 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src2 10825 GIR_EraseFromParent, /*InsnID*/0, 10826 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10827 // GIR_Coverage, 2718, 10828 GIR_Done, 10829 // Label 777: @24507 10830 GIM_Try, /*On fail goto*//*Label 778*/ 24559, // Rule ID 2720 // 10831 GIM_CheckFeatures, GIFBS_HasAVX, 10832 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_ssse3_phadd_sw_128, 10833 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, 10834 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 10835 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, 10836 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 10837 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 10838 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::VR128RegClassID, 10839 // (intrinsic_wo_chain:{ *:[v8i16] } 11171:{ *:[iPTR] }, VR128:{ *:[v8i16] }:$src1, VR128:{ *:[v8i16] }:$src2) => (VPHADDSWrr:{ *:[v8i16] } VR128:{ *:[v8i16] }:$src1, VR128:{ *:[v8i16] }:$src2) 10840 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VPHADDSWrr, 10841 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 10842 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 10843 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src2 10844 GIR_EraseFromParent, /*InsnID*/0, 10845 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10846 // GIR_Coverage, 2720, 10847 GIR_Done, 10848 // Label 778: @24559 10849 GIM_Try, /*On fail goto*//*Label 779*/ 24611, // Rule ID 2722 // 10850 GIM_CheckFeatures, GIFBS_HasAVX, 10851 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_ssse3_phsub_sw_128, 10852 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, 10853 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 10854 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, 10855 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 10856 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 10857 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::VR128RegClassID, 10858 // (intrinsic_wo_chain:{ *:[v8i16] } 11177:{ *:[iPTR] }, VR128:{ *:[v8i16] }:$src1, VR128:{ *:[v8i16] }:$src2) => (VPHSUBSWrr:{ *:[v8i16] } VR128:{ *:[v8i16] }:$src1, VR128:{ *:[v8i16] }:$src2) 10859 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VPHSUBSWrr, 10860 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 10861 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 10862 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src2 10863 GIR_EraseFromParent, /*InsnID*/0, 10864 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10865 // GIR_Coverage, 2722, 10866 GIR_Done, 10867 // Label 779: @24611 10868 GIM_Try, /*On fail goto*//*Label 780*/ 24663, // Rule ID 2738 // 10869 GIM_CheckFeatures, GIFBS_HasAVX2, 10870 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_avx2_psign_b, 10871 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v32s8, 10872 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v32s8, 10873 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v32s8, 10874 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID, 10875 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256RegClassID, 10876 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::VR256RegClassID, 10877 // (intrinsic_wo_chain:{ *:[v32i8] } 10076:{ *:[iPTR] }, VR256:{ *:[v32i8] }:$src1, VR256:{ *:[v32i8] }:$src2) => (VPSIGNBYrr:{ *:[v32i8] } VR256:{ *:[v32i8] }:$src1, VR256:{ *:[v32i8] }:$src2) 10878 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VPSIGNBYrr, 10879 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 10880 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 10881 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src2 10882 GIR_EraseFromParent, /*InsnID*/0, 10883 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10884 // GIR_Coverage, 2738, 10885 GIR_Done, 10886 // Label 780: @24663 10887 GIM_Try, /*On fail goto*//*Label 781*/ 24715, // Rule ID 2740 // 10888 GIM_CheckFeatures, GIFBS_HasAVX2, 10889 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_avx2_psign_w, 10890 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s16, 10891 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s16, 10892 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s16, 10893 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID, 10894 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256RegClassID, 10895 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::VR256RegClassID, 10896 // (intrinsic_wo_chain:{ *:[v16i16] } 10078:{ *:[iPTR] }, VR256:{ *:[v16i16] }:$src1, VR256:{ *:[v16i16] }:$src2) => (VPSIGNWYrr:{ *:[v16i16] } VR256:{ *:[v16i16] }:$src1, VR256:{ *:[v16i16] }:$src2) 10897 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VPSIGNWYrr, 10898 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 10899 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 10900 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src2 10901 GIR_EraseFromParent, /*InsnID*/0, 10902 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10903 // GIR_Coverage, 2740, 10904 GIR_Done, 10905 // Label 781: @24715 10906 GIM_Try, /*On fail goto*//*Label 782*/ 24767, // Rule ID 2742 // 10907 GIM_CheckFeatures, GIFBS_HasAVX2, 10908 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_avx2_psign_d, 10909 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s32, 10910 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s32, 10911 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s32, 10912 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID, 10913 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256RegClassID, 10914 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::VR256RegClassID, 10915 // (intrinsic_wo_chain:{ *:[v8i32] } 10077:{ *:[iPTR] }, VR256:{ *:[v8i32] }:$src1, VR256:{ *:[v8i32] }:$src2) => (VPSIGNDYrr:{ *:[v8i32] } VR256:{ *:[v8i32] }:$src1, VR256:{ *:[v8i32] }:$src2) 10916 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VPSIGNDYrr, 10917 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 10918 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 10919 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src2 10920 GIR_EraseFromParent, /*InsnID*/0, 10921 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10922 // GIR_Coverage, 2742, 10923 GIR_Done, 10924 // Label 782: @24767 10925 GIM_Try, /*On fail goto*//*Label 783*/ 24819, // Rule ID 2744 // 10926 GIM_CheckFeatures, GIFBS_HasAVX2, 10927 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_avx2_phadd_sw, 10928 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s16, 10929 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s16, 10930 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s16, 10931 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID, 10932 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256RegClassID, 10933 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::VR256RegClassID, 10934 // (intrinsic_wo_chain:{ *:[v16i16] } 10063:{ *:[iPTR] }, VR256:{ *:[v16i16] }:$src1, VR256:{ *:[v16i16] }:$src2) => (VPHADDSWYrr:{ *:[v16i16] } VR256:{ *:[v16i16] }:$src1, VR256:{ *:[v16i16] }:$src2) 10935 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VPHADDSWYrr, 10936 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 10937 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 10938 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src2 10939 GIR_EraseFromParent, /*InsnID*/0, 10940 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10941 // GIR_Coverage, 2744, 10942 GIR_Done, 10943 // Label 783: @24819 10944 GIM_Try, /*On fail goto*//*Label 784*/ 24871, // Rule ID 2746 // 10945 GIM_CheckFeatures, GIFBS_HasAVX2, 10946 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_avx2_phsub_sw, 10947 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s16, 10948 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s16, 10949 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s16, 10950 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID, 10951 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256RegClassID, 10952 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::VR256RegClassID, 10953 // (intrinsic_wo_chain:{ *:[v16i16] } 10066:{ *:[iPTR] }, VR256:{ *:[v16i16] }:$src1, VR256:{ *:[v16i16] }:$src2) => (VPHSUBSWYrr:{ *:[v16i16] } VR256:{ *:[v16i16] }:$src1, VR256:{ *:[v16i16] }:$src2) 10954 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VPHSUBSWYrr, 10955 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 10956 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 10957 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src2 10958 GIR_EraseFromParent, /*InsnID*/0, 10959 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10960 // GIR_Coverage, 2746, 10961 GIR_Done, 10962 // Label 784: @24871 10963 GIM_Try, /*On fail goto*//*Label 785*/ 24923, // Rule ID 2756 // 10964 GIM_CheckFeatures, GIFBS_UseSSSE3, 10965 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_ssse3_psign_b_128, 10966 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, 10967 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, 10968 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, 10969 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 10970 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 10971 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::VR128RegClassID, 10972 // (intrinsic_wo_chain:{ *:[v16i8] } 11187:{ *:[iPTR] }, VR128:{ *:[v16i8] }:$src1, VR128:{ *:[v16i8] }:$src2) => (PSIGNBrr:{ *:[v16i8] } VR128:{ *:[v16i8] }:$src1, VR128:{ *:[v16i8] }:$src2) 10973 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::PSIGNBrr, 10974 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 10975 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 10976 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src2 10977 GIR_EraseFromParent, /*InsnID*/0, 10978 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10979 // GIR_Coverage, 2756, 10980 GIR_Done, 10981 // Label 785: @24923 10982 GIM_Try, /*On fail goto*//*Label 786*/ 24975, // Rule ID 2758 // 10983 GIM_CheckFeatures, GIFBS_UseSSSE3, 10984 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_ssse3_psign_w_128, 10985 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, 10986 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 10987 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, 10988 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 10989 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 10990 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::VR128RegClassID, 10991 // (intrinsic_wo_chain:{ *:[v8i16] } 11191:{ *:[iPTR] }, VR128:{ *:[v8i16] }:$src1, VR128:{ *:[v8i16] }:$src2) => (PSIGNWrr:{ *:[v8i16] } VR128:{ *:[v8i16] }:$src1, VR128:{ *:[v8i16] }:$src2) 10992 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::PSIGNWrr, 10993 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 10994 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 10995 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src2 10996 GIR_EraseFromParent, /*InsnID*/0, 10997 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10998 // GIR_Coverage, 2758, 10999 GIR_Done, 11000 // Label 786: @24975 11001 GIM_Try, /*On fail goto*//*Label 787*/ 25027, // Rule ID 2760 // 11002 GIM_CheckFeatures, GIFBS_UseSSSE3, 11003 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_ssse3_psign_d_128, 11004 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 11005 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 11006 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, 11007 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 11008 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 11009 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::VR128RegClassID, 11010 // (intrinsic_wo_chain:{ *:[v4i32] } 11189:{ *:[iPTR] }, VR128:{ *:[v4i32] }:$src1, VR128:{ *:[v4i32] }:$src2) => (PSIGNDrr:{ *:[v4i32] } VR128:{ *:[v4i32] }:$src1, VR128:{ *:[v4i32] }:$src2) 11011 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::PSIGNDrr, 11012 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 11013 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 11014 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src2 11015 GIR_EraseFromParent, /*InsnID*/0, 11016 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11017 // GIR_Coverage, 2760, 11018 GIR_Done, 11019 // Label 787: @25027 11020 GIM_Try, /*On fail goto*//*Label 788*/ 25079, // Rule ID 2764 // 11021 GIM_CheckFeatures, GIFBS_UseSSSE3, 11022 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_ssse3_phadd_sw_128, 11023 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, 11024 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 11025 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, 11026 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 11027 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 11028 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::VR128RegClassID, 11029 // (intrinsic_wo_chain:{ *:[v8i16] } 11171:{ *:[iPTR] }, VR128:{ *:[v8i16] }:$src1, VR128:{ *:[v8i16] }:$src2) => (PHADDSWrr:{ *:[v8i16] } VR128:{ *:[v8i16] }:$src1, VR128:{ *:[v8i16] }:$src2) 11030 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::PHADDSWrr, 11031 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 11032 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 11033 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src2 11034 GIR_EraseFromParent, /*InsnID*/0, 11035 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11036 // GIR_Coverage, 2764, 11037 GIR_Done, 11038 // Label 788: @25079 11039 GIM_Try, /*On fail goto*//*Label 789*/ 25131, // Rule ID 2766 // 11040 GIM_CheckFeatures, GIFBS_UseSSSE3, 11041 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_ssse3_phsub_sw_128, 11042 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, 11043 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 11044 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, 11045 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 11046 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 11047 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::VR128RegClassID, 11048 // (intrinsic_wo_chain:{ *:[v8i16] } 11177:{ *:[iPTR] }, VR128:{ *:[v8i16] }:$src1, VR128:{ *:[v8i16] }:$src2) => (PHSUBSWrr:{ *:[v8i16] } VR128:{ *:[v8i16] }:$src1, VR128:{ *:[v8i16] }:$src2) 11049 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::PHSUBSWrr, 11050 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 11051 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 11052 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src2 11053 GIR_EraseFromParent, /*InsnID*/0, 11054 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11055 // GIR_Coverage, 2766, 11056 GIR_Done, 11057 // Label 789: @25131 11058 GIM_Try, /*On fail goto*//*Label 790*/ 25183, // Rule ID 3002 // 11059 GIM_CheckFeatures, GIFBS_HasCRC32, 11060 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_sse42_crc32_32_8, 11061 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, 11062 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 11063 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s8, 11064 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID, 11065 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::GR32RegClassID, 11066 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::GR8RegClassID, 11067 // (intrinsic_wo_chain:{ *:[i32] } 11145:{ *:[iPTR] }, GR32:{ *:[i32] }:$src1, GR8:{ *:[i8] }:$src2) => (CRC32r32r8:{ *:[i32] } GR32:{ *:[i32] }:$src1, GR8:{ *:[i8] }:$src2) 11068 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::CRC32r32r8, 11069 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 11070 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 11071 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src2 11072 GIR_EraseFromParent, /*InsnID*/0, 11073 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11074 // GIR_Coverage, 3002, 11075 GIR_Done, 11076 // Label 790: @25183 11077 GIM_Try, /*On fail goto*//*Label 791*/ 25235, // Rule ID 3004 // 11078 GIM_CheckFeatures, GIFBS_HasCRC32, 11079 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_sse42_crc32_32_16, 11080 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, 11081 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 11082 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s16, 11083 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID, 11084 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::GR32RegClassID, 11085 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::GR16RegClassID, 11086 // (intrinsic_wo_chain:{ *:[i32] } 11143:{ *:[iPTR] }, GR32:{ *:[i32] }:$src1, GR16:{ *:[i16] }:$src2) => (CRC32r32r16:{ *:[i32] } GR32:{ *:[i32] }:$src1, GR16:{ *:[i16] }:$src2) 11087 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::CRC32r32r16, 11088 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 11089 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 11090 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src2 11091 GIR_EraseFromParent, /*InsnID*/0, 11092 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11093 // GIR_Coverage, 3004, 11094 GIR_Done, 11095 // Label 791: @25235 11096 GIM_Try, /*On fail goto*//*Label 792*/ 25287, // Rule ID 3006 // 11097 GIM_CheckFeatures, GIFBS_HasCRC32, 11098 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_sse42_crc32_32_32, 11099 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, 11100 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 11101 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 11102 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID, 11103 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::GR32RegClassID, 11104 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::GR32RegClassID, 11105 // (intrinsic_wo_chain:{ *:[i32] } 11144:{ *:[iPTR] }, GR32:{ *:[i32] }:$src1, GR32:{ *:[i32] }:$src2) => (CRC32r32r32:{ *:[i32] } GR32:{ *:[i32] }:$src1, GR32:{ *:[i32] }:$src2) 11106 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::CRC32r32r32, 11107 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 11108 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 11109 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src2 11110 GIR_EraseFromParent, /*InsnID*/0, 11111 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11112 // GIR_Coverage, 3006, 11113 GIR_Done, 11114 // Label 792: @25287 11115 GIM_Try, /*On fail goto*//*Label 793*/ 25339, // Rule ID 3008 // 11116 GIM_CheckFeatures, GIFBS_HasCRC32, 11117 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_sse42_crc32_64_64, 11118 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, 11119 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 11120 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, 11121 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID, 11122 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::GR64RegClassID, 11123 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::GR64RegClassID, 11124 // (intrinsic_wo_chain:{ *:[i64] } 11146:{ *:[iPTR] }, GR64:{ *:[i64] }:$src1, GR64:{ *:[i64] }:$src2) => (CRC32r64r64:{ *:[i64] } GR64:{ *:[i64] }:$src1, GR64:{ *:[i64] }:$src2) 11125 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::CRC32r64r64, 11126 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 11127 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 11128 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src2 11129 GIR_EraseFromParent, /*InsnID*/0, 11130 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11131 // GIR_Coverage, 3008, 11132 GIR_Done, 11133 // Label 793: @25339 11134 GIM_Try, /*On fail goto*//*Label 794*/ 25391, // Rule ID 3011 // 11135 GIM_CheckFeatures, GIFBS_HasSHA, 11136 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_sha1nexte, 11137 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 11138 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 11139 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, 11140 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 11141 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 11142 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::VR128RegClassID, 11143 // (intrinsic_wo_chain:{ *:[v4i32] } 11015:{ *:[iPTR] }, VR128:{ *:[v4i32] }:$src1, VR128:{ *:[v4i32] }:$src2) => (SHA1NEXTErr:{ *:[v4i32] } VR128:{ *:[v4i32] }:$src1, VR128:{ *:[v4i32] }:$src2) 11144 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SHA1NEXTErr, 11145 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 11146 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 11147 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src2 11148 GIR_EraseFromParent, /*InsnID*/0, 11149 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11150 // GIR_Coverage, 3011, 11151 GIR_Done, 11152 // Label 794: @25391 11153 GIM_Try, /*On fail goto*//*Label 795*/ 25443, // Rule ID 3013 // 11154 GIM_CheckFeatures, GIFBS_HasSHA, 11155 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_sha1msg1, 11156 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 11157 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 11158 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, 11159 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 11160 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 11161 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::VR128RegClassID, 11162 // (intrinsic_wo_chain:{ *:[v4i32] } 11013:{ *:[iPTR] }, VR128:{ *:[v4i32] }:$src1, VR128:{ *:[v4i32] }:$src2) => (SHA1MSG1rr:{ *:[v4i32] } VR128:{ *:[v4i32] }:$src1, VR128:{ *:[v4i32] }:$src2) 11163 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SHA1MSG1rr, 11164 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 11165 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 11166 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src2 11167 GIR_EraseFromParent, /*InsnID*/0, 11168 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11169 // GIR_Coverage, 3013, 11170 GIR_Done, 11171 // Label 795: @25443 11172 GIM_Try, /*On fail goto*//*Label 796*/ 25495, // Rule ID 3015 // 11173 GIM_CheckFeatures, GIFBS_HasSHA, 11174 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_sha1msg2, 11175 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 11176 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 11177 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, 11178 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 11179 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 11180 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::VR128RegClassID, 11181 // (intrinsic_wo_chain:{ *:[v4i32] } 11014:{ *:[iPTR] }, VR128:{ *:[v4i32] }:$src1, VR128:{ *:[v4i32] }:$src2) => (SHA1MSG2rr:{ *:[v4i32] } VR128:{ *:[v4i32] }:$src1, VR128:{ *:[v4i32] }:$src2) 11182 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SHA1MSG2rr, 11183 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 11184 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 11185 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src2 11186 GIR_EraseFromParent, /*InsnID*/0, 11187 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11188 // GIR_Coverage, 3015, 11189 GIR_Done, 11190 // Label 796: @25495 11191 GIM_Try, /*On fail goto*//*Label 797*/ 25547, // Rule ID 3019 // 11192 GIM_CheckFeatures, GIFBS_HasSHA, 11193 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_sha256msg1, 11194 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 11195 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 11196 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, 11197 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 11198 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 11199 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::VR128RegClassID, 11200 // (intrinsic_wo_chain:{ *:[v4i32] } 11017:{ *:[iPTR] }, VR128:{ *:[v4i32] }:$src1, VR128:{ *:[v4i32] }:$src2) => (SHA256MSG1rr:{ *:[v4i32] } VR128:{ *:[v4i32] }:$src1, VR128:{ *:[v4i32] }:$src2) 11201 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SHA256MSG1rr, 11202 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 11203 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 11204 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src2 11205 GIR_EraseFromParent, /*InsnID*/0, 11206 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11207 // GIR_Coverage, 3019, 11208 GIR_Done, 11209 // Label 797: @25547 11210 GIM_Try, /*On fail goto*//*Label 798*/ 25599, // Rule ID 3021 // 11211 GIM_CheckFeatures, GIFBS_HasSHA, 11212 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_sha256msg2, 11213 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 11214 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 11215 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, 11216 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 11217 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 11218 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::VR128RegClassID, 11219 // (intrinsic_wo_chain:{ *:[v4i32] } 11018:{ *:[iPTR] }, VR128:{ *:[v4i32] }:$src1, VR128:{ *:[v4i32] }:$src2) => (SHA256MSG2rr:{ *:[v4i32] } VR128:{ *:[v4i32] }:$src1, VR128:{ *:[v4i32] }:$src2) 11220 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SHA256MSG2rr, 11221 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 11222 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 11223 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src2 11224 GIR_EraseFromParent, /*InsnID*/0, 11225 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11226 // GIR_Coverage, 3021, 11227 GIR_Done, 11228 // Label 798: @25599 11229 GIM_Try, /*On fail goto*//*Label 799*/ 25651, // Rule ID 3023 // 11230 GIM_CheckFeatures, GIFBS_HasAES_HasAVX_NoVLX_Or_NoVAES, 11231 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_aesni_aesenc, 11232 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 11233 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 11234 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, 11235 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 11236 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 11237 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::VR128RegClassID, 11238 // (intrinsic_wo_chain:{ *:[v2i64] } 9951:{ *:[iPTR] }, VR128:{ *:[v2i64] }:$src1, VR128:{ *:[v2i64] }:$src2) => (VAESENCrr:{ *:[v2i64] } VR128:{ *:[v2i64] }:$src1, VR128:{ *:[v2i64] }:$src2) 11239 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VAESENCrr, 11240 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 11241 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 11242 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src2 11243 GIR_EraseFromParent, /*InsnID*/0, 11244 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11245 // GIR_Coverage, 3023, 11246 GIR_Done, 11247 // Label 799: @25651 11248 GIM_Try, /*On fail goto*//*Label 800*/ 25703, // Rule ID 3025 // 11249 GIM_CheckFeatures, GIFBS_HasAES_HasAVX_NoVLX_Or_NoVAES, 11250 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_aesni_aesenclast, 11251 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 11252 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 11253 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, 11254 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 11255 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 11256 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::VR128RegClassID, 11257 // (intrinsic_wo_chain:{ *:[v2i64] } 9954:{ *:[iPTR] }, VR128:{ *:[v2i64] }:$src1, VR128:{ *:[v2i64] }:$src2) => (VAESENCLASTrr:{ *:[v2i64] } VR128:{ *:[v2i64] }:$src1, VR128:{ *:[v2i64] }:$src2) 11258 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VAESENCLASTrr, 11259 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 11260 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 11261 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src2 11262 GIR_EraseFromParent, /*InsnID*/0, 11263 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11264 // GIR_Coverage, 3025, 11265 GIR_Done, 11266 // Label 800: @25703 11267 GIM_Try, /*On fail goto*//*Label 801*/ 25755, // Rule ID 3027 // 11268 GIM_CheckFeatures, GIFBS_HasAES_HasAVX_NoVLX_Or_NoVAES, 11269 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_aesni_aesdec, 11270 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 11271 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 11272 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, 11273 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 11274 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 11275 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::VR128RegClassID, 11276 // (intrinsic_wo_chain:{ *:[v2i64] } 9945:{ *:[iPTR] }, VR128:{ *:[v2i64] }:$src1, VR128:{ *:[v2i64] }:$src2) => (VAESDECrr:{ *:[v2i64] } VR128:{ *:[v2i64] }:$src1, VR128:{ *:[v2i64] }:$src2) 11277 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VAESDECrr, 11278 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 11279 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 11280 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src2 11281 GIR_EraseFromParent, /*InsnID*/0, 11282 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11283 // GIR_Coverage, 3027, 11284 GIR_Done, 11285 // Label 801: @25755 11286 GIM_Try, /*On fail goto*//*Label 802*/ 25807, // Rule ID 3029 // 11287 GIM_CheckFeatures, GIFBS_HasAES_HasAVX_NoVLX_Or_NoVAES, 11288 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_aesni_aesdeclast, 11289 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 11290 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 11291 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, 11292 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 11293 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 11294 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::VR128RegClassID, 11295 // (intrinsic_wo_chain:{ *:[v2i64] } 9948:{ *:[iPTR] }, VR128:{ *:[v2i64] }:$src1, VR128:{ *:[v2i64] }:$src2) => (VAESDECLASTrr:{ *:[v2i64] } VR128:{ *:[v2i64] }:$src1, VR128:{ *:[v2i64] }:$src2) 11296 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VAESDECLASTrr, 11297 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 11298 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 11299 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src2 11300 GIR_EraseFromParent, /*InsnID*/0, 11301 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11302 // GIR_Coverage, 3029, 11303 GIR_Done, 11304 // Label 802: @25807 11305 GIM_Try, /*On fail goto*//*Label 803*/ 25859, // Rule ID 3031 // 11306 GIM_CheckFeatures, GIFBS_HasVAES_NoVLX, 11307 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_aesni_aesenc_256, 11308 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s64, 11309 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s64, 11310 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s64, 11311 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID, 11312 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256RegClassID, 11313 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::VR256RegClassID, 11314 // (intrinsic_wo_chain:{ *:[v4i64] } 9952:{ *:[iPTR] }, VR256:{ *:[v4i64] }:$src1, VR256:{ *:[v4i64] }:$src2) => (VAESENCYrr:{ *:[v4i64] } VR256:{ *:[v4i64] }:$src1, VR256:{ *:[v4i64] }:$src2) 11315 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VAESENCYrr, 11316 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 11317 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 11318 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src2 11319 GIR_EraseFromParent, /*InsnID*/0, 11320 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11321 // GIR_Coverage, 3031, 11322 GIR_Done, 11323 // Label 803: @25859 11324 GIM_Try, /*On fail goto*//*Label 804*/ 25911, // Rule ID 3033 // 11325 GIM_CheckFeatures, GIFBS_HasVAES_NoVLX, 11326 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_aesni_aesenclast_256, 11327 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s64, 11328 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s64, 11329 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s64, 11330 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID, 11331 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256RegClassID, 11332 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::VR256RegClassID, 11333 // (intrinsic_wo_chain:{ *:[v4i64] } 9955:{ *:[iPTR] }, VR256:{ *:[v4i64] }:$src1, VR256:{ *:[v4i64] }:$src2) => (VAESENCLASTYrr:{ *:[v4i64] } VR256:{ *:[v4i64] }:$src1, VR256:{ *:[v4i64] }:$src2) 11334 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VAESENCLASTYrr, 11335 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 11336 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 11337 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src2 11338 GIR_EraseFromParent, /*InsnID*/0, 11339 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11340 // GIR_Coverage, 3033, 11341 GIR_Done, 11342 // Label 804: @25911 11343 GIM_Try, /*On fail goto*//*Label 805*/ 25963, // Rule ID 3035 // 11344 GIM_CheckFeatures, GIFBS_HasVAES_NoVLX, 11345 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_aesni_aesdec_256, 11346 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s64, 11347 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s64, 11348 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s64, 11349 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID, 11350 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256RegClassID, 11351 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::VR256RegClassID, 11352 // (intrinsic_wo_chain:{ *:[v4i64] } 9946:{ *:[iPTR] }, VR256:{ *:[v4i64] }:$src1, VR256:{ *:[v4i64] }:$src2) => (VAESDECYrr:{ *:[v4i64] } VR256:{ *:[v4i64] }:$src1, VR256:{ *:[v4i64] }:$src2) 11353 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VAESDECYrr, 11354 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 11355 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 11356 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src2 11357 GIR_EraseFromParent, /*InsnID*/0, 11358 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11359 // GIR_Coverage, 3035, 11360 GIR_Done, 11361 // Label 805: @25963 11362 GIM_Try, /*On fail goto*//*Label 806*/ 26015, // Rule ID 3037 // 11363 GIM_CheckFeatures, GIFBS_HasVAES_NoVLX, 11364 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_aesni_aesdeclast_256, 11365 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s64, 11366 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s64, 11367 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s64, 11368 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID, 11369 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256RegClassID, 11370 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::VR256RegClassID, 11371 // (intrinsic_wo_chain:{ *:[v4i64] } 9949:{ *:[iPTR] }, VR256:{ *:[v4i64] }:$src1, VR256:{ *:[v4i64] }:$src2) => (VAESDECLASTYrr:{ *:[v4i64] } VR256:{ *:[v4i64] }:$src1, VR256:{ *:[v4i64] }:$src2) 11372 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VAESDECLASTYrr, 11373 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 11374 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 11375 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src2 11376 GIR_EraseFromParent, /*InsnID*/0, 11377 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11378 // GIR_Coverage, 3037, 11379 GIR_Done, 11380 // Label 806: @26015 11381 GIM_Try, /*On fail goto*//*Label 807*/ 26067, // Rule ID 3039 // 11382 GIM_CheckFeatures, GIFBS_HasAES_NoAVX, 11383 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_aesni_aesenc, 11384 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 11385 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 11386 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, 11387 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 11388 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 11389 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::VR128RegClassID, 11390 // (intrinsic_wo_chain:{ *:[v2i64] } 9951:{ *:[iPTR] }, VR128:{ *:[v2i64] }:$src1, VR128:{ *:[v2i64] }:$src2) => (AESENCrr:{ *:[v2i64] } VR128:{ *:[v2i64] }:$src1, VR128:{ *:[v2i64] }:$src2) 11391 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::AESENCrr, 11392 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 11393 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 11394 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src2 11395 GIR_EraseFromParent, /*InsnID*/0, 11396 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11397 // GIR_Coverage, 3039, 11398 GIR_Done, 11399 // Label 807: @26067 11400 GIM_Try, /*On fail goto*//*Label 808*/ 26119, // Rule ID 3041 // 11401 GIM_CheckFeatures, GIFBS_HasAES_NoAVX, 11402 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_aesni_aesenclast, 11403 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 11404 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 11405 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, 11406 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 11407 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 11408 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::VR128RegClassID, 11409 // (intrinsic_wo_chain:{ *:[v2i64] } 9954:{ *:[iPTR] }, VR128:{ *:[v2i64] }:$src1, VR128:{ *:[v2i64] }:$src2) => (AESENCLASTrr:{ *:[v2i64] } VR128:{ *:[v2i64] }:$src1, VR128:{ *:[v2i64] }:$src2) 11410 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::AESENCLASTrr, 11411 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 11412 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 11413 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src2 11414 GIR_EraseFromParent, /*InsnID*/0, 11415 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11416 // GIR_Coverage, 3041, 11417 GIR_Done, 11418 // Label 808: @26119 11419 GIM_Try, /*On fail goto*//*Label 809*/ 26171, // Rule ID 3043 // 11420 GIM_CheckFeatures, GIFBS_HasAES_NoAVX, 11421 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_aesni_aesdec, 11422 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 11423 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 11424 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, 11425 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 11426 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 11427 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::VR128RegClassID, 11428 // (intrinsic_wo_chain:{ *:[v2i64] } 9945:{ *:[iPTR] }, VR128:{ *:[v2i64] }:$src1, VR128:{ *:[v2i64] }:$src2) => (AESDECrr:{ *:[v2i64] } VR128:{ *:[v2i64] }:$src1, VR128:{ *:[v2i64] }:$src2) 11429 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::AESDECrr, 11430 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 11431 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 11432 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src2 11433 GIR_EraseFromParent, /*InsnID*/0, 11434 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11435 // GIR_Coverage, 3043, 11436 GIR_Done, 11437 // Label 809: @26171 11438 GIM_Try, /*On fail goto*//*Label 810*/ 26223, // Rule ID 3045 // 11439 GIM_CheckFeatures, GIFBS_HasAES_NoAVX, 11440 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_aesni_aesdeclast, 11441 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 11442 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 11443 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, 11444 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 11445 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 11446 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::VR128RegClassID, 11447 // (intrinsic_wo_chain:{ *:[v2i64] } 9948:{ *:[iPTR] }, VR128:{ *:[v2i64] }:$src1, VR128:{ *:[v2i64] }:$src2) => (AESDECLASTrr:{ *:[v2i64] } VR128:{ *:[v2i64] }:$src1, VR128:{ *:[v2i64] }:$src2) 11448 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::AESDECLASTrr, 11449 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 11450 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 11451 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src2 11452 GIR_EraseFromParent, /*InsnID*/0, 11453 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11454 // GIR_Coverage, 3045, 11455 GIR_Done, 11456 // Label 810: @26223 11457 GIM_Try, /*On fail goto*//*Label 811*/ 26275, // Rule ID 3062 // 11458 GIM_CheckFeatures, GIFBS_HasSSE4A, 11459 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_sse4a_extrq, 11460 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 11461 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 11462 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, 11463 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 11464 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 11465 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::VR128RegClassID, 11466 // (intrinsic_wo_chain:{ *:[v2i64] } 11161:{ *:[iPTR] }, VR128:{ *:[v2i64] }:$src, VR128:{ *:[v16i8] }:$mask) => (EXTRQ:{ *:[v2i64] } VR128:{ *:[v2i64] }:$src, VR128:{ *:[v16i8] }:$mask) 11467 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::EXTRQ, 11468 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 11469 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src 11470 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // mask 11471 GIR_EraseFromParent, /*InsnID*/0, 11472 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11473 // GIR_Coverage, 3062, 11474 GIR_Done, 11475 // Label 811: @26275 11476 GIM_Try, /*On fail goto*//*Label 812*/ 26327, // Rule ID 3064 // 11477 GIM_CheckFeatures, GIFBS_HasSSE4A, 11478 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_sse4a_insertq, 11479 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 11480 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 11481 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, 11482 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 11483 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 11484 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::VR128RegClassID, 11485 // (intrinsic_wo_chain:{ *:[v2i64] } 11163:{ *:[iPTR] }, VR128:{ *:[v2i64] }:$src, VR128:{ *:[v2i64] }:$mask) => (INSERTQ:{ *:[v2i64] } VR128:{ *:[v2i64] }:$src, VR128:{ *:[v2i64] }:$mask) 11486 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::INSERTQ, 11487 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 11488 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src 11489 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // mask 11490 GIR_EraseFromParent, /*InsnID*/0, 11491 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11492 // GIR_Coverage, 3064, 11493 GIR_Done, 11494 // Label 812: @26327 11495 GIM_Try, /*On fail goto*//*Label 813*/ 26379, // Rule ID 13765 // 11496 GIM_CheckFeatures, GIFBS_HasVAES_HasVLX, 11497 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_aesni_aesenc, 11498 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 11499 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 11500 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, 11501 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID, 11502 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128XRegClassID, 11503 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::VR128XRegClassID, 11504 // (intrinsic_wo_chain:{ *:[v2i64] } 9951:{ *:[iPTR] }, VR128X:{ *:[v2i64] }:$src1, VR128X:{ *:[v2i64] }:$src2) => (VAESENCZ128rr:{ *:[v2i64] } VR128X:{ *:[v2i64] }:$src1, VR128X:{ *:[v2i64] }:$src2) 11505 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VAESENCZ128rr, 11506 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 11507 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 11508 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src2 11509 GIR_EraseFromParent, /*InsnID*/0, 11510 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11511 // GIR_Coverage, 13765, 11512 GIR_Done, 11513 // Label 813: @26379 11514 GIM_Try, /*On fail goto*//*Label 814*/ 26431, // Rule ID 13767 // 11515 GIM_CheckFeatures, GIFBS_HasVAES_HasVLX, 11516 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_aesni_aesenc_256, 11517 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s64, 11518 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s64, 11519 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s64, 11520 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID, 11521 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256XRegClassID, 11522 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::VR256XRegClassID, 11523 // (intrinsic_wo_chain:{ *:[v4i64] } 9952:{ *:[iPTR] }, VR256X:{ *:[v4i64] }:$src1, VR256X:{ *:[v4i64] }:$src2) => (VAESENCZ256rr:{ *:[v4i64] } VR256X:{ *:[v4i64] }:$src1, VR256X:{ *:[v4i64] }:$src2) 11524 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VAESENCZ256rr, 11525 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 11526 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 11527 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src2 11528 GIR_EraseFromParent, /*InsnID*/0, 11529 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11530 // GIR_Coverage, 13767, 11531 GIR_Done, 11532 // Label 814: @26431 11533 GIM_Try, /*On fail goto*//*Label 815*/ 26483, // Rule ID 13769 // 11534 GIM_CheckFeatures, GIFBS_HasAVX512_HasVAES, 11535 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_aesni_aesenc_512, 11536 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s64, 11537 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s64, 11538 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s64, 11539 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 11540 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR512RegClassID, 11541 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::VR512RegClassID, 11542 // (intrinsic_wo_chain:{ *:[v8i64] } 9953:{ *:[iPTR] }, VR512:{ *:[v8i64] }:$src1, VR512:{ *:[v8i64] }:$src2) => (VAESENCZrr:{ *:[v8i64] } VR512:{ *:[v8i64] }:$src1, VR512:{ *:[v8i64] }:$src2) 11543 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VAESENCZrr, 11544 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 11545 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 11546 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src2 11547 GIR_EraseFromParent, /*InsnID*/0, 11548 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11549 // GIR_Coverage, 13769, 11550 GIR_Done, 11551 // Label 815: @26483 11552 GIM_Try, /*On fail goto*//*Label 816*/ 26535, // Rule ID 13771 // 11553 GIM_CheckFeatures, GIFBS_HasVAES_HasVLX, 11554 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_aesni_aesenclast, 11555 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 11556 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 11557 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, 11558 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID, 11559 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128XRegClassID, 11560 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::VR128XRegClassID, 11561 // (intrinsic_wo_chain:{ *:[v2i64] } 9954:{ *:[iPTR] }, VR128X:{ *:[v2i64] }:$src1, VR128X:{ *:[v2i64] }:$src2) => (VAESENCLASTZ128rr:{ *:[v2i64] } VR128X:{ *:[v2i64] }:$src1, VR128X:{ *:[v2i64] }:$src2) 11562 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VAESENCLASTZ128rr, 11563 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 11564 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 11565 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src2 11566 GIR_EraseFromParent, /*InsnID*/0, 11567 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11568 // GIR_Coverage, 13771, 11569 GIR_Done, 11570 // Label 816: @26535 11571 GIM_Try, /*On fail goto*//*Label 817*/ 26587, // Rule ID 13773 // 11572 GIM_CheckFeatures, GIFBS_HasVAES_HasVLX, 11573 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_aesni_aesenclast_256, 11574 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s64, 11575 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s64, 11576 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s64, 11577 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID, 11578 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256XRegClassID, 11579 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::VR256XRegClassID, 11580 // (intrinsic_wo_chain:{ *:[v4i64] } 9955:{ *:[iPTR] }, VR256X:{ *:[v4i64] }:$src1, VR256X:{ *:[v4i64] }:$src2) => (VAESENCLASTZ256rr:{ *:[v4i64] } VR256X:{ *:[v4i64] }:$src1, VR256X:{ *:[v4i64] }:$src2) 11581 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VAESENCLASTZ256rr, 11582 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 11583 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 11584 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src2 11585 GIR_EraseFromParent, /*InsnID*/0, 11586 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11587 // GIR_Coverage, 13773, 11588 GIR_Done, 11589 // Label 817: @26587 11590 GIM_Try, /*On fail goto*//*Label 818*/ 26639, // Rule ID 13775 // 11591 GIM_CheckFeatures, GIFBS_HasAVX512_HasVAES, 11592 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_aesni_aesenclast_512, 11593 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s64, 11594 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s64, 11595 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s64, 11596 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 11597 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR512RegClassID, 11598 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::VR512RegClassID, 11599 // (intrinsic_wo_chain:{ *:[v8i64] } 9956:{ *:[iPTR] }, VR512:{ *:[v8i64] }:$src1, VR512:{ *:[v8i64] }:$src2) => (VAESENCLASTZrr:{ *:[v8i64] } VR512:{ *:[v8i64] }:$src1, VR512:{ *:[v8i64] }:$src2) 11600 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VAESENCLASTZrr, 11601 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 11602 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 11603 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src2 11604 GIR_EraseFromParent, /*InsnID*/0, 11605 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11606 // GIR_Coverage, 13775, 11607 GIR_Done, 11608 // Label 818: @26639 11609 GIM_Try, /*On fail goto*//*Label 819*/ 26691, // Rule ID 13777 // 11610 GIM_CheckFeatures, GIFBS_HasVAES_HasVLX, 11611 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_aesni_aesdec, 11612 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 11613 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 11614 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, 11615 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID, 11616 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128XRegClassID, 11617 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::VR128XRegClassID, 11618 // (intrinsic_wo_chain:{ *:[v2i64] } 9945:{ *:[iPTR] }, VR128X:{ *:[v2i64] }:$src1, VR128X:{ *:[v2i64] }:$src2) => (VAESDECZ128rr:{ *:[v2i64] } VR128X:{ *:[v2i64] }:$src1, VR128X:{ *:[v2i64] }:$src2) 11619 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VAESDECZ128rr, 11620 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 11621 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 11622 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src2 11623 GIR_EraseFromParent, /*InsnID*/0, 11624 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11625 // GIR_Coverage, 13777, 11626 GIR_Done, 11627 // Label 819: @26691 11628 GIM_Try, /*On fail goto*//*Label 820*/ 26743, // Rule ID 13779 // 11629 GIM_CheckFeatures, GIFBS_HasVAES_HasVLX, 11630 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_aesni_aesdec_256, 11631 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s64, 11632 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s64, 11633 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s64, 11634 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID, 11635 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256XRegClassID, 11636 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::VR256XRegClassID, 11637 // (intrinsic_wo_chain:{ *:[v4i64] } 9946:{ *:[iPTR] }, VR256X:{ *:[v4i64] }:$src1, VR256X:{ *:[v4i64] }:$src2) => (VAESDECZ256rr:{ *:[v4i64] } VR256X:{ *:[v4i64] }:$src1, VR256X:{ *:[v4i64] }:$src2) 11638 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VAESDECZ256rr, 11639 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 11640 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 11641 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src2 11642 GIR_EraseFromParent, /*InsnID*/0, 11643 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11644 // GIR_Coverage, 13779, 11645 GIR_Done, 11646 // Label 820: @26743 11647 GIM_Try, /*On fail goto*//*Label 821*/ 26795, // Rule ID 13781 // 11648 GIM_CheckFeatures, GIFBS_HasAVX512_HasVAES, 11649 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_aesni_aesdec_512, 11650 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s64, 11651 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s64, 11652 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s64, 11653 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 11654 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR512RegClassID, 11655 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::VR512RegClassID, 11656 // (intrinsic_wo_chain:{ *:[v8i64] } 9947:{ *:[iPTR] }, VR512:{ *:[v8i64] }:$src1, VR512:{ *:[v8i64] }:$src2) => (VAESDECZrr:{ *:[v8i64] } VR512:{ *:[v8i64] }:$src1, VR512:{ *:[v8i64] }:$src2) 11657 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VAESDECZrr, 11658 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 11659 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 11660 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src2 11661 GIR_EraseFromParent, /*InsnID*/0, 11662 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11663 // GIR_Coverage, 13781, 11664 GIR_Done, 11665 // Label 821: @26795 11666 GIM_Try, /*On fail goto*//*Label 822*/ 26847, // Rule ID 13783 // 11667 GIM_CheckFeatures, GIFBS_HasVAES_HasVLX, 11668 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_aesni_aesdeclast, 11669 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 11670 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 11671 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, 11672 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID, 11673 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128XRegClassID, 11674 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::VR128XRegClassID, 11675 // (intrinsic_wo_chain:{ *:[v2i64] } 9948:{ *:[iPTR] }, VR128X:{ *:[v2i64] }:$src1, VR128X:{ *:[v2i64] }:$src2) => (VAESDECLASTZ128rr:{ *:[v2i64] } VR128X:{ *:[v2i64] }:$src1, VR128X:{ *:[v2i64] }:$src2) 11676 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VAESDECLASTZ128rr, 11677 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 11678 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 11679 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src2 11680 GIR_EraseFromParent, /*InsnID*/0, 11681 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11682 // GIR_Coverage, 13783, 11683 GIR_Done, 11684 // Label 822: @26847 11685 GIM_Try, /*On fail goto*//*Label 823*/ 26899, // Rule ID 13785 // 11686 GIM_CheckFeatures, GIFBS_HasVAES_HasVLX, 11687 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_aesni_aesdeclast_256, 11688 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s64, 11689 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s64, 11690 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s64, 11691 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID, 11692 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256XRegClassID, 11693 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::VR256XRegClassID, 11694 // (intrinsic_wo_chain:{ *:[v4i64] } 9949:{ *:[iPTR] }, VR256X:{ *:[v4i64] }:$src1, VR256X:{ *:[v4i64] }:$src2) => (VAESDECLASTZ256rr:{ *:[v4i64] } VR256X:{ *:[v4i64] }:$src1, VR256X:{ *:[v4i64] }:$src2) 11695 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VAESDECLASTZ256rr, 11696 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 11697 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 11698 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src2 11699 GIR_EraseFromParent, /*InsnID*/0, 11700 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11701 // GIR_Coverage, 13785, 11702 GIR_Done, 11703 // Label 823: @26899 11704 GIM_Try, /*On fail goto*//*Label 824*/ 26951, // Rule ID 13787 // 11705 GIM_CheckFeatures, GIFBS_HasAVX512_HasVAES, 11706 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_aesni_aesdeclast_512, 11707 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s64, 11708 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s64, 11709 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s64, 11710 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 11711 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR512RegClassID, 11712 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::VR512RegClassID, 11713 // (intrinsic_wo_chain:{ *:[v8i64] } 9950:{ *:[iPTR] }, VR512:{ *:[v8i64] }:$src1, VR512:{ *:[v8i64] }:$src2) => (VAESDECLASTZrr:{ *:[v8i64] } VR512:{ *:[v8i64] }:$src1, VR512:{ *:[v8i64] }:$src2) 11714 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VAESDECLASTZrr, 11715 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 11716 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 11717 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src2 11718 GIR_EraseFromParent, /*InsnID*/0, 11719 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11720 // GIR_Coverage, 13787, 11721 GIR_Done, 11722 // Label 824: @26951 11723 GIM_Reject, 11724 // Label 772: @26952 11725 GIM_Try, /*On fail goto*//*Label 825*/ 28682, 11726 GIM_CheckNumOperands, /*MI*/0, /*Expected*/5, 11727 GIM_Try, /*On fail goto*//*Label 826*/ 27016, // Rule ID 2943 // 11728 GIM_CheckFeatures, GIFBS_HasAVX, 11729 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_sse41_mpsadbw, 11730 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, 11731 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, 11732 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, 11733 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 11734 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 11735 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::VR128RegClassID, 11736 // MIs[0] src3 11737 GIM_CheckIsImm, /*MI*/0, /*Op*/4, 11738 // (intrinsic_wo_chain:{ *:[v8i16] } 11132:{ *:[iPTR] }, VR128:{ *:[v16i8] }:$src1, VR128:{ *:[v16i8] }:$src2, (timm:{ *:[i8] }):$src3) => (VMPSADBWrri:{ *:[v8i16] } VR128:{ *:[v16i8] }:$src1, VR128:{ *:[v16i8] }:$src2, (timm:{ *:[i8] }):$src3) 11739 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VMPSADBWrri, 11740 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 11741 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 11742 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src2 11743 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src3 11744 GIR_EraseFromParent, /*InsnID*/0, 11745 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11746 // GIR_Coverage, 2943, 11747 GIR_Done, 11748 // Label 826: @27016 11749 GIM_Try, /*On fail goto*//*Label 827*/ 27075, // Rule ID 2945 // 11750 GIM_CheckFeatures, GIFBS_HasAVX, 11751 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_sse41_dpps, 11752 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 11753 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 11754 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, 11755 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 11756 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 11757 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::VR128RegClassID, 11758 // MIs[0] src3 11759 GIM_CheckIsImm, /*MI*/0, /*Op*/4, 11760 // (intrinsic_wo_chain:{ *:[v4f32] } 11130:{ *:[iPTR] }, VR128:{ *:[v4f32] }:$src1, VR128:{ *:[v4f32] }:$src2, (timm:{ *:[i8] }):$src3) => (VDPPSrri:{ *:[v4f32] } VR128:{ *:[v4f32] }:$src1, VR128:{ *:[v4f32] }:$src2, (timm:{ *:[i8] }):$src3) 11761 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VDPPSrri, 11762 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 11763 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 11764 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src2 11765 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src3 11766 GIR_EraseFromParent, /*InsnID*/0, 11767 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11768 // GIR_Coverage, 2945, 11769 GIR_Done, 11770 // Label 827: @27075 11771 GIM_Try, /*On fail goto*//*Label 828*/ 27134, // Rule ID 2947 // 11772 GIM_CheckFeatures, GIFBS_HasAVX, 11773 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_sse41_dppd, 11774 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 11775 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 11776 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, 11777 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 11778 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 11779 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::VR128RegClassID, 11780 // MIs[0] src3 11781 GIM_CheckIsImm, /*MI*/0, /*Op*/4, 11782 // (intrinsic_wo_chain:{ *:[v2f64] } 11129:{ *:[iPTR] }, VR128:{ *:[v2f64] }:$src1, VR128:{ *:[v2f64] }:$src2, (timm:{ *:[i8] }):$src3) => (VDPPDrri:{ *:[v2f64] } VR128:{ *:[v2f64] }:$src1, VR128:{ *:[v2f64] }:$src2, (timm:{ *:[i8] }):$src3) 11783 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VDPPDrri, 11784 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 11785 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 11786 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src2 11787 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src3 11788 GIR_EraseFromParent, /*InsnID*/0, 11789 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11790 // GIR_Coverage, 2947, 11791 GIR_Done, 11792 // Label 828: @27134 11793 GIM_Try, /*On fail goto*//*Label 829*/ 27193, // Rule ID 2949 // 11794 GIM_CheckFeatures, GIFBS_HasAVX, 11795 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_avx_dp_ps_256, 11796 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s32, 11797 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s32, 11798 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s32, 11799 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID, 11800 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256RegClassID, 11801 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::VR256RegClassID, 11802 // MIs[0] src3 11803 GIM_CheckIsImm, /*MI*/0, /*Op*/4, 11804 // (intrinsic_wo_chain:{ *:[v8f32] } 9983:{ *:[iPTR] }, VR256:{ *:[v8f32] }:$src1, VR256:{ *:[v8f32] }:$src2, (timm:{ *:[i8] }):$src3) => (VDPPSYrri:{ *:[v8f32] } VR256:{ *:[v8f32] }:$src1, VR256:{ *:[v8f32] }:$src2, (timm:{ *:[i8] }):$src3) 11805 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VDPPSYrri, 11806 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 11807 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 11808 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src2 11809 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src3 11810 GIR_EraseFromParent, /*InsnID*/0, 11811 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11812 // GIR_Coverage, 2949, 11813 GIR_Done, 11814 // Label 829: @27193 11815 GIM_Try, /*On fail goto*//*Label 830*/ 27252, // Rule ID 2951 // 11816 GIM_CheckFeatures, GIFBS_HasAVX2, 11817 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_avx2_mpsadbw, 11818 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s16, 11819 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v32s8, 11820 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v32s8, 11821 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID, 11822 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256RegClassID, 11823 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::VR256RegClassID, 11824 // MIs[0] src3 11825 GIM_CheckIsImm, /*MI*/0, /*Op*/4, 11826 // (intrinsic_wo_chain:{ *:[v16i16] } 10052:{ *:[iPTR] }, VR256:{ *:[v32i8] }:$src1, VR256:{ *:[v32i8] }:$src2, (timm:{ *:[i8] }):$src3) => (VMPSADBWYrri:{ *:[v16i16] } VR256:{ *:[v32i8] }:$src1, VR256:{ *:[v32i8] }:$src2, (timm:{ *:[i8] }):$src3) 11827 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VMPSADBWYrri, 11828 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 11829 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 11830 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src2 11831 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src3 11832 GIR_EraseFromParent, /*InsnID*/0, 11833 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11834 // GIR_Coverage, 2951, 11835 GIR_Done, 11836 // Label 830: @27252 11837 GIM_Try, /*On fail goto*//*Label 831*/ 27311, // Rule ID 2953 // 11838 GIM_CheckFeatures, GIFBS_UseSSE41, 11839 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_sse41_mpsadbw, 11840 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, 11841 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, 11842 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, 11843 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 11844 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 11845 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::VR128RegClassID, 11846 // MIs[0] src3 11847 GIM_CheckIsImm, /*MI*/0, /*Op*/4, 11848 // (intrinsic_wo_chain:{ *:[v8i16] } 11132:{ *:[iPTR] }, VR128:{ *:[v16i8] }:$src1, VR128:{ *:[v16i8] }:$src2, (timm:{ *:[i8] }):$src3) => (MPSADBWrri:{ *:[v8i16] } VR128:{ *:[v16i8] }:$src1, VR128:{ *:[v16i8] }:$src2, (timm:{ *:[i8] }):$src3) 11849 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::MPSADBWrri, 11850 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 11851 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 11852 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src2 11853 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src3 11854 GIR_EraseFromParent, /*InsnID*/0, 11855 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11856 // GIR_Coverage, 2953, 11857 GIR_Done, 11858 // Label 831: @27311 11859 GIM_Try, /*On fail goto*//*Label 832*/ 27370, // Rule ID 2955 // 11860 GIM_CheckFeatures, GIFBS_UseSSE41, 11861 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_sse41_dpps, 11862 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 11863 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 11864 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, 11865 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 11866 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 11867 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::VR128RegClassID, 11868 // MIs[0] src3 11869 GIM_CheckIsImm, /*MI*/0, /*Op*/4, 11870 // (intrinsic_wo_chain:{ *:[v4f32] } 11130:{ *:[iPTR] }, VR128:{ *:[v4f32] }:$src1, VR128:{ *:[v4f32] }:$src2, (timm:{ *:[i8] }):$src3) => (DPPSrri:{ *:[v4f32] } VR128:{ *:[v4f32] }:$src1, VR128:{ *:[v4f32] }:$src2, (timm:{ *:[i8] }):$src3) 11871 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::DPPSrri, 11872 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 11873 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 11874 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src2 11875 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src3 11876 GIR_EraseFromParent, /*InsnID*/0, 11877 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11878 // GIR_Coverage, 2955, 11879 GIR_Done, 11880 // Label 832: @27370 11881 GIM_Try, /*On fail goto*//*Label 833*/ 27429, // Rule ID 2957 // 11882 GIM_CheckFeatures, GIFBS_UseSSE41, 11883 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_sse41_dppd, 11884 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 11885 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 11886 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, 11887 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 11888 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 11889 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::VR128RegClassID, 11890 // MIs[0] src3 11891 GIM_CheckIsImm, /*MI*/0, /*Op*/4, 11892 // (intrinsic_wo_chain:{ *:[v2f64] } 11129:{ *:[iPTR] }, VR128:{ *:[v2f64] }:$src1, VR128:{ *:[v2f64] }:$src2, (timm:{ *:[i8] }):$src3) => (DPPDrri:{ *:[v2f64] } VR128:{ *:[v2f64] }:$src1, VR128:{ *:[v2f64] }:$src2, (timm:{ *:[i8] }):$src3) 11893 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::DPPDrri, 11894 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 11895 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 11896 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src2 11897 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src3 11898 GIR_EraseFromParent, /*InsnID*/0, 11899 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11900 // GIR_Coverage, 2957, 11901 GIR_Done, 11902 // Label 833: @27429 11903 GIM_Try, /*On fail goto*//*Label 834*/ 27488, // Rule ID 3009 // 11904 GIM_CheckFeatures, GIFBS_HasSHA, 11905 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_sha1rnds4, 11906 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 11907 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 11908 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, 11909 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 11910 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 11911 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::VR128RegClassID, 11912 // MIs[0] src3 11913 GIM_CheckIsImm, /*MI*/0, /*Op*/4, 11914 // (intrinsic_wo_chain:{ *:[v4i32] } 11016:{ *:[iPTR] }, VR128:{ *:[v4i32] }:$src1, VR128:{ *:[v4i32] }:$src2, (timm:{ *:[i8] }):$src3) => (SHA1RNDS4rri:{ *:[v4i32] } VR128:{ *:[v4i32] }:$src1, VR128:{ *:[v4i32] }:$src2, (timm:{ *:[i8] }):$src3) 11915 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SHA1RNDS4rri, 11916 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 11917 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 11918 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src2 11919 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src3 11920 GIR_EraseFromParent, /*InsnID*/0, 11921 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11922 // GIR_Coverage, 3009, 11923 GIR_Done, 11924 // Label 834: @27488 11925 GIM_Try, /*On fail goto*//*Label 835*/ 27547, // Rule ID 3055 // 11926 GIM_CheckFeatures, GIFBS_HasPCLMUL_NoAVX, 11927 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_pclmulqdq, 11928 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 11929 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 11930 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, 11931 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 11932 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 11933 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::VR128RegClassID, 11934 // MIs[0] src3 11935 GIM_CheckIsImm, /*MI*/0, /*Op*/4, 11936 // (intrinsic_wo_chain:{ *:[v2i64] } 10982:{ *:[iPTR] }, VR128:{ *:[v2i64] }:$src1, VR128:{ *:[v2i64] }:$src2, (timm:{ *:[i8] }):$src3) => (PCLMULQDQrr:{ *:[v2i64] } VR128:{ *:[v2i64] }:$src1, VR128:{ *:[v2i64] }:$src2, (timm:{ *:[i8] }):$src3) 11937 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::PCLMULQDQrr, 11938 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 11939 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 11940 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src2 11941 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src3 11942 GIR_EraseFromParent, /*InsnID*/0, 11943 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11944 // GIR_Coverage, 3055, 11945 GIR_Done, 11946 // Label 835: @27547 11947 GIM_Try, /*On fail goto*//*Label 836*/ 27606, // Rule ID 3057 // 11948 GIM_CheckFeatures, GIFBS_HasAVX_HasPCLMUL_NoVLX_Or_NoVPCLMULQDQ, 11949 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_pclmulqdq, 11950 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 11951 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 11952 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, 11953 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 11954 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 11955 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::VR128RegClassID, 11956 // MIs[0] src3 11957 GIM_CheckIsImm, /*MI*/0, /*Op*/4, 11958 // (intrinsic_wo_chain:{ *:[v2i64] } 10982:{ *:[iPTR] }, VR128:{ *:[v2i64] }:$src1, VR128:{ *:[v2i64] }:$src2, (timm:{ *:[i8] }):$src3) => (VPCLMULQDQrr:{ *:[v2i64] } VR128:{ *:[v2i64] }:$src1, VR128:{ *:[v2i64] }:$src2, (timm:{ *:[i8] }):$src3) 11959 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VPCLMULQDQrr, 11960 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 11961 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 11962 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src2 11963 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src3 11964 GIR_EraseFromParent, /*InsnID*/0, 11965 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11966 // GIR_Coverage, 3057, 11967 GIR_Done, 11968 // Label 836: @27606 11969 GIM_Try, /*On fail goto*//*Label 837*/ 27665, // Rule ID 3059 // 11970 GIM_CheckFeatures, GIFBS_HasVPCLMULQDQ_NoVLX, 11971 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_pclmulqdq_256, 11972 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s64, 11973 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s64, 11974 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s64, 11975 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID, 11976 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256RegClassID, 11977 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::VR256RegClassID, 11978 // MIs[0] src3 11979 GIM_CheckIsImm, /*MI*/0, /*Op*/4, 11980 // (intrinsic_wo_chain:{ *:[v4i64] } 10983:{ *:[iPTR] }, VR256:{ *:[v4i64] }:$src1, VR256:{ *:[v4i64] }:$src2, (timm:{ *:[i8] }):$src3) => (VPCLMULQDQYrr:{ *:[v4i64] } VR256:{ *:[v4i64] }:$src1, VR256:{ *:[v4i64] }:$src2, (timm:{ *:[i8] }):$src3) 11981 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VPCLMULQDQYrr, 11982 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 11983 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 11984 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src2 11985 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src3 11986 GIR_EraseFromParent, /*InsnID*/0, 11987 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11988 // GIR_Coverage, 3059, 11989 GIR_Done, 11990 // Label 837: @27665 11991 GIM_Try, /*On fail goto*//*Label 838*/ 27724, // Rule ID 13789 // 11992 GIM_CheckFeatures, GIFBS_HasAVX512_HasVPCLMULQDQ, 11993 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_pclmulqdq_512, 11994 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s64, 11995 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s64, 11996 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s64, 11997 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 11998 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR512RegClassID, 11999 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::VR512RegClassID, 12000 // MIs[0] src3 12001 GIM_CheckIsImm, /*MI*/0, /*Op*/4, 12002 // (intrinsic_wo_chain:{ *:[v8i64] } 10984:{ *:[iPTR] }, VR512:{ *:[v8i64] }:$src1, VR512:{ *:[v8i64] }:$src2, (timm:{ *:[i8] }):$src3) => (VPCLMULQDQZrr:{ *:[v8i64] } VR512:{ *:[v8i64] }:$src1, VR512:{ *:[v8i64] }:$src2, (timm:{ *:[i8] }):$src3) 12003 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VPCLMULQDQZrr, 12004 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 12005 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 12006 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src2 12007 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src3 12008 GIR_EraseFromParent, /*InsnID*/0, 12009 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12010 // GIR_Coverage, 13789, 12011 GIR_Done, 12012 // Label 838: @27724 12013 GIM_Try, /*On fail goto*//*Label 839*/ 27783, // Rule ID 13791 // 12014 GIM_CheckFeatures, GIFBS_HasVLX_HasVPCLMULQDQ, 12015 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_pclmulqdq, 12016 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 12017 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 12018 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, 12019 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID, 12020 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128XRegClassID, 12021 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::VR128XRegClassID, 12022 // MIs[0] src3 12023 GIM_CheckIsImm, /*MI*/0, /*Op*/4, 12024 // (intrinsic_wo_chain:{ *:[v2i64] } 10982:{ *:[iPTR] }, VR128X:{ *:[v2i64] }:$src1, VR128X:{ *:[v2i64] }:$src2, (timm:{ *:[i8] }):$src3) => (VPCLMULQDQZ128rr:{ *:[v2i64] } VR128X:{ *:[v2i64] }:$src1, VR128X:{ *:[v2i64] }:$src2, (timm:{ *:[i8] }):$src3) 12025 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VPCLMULQDQZ128rr, 12026 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 12027 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 12028 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src2 12029 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src3 12030 GIR_EraseFromParent, /*InsnID*/0, 12031 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12032 // GIR_Coverage, 13791, 12033 GIR_Done, 12034 // Label 839: @27783 12035 GIM_Try, /*On fail goto*//*Label 840*/ 27842, // Rule ID 13793 // 12036 GIM_CheckFeatures, GIFBS_HasVLX_HasVPCLMULQDQ, 12037 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_pclmulqdq_256, 12038 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s64, 12039 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s64, 12040 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s64, 12041 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID, 12042 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256XRegClassID, 12043 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::VR256XRegClassID, 12044 // MIs[0] src3 12045 GIM_CheckIsImm, /*MI*/0, /*Op*/4, 12046 // (intrinsic_wo_chain:{ *:[v4i64] } 10983:{ *:[iPTR] }, VR256X:{ *:[v4i64] }:$src1, VR256X:{ *:[v4i64] }:$src2, (timm:{ *:[i8] }):$src3) => (VPCLMULQDQZ256rr:{ *:[v4i64] } VR256X:{ *:[v4i64] }:$src1, VR256X:{ *:[v4i64] }:$src2, (timm:{ *:[i8] }):$src3) 12047 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VPCLMULQDQZ256rr, 12048 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 12049 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 12050 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src2 12051 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src3 12052 GIR_EraseFromParent, /*InsnID*/0, 12053 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12054 // GIR_Coverage, 13793, 12055 GIR_Done, 12056 // Label 840: @27842 12057 GIM_Try, /*On fail goto*//*Label 841*/ 27906, // Rule ID 1351 // 12058 GIM_CheckFeatures, GIFBS_HasXOP, 12059 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_xop_vpmadcswd, 12060 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 12061 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 12062 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, 12063 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32, 12064 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 12065 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 12066 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::VR128RegClassID, 12067 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/X86::VR128RegClassID, 12068 // (intrinsic_wo_chain:{ *:[v4i32] } 11299:{ *:[iPTR] }, VR128:{ *:[v8i16] }:$src1, VR128:{ *:[v8i16] }:$src2, VR128:{ *:[v4i32] }:$src3) => (VPMADCSWDrr:{ *:[v4i32] } VR128:{ *:[v8i16] }:$src1, VR128:{ *:[v8i16] }:$src2, VR128:{ *:[v4i32] }:$src3) 12069 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VPMADCSWDrr, 12070 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 12071 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 12072 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src2 12073 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src3 12074 GIR_EraseFromParent, /*InsnID*/0, 12075 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12076 // GIR_Coverage, 1351, 12077 GIR_Done, 12078 // Label 841: @27906 12079 GIM_Try, /*On fail goto*//*Label 842*/ 27970, // Rule ID 1353 // 12080 GIM_CheckFeatures, GIFBS_HasXOP, 12081 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_xop_vpmadcsswd, 12082 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 12083 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 12084 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, 12085 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32, 12086 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 12087 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 12088 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::VR128RegClassID, 12089 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/X86::VR128RegClassID, 12090 // (intrinsic_wo_chain:{ *:[v4i32] } 11298:{ *:[iPTR] }, VR128:{ *:[v8i16] }:$src1, VR128:{ *:[v8i16] }:$src2, VR128:{ *:[v4i32] }:$src3) => (VPMADCSSWDrr:{ *:[v4i32] } VR128:{ *:[v8i16] }:$src1, VR128:{ *:[v8i16] }:$src2, VR128:{ *:[v4i32] }:$src3) 12091 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VPMADCSSWDrr, 12092 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 12093 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 12094 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src2 12095 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src3 12096 GIR_EraseFromParent, /*InsnID*/0, 12097 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12098 // GIR_Coverage, 1353, 12099 GIR_Done, 12100 // Label 842: @27970 12101 GIM_Try, /*On fail goto*//*Label 843*/ 28034, // Rule ID 1355 // 12102 GIM_CheckFeatures, GIFBS_HasXOP, 12103 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_xop_vpmacsww, 12104 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, 12105 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 12106 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, 12107 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s16, 12108 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 12109 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 12110 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::VR128RegClassID, 12111 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/X86::VR128RegClassID, 12112 // (intrinsic_wo_chain:{ *:[v8i16] } 11297:{ *:[iPTR] }, VR128:{ *:[v8i16] }:$src1, VR128:{ *:[v8i16] }:$src2, VR128:{ *:[v8i16] }:$src3) => (VPMACSWWrr:{ *:[v8i16] } VR128:{ *:[v8i16] }:$src1, VR128:{ *:[v8i16] }:$src2, VR128:{ *:[v8i16] }:$src3) 12113 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VPMACSWWrr, 12114 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 12115 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 12116 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src2 12117 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src3 12118 GIR_EraseFromParent, /*InsnID*/0, 12119 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12120 // GIR_Coverage, 1355, 12121 GIR_Done, 12122 // Label 843: @28034 12123 GIM_Try, /*On fail goto*//*Label 844*/ 28098, // Rule ID 1357 // 12124 GIM_CheckFeatures, GIFBS_HasXOP, 12125 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_xop_vpmacswd, 12126 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 12127 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 12128 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, 12129 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32, 12130 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 12131 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 12132 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::VR128RegClassID, 12133 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/X86::VR128RegClassID, 12134 // (intrinsic_wo_chain:{ *:[v4i32] } 11296:{ *:[iPTR] }, VR128:{ *:[v8i16] }:$src1, VR128:{ *:[v8i16] }:$src2, VR128:{ *:[v4i32] }:$src3) => (VPMACSWDrr:{ *:[v4i32] } VR128:{ *:[v8i16] }:$src1, VR128:{ *:[v8i16] }:$src2, VR128:{ *:[v4i32] }:$src3) 12135 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VPMACSWDrr, 12136 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 12137 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 12138 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src2 12139 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src3 12140 GIR_EraseFromParent, /*InsnID*/0, 12141 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12142 // GIR_Coverage, 1357, 12143 GIR_Done, 12144 // Label 844: @28098 12145 GIM_Try, /*On fail goto*//*Label 845*/ 28162, // Rule ID 1359 // 12146 GIM_CheckFeatures, GIFBS_HasXOP, 12147 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_xop_vpmacssww, 12148 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, 12149 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 12150 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, 12151 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s16, 12152 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 12153 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 12154 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::VR128RegClassID, 12155 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/X86::VR128RegClassID, 12156 // (intrinsic_wo_chain:{ *:[v8i16] } 11295:{ *:[iPTR] }, VR128:{ *:[v8i16] }:$src1, VR128:{ *:[v8i16] }:$src2, VR128:{ *:[v8i16] }:$src3) => (VPMACSSWWrr:{ *:[v8i16] } VR128:{ *:[v8i16] }:$src1, VR128:{ *:[v8i16] }:$src2, VR128:{ *:[v8i16] }:$src3) 12157 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VPMACSSWWrr, 12158 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 12159 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 12160 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src2 12161 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src3 12162 GIR_EraseFromParent, /*InsnID*/0, 12163 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12164 // GIR_Coverage, 1359, 12165 GIR_Done, 12166 // Label 845: @28162 12167 GIM_Try, /*On fail goto*//*Label 846*/ 28226, // Rule ID 1361 // 12168 GIM_CheckFeatures, GIFBS_HasXOP, 12169 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_xop_vpmacsswd, 12170 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 12171 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 12172 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, 12173 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32, 12174 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 12175 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 12176 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::VR128RegClassID, 12177 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/X86::VR128RegClassID, 12178 // (intrinsic_wo_chain:{ *:[v4i32] } 11294:{ *:[iPTR] }, VR128:{ *:[v8i16] }:$src1, VR128:{ *:[v8i16] }:$src2, VR128:{ *:[v4i32] }:$src3) => (VPMACSSWDrr:{ *:[v4i32] } VR128:{ *:[v8i16] }:$src1, VR128:{ *:[v8i16] }:$src2, VR128:{ *:[v4i32] }:$src3) 12179 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VPMACSSWDrr, 12180 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 12181 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 12182 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src2 12183 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src3 12184 GIR_EraseFromParent, /*InsnID*/0, 12185 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12186 // GIR_Coverage, 1361, 12187 GIR_Done, 12188 // Label 846: @28226 12189 GIM_Try, /*On fail goto*//*Label 847*/ 28290, // Rule ID 1363 // 12190 GIM_CheckFeatures, GIFBS_HasXOP, 12191 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_xop_vpmacssdql, 12192 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 12193 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 12194 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, 12195 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v2s64, 12196 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 12197 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 12198 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::VR128RegClassID, 12199 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/X86::VR128RegClassID, 12200 // (intrinsic_wo_chain:{ *:[v2i64] } 11293:{ *:[iPTR] }, VR128:{ *:[v4i32] }:$src1, VR128:{ *:[v4i32] }:$src2, VR128:{ *:[v2i64] }:$src3) => (VPMACSSDQLrr:{ *:[v2i64] } VR128:{ *:[v4i32] }:$src1, VR128:{ *:[v4i32] }:$src2, VR128:{ *:[v2i64] }:$src3) 12201 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VPMACSSDQLrr, 12202 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 12203 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 12204 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src2 12205 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src3 12206 GIR_EraseFromParent, /*InsnID*/0, 12207 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12208 // GIR_Coverage, 1363, 12209 GIR_Done, 12210 // Label 847: @28290 12211 GIM_Try, /*On fail goto*//*Label 848*/ 28354, // Rule ID 1365 // 12212 GIM_CheckFeatures, GIFBS_HasXOP, 12213 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_xop_vpmacssdqh, 12214 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 12215 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 12216 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, 12217 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v2s64, 12218 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 12219 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 12220 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::VR128RegClassID, 12221 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/X86::VR128RegClassID, 12222 // (intrinsic_wo_chain:{ *:[v2i64] } 11292:{ *:[iPTR] }, VR128:{ *:[v4i32] }:$src1, VR128:{ *:[v4i32] }:$src2, VR128:{ *:[v2i64] }:$src3) => (VPMACSSDQHrr:{ *:[v2i64] } VR128:{ *:[v4i32] }:$src1, VR128:{ *:[v4i32] }:$src2, VR128:{ *:[v2i64] }:$src3) 12223 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VPMACSSDQHrr, 12224 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 12225 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 12226 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src2 12227 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src3 12228 GIR_EraseFromParent, /*InsnID*/0, 12229 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12230 // GIR_Coverage, 1365, 12231 GIR_Done, 12232 // Label 848: @28354 12233 GIM_Try, /*On fail goto*//*Label 849*/ 28418, // Rule ID 1367 // 12234 GIM_CheckFeatures, GIFBS_HasXOP, 12235 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_xop_vpmacssdd, 12236 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 12237 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 12238 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, 12239 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32, 12240 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 12241 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 12242 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::VR128RegClassID, 12243 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/X86::VR128RegClassID, 12244 // (intrinsic_wo_chain:{ *:[v4i32] } 11291:{ *:[iPTR] }, VR128:{ *:[v4i32] }:$src1, VR128:{ *:[v4i32] }:$src2, VR128:{ *:[v4i32] }:$src3) => (VPMACSSDDrr:{ *:[v4i32] } VR128:{ *:[v4i32] }:$src1, VR128:{ *:[v4i32] }:$src2, VR128:{ *:[v4i32] }:$src3) 12245 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VPMACSSDDrr, 12246 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 12247 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 12248 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src2 12249 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src3 12250 GIR_EraseFromParent, /*InsnID*/0, 12251 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12252 // GIR_Coverage, 1367, 12253 GIR_Done, 12254 // Label 849: @28418 12255 GIM_Try, /*On fail goto*//*Label 850*/ 28482, // Rule ID 1369 // 12256 GIM_CheckFeatures, GIFBS_HasXOP, 12257 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_xop_vpmacsdql, 12258 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 12259 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 12260 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, 12261 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v2s64, 12262 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 12263 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 12264 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::VR128RegClassID, 12265 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/X86::VR128RegClassID, 12266 // (intrinsic_wo_chain:{ *:[v2i64] } 11290:{ *:[iPTR] }, VR128:{ *:[v4i32] }:$src1, VR128:{ *:[v4i32] }:$src2, VR128:{ *:[v2i64] }:$src3) => (VPMACSDQLrr:{ *:[v2i64] } VR128:{ *:[v4i32] }:$src1, VR128:{ *:[v4i32] }:$src2, VR128:{ *:[v2i64] }:$src3) 12267 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VPMACSDQLrr, 12268 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 12269 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 12270 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src2 12271 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src3 12272 GIR_EraseFromParent, /*InsnID*/0, 12273 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12274 // GIR_Coverage, 1369, 12275 GIR_Done, 12276 // Label 850: @28482 12277 GIM_Try, /*On fail goto*//*Label 851*/ 28546, // Rule ID 1371 // 12278 GIM_CheckFeatures, GIFBS_HasXOP, 12279 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_xop_vpmacsdqh, 12280 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 12281 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 12282 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, 12283 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v2s64, 12284 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 12285 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 12286 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::VR128RegClassID, 12287 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/X86::VR128RegClassID, 12288 // (intrinsic_wo_chain:{ *:[v2i64] } 11289:{ *:[iPTR] }, VR128:{ *:[v4i32] }:$src1, VR128:{ *:[v4i32] }:$src2, VR128:{ *:[v2i64] }:$src3) => (VPMACSDQHrr:{ *:[v2i64] } VR128:{ *:[v4i32] }:$src1, VR128:{ *:[v4i32] }:$src2, VR128:{ *:[v2i64] }:$src3) 12289 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VPMACSDQHrr, 12290 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 12291 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 12292 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src2 12293 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src3 12294 GIR_EraseFromParent, /*InsnID*/0, 12295 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12296 // GIR_Coverage, 1371, 12297 GIR_Done, 12298 // Label 851: @28546 12299 GIM_Try, /*On fail goto*//*Label 852*/ 28610, // Rule ID 1373 // 12300 GIM_CheckFeatures, GIFBS_HasXOP, 12301 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_xop_vpmacsdd, 12302 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 12303 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 12304 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, 12305 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32, 12306 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 12307 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 12308 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::VR128RegClassID, 12309 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/X86::VR128RegClassID, 12310 // (intrinsic_wo_chain:{ *:[v4i32] } 11288:{ *:[iPTR] }, VR128:{ *:[v4i32] }:$src1, VR128:{ *:[v4i32] }:$src2, VR128:{ *:[v4i32] }:$src3) => (VPMACSDDrr:{ *:[v4i32] } VR128:{ *:[v4i32] }:$src1, VR128:{ *:[v4i32] }:$src2, VR128:{ *:[v4i32] }:$src3) 12311 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VPMACSDDrr, 12312 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 12313 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 12314 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src2 12315 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src3 12316 GIR_EraseFromParent, /*InsnID*/0, 12317 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12318 // GIR_Coverage, 1373, 12319 GIR_Done, 12320 // Label 852: @28610 12321 GIM_Try, /*On fail goto*//*Label 853*/ 28681, // Rule ID 3017 // 12322 GIM_CheckFeatures, GIFBS_HasSHA, 12323 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_sha256rnds2, 12324 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 12325 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 12326 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, 12327 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32, 12328 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 12329 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 12330 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::VR128RegClassID, 12331 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/X86::VR128RegClassID, 12332 // (intrinsic_wo_chain:{ *:[v4i32] } 11019:{ *:[iPTR] }, VR128:{ *:[v4i32] }:$src1, VR128:{ *:[v4i32] }:$src2, XMM0:{ *:[v4i32] }) => (SHA256RNDS2rr:{ *:[v4i32] } VR128:{ *:[v4i32] }:$src1, VR128:{ *:[v4i32] }:$src2) 12333 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, 12334 GIR_AddRegister, /*InsnID*/1, X86::XMM0, /*AddRegisterRegFlags*/RegState::Define, 12335 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // XMM0 12336 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SHA256RNDS2rr, 12337 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 12338 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 12339 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src2 12340 GIR_EraseFromParent, /*InsnID*/0, 12341 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12342 // GIR_Coverage, 3017, 12343 GIR_Done, 12344 // Label 853: @28681 12345 GIM_Reject, 12346 // Label 825: @28682 12347 GIM_Reject, 12348 // Label 10: @28683 12349 GIM_Try, /*On fail goto*//*Label 854*/ 29053, 12350 GIM_CheckNumOperands, /*MI*/0, /*Expected*/1, 12351 GIM_Try, /*On fail goto*//*Label 855*/ 28708, // Rule ID 120 // 12352 GIM_CheckFeatures, GIFBS_HasSERIALIZE, 12353 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::x86_serialize, 12354 // (intrinsic_void 11011:{ *:[iPTR] }) => (SERIALIZE) 12355 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SERIALIZE, 12356 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 12357 GIR_EraseFromParent, /*InsnID*/0, 12358 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12359 // GIR_Coverage, 120, 12360 GIR_Done, 12361 // Label 855: @28708 12362 GIM_Try, /*On fail goto*//*Label 856*/ 28728, // Rule ID 121 // 12363 GIM_CheckFeatures, GIFBS_HasTSXLDTRK, 12364 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::x86_xsusldtrk, 12365 // (intrinsic_void 11323:{ *:[iPTR] }) => (XSUSLDTRK) 12366 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::XSUSLDTRK, 12367 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 12368 GIR_EraseFromParent, /*InsnID*/0, 12369 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12370 // GIR_Coverage, 121, 12371 GIR_Done, 12372 // Label 856: @28728 12373 GIM_Try, /*On fail goto*//*Label 857*/ 28748, // Rule ID 122 // 12374 GIM_CheckFeatures, GIFBS_HasTSXLDTRK, 12375 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::x86_xresldtrk, 12376 // (intrinsic_void 11309:{ *:[iPTR] }) => (XRESLDTRK) 12377 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::XRESLDTRK, 12378 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 12379 GIR_EraseFromParent, /*InsnID*/0, 12380 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12381 // GIR_Coverage, 122, 12382 GIR_Done, 12383 // Label 857: @28748 12384 GIM_Try, /*On fail goto*//*Label 858*/ 28768, // Rule ID 123 // 12385 GIM_CheckFeatures, GIFBS_HasUINTR_In64BitMode, 12386 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::x86_clui, 12387 // (intrinsic_void 10873:{ *:[iPTR] }) => (CLUI) 12388 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::CLUI, 12389 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 12390 GIR_EraseFromParent, /*InsnID*/0, 12391 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12392 // GIR_Coverage, 123, 12393 GIR_Done, 12394 // Label 858: @28768 12395 GIM_Try, /*On fail goto*//*Label 859*/ 28788, // Rule ID 124 // 12396 GIM_CheckFeatures, GIFBS_HasUINTR_In64BitMode, 12397 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::x86_stui, 12398 // (intrinsic_void 11193:{ *:[iPTR] }) => (STUI) 12399 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::STUI, 12400 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 12401 GIR_EraseFromParent, /*InsnID*/0, 12402 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12403 // GIR_Coverage, 124, 12404 GIR_Done, 12405 // Label 859: @28788 12406 GIM_Try, /*On fail goto*//*Label 860*/ 28806, // Rule ID 2202 // 12407 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::x86_sse2_pause, 12408 // (intrinsic_void 11088:{ *:[iPTR] }) => (PAUSE) 12409 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::PAUSE, 12410 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 12411 GIR_EraseFromParent, /*InsnID*/0, 12412 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12413 // GIR_Coverage, 2202, 12414 GIR_Done, 12415 // Label 860: @28806 12416 GIM_Try, /*On fail goto*//*Label 861*/ 28826, // Rule ID 2203 // 12417 GIM_CheckFeatures, GIFBS_HasSSE1, 12418 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::x86_sse_sfence, 12419 // (intrinsic_void 11050:{ *:[iPTR] }) => (SFENCE) 12420 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SFENCE, 12421 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 12422 GIR_EraseFromParent, /*InsnID*/0, 12423 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12424 // GIR_Coverage, 2203, 12425 GIR_Done, 12426 // Label 861: @28826 12427 GIM_Try, /*On fail goto*//*Label 862*/ 28846, // Rule ID 2204 // 12428 GIM_CheckFeatures, GIFBS_HasSSE2, 12429 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::x86_sse2_lfence, 12430 // (intrinsic_void 11077:{ *:[iPTR] }) => (LFENCE) 12431 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::LFENCE, 12432 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 12433 GIR_EraseFromParent, /*InsnID*/0, 12434 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12435 // GIR_Coverage, 2204, 12436 GIR_Done, 12437 // Label 862: @28846 12438 GIM_Try, /*On fail goto*//*Label 863*/ 28866, // Rule ID 2205 // 12439 GIM_CheckFeatures, GIFBS_HasMFence, 12440 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::x86_sse2_mfence, 12441 // (intrinsic_void 11081:{ *:[iPTR] }) => (MFENCE) 12442 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::MFENCE, 12443 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 12444 GIR_EraseFromParent, /*InsnID*/0, 12445 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12446 // GIR_Coverage, 2205, 12447 GIR_Done, 12448 // Label 863: @28866 12449 GIM_Try, /*On fail goto*//*Label 864*/ 28882, // Rule ID 3111 // 12450 GIM_CheckFeatures, GIFBS_HasAVX, 12451 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::x86_avx_vzeroall, 12452 // (intrinsic_void 10026:{ *:[iPTR] }) => (VZEROALL) 12453 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VZEROALL, 12454 GIR_EraseFromParent, /*InsnID*/0, 12455 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12456 // GIR_Coverage, 3111, 12457 GIR_Done, 12458 // Label 864: @28882 12459 GIM_Try, /*On fail goto*//*Label 865*/ 28898, // Rule ID 3112 // 12460 GIM_CheckFeatures, GIFBS_HasAVX, 12461 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::x86_avx_vzeroupper, 12462 // (intrinsic_void 10027:{ *:[iPTR] }) => (VZEROUPPER) 12463 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VZEROUPPER, 12464 GIR_EraseFromParent, /*InsnID*/0, 12465 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12466 // GIR_Coverage, 3112, 12467 GIR_Done, 12468 // Label 865: @28898 12469 GIM_Try, /*On fail goto*//*Label 866*/ 28918, // Rule ID 15174 // 12470 GIM_CheckFeatures, GIFBS_HasMMX, 12471 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::x86_mmx_emms, 12472 // (intrinsic_void 10908:{ *:[iPTR] }) => (MMX_EMMS:{ *:[x86mmx] }) 12473 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::MMX_EMMS, 12474 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 12475 GIR_EraseFromParent, /*InsnID*/0, 12476 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12477 // GIR_Coverage, 15174, 12478 GIR_Done, 12479 // Label 866: @28918 12480 GIM_Try, /*On fail goto*//*Label 867*/ 28938, // Rule ID 15393 // 12481 GIM_CheckFeatures, GIFBS_Has3DNow, 12482 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::x86_mmx_femms, 12483 // (intrinsic_void 10909:{ *:[iPTR] }) => (FEMMS:{ *:[x86mmx] }) 12484 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::FEMMS, 12485 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 12486 GIR_EraseFromParent, /*InsnID*/0, 12487 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12488 // GIR_Coverage, 15393, 12489 GIR_Done, 12490 // Label 867: @28938 12491 GIM_Try, /*On fail goto*//*Label 868*/ 28958, // Rule ID 15408 // 12492 GIM_CheckFeatures, GIFBS_HasRTM, 12493 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::x86_xend, 12494 // (intrinsic_void 11261:{ *:[iPTR] }) => (XEND) 12495 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::XEND, 12496 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 12497 GIR_EraseFromParent, /*InsnID*/0, 12498 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12499 // GIR_Coverage, 15408, 12500 GIR_Done, 12501 // Label 868: @28958 12502 GIM_Try, /*On fail goto*//*Label 869*/ 28978, // Rule ID 15418 // 12503 GIM_CheckFeatures, GIFBS_HasAMXTILE_In64BitMode, 12504 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::x86_tilerelease, 12505 // (intrinsic_void 11215:{ *:[iPTR] }) => (TILERELEASE:{ *:[x86amx] }) 12506 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::TILERELEASE, 12507 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 12508 GIR_EraseFromParent, /*InsnID*/0, 12509 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12510 // GIR_Coverage, 15418, 12511 GIR_Done, 12512 // Label 869: @28978 12513 GIM_Try, /*On fail goto*//*Label 870*/ 28996, // Rule ID 15445 // 12514 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::x86_wbinvd, 12515 // (intrinsic_void 11248:{ *:[iPTR] }) => (WBINVD) 12516 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::WBINVD, 12517 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 12518 GIR_EraseFromParent, /*InsnID*/0, 12519 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12520 // GIR_Coverage, 15445, 12521 GIR_Done, 12522 // Label 870: @28996 12523 GIM_Try, /*On fail goto*//*Label 871*/ 29016, // Rule ID 15446 // 12524 GIM_CheckFeatures, GIFBS_HasWBNOINVD, 12525 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::x86_wbnoinvd, 12526 // (intrinsic_void 11249:{ *:[iPTR] }) => (WBNOINVD) 12527 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::WBNOINVD, 12528 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 12529 GIR_EraseFromParent, /*InsnID*/0, 12530 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12531 // GIR_Coverage, 15446, 12532 GIR_Done, 12533 // Label 871: @29016 12534 GIM_Try, /*On fail goto*//*Label 872*/ 29034, // Rule ID 15451 // 12535 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::x86_saveprevssp, 12536 // (intrinsic_void 11006:{ *:[iPTR] }) => (SAVEPREVSSP) 12537 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SAVEPREVSSP, 12538 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 12539 GIR_EraseFromParent, /*InsnID*/0, 12540 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12541 // GIR_Coverage, 15451, 12542 GIR_Done, 12543 // Label 872: @29034 12544 GIM_Try, /*On fail goto*//*Label 873*/ 29052, // Rule ID 15457 // 12545 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::x86_setssbsy, 12546 // (intrinsic_void 11012:{ *:[iPTR] }) => (SETSSBSY) 12547 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SETSSBSY, 12548 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 12549 GIR_EraseFromParent, /*InsnID*/0, 12550 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12551 // GIR_Coverage, 15457, 12552 GIR_Done, 12553 // Label 873: @29052 12554 GIM_Reject, 12555 // Label 854: @29053 12556 GIM_Try, /*On fail goto*//*Label 874*/ 30039, 12557 GIM_CheckNumOperands, /*MI*/0, /*Expected*/2, 12558 GIM_Try, /*On fail goto*//*Label 875*/ 29080, // Rule ID 15442 // 12559 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::x86_int, 12560 // MIs[0] Operand 1 12561 GIM_CheckLiteralInt, /*MI*/0, /*Op*/1, 3, 12562 // (intrinsic_void 10898:{ *:[iPTR] }, 3:{ *:[i8] }) => (INT3) 12563 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::INT3, 12564 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 12565 GIR_EraseFromParent, /*InsnID*/0, 12566 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12567 // GIR_Coverage, 15442, 12568 GIR_Done, 12569 // Label 875: @29080 12570 GIM_Try, /*On fail goto*//*Label 876*/ 29107, // Rule ID 15410 // 12571 GIM_CheckFeatures, GIFBS_HasRTM, 12572 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::x86_xabort, 12573 // MIs[0] imm 12574 GIM_CheckIsImm, /*MI*/0, /*Op*/1, 12575 // (intrinsic_void 11259:{ *:[iPTR] }, (timm:{ *:[i8] }):$imm) => (XABORT (timm:{ *:[i8] }):$imm) 12576 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::XABORT, 12577 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // imm 12578 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 12579 GIR_EraseFromParent, /*InsnID*/0, 12580 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12581 // GIR_Coverage, 15410, 12582 GIR_Done, 12583 // Label 876: @29107 12584 GIM_Try, /*On fail goto*//*Label 877*/ 29134, // Rule ID 15420 // 12585 GIM_CheckFeatures, GIFBS_HasAMXTILE_In64BitMode, 12586 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::x86_tilezero, 12587 // MIs[0] src 12588 GIM_CheckIsImm, /*MI*/0, /*Op*/1, 12589 // (intrinsic_void 11218:{ *:[iPTR] }, (timm:{ *:[i8] }):$src) => (PTILEZERO (timm:{ *:[i8] }):$src) 12590 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::PTILEZERO, 12591 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 12592 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 12593 GIR_EraseFromParent, /*InsnID*/0, 12594 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12595 // GIR_Coverage, 15420, 12596 GIR_Done, 12597 // Label 877: @29134 12598 GIM_Try, /*On fail goto*//*Label 878*/ 29159, // Rule ID 15444 // 12599 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::x86_int, 12600 // MIs[0] trap 12601 GIM_CheckIsImm, /*MI*/0, /*Op*/1, 12602 // (intrinsic_void 10898:{ *:[iPTR] }, (timm:{ *:[i8] }):$trap) => (INT (timm:{ *:[i8] }):$trap) 12603 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::INT, 12604 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // trap 12605 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 12606 GIR_EraseFromParent, /*InsnID*/0, 12607 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12608 // GIR_Coverage, 15444, 12609 GIR_Done, 12610 // Label 878: @29159 12611 GIM_Try, /*On fail goto*//*Label 879*/ 29191, // Rule ID 1 // 12612 GIM_CheckFeatures, GIFBS_Not64BitMode, 12613 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_flags_read_u32, 12614 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, 12615 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID, 12616 // (intrinsic_w_chain:{ *:[i32] } 10884:{ *:[iPTR] }) => (RDFLAGS32:{ *:[i32] }:{ *:[i32] }) 12617 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::RDFLAGS32, 12618 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 12619 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 12620 GIR_EraseFromParent, /*InsnID*/0, 12621 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12622 // GIR_Coverage, 1, 12623 GIR_Done, 12624 // Label 879: @29191 12625 GIM_Try, /*On fail goto*//*Label 880*/ 29223, // Rule ID 2 // 12626 GIM_CheckFeatures, GIFBS_In64BitMode, 12627 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_flags_read_u64, 12628 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, 12629 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID, 12630 // (intrinsic_w_chain:{ *:[i64] } 10885:{ *:[iPTR] }) => (RDFLAGS64:{ *:[i64] }:{ *:[i32] }) 12631 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::RDFLAGS64, 12632 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 12633 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 12634 GIR_EraseFromParent, /*InsnID*/0, 12635 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12636 // GIR_Coverage, 2, 12637 GIR_Done, 12638 // Label 880: @29223 12639 GIM_Try, /*On fail goto*//*Label 881*/ 29255, // Rule ID 94 // 12640 GIM_CheckFeatures, GIFBS_HasLWP, 12641 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_slwpcb, 12642 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, 12643 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID, 12644 // (intrinsic_w_chain:{ *:[i32] } 11020:{ *:[iPTR] }) => (SLWPCB:{ *:[i32] }) 12645 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SLWPCB, 12646 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 12647 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 12648 GIR_EraseFromParent, /*InsnID*/0, 12649 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12650 // GIR_Coverage, 94, 12651 GIR_Done, 12652 // Label 881: @29255 12653 GIM_Try, /*On fail goto*//*Label 882*/ 29287, // Rule ID 96 // 12654 GIM_CheckFeatures, GIFBS_HasLWP, 12655 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_slwpcb, 12656 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, 12657 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID, 12658 // (intrinsic_w_chain:{ *:[i64] } 11020:{ *:[iPTR] }) => (SLWPCB64:{ *:[i64] }) 12659 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SLWPCB64, 12660 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 12661 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 12662 GIR_EraseFromParent, /*InsnID*/0, 12663 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12664 // GIR_Coverage, 96, 12665 GIR_Done, 12666 // Label 882: @29287 12667 GIM_Try, /*On fail goto*//*Label 883*/ 29319, // Rule ID 15407 // 12668 GIM_CheckFeatures, GIFBS_HasRTM, 12669 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_xbegin, 12670 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, 12671 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID, 12672 // (intrinsic_w_chain:{ *:[i32] } 11260:{ *:[iPTR] }) => (XBEGIN:{ *:[i32] }) 12673 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::XBEGIN, 12674 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 12675 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 12676 GIR_EraseFromParent, /*InsnID*/0, 12677 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12678 // GIR_Coverage, 15407, 12679 GIR_Done, 12680 // Label 883: @29319 12681 GIM_Try, /*On fail goto*//*Label 884*/ 29351, // Rule ID 15474 // 12682 GIM_CheckFeatures, GIFBS_HasFSGSBase_In64BitMode, 12683 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_rdfsbase_32, 12684 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, 12685 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID, 12686 // (intrinsic_w_chain:{ *:[i32] } 10987:{ *:[iPTR] }) => (RDFSBASE:{ *:[i32] }) 12687 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::RDFSBASE, 12688 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 12689 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 12690 GIR_EraseFromParent, /*InsnID*/0, 12691 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12692 // GIR_Coverage, 15474, 12693 GIR_Done, 12694 // Label 884: @29351 12695 GIM_Try, /*On fail goto*//*Label 885*/ 29383, // Rule ID 15475 // 12696 GIM_CheckFeatures, GIFBS_HasFSGSBase_In64BitMode, 12697 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_rdfsbase_64, 12698 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, 12699 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID, 12700 // (intrinsic_w_chain:{ *:[i64] } 10988:{ *:[iPTR] }) => (RDFSBASE64:{ *:[i64] }) 12701 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::RDFSBASE64, 12702 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 12703 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 12704 GIR_EraseFromParent, /*InsnID*/0, 12705 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12706 // GIR_Coverage, 15475, 12707 GIR_Done, 12708 // Label 885: @29383 12709 GIM_Try, /*On fail goto*//*Label 886*/ 29415, // Rule ID 15476 // 12710 GIM_CheckFeatures, GIFBS_HasFSGSBase_In64BitMode, 12711 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_rdgsbase_32, 12712 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, 12713 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID, 12714 // (intrinsic_w_chain:{ *:[i32] } 10989:{ *:[iPTR] }) => (RDGSBASE:{ *:[i32] }) 12715 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::RDGSBASE, 12716 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 12717 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 12718 GIR_EraseFromParent, /*InsnID*/0, 12719 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12720 // GIR_Coverage, 15476, 12721 GIR_Done, 12722 // Label 886: @29415 12723 GIM_Try, /*On fail goto*//*Label 887*/ 29447, // Rule ID 15477 // 12724 GIM_CheckFeatures, GIFBS_HasFSGSBase_In64BitMode, 12725 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_rdgsbase_64, 12726 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, 12727 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID, 12728 // (intrinsic_w_chain:{ *:[i64] } 10990:{ *:[iPTR] }) => (RDGSBASE64:{ *:[i64] }) 12729 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::RDGSBASE64, 12730 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 12731 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 12732 GIR_EraseFromParent, /*InsnID*/0, 12733 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12734 // GIR_Coverage, 15477, 12735 GIR_Done, 12736 // Label 887: @29447 12737 GIM_Try, /*On fail goto*//*Label 888*/ 29479, // Rule ID 15483 // 12738 GIM_CheckFeatures, GIFBS_HasRDPID_Not64BitMode, 12739 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_rdpid, 12740 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, 12741 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID, 12742 // (intrinsic_w_chain:{ *:[i32] } 10991:{ *:[iPTR] }) => (RDPID32:{ *:[i32] }) 12743 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::RDPID32, 12744 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 12745 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 12746 GIR_EraseFromParent, /*InsnID*/0, 12747 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12748 // GIR_Coverage, 15483, 12749 GIR_Done, 12750 // Label 888: @29479 12751 GIM_Try, /*On fail goto*//*Label 889*/ 29530, // Rule ID 20658 // 12752 GIM_CheckFeatures, GIFBS_HasRDPID_In64BitMode, 12753 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_rdpid, 12754 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, 12755 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID, 12756 // (intrinsic_w_chain:{ *:[i32] } 10991:{ *:[iPTR] }) => (EXTRACT_SUBREG:{ *:[i32] } (RDPID64:{ *:[i64] }), sub_32bit:{ *:[i32] }) 12757 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, 12758 GIR_BuildMI, /*InsnID*/1, /*Opcode*/X86::RDPID64, 12759 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 12760 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 12761 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 12762 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 12763 GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, X86::sub_32bit, 12764 GIR_EraseFromParent, /*InsnID*/0, 12765 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, X86::GR32RegClassID, 12766 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, X86::GR64_with_sub_8bitRegClassID, 12767 // GIR_Coverage, 20658, 12768 GIR_Done, 12769 // Label 889: @29530 12770 GIM_Try, /*On fail goto*//*Label 890*/ 29562, // Rule ID 3 // 12771 GIM_CheckFeatures, GIFBS_Not64BitMode, 12772 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::x86_flags_write_u32, 12773 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 12774 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR32RegClassID, 12775 // (intrinsic_void 10886:{ *:[iPTR] }, GR32:{ *:[i32] }:$src) => (WRFLAGS32:{ *:[i32] } GR32:{ *:[i32] }:$src) 12776 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::WRFLAGS32, 12777 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 12778 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 12779 GIR_EraseFromParent, /*InsnID*/0, 12780 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12781 // GIR_Coverage, 3, 12782 GIR_Done, 12783 // Label 890: @29562 12784 GIM_Try, /*On fail goto*//*Label 891*/ 29594, // Rule ID 4 // 12785 GIM_CheckFeatures, GIFBS_In64BitMode, 12786 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::x86_flags_write_u64, 12787 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 12788 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR64RegClassID, 12789 // (intrinsic_void 10887:{ *:[iPTR] }, GR64:{ *:[i64] }:$src) => (WRFLAGS64:{ *:[i64] } GR64:{ *:[i64] }:$src) 12790 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::WRFLAGS64, 12791 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 12792 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 12793 GIR_EraseFromParent, /*InsnID*/0, 12794 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12795 // GIR_Coverage, 4, 12796 GIR_Done, 12797 // Label 891: @29594 12798 GIM_Try, /*On fail goto*//*Label 892*/ 29626, // Rule ID 125 // 12799 GIM_CheckFeatures, GIFBS_HasUINTR_In64BitMode, 12800 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::x86_senduipi, 12801 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 12802 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR64RegClassID, 12803 // (intrinsic_void 11010:{ *:[iPTR] }, GR64:{ *:[i64] }:$arg) => (SENDUIPI GR64:{ *:[i64] }:$arg) 12804 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SENDUIPI, 12805 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // arg 12806 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 12807 GIR_EraseFromParent, /*InsnID*/0, 12808 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12809 // GIR_Coverage, 125, 12810 GIR_Done, 12811 // Label 892: @29626 12812 GIM_Try, /*On fail goto*//*Label 893*/ 29656, // Rule ID 15447 // 12813 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::x86_incsspd, 12814 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 12815 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR32RegClassID, 12816 // (intrinsic_void 10896:{ *:[iPTR] }, GR32:{ *:[i32] }:$src) => (INCSSPD GR32:{ *:[i32] }:$src) 12817 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::INCSSPD, 12818 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 12819 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 12820 GIR_EraseFromParent, /*InsnID*/0, 12821 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12822 // GIR_Coverage, 15447, 12823 GIR_Done, 12824 // Label 893: @29656 12825 GIM_Try, /*On fail goto*//*Label 894*/ 29686, // Rule ID 15448 // 12826 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::x86_incsspq, 12827 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 12828 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR64RegClassID, 12829 // (intrinsic_void 10897:{ *:[iPTR] }, GR64:{ *:[i64] }:$src) => (INCSSPQ GR64:{ *:[i64] }:$src) 12830 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::INCSSPQ, 12831 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 12832 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 12833 GIR_EraseFromParent, /*InsnID*/0, 12834 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12835 // GIR_Coverage, 15448, 12836 GIR_Done, 12837 // Label 894: @29686 12838 GIM_Try, /*On fail goto*//*Label 895*/ 29718, // Rule ID 15478 // 12839 GIM_CheckFeatures, GIFBS_HasFSGSBase_In64BitMode, 12840 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::x86_wrfsbase_32, 12841 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 12842 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR32RegClassID, 12843 // (intrinsic_void 11250:{ *:[iPTR] }, GR32:{ *:[i32] }:$src) => (WRFSBASE GR32:{ *:[i32] }:$src) 12844 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::WRFSBASE, 12845 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 12846 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 12847 GIR_EraseFromParent, /*InsnID*/0, 12848 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12849 // GIR_Coverage, 15478, 12850 GIR_Done, 12851 // Label 895: @29718 12852 GIM_Try, /*On fail goto*//*Label 896*/ 29750, // Rule ID 15479 // 12853 GIM_CheckFeatures, GIFBS_HasFSGSBase_In64BitMode, 12854 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::x86_wrfsbase_64, 12855 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 12856 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR64RegClassID, 12857 // (intrinsic_void 11251:{ *:[iPTR] }, GR64:{ *:[i64] }:$src) => (WRFSBASE64 GR64:{ *:[i64] }:$src) 12858 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::WRFSBASE64, 12859 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 12860 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 12861 GIR_EraseFromParent, /*InsnID*/0, 12862 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12863 // GIR_Coverage, 15479, 12864 GIR_Done, 12865 // Label 896: @29750 12866 GIM_Try, /*On fail goto*//*Label 897*/ 29782, // Rule ID 15480 // 12867 GIM_CheckFeatures, GIFBS_HasFSGSBase_In64BitMode, 12868 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::x86_wrgsbase_32, 12869 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 12870 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR32RegClassID, 12871 // (intrinsic_void 11252:{ *:[iPTR] }, GR32:{ *:[i32] }:$src) => (WRGSBASE GR32:{ *:[i32] }:$src) 12872 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::WRGSBASE, 12873 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 12874 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 12875 GIR_EraseFromParent, /*InsnID*/0, 12876 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12877 // GIR_Coverage, 15480, 12878 GIR_Done, 12879 // Label 897: @29782 12880 GIM_Try, /*On fail goto*//*Label 898*/ 29814, // Rule ID 15481 // 12881 GIM_CheckFeatures, GIFBS_HasFSGSBase_In64BitMode, 12882 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::x86_wrgsbase_64, 12883 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 12884 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR64RegClassID, 12885 // (intrinsic_void 11253:{ *:[iPTR] }, GR64:{ *:[i64] }:$src) => (WRGSBASE64 GR64:{ *:[i64] }:$src) 12886 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::WRGSBASE64, 12887 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 12888 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 12889 GIR_EraseFromParent, /*InsnID*/0, 12890 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12891 // GIR_Coverage, 15481, 12892 GIR_Done, 12893 // Label 898: @29814 12894 GIM_Try, /*On fail goto*//*Label 899*/ 29846, // Rule ID 15486 // 12895 GIM_CheckFeatures, GIFBS_HasPTWRITE, 12896 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::x86_ptwrite32, 12897 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 12898 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR32RegClassID, 12899 // (intrinsic_void 10985:{ *:[iPTR] }, GR32:{ *:[i32] }:$dst) => (PTWRITEr GR32:{ *:[i32] }:$dst) 12900 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::PTWRITEr, 12901 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // dst 12902 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 12903 GIR_EraseFromParent, /*InsnID*/0, 12904 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12905 // GIR_Coverage, 15486, 12906 GIR_Done, 12907 // Label 899: @29846 12908 GIM_Try, /*On fail goto*//*Label 900*/ 29878, // Rule ID 15487 // 12909 GIM_CheckFeatures, GIFBS_HasPTWRITE_In64BitMode, 12910 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::x86_ptwrite64, 12911 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 12912 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR64RegClassID, 12913 // (intrinsic_void 10986:{ *:[iPTR] }, GR64:{ *:[i64] }:$dst) => (PTWRITE64r GR64:{ *:[i64] }:$dst) 12914 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::PTWRITE64r, 12915 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // dst 12916 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 12917 GIR_EraseFromParent, /*InsnID*/0, 12918 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12919 // GIR_Coverage, 15487, 12920 GIR_Done, 12921 // Label 900: @29878 12922 GIM_Try, /*On fail goto*//*Label 901*/ 29910, // Rule ID 93 // 12923 GIM_CheckFeatures, GIFBS_HasLWP, 12924 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::x86_llwpcb, 12925 // MIs[0] src 12926 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 12927 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR32RegClassID, 12928 // (intrinsic_void 10902:{ *:[iPTR] }, GR32:{ *:[i32] }:$src) => (LLWPCB GR32:{ *:[i32] }:$src) 12929 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::LLWPCB, 12930 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 12931 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 12932 GIR_EraseFromParent, /*InsnID*/0, 12933 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12934 // GIR_Coverage, 93, 12935 GIR_Done, 12936 // Label 901: @29910 12937 GIM_Try, /*On fail goto*//*Label 902*/ 29942, // Rule ID 95 // 12938 GIM_CheckFeatures, GIFBS_HasLWP, 12939 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::x86_llwpcb, 12940 // MIs[0] src 12941 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 12942 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR64RegClassID, 12943 // (intrinsic_void 10902:{ *:[iPTR] }, GR64:{ *:[i64] }:$src) => (LLWPCB64 GR64:{ *:[i64] }:$src) 12944 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::LLWPCB64, 12945 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 12946 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 12947 GIR_EraseFromParent, /*InsnID*/0, 12948 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12949 // GIR_Coverage, 95, 12950 GIR_Done, 12951 // Label 902: @29942 12952 GIM_Try, /*On fail goto*//*Label 903*/ 29974, // Rule ID 105 // 12953 GIM_CheckFeatures, GIFBS_HasWAITPKG_Not64BitMode, 12954 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::x86_umonitor, 12955 // MIs[0] src 12956 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/16, 12957 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR16RegClassID, 12958 // (intrinsic_void 11221:{ *:[iPTR] }, GR16:{ *:[i16] }:$src) => (UMONITOR16 GR16:{ *:[i16] }:$src) 12959 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::UMONITOR16, 12960 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 12961 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 12962 GIR_EraseFromParent, /*InsnID*/0, 12963 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12964 // GIR_Coverage, 105, 12965 GIR_Done, 12966 // Label 903: @29974 12967 GIM_Try, /*On fail goto*//*Label 904*/ 30006, // Rule ID 106 // 12968 GIM_CheckFeatures, GIFBS_HasWAITPKG, 12969 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::x86_umonitor, 12970 // MIs[0] src 12971 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 12972 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR32RegClassID, 12973 // (intrinsic_void 11221:{ *:[iPTR] }, GR32:{ *:[i32] }:$src) => (UMONITOR32 GR32:{ *:[i32] }:$src) 12974 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::UMONITOR32, 12975 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 12976 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 12977 GIR_EraseFromParent, /*InsnID*/0, 12978 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12979 // GIR_Coverage, 106, 12980 GIR_Done, 12981 // Label 904: @30006 12982 GIM_Try, /*On fail goto*//*Label 905*/ 30038, // Rule ID 107 // 12983 GIM_CheckFeatures, GIFBS_HasWAITPKG_In64BitMode, 12984 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::x86_umonitor, 12985 // MIs[0] src 12986 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 12987 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR64RegClassID, 12988 // (intrinsic_void 11221:{ *:[iPTR] }, GR64:{ *:[i64] }:$src) => (UMONITOR64 GR64:{ *:[i64] }:$src) 12989 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::UMONITOR64, 12990 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 12991 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 12992 GIR_EraseFromParent, /*InsnID*/0, 12993 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12994 // GIR_Coverage, 107, 12995 GIR_Done, 12996 // Label 905: @30038 12997 GIM_Reject, 12998 // Label 874: @30039 12999 GIM_Try, /*On fail goto*//*Label 906*/ 30224, 13000 GIM_CheckNumOperands, /*MI*/0, /*Expected*/3, 13001 GIM_Try, /*On fail goto*//*Label 907*/ 30081, // Rule ID 15507 // 13002 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::asan_check_memaccess, 13003 // MIs[0] addr 13004 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 13005 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR64PLTSafeRegClassID, 13006 // MIs[0] accessinfo 13007 GIM_CheckIsImm, /*MI*/0, /*Op*/2, 13008 // (intrinsic_void 6:{ *:[iPTR] }, GR64PLTSafe:{ *:[i64] }:$addr, (timm:{ *:[i32] }):$accessinfo) => (ASAN_CHECK_MEMACCESS:{ *:[i64] } GR64PLTSafe:{ *:[i64] }:$addr, (timm:{ *:[i32] }):$accessinfo) 13009 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::ASAN_CHECK_MEMACCESS, 13010 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // addr 13011 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // accessinfo 13012 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 13013 GIR_EraseFromParent, /*InsnID*/0, 13014 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13015 // GIR_Coverage, 15507, 13016 GIR_Done, 13017 // Label 907: @30081 13018 GIM_Try, /*On fail goto*//*Label 908*/ 30123, // Rule ID 15449 // 13019 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_rdsspd, 13020 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, 13021 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 13022 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID, 13023 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::GR32RegClassID, 13024 // (intrinsic_w_chain:{ *:[i32] } 11001:{ *:[iPTR] }, GR32:{ *:[i32] }:$src) => (RDSSPD:{ *:[i32] } GR32:{ *:[i32] }:$src) 13025 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::RDSSPD, 13026 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 13027 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src 13028 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 13029 GIR_EraseFromParent, /*InsnID*/0, 13030 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13031 // GIR_Coverage, 15449, 13032 GIR_Done, 13033 // Label 908: @30123 13034 GIM_Try, /*On fail goto*//*Label 909*/ 30165, // Rule ID 15450 // 13035 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_rdsspq, 13036 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, 13037 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 13038 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID, 13039 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::GR64RegClassID, 13040 // (intrinsic_w_chain:{ *:[i64] } 11002:{ *:[iPTR] }, GR64:{ *:[i64] }:$src) => (RDSSPQ:{ *:[i64] } GR64:{ *:[i64] }:$src) 13041 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::RDSSPQ, 13042 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 13043 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src 13044 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 13045 GIR_EraseFromParent, /*InsnID*/0, 13046 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13047 // GIR_Coverage, 15450, 13048 GIR_Done, 13049 // Label 909: @30165 13050 GIM_Try, /*On fail goto*//*Label 910*/ 30223, // Rule ID 2778 // 13051 GIM_CheckFeatures, GIFBS_HasSSE3, 13052 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::x86_sse3_mwait, 13053 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 13054 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 13055 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR32_CB_and_GR32_DCRegClassID, 13056 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::GR32_ADRegClassID, 13057 // (intrinsic_void 11126:{ *:[iPTR] }, ECX:{ *:[i32] }, EAX:{ *:[i32] }) => (MWAITrr) 13058 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY, 13059 GIR_AddRegister, /*InsnID*/2, X86::EAX, /*AddRegisterRegFlags*/RegState::Define, 13060 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // EAX 13061 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, 13062 GIR_AddRegister, /*InsnID*/1, X86::ECX, /*AddRegisterRegFlags*/RegState::Define, 13063 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // ECX 13064 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::MWAITrr, 13065 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 13066 GIR_EraseFromParent, /*InsnID*/0, 13067 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13068 // GIR_Coverage, 2778, 13069 GIR_Done, 13070 // Label 910: @30223 13071 GIM_Reject, 13072 // Label 906: @30224 13073 GIM_Try, /*On fail goto*//*Label 911*/ 30961, 13074 GIM_CheckNumOperands, /*MI*/0, /*Expected*/4, 13075 GIM_Try, /*On fail goto*//*Label 912*/ 30270, // Rule ID 15425 // 13076 GIM_CheckFeatures, GIFBS_HasAMXINT8_In64BitMode, 13077 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::x86_tdpbssd, 13078 // MIs[0] src1 13079 GIM_CheckIsImm, /*MI*/0, /*Op*/1, 13080 // MIs[0] src2 13081 GIM_CheckIsImm, /*MI*/0, /*Op*/2, 13082 // MIs[0] src3 13083 GIM_CheckIsImm, /*MI*/0, /*Op*/3, 13084 // (intrinsic_void 11200:{ *:[iPTR] }, (timm:{ *:[i8] }):$src1, (timm:{ *:[i8] }):$src2, (timm:{ *:[i8] }):$src3) => (PTDPBSSD (timm:{ *:[i8] }):$src1, (timm:{ *:[i8] }):$src2, (timm:{ *:[i8] }):$src3) 13085 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::PTDPBSSD, 13086 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 13087 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src2 13088 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src3 13089 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 13090 GIR_EraseFromParent, /*InsnID*/0, 13091 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13092 // GIR_Coverage, 15425, 13093 GIR_Done, 13094 // Label 912: @30270 13095 GIM_Try, /*On fail goto*//*Label 913*/ 30311, // Rule ID 15426 // 13096 GIM_CheckFeatures, GIFBS_HasAMXINT8_In64BitMode, 13097 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::x86_tdpbsud, 13098 // MIs[0] src1 13099 GIM_CheckIsImm, /*MI*/0, /*Op*/1, 13100 // MIs[0] src2 13101 GIM_CheckIsImm, /*MI*/0, /*Op*/2, 13102 // MIs[0] src3 13103 GIM_CheckIsImm, /*MI*/0, /*Op*/3, 13104 // (intrinsic_void 11202:{ *:[iPTR] }, (timm:{ *:[i8] }):$src1, (timm:{ *:[i8] }):$src2, (timm:{ *:[i8] }):$src3) => (PTDPBSUD (timm:{ *:[i8] }):$src1, (timm:{ *:[i8] }):$src2, (timm:{ *:[i8] }):$src3) 13105 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::PTDPBSUD, 13106 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 13107 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src2 13108 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src3 13109 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 13110 GIR_EraseFromParent, /*InsnID*/0, 13111 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13112 // GIR_Coverage, 15426, 13113 GIR_Done, 13114 // Label 913: @30311 13115 GIM_Try, /*On fail goto*//*Label 914*/ 30352, // Rule ID 15427 // 13116 GIM_CheckFeatures, GIFBS_HasAMXINT8_In64BitMode, 13117 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::x86_tdpbusd, 13118 // MIs[0] src1 13119 GIM_CheckIsImm, /*MI*/0, /*Op*/1, 13120 // MIs[0] src2 13121 GIM_CheckIsImm, /*MI*/0, /*Op*/2, 13122 // MIs[0] src3 13123 GIM_CheckIsImm, /*MI*/0, /*Op*/3, 13124 // (intrinsic_void 11204:{ *:[iPTR] }, (timm:{ *:[i8] }):$src1, (timm:{ *:[i8] }):$src2, (timm:{ *:[i8] }):$src3) => (PTDPBUSD (timm:{ *:[i8] }):$src1, (timm:{ *:[i8] }):$src2, (timm:{ *:[i8] }):$src3) 13125 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::PTDPBUSD, 13126 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 13127 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src2 13128 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src3 13129 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 13130 GIR_EraseFromParent, /*InsnID*/0, 13131 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13132 // GIR_Coverage, 15427, 13133 GIR_Done, 13134 // Label 914: @30352 13135 GIM_Try, /*On fail goto*//*Label 915*/ 30393, // Rule ID 15428 // 13136 GIM_CheckFeatures, GIFBS_HasAMXINT8_In64BitMode, 13137 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::x86_tdpbuud, 13138 // MIs[0] src1 13139 GIM_CheckIsImm, /*MI*/0, /*Op*/1, 13140 // MIs[0] src2 13141 GIM_CheckIsImm, /*MI*/0, /*Op*/2, 13142 // MIs[0] src3 13143 GIM_CheckIsImm, /*MI*/0, /*Op*/3, 13144 // (intrinsic_void 11206:{ *:[iPTR] }, (timm:{ *:[i8] }):$src1, (timm:{ *:[i8] }):$src2, (timm:{ *:[i8] }):$src3) => (PTDPBUUD (timm:{ *:[i8] }):$src1, (timm:{ *:[i8] }):$src2, (timm:{ *:[i8] }):$src3) 13145 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::PTDPBUUD, 13146 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 13147 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src2 13148 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src3 13149 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 13150 GIR_EraseFromParent, /*InsnID*/0, 13151 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13152 // GIR_Coverage, 15428, 13153 GIR_Done, 13154 // Label 915: @30393 13155 GIM_Try, /*On fail goto*//*Label 916*/ 30434, // Rule ID 15430 // 13156 GIM_CheckFeatures, GIFBS_HasAMXBF16_In64BitMode, 13157 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::x86_tdpbf16ps, 13158 // MIs[0] src1 13159 GIM_CheckIsImm, /*MI*/0, /*Op*/1, 13160 // MIs[0] src2 13161 GIM_CheckIsImm, /*MI*/0, /*Op*/2, 13162 // MIs[0] src3 13163 GIM_CheckIsImm, /*MI*/0, /*Op*/3, 13164 // (intrinsic_void 11198:{ *:[iPTR] }, (timm:{ *:[i8] }):$src1, (timm:{ *:[i8] }):$src2, (timm:{ *:[i8] }):$src3) => (PTDPBF16PS (timm:{ *:[i8] }):$src1, (timm:{ *:[i8] }):$src2, (timm:{ *:[i8] }):$src3) 13165 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::PTDPBF16PS, 13166 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 13167 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src2 13168 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src3 13169 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 13170 GIR_EraseFromParent, /*InsnID*/0, 13171 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13172 // GIR_Coverage, 15430, 13173 GIR_Done, 13174 // Label 916: @30434 13175 GIM_Try, /*On fail goto*//*Label 917*/ 30475, // Rule ID 15432 // 13176 GIM_CheckFeatures, GIFBS_HasAMXFP16_In64BitMode, 13177 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::x86_tdpfp16ps, 13178 // MIs[0] src1 13179 GIM_CheckIsImm, /*MI*/0, /*Op*/1, 13180 // MIs[0] src2 13181 GIM_CheckIsImm, /*MI*/0, /*Op*/2, 13182 // MIs[0] src3 13183 GIM_CheckIsImm, /*MI*/0, /*Op*/3, 13184 // (intrinsic_void 11208:{ *:[iPTR] }, (timm:{ *:[i8] }):$src1, (timm:{ *:[i8] }):$src2, (timm:{ *:[i8] }):$src3) => (PTDPFP16PS (timm:{ *:[i8] }):$src1, (timm:{ *:[i8] }):$src2, (timm:{ *:[i8] }):$src3) 13185 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::PTDPFP16PS, 13186 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 13187 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src2 13188 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src3 13189 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 13190 GIR_EraseFromParent, /*InsnID*/0, 13191 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13192 // GIR_Coverage, 15432, 13193 GIR_Done, 13194 // Label 917: @30475 13195 GIM_Try, /*On fail goto*//*Label 918*/ 30526, // Rule ID 101 // 13196 GIM_CheckFeatures, GIFBS_HasLWP, 13197 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::x86_lwpval32, 13198 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 13199 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 13200 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR32RegClassID, 13201 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::GR32RegClassID, 13202 // MIs[0] cntl 13203 GIM_CheckIsImm, /*MI*/0, /*Op*/3, 13204 // (intrinsic_void 10906:{ *:[iPTR] }, GR32:{ *:[i32] }:$src0, GR32:{ *:[i32] }:$src1, (timm:{ *:[i32] }):$cntl) => (LWPVAL32rri GR32:{ *:[i32] }:$src0, GR32:{ *:[i32] }:$src1, (timm:{ *:[i32] }):$cntl) 13205 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::LWPVAL32rri, 13206 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0 13207 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 13208 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // cntl 13209 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 13210 GIR_EraseFromParent, /*InsnID*/0, 13211 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13212 // GIR_Coverage, 101, 13213 GIR_Done, 13214 // Label 918: @30526 13215 GIM_Try, /*On fail goto*//*Label 919*/ 30577, // Rule ID 103 // 13216 GIM_CheckFeatures, GIFBS_HasLWP, 13217 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::x86_lwpval64, 13218 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 13219 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 13220 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR64RegClassID, 13221 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::GR32RegClassID, 13222 // MIs[0] cntl 13223 GIM_CheckIsImm, /*MI*/0, /*Op*/3, 13224 // (intrinsic_void 10907:{ *:[iPTR] }, GR64:{ *:[i64] }:$src0, GR32:{ *:[i32] }:$src1, (timm:{ *:[i32] }):$cntl) => (LWPVAL64rri GR64:{ *:[i64] }:$src0, GR32:{ *:[i32] }:$src1, (timm:{ *:[i32] }):$cntl) 13225 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::LWPVAL64rri, 13226 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0 13227 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 13228 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // cntl 13229 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 13230 GIR_EraseFromParent, /*InsnID*/0, 13231 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13232 // GIR_Coverage, 103, 13233 GIR_Done, 13234 // Label 919: @30577 13235 GIM_Try, /*On fail goto*//*Label 920*/ 30652, // Rule ID 15459 // 13236 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::x86_xsetbv, 13237 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 13238 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 13239 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 13240 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR32_CB_and_GR32_DCRegClassID, 13241 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::GR32_AD_and_GR32_DCRegClassID, 13242 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::GR32_ADRegClassID, 13243 // (intrinsic_void 11322:{ *:[iPTR] }, ECX:{ *:[i32] }, EDX:{ *:[i32] }, EAX:{ *:[i32] }) => (XSETBV) 13244 GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::COPY, 13245 GIR_AddRegister, /*InsnID*/3, X86::EAX, /*AddRegisterRegFlags*/RegState::Define, 13246 GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/3, // EAX 13247 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY, 13248 GIR_AddRegister, /*InsnID*/2, X86::EDX, /*AddRegisterRegFlags*/RegState::Define, 13249 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // EDX 13250 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, 13251 GIR_AddRegister, /*InsnID*/1, X86::ECX, /*AddRegisterRegFlags*/RegState::Define, 13252 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // ECX 13253 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::XSETBV, 13254 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 13255 GIR_EraseFromParent, /*InsnID*/0, 13256 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13257 // GIR_Coverage, 15459, 13258 GIR_Done, 13259 // Label 920: @30652 13260 GIM_Try, /*On fail goto*//*Label 921*/ 30708, // Rule ID 15646 // 13261 GIM_CheckFeatures, GIFBS_HasMWAITX, 13262 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::x86_mwaitx, 13263 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 13264 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 13265 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 13266 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR32RegClassID, 13267 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::GR32RegClassID, 13268 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::GR32RegClassID, 13269 // (intrinsic_void 10981:{ *:[iPTR] }, GR32:{ *:[i32] }:$ecx, GR32:{ *:[i32] }:$eax, GR32:{ *:[i32] }:$ebx) => (MWAITX GR32:{ *:[i32] }:$ecx, GR32:{ *:[i32] }:$eax, GR32:{ *:[i32] }:$ebx) 13270 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::MWAITX, 13271 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // ecx 13272 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // eax 13273 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ebx 13274 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 13275 GIR_EraseFromParent, /*InsnID*/0, 13276 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13277 // GIR_Coverage, 15646, 13278 GIR_Done, 13279 // Label 921: @30708 13280 GIM_Try, /*On fail goto*//*Label 922*/ 30771, // Rule ID 2595 // 13281 GIM_CheckFeatures, GIFBS_HasAVX, 13282 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::x86_sse2_maskmov_dqu, 13283 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, 13284 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, 13285 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 13286 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 13287 // MIs[0] Operand 3 13288 GIM_CheckPointerToAny, /*MI*/0, /*Op*/3, /*SizeInBits*/32, 13289 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::GR32_DIBP_and_GR32_SIDIRegClassID, 13290 // (intrinsic_void 11078:{ *:[iPTR] }, VR128:{ *:[v16i8] }:$src, VR128:{ *:[v16i8] }:$mask, EDI:{ *:[i32] }) => (VMASKMOVDQU VR128:{ *:[v16i8] }:$src, VR128:{ *:[v16i8] }:$mask) 13291 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, 13292 GIR_AddRegister, /*InsnID*/1, X86::EDI, /*AddRegisterRegFlags*/RegState::Define, 13293 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // EDI 13294 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VMASKMOVDQU, 13295 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 13296 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // mask 13297 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 13298 GIR_EraseFromParent, /*InsnID*/0, 13299 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13300 // GIR_Coverage, 2595, 13301 GIR_Done, 13302 // Label 922: @30771 13303 GIM_Try, /*On fail goto*//*Label 923*/ 30834, // Rule ID 2596 // 13304 GIM_CheckFeatures, GIFBS_HasAVX_In64BitMode, 13305 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::x86_sse2_maskmov_dqu, 13306 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, 13307 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, 13308 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 13309 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 13310 // MIs[0] Operand 3 13311 GIM_CheckPointerToAny, /*MI*/0, /*Op*/3, /*SizeInBits*/64, 13312 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDIRegClassID, 13313 // (intrinsic_void 11078:{ *:[iPTR] }, VR128:{ *:[v16i8] }:$src, VR128:{ *:[v16i8] }:$mask, RDI:{ *:[i64] }) => (VMASKMOVDQU64 VR128:{ *:[v16i8] }:$src, VR128:{ *:[v16i8] }:$mask) 13314 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, 13315 GIR_AddRegister, /*InsnID*/1, X86::RDI, /*AddRegisterRegFlags*/RegState::Define, 13316 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // RDI 13317 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VMASKMOVDQU64, 13318 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 13319 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // mask 13320 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 13321 GIR_EraseFromParent, /*InsnID*/0, 13322 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13323 // GIR_Coverage, 2596, 13324 GIR_Done, 13325 // Label 923: @30834 13326 GIM_Try, /*On fail goto*//*Label 924*/ 30897, // Rule ID 2597 // 13327 GIM_CheckFeatures, GIFBS_UseSSE2, 13328 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::x86_sse2_maskmov_dqu, 13329 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, 13330 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, 13331 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 13332 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 13333 // MIs[0] Operand 3 13334 GIM_CheckPointerToAny, /*MI*/0, /*Op*/3, /*SizeInBits*/32, 13335 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::GR32_DIBP_and_GR32_SIDIRegClassID, 13336 // (intrinsic_void 11078:{ *:[iPTR] }, VR128:{ *:[v16i8] }:$src, VR128:{ *:[v16i8] }:$mask, EDI:{ *:[i32] }) => (MASKMOVDQU VR128:{ *:[v16i8] }:$src, VR128:{ *:[v16i8] }:$mask) 13337 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, 13338 GIR_AddRegister, /*InsnID*/1, X86::EDI, /*AddRegisterRegFlags*/RegState::Define, 13339 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // EDI 13340 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::MASKMOVDQU, 13341 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 13342 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // mask 13343 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 13344 GIR_EraseFromParent, /*InsnID*/0, 13345 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13346 // GIR_Coverage, 2597, 13347 GIR_Done, 13348 // Label 924: @30897 13349 GIM_Try, /*On fail goto*//*Label 925*/ 30960, // Rule ID 2598 // 13350 GIM_CheckFeatures, GIFBS_In64BitMode_UseSSE2, 13351 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::x86_sse2_maskmov_dqu, 13352 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, 13353 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, 13354 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 13355 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 13356 // MIs[0] Operand 3 13357 GIM_CheckPointerToAny, /*MI*/0, /*Op*/3, /*SizeInBits*/64, 13358 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDIRegClassID, 13359 // (intrinsic_void 11078:{ *:[iPTR] }, VR128:{ *:[v16i8] }:$src, VR128:{ *:[v16i8] }:$mask, RDI:{ *:[i64] }) => (MASKMOVDQU64 VR128:{ *:[v16i8] }:$src, VR128:{ *:[v16i8] }:$mask) 13360 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, 13361 GIR_AddRegister, /*InsnID*/1, X86::RDI, /*AddRegisterRegFlags*/RegState::Define, 13362 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // RDI 13363 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::MASKMOVDQU64, 13364 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 13365 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // mask 13366 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 13367 GIR_EraseFromParent, /*InsnID*/0, 13368 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13369 // GIR_Coverage, 2598, 13370 GIR_Done, 13371 // Label 925: @30960 13372 GIM_Reject, 13373 // Label 911: @30961 13374 GIM_Try, /*On fail goto*//*Label 926*/ 31046, // Rule ID 15411 // 13375 GIM_CheckFeatures, GIFBS_HasKL, 13376 GIM_CheckNumOperands, /*MI*/0, /*Expected*/5, 13377 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::x86_loadiwkey, 13378 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, 13379 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 13380 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, 13381 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, 13382 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 13383 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 13384 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::VR128RegClassID, 13385 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/X86::GR32_ADRegClassID, 13386 // (intrinsic_void 10903:{ *:[iPTR] }, XMM0:{ *:[v2i64] }, VR128:{ *:[v2i64] }:$src1, VR128:{ *:[v2i64] }:$src2, EAX:{ *:[i32] }) => (LOADIWKEY:{ *:[i32] } VR128:{ *:[v2i64] }:$src1, VR128:{ *:[v2i64] }:$src2) 13387 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY, 13388 GIR_AddRegister, /*InsnID*/2, X86::EAX, /*AddRegisterRegFlags*/RegState::Define, 13389 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/4, // EAX 13390 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, 13391 GIR_AddRegister, /*InsnID*/1, X86::XMM0, /*AddRegisterRegFlags*/RegState::Define, 13392 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // XMM0 13393 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::LOADIWKEY, 13394 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 13395 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src2 13396 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 13397 GIR_EraseFromParent, /*InsnID*/0, 13398 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13399 // GIR_Coverage, 15411, 13400 GIR_Done, 13401 // Label 926: @31046 13402 GIM_Reject, 13403 // Label 11: @31047 13404 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/2, 5, /*)*//*default:*//*Label 930*/ 31457, 13405 /*GILLT_s16*//*Label 927*/ 31056, 13406 /*GILLT_s32*//*Label 928*/ 31110, 13407 /*GILLT_s64*//*Label 929*/ 31281, 13408 // Label 927: @31056 13409 GIM_Try, /*On fail goto*//*Label 931*/ 31109, // Rule ID 20847 // 13410 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s8, 13411 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID, 13412 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR8RegClassID, 13413 // (anyext:{ *:[i16] } GR8:{ *:[i8] }:$src) => (EXTRACT_SUBREG:{ *:[i16] } (MOVZX32rr8:{ *:[i32] } GR8:{ *:[i8] }:$src), sub_16bit:{ *:[i32] }) 13414 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, 13415 GIR_BuildMI, /*InsnID*/1, /*Opcode*/X86::MOVZX32rr8, 13416 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 13417 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src 13418 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 13419 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 13420 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 13421 GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, X86::sub_16bit, 13422 GIR_EraseFromParent, /*InsnID*/0, 13423 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, X86::GR16RegClassID, 13424 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, X86::GR32RegClassID, 13425 // GIR_Coverage, 20847, 13426 GIR_Done, 13427 // Label 931: @31109 13428 GIM_Reject, 13429 // Label 928: @31110 13430 GIM_Try, /*On fail goto*//*Label 932*/ 31155, // Rule ID 17876 // 13431 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16, 13432 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID, 13433 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 13434 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_BITCAST, 13435 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s1, 13436 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::VK16RegClassID, 13437 GIM_CheckIsSafeToFold, /*InsnID*/1, 13438 // (anyext:{ *:[i32] } (bitconvert:{ *:[i16] } VK16:{ *:[v16i1] }:$src)) => (COPY_TO_REGCLASS:{ *:[i32] } VK16:{ *:[v16i1] }:$src, GR32:{ *:[i32] }) 13439 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 13440 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 13441 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src 13442 GIR_EraseFromParent, /*InsnID*/0, 13443 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, X86::GR32RegClassID, 13444 // GIR_Coverage, 17876, 13445 GIR_Done, 13446 // Label 932: @31155 13447 GIM_Try, /*On fail goto*//*Label 933*/ 31200, // Rule ID 17879 // 13448 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s8, 13449 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID, 13450 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 13451 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_BITCAST, 13452 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s1, 13453 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::VK8RegClassID, 13454 GIM_CheckIsSafeToFold, /*InsnID*/1, 13455 // (anyext:{ *:[i32] } (bitconvert:{ *:[i8] } VK8:{ *:[v8i1] }:$src)) => (COPY_TO_REGCLASS:{ *:[i32] } VK8:{ *:[v8i1] }:$src, GR32:{ *:[i32] }) 13456 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 13457 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 13458 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src 13459 GIR_EraseFromParent, /*InsnID*/0, 13460 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, X86::GR32RegClassID, 13461 // GIR_Coverage, 17879, 13462 GIR_Done, 13463 // Label 933: @31200 13464 GIM_Try, /*On fail goto*//*Label 934*/ 31221, // Rule ID 20848 // 13465 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s8, 13466 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID, 13467 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR8RegClassID, 13468 // (anyext:{ *:[i32] } GR8:{ *:[i8] }:$src) => (MOVZX32rr8:{ *:[i32] } GR8:{ *:[i8] }:$src) 13469 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::MOVZX32rr8, 13470 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13471 // GIR_Coverage, 20848, 13472 GIR_Done, 13473 // Label 934: @31221 13474 GIM_Try, /*On fail goto*//*Label 935*/ 31280, // Rule ID 20849 // 13475 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16, 13476 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::LOW32_ADDR_ACCESS_RBPRegClassID, 13477 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR16RegClassID, 13478 // (anyext:{ *:[i32] } GR16:{ *:[i16] }:$src) => (INSERT_SUBREG:{ *:[i32] } (IMPLICIT_DEF:{ *:[i32] }), GR16:{ *:[i16] }:$src, sub_16bit:{ *:[i32] }) 13479 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, 13480 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, 13481 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 13482 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 13483 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::INSERT_SUBREG, 13484 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 13485 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 13486 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 13487 GIR_AddImm, /*InsnID*/0, /*Imm*/4, 13488 GIR_EraseFromParent, /*InsnID*/0, 13489 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, X86::LOW32_ADDR_ACCESS_RBPRegClassID, 13490 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, X86::LOW32_ADDR_ACCESS_RBPRegClassID, 13491 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, X86::GR16RegClassID, 13492 // GIR_Coverage, 20849, 13493 GIR_Done, 13494 // Label 935: @31280 13495 GIM_Reject, 13496 // Label 929: @31281 13497 GIM_Try, /*On fail goto*//*Label 936*/ 31339, // Rule ID 20850 // 13498 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s8, 13499 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID, 13500 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR8RegClassID, 13501 // (anyext:{ *:[i64] } GR8:{ *:[i8] }:$src) => (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (MOVZX32rr8:{ *:[i32] } GR8:{ *:[i8] }:$src), sub_32bit:{ *:[i32] }) 13502 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, 13503 GIR_BuildMI, /*InsnID*/1, /*Opcode*/X86::MOVZX32rr8, 13504 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 13505 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src 13506 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 13507 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::SUBREG_TO_REG, 13508 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 13509 GIR_AddImm, /*InsnID*/0, /*Imm*/0, 13510 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 13511 GIR_AddImm, /*InsnID*/0, /*Imm*/6, 13512 GIR_EraseFromParent, /*InsnID*/0, 13513 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, X86::GR64RegClassID, 13514 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, X86::GR32RegClassID, 13515 // GIR_Coverage, 20850, 13516 GIR_Done, 13517 // Label 936: @31339 13518 GIM_Try, /*On fail goto*//*Label 937*/ 31397, // Rule ID 20851 // 13519 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16, 13520 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID, 13521 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR16RegClassID, 13522 // (anyext:{ *:[i64] } GR16:{ *:[i16] }:$src) => (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (MOVZX32rr16:{ *:[i32] } GR16:{ *:[i16] }:$src), sub_32bit:{ *:[i32] }) 13523 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, 13524 GIR_BuildMI, /*InsnID*/1, /*Opcode*/X86::MOVZX32rr16, 13525 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 13526 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src 13527 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 13528 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::SUBREG_TO_REG, 13529 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 13530 GIR_AddImm, /*InsnID*/0, /*Imm*/0, 13531 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 13532 GIR_AddImm, /*InsnID*/0, /*Imm*/6, 13533 GIR_EraseFromParent, /*InsnID*/0, 13534 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, X86::GR64RegClassID, 13535 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, X86::GR32RegClassID, 13536 // GIR_Coverage, 20851, 13537 GIR_Done, 13538 // Label 937: @31397 13539 GIM_Try, /*On fail goto*//*Label 938*/ 31456, // Rule ID 20852 // 13540 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 13541 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID, 13542 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR32RegClassID, 13543 // (anyext:{ *:[i64] } GR32:{ *:[i32] }:$src) => (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), GR32:{ *:[i32] }:$src, sub_32bit:{ *:[i32] }) 13544 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, 13545 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, 13546 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 13547 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 13548 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::INSERT_SUBREG, 13549 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 13550 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 13551 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 13552 GIR_AddImm, /*InsnID*/0, /*Imm*/6, 13553 GIR_EraseFromParent, /*InsnID*/0, 13554 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, X86::GR64RegClassID, 13555 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, X86::GR64RegClassID, 13556 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, X86::GR32RegClassID, 13557 // GIR_Coverage, 20852, 13558 GIR_Done, 13559 // Label 938: @31456 13560 GIM_Reject, 13561 // Label 930: @31457 13562 GIM_Reject, 13563 // Label 12: @31458 13564 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 22, /*)*//*default:*//*Label 947*/ 32315, 13565 /*GILLT_s8*//*Label 939*/ 31485, 13566 /*GILLT_s16*//*Label 940*/ 31740, 0, 0, 0, 0, 0, 0, 0, 13567 /*GILLT_v4s32*//*Label 941*/ 31778, 0, 0, 13568 /*GILLT_v8s16*//*Label 942*/ 31901, 13569 /*GILLT_v8s32*//*Label 943*/ 32048, 0, 0, 13570 /*GILLT_v16s8*//*Label 944*/ 32072, 13571 /*GILLT_v16s16*//*Label 945*/ 32267, 0, 0, 13572 /*GILLT_v32s8*//*Label 946*/ 32291, 13573 // Label 939: @31485 13574 GIM_Try, /*On fail goto*//*Label 948*/ 31551, // Rule ID 17871 // 13575 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16, 13576 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID, 13577 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 13578 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_BITCAST, 13579 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s1, 13580 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::VK16RegClassID, 13581 GIM_CheckIsSafeToFold, /*InsnID*/1, 13582 // (trunc:{ *:[i8] } (bitconvert:{ *:[i16] } VK16:{ *:[v16i1] }:$src)) => (EXTRACT_SUBREG:{ *:[i8] } (COPY_TO_REGCLASS:{ *:[i32] } VK16:{ *:[v16i1] }:$src, GR32:{ *:[i32] }), sub_8bit:{ *:[i32] }) 13583 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, 13584 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, 13585 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 13586 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // src 13587 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 13588 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 13589 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 13590 GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, X86::sub_8bit, 13591 GIR_EraseFromParent, /*InsnID*/0, 13592 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, X86::GR8RegClassID, 13593 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, X86::GR32RegClassID, 13594 // GIR_Coverage, 17871, 13595 GIR_Done, 13596 // Label 948: @31551 13597 GIM_Try, /*On fail goto*//*Label 949*/ 31606, // Rule ID 20893 // 13598 GIM_CheckFeatures, GIFBS_Not64BitMode, 13599 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 13600 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32_ABCDRegClassID, 13601 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR32RegClassID, 13602 // (trunc:{ *:[i8] } GR32:{ *:[i32] }:$src) => (EXTRACT_SUBREG:{ *:[i8] } (COPY_TO_REGCLASS:{ *:[i32] } GR32:{ *:[i32] }:$src, GR32_ABCD:{ *:[i32] }), sub_8bit:{ *:[i32] }) 13603 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, 13604 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, 13605 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 13606 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src 13607 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 13608 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 13609 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 13610 GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, X86::sub_8bit, 13611 GIR_EraseFromParent, /*InsnID*/0, 13612 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, X86::GR8_ABCD_LRegClassID, 13613 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, X86::GR32_ABCDRegClassID, 13614 // GIR_Coverage, 20893, 13615 GIR_Done, 13616 // Label 949: @31606 13617 GIM_Try, /*On fail goto*//*Label 950*/ 31661, // Rule ID 20894 // 13618 GIM_CheckFeatures, GIFBS_Not64BitMode, 13619 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16, 13620 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR16_ABCDRegClassID, 13621 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR16RegClassID, 13622 // (trunc:{ *:[i8] } GR16:{ *:[i16] }:$src) => (EXTRACT_SUBREG:{ *:[i8] } (COPY_TO_REGCLASS:{ *:[i16] } GR16:{ *:[i16] }:$src, GR16_ABCD:{ *:[i32] }), sub_8bit:{ *:[i32] }) 13623 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16, 13624 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, 13625 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 13626 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src 13627 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 13628 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 13629 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 13630 GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, X86::sub_8bit, 13631 GIR_EraseFromParent, /*InsnID*/0, 13632 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, X86::GR8_ABCD_LRegClassID, 13633 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, X86::GR16_ABCDRegClassID, 13634 // GIR_Coverage, 20894, 13635 GIR_Done, 13636 // Label 950: @31661 13637 GIM_Try, /*On fail goto*//*Label 951*/ 31700, // Rule ID 20898 // 13638 GIM_CheckFeatures, GIFBS_In64BitMode, 13639 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 13640 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID, 13641 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR32RegClassID, 13642 // (trunc:{ *:[i8] } GR32:{ *:[i32] }:$src) => (EXTRACT_SUBREG:{ *:[i8] } GR32:{ *:[i32] }:$src, sub_8bit:{ *:[i32] }) 13643 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 13644 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 13645 GIR_CopySubReg, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/1, // src 13646 GIR_EraseFromParent, /*InsnID*/0, 13647 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, X86::GR8RegClassID, 13648 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, X86::GR32RegClassID, 13649 // GIR_Coverage, 20898, 13650 GIR_Done, 13651 // Label 951: @31700 13652 GIM_Try, /*On fail goto*//*Label 952*/ 31739, // Rule ID 20899 // 13653 GIM_CheckFeatures, GIFBS_In64BitMode, 13654 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16, 13655 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR16RegClassID, 13656 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR16RegClassID, 13657 // (trunc:{ *:[i8] } GR16:{ *:[i16] }:$src) => (EXTRACT_SUBREG:{ *:[i8] } GR16:{ *:[i16] }:$src, sub_8bit:{ *:[i32] }) 13658 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 13659 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 13660 GIR_CopySubReg, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/1, // src 13661 GIR_EraseFromParent, /*InsnID*/0, 13662 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, X86::GR8RegClassID, 13663 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, X86::GR16RegClassID, 13664 // GIR_Coverage, 20899, 13665 GIR_Done, 13666 // Label 952: @31739 13667 GIM_Reject, 13668 // Label 940: @31740 13669 GIM_Try, /*On fail goto*//*Label 953*/ 31777, // Rule ID 20892 // 13670 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 13671 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID, 13672 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR32RegClassID, 13673 // (trunc:{ *:[i16] } GR32:{ *:[i32] }:$src) => (EXTRACT_SUBREG:{ *:[i16] } GR32:{ *:[i32] }:$src, sub_16bit:{ *:[i32] }) 13674 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 13675 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 13676 GIR_CopySubReg, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/4, // src 13677 GIR_EraseFromParent, /*InsnID*/0, 13678 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, X86::GR16RegClassID, 13679 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, X86::GR32RegClassID, 13680 // GIR_Coverage, 20892, 13681 GIR_Done, 13682 // Label 953: @31777 13683 GIM_Reject, 13684 // Label 941: @31778 13685 GIM_Try, /*On fail goto*//*Label 954*/ 31900, 13686 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s64, 13687 GIM_Try, /*On fail goto*//*Label 955*/ 31803, // Rule ID 11967 // 13688 GIM_CheckFeatures, GIFBS_HasAVX512_HasVLX, 13689 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID, 13690 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID, 13691 // (trunc:{ *:[v4i32] } VR256X:{ *:[v4i64] }:$src) => (VPMOVQDZ256rr:{ *:[v4i32] } VR256X:{ *:[v4i64] }:$src) 13692 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMOVQDZ256rr, 13693 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13694 // GIR_Coverage, 11967, 13695 GIR_Done, 13696 // Label 955: @31803 13697 GIM_Try, /*On fail goto*//*Label 956*/ 31899, // Rule ID 20012 // 13698 GIM_CheckFeatures, GIFBS_HasAVX512_NoVLX, 13699 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID, 13700 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID, 13701 // (trunc:{ *:[v4i32] } VR256X:{ *:[v4i64] }:$src) => (EXTRACT_SUBREG:{ *:[v4i32] } (VPMOVQDZrr:{ *:[v8i32] } (INSERT_SUBREG:{ *:[v8i64] } (IMPLICIT_DEF:{ *:[v8i64] }), VR256X:{ *:[v4i64] }:$src, sub_ymm:{ *:[i32] })), sub_xmm:{ *:[i32] }) 13702 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s32, 13703 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s64, 13704 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v8s64, 13705 GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::IMPLICIT_DEF, 13706 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, 13707 GIR_ConstrainSelectedInstOperands, /*InsnID*/3, 13708 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::INSERT_SUBREG, 13709 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 13710 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/2, /*TempRegFlags*/0, 13711 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src 13712 GIR_AddImm, /*InsnID*/2, /*Imm*/10, 13713 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, X86::VR512RegClassID, 13714 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, X86::VR512RegClassID, 13715 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, X86::VR256XRegClassID, 13716 GIR_BuildMI, /*InsnID*/1, /*Opcode*/X86::VPMOVQDZrr, 13717 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 13718 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, 13719 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 13720 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 13721 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 13722 GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, X86::sub_xmm, 13723 GIR_EraseFromParent, /*InsnID*/0, 13724 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, X86::FR16XRegClassID, 13725 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, X86::VR256XRegClassID, 13726 // GIR_Coverage, 20012, 13727 GIR_Done, 13728 // Label 956: @31899 13729 GIM_Reject, 13730 // Label 954: @31900 13731 GIM_Reject, 13732 // Label 942: @31901 13733 GIM_Try, /*On fail goto*//*Label 957*/ 31924, // Rule ID 11943 // 13734 GIM_CheckFeatures, GIFBS_HasAVX512, 13735 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s64, 13736 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID, 13737 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR512RegClassID, 13738 // (trunc:{ *:[v8i16] } VR512:{ *:[v8i64] }:$src) => (VPMOVQWZrr:{ *:[v8i16] } VR512:{ *:[v8i64] }:$src) 13739 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMOVQWZrr, 13740 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13741 // GIR_Coverage, 11943, 13742 GIR_Done, 13743 // Label 957: @31924 13744 GIM_Try, /*On fail goto*//*Label 958*/ 31947, // Rule ID 12021 // 13745 GIM_CheckFeatures, GIFBS_HasAVX512_HasVLX, 13746 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s32, 13747 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID, 13748 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID, 13749 // (trunc:{ *:[v8i16] } VR256X:{ *:[v8i32] }:$src) => (VPMOVDWZ256rr:{ *:[v8i16] } VR256X:{ *:[v8i32] }:$src) 13750 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMOVDWZ256rr, 13751 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13752 // GIR_Coverage, 12021, 13753 GIR_Done, 13754 // Label 958: @31947 13755 GIM_Try, /*On fail goto*//*Label 959*/ 32047, // Rule ID 20011 // 13756 GIM_CheckFeatures, GIFBS_HasAVX512_NoVLX, 13757 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s32, 13758 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID, 13759 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID, 13760 // (trunc:{ *:[v8i16] } VR256X:{ *:[v8i32] }:$src) => (EXTRACT_SUBREG:{ *:[v8i16] } (VPMOVDWZrr:{ *:[v16i16] } (INSERT_SUBREG:{ *:[v16i32] } (IMPLICIT_DEF:{ *:[v16i32] }), VR256X:{ *:[v8i32] }:$src, sub_ymm:{ *:[i32] })), sub_xmm:{ *:[i32] }) 13761 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s16, 13762 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s32, 13763 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s32, 13764 GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::IMPLICIT_DEF, 13765 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, 13766 GIR_ConstrainSelectedInstOperands, /*InsnID*/3, 13767 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::INSERT_SUBREG, 13768 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 13769 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/2, /*TempRegFlags*/0, 13770 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src 13771 GIR_AddImm, /*InsnID*/2, /*Imm*/10, 13772 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, X86::VR512RegClassID, 13773 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, X86::VR512RegClassID, 13774 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, X86::VR256XRegClassID, 13775 GIR_BuildMI, /*InsnID*/1, /*Opcode*/X86::VPMOVDWZrr, 13776 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 13777 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, 13778 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 13779 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 13780 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 13781 GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, X86::sub_xmm, 13782 GIR_EraseFromParent, /*InsnID*/0, 13783 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, X86::FR16XRegClassID, 13784 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, X86::VR256XRegClassID, 13785 // GIR_Coverage, 20011, 13786 GIR_Done, 13787 // Label 959: @32047 13788 GIM_Reject, 13789 // Label 943: @32048 13790 GIM_Try, /*On fail goto*//*Label 960*/ 32071, // Rule ID 11970 // 13791 GIM_CheckFeatures, GIFBS_HasAVX512, 13792 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s64, 13793 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID, 13794 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR512RegClassID, 13795 // (trunc:{ *:[v8i32] } VR512:{ *:[v8i64] }:$src) => (VPMOVQDZrr:{ *:[v8i32] } VR512:{ *:[v8i64] }:$src) 13796 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMOVQDZrr, 13797 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13798 // GIR_Coverage, 11970, 13799 GIR_Done, 13800 // Label 960: @32071 13801 GIM_Reject, 13802 // Label 944: @32072 13803 GIM_Try, /*On fail goto*//*Label 961*/ 32095, // Rule ID 11997 // 13804 GIM_CheckFeatures, GIFBS_HasAVX512, 13805 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s32, 13806 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID, 13807 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR512RegClassID, 13808 // (trunc:{ *:[v16i8] } VR512:{ *:[v16i32] }:$src) => (VPMOVDBZrr:{ *:[v16i8] } VR512:{ *:[v16i32] }:$src) 13809 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMOVDBZrr, 13810 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13811 // GIR_Coverage, 11997, 13812 GIR_Done, 13813 // Label 961: @32095 13814 GIM_Try, /*On fail goto*//*Label 962*/ 32118, // Rule ID 12048 // 13815 GIM_CheckFeatures, GIFBS_HasBWI_HasVLX, 13816 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s16, 13817 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID, 13818 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID, 13819 // (trunc:{ *:[v16i8] } VR256X:{ *:[v16i16] }:$src) => (VPMOVWBZ256rr:{ *:[v16i8] } VR256X:{ *:[v16i16] }:$src) 13820 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMOVWBZ256rr, 13821 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13822 // GIR_Coverage, 12048, 13823 GIR_Done, 13824 // Label 962: @32118 13825 GIM_Try, /*On fail goto*//*Label 963*/ 32218, // Rule ID 20013 // 13826 GIM_CheckFeatures, GIFBS_HasBWI_NoVLX, 13827 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s16, 13828 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID, 13829 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID, 13830 // (trunc:{ *:[v16i8] } VR256X:{ *:[v16i16] }:$src) => (EXTRACT_SUBREG:{ *:[v16i8] } (VPMOVWBZrr:{ *:[v32i8] } (INSERT_SUBREG:{ *:[v32i16] } (IMPLICIT_DEF:{ *:[v32i16] }), VR256X:{ *:[v16i16] }:$src, sub_ymm:{ *:[i32] })), sub_xmm:{ *:[i32] }) 13831 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v32s8, 13832 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v32s16, 13833 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v32s16, 13834 GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::IMPLICIT_DEF, 13835 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, 13836 GIR_ConstrainSelectedInstOperands, /*InsnID*/3, 13837 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::INSERT_SUBREG, 13838 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 13839 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/2, /*TempRegFlags*/0, 13840 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src 13841 GIR_AddImm, /*InsnID*/2, /*Imm*/10, 13842 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, X86::VR512RegClassID, 13843 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, X86::VR512RegClassID, 13844 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, X86::VR256XRegClassID, 13845 GIR_BuildMI, /*InsnID*/1, /*Opcode*/X86::VPMOVWBZrr, 13846 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 13847 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, 13848 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 13849 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 13850 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 13851 GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, X86::sub_xmm, 13852 GIR_EraseFromParent, /*InsnID*/0, 13853 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, X86::FR16XRegClassID, 13854 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, X86::VR256XRegClassID, 13855 // GIR_Coverage, 20013, 13856 GIR_Done, 13857 // Label 963: @32218 13858 GIM_Try, /*On fail goto*//*Label 964*/ 32266, // Rule ID 20104 // 13859 GIM_CheckFeatures, GIFBS_HasAVX512_NoBWI, 13860 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s16, 13861 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID, 13862 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID, 13863 // (trunc:{ *:[v16i8] } VR256X:{ *:[v16i16] }:$src) => (VPMOVDBZrr:{ *:[v16i8] } (VPMOVZXWDZrr:{ *:[v16i32] } VR256X:{ *:[v16i16] }:$src)) 13864 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s32, 13865 GIR_BuildMI, /*InsnID*/1, /*Opcode*/X86::VPMOVZXWDZrr, 13866 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 13867 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src 13868 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 13869 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VPMOVDBZrr, 13870 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 13871 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 13872 GIR_EraseFromParent, /*InsnID*/0, 13873 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13874 // GIR_Coverage, 20104, 13875 GIR_Done, 13876 // Label 964: @32266 13877 GIM_Reject, 13878 // Label 945: @32267 13879 GIM_Try, /*On fail goto*//*Label 965*/ 32290, // Rule ID 12024 // 13880 GIM_CheckFeatures, GIFBS_HasAVX512, 13881 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s32, 13882 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID, 13883 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR512RegClassID, 13884 // (trunc:{ *:[v16i16] } VR512:{ *:[v16i32] }:$src) => (VPMOVDWZrr:{ *:[v16i16] } VR512:{ *:[v16i32] }:$src) 13885 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMOVDWZrr, 13886 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13887 // GIR_Coverage, 12024, 13888 GIR_Done, 13889 // Label 965: @32290 13890 GIM_Reject, 13891 // Label 946: @32291 13892 GIM_Try, /*On fail goto*//*Label 966*/ 32314, // Rule ID 12051 // 13893 GIM_CheckFeatures, GIFBS_HasBWI, 13894 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v32s16, 13895 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID, 13896 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR512RegClassID, 13897 // (trunc:{ *:[v32i8] } VR512:{ *:[v32i16] }:$src) => (VPMOVWBZrr:{ *:[v32i8] } VR512:{ *:[v32i16] }:$src) 13898 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMOVWBZrr, 13899 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13900 // GIR_Coverage, 12051, 13901 GIR_Done, 13902 // Label 966: @32314 13903 GIM_Reject, 13904 // Label 947: @32315 13905 GIM_Reject, 13906 // Label 13: @32316 13907 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 5, /*)*//*default:*//*Label 971*/ 32584, 13908 /*GILLT_s8*//*Label 967*/ 32326, 13909 /*GILLT_s16*//*Label 968*/ 32348, 13910 /*GILLT_s32*//*Label 969*/ 32370, 13911 /*GILLT_s64*//*Label 970*/ 32488, 13912 // Label 967: @32326 13913 GIM_Try, /*On fail goto*//*Label 972*/ 32347, // Rule ID 19 // 13914 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR8RegClassID, 13915 // MIs[0] Operand 1 13916 // No operand predicates 13917 // (imm:{ *:[i8] }):$src => (MOV8ri:{ *:[i8] } (imm:{ *:[i8] }):$src) 13918 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::MOV8ri, 13919 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 13920 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // src 13921 GIR_EraseFromParent, /*InsnID*/0, 13922 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13923 // GIR_Coverage, 19, 13924 GIR_Done, 13925 // Label 972: @32347 13926 GIM_Reject, 13927 // Label 968: @32348 13928 GIM_Try, /*On fail goto*//*Label 973*/ 32369, // Rule ID 20 // 13929 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR16RegClassID, 13930 // MIs[0] Operand 1 13931 // No operand predicates 13932 // (imm:{ *:[i16] }):$src => (MOV16ri:{ *:[i16] } (imm:{ *:[i16] }):$src) 13933 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::MOV16ri, 13934 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 13935 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // src 13936 GIR_EraseFromParent, /*InsnID*/0, 13937 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13938 // GIR_Coverage, 20, 13939 GIR_Done, 13940 // Label 973: @32369 13941 GIM_Reject, 13942 // Label 969: @32370 13943 GIM_Try, /*On fail goto*//*Label 974*/ 32392, // Rule ID 15508 // 13944 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID, 13945 // MIs[0] Operand 1 13946 GIM_CheckLiteralInt, /*MI*/0, /*Op*/1, 0, 13947 // 0:{ *:[i32] } => (MOV32r0:{ *:[i32] }:{ *:[i32] }) 13948 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::MOV32r0, 13949 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 13950 GIR_EraseFromParent, /*InsnID*/0, 13951 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13952 // GIR_Coverage, 15508, 13953 GIR_Done, 13954 // Label 974: @32392 13955 GIM_Try, /*On fail goto*//*Label 975*/ 32416, // Rule ID 15509 // 13956 GIM_CheckFeatures, GIFBS_Not64BitMode_OptForSize, 13957 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID, 13958 // MIs[0] Operand 1 13959 GIM_CheckLiteralInt, /*MI*/0, /*Op*/1, 1, 13960 // 1:{ *:[i32] } => (MOV32r1:{ *:[i32] }:{ *:[i32] }) 13961 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::MOV32r1, 13962 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 13963 GIR_EraseFromParent, /*InsnID*/0, 13964 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13965 // GIR_Coverage, 15509, 13966 GIR_Done, 13967 // Label 975: @32416 13968 GIM_Try, /*On fail goto*//*Label 976*/ 32440, // Rule ID 15510 // 13969 GIM_CheckFeatures, GIFBS_Not64BitMode_OptForSize, 13970 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID, 13971 // MIs[0] Operand 1 13972 GIM_CheckLiteralInt, /*MI*/0, /*Op*/1, -1, 13973 // -1:{ *:[i32] } => (MOV32r_1:{ *:[i32] }:{ *:[i32] }) 13974 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::MOV32r_1, 13975 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 13976 GIR_EraseFromParent, /*InsnID*/0, 13977 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13978 // GIR_Coverage, 15510, 13979 GIR_Done, 13980 // Label 976: @32440 13981 GIM_Try, /*On fail goto*//*Label 977*/ 32466, // Rule ID 15511 // 13982 GIM_CheckFeatures, GIFBS_NotWin64WithoutFP_OptForMinSize, 13983 GIM_CheckI64ImmPredicate, /*MI*/0, /*Predicate*/GIPFP_I64_Predicate_i32immSExt8, 13984 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID, 13985 // MIs[0] Operand 1 13986 // No operand predicates 13987 // (imm:{ *:[i32] })<<P:Predicate_i32immSExt8>>:$src => (MOV32ImmSExti8:{ *:[i32] } (imm:{ *:[i32] }):$src) 13988 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::MOV32ImmSExti8, 13989 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 13990 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // src 13991 GIR_EraseFromParent, /*InsnID*/0, 13992 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13993 // GIR_Coverage, 15511, 13994 GIR_Done, 13995 // Label 977: @32466 13996 GIM_Try, /*On fail goto*//*Label 978*/ 32487, // Rule ID 21 // 13997 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID, 13998 // MIs[0] Operand 1 13999 // No operand predicates 14000 // (imm:{ *:[i32] }):$src => (MOV32ri:{ *:[i32] } (imm:{ *:[i32] }):$src) 14001 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::MOV32ri, 14002 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 14003 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // src 14004 GIR_EraseFromParent, /*InsnID*/0, 14005 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14006 // GIR_Coverage, 21, 14007 GIR_Done, 14008 // Label 978: @32487 14009 GIM_Reject, 14010 // Label 970: @32488 14011 GIM_Try, /*On fail goto*//*Label 979*/ 32514, // Rule ID 15512 // 14012 GIM_CheckFeatures, GIFBS_NotWin64WithoutFP_OptForMinSize, 14013 GIM_CheckI64ImmPredicate, /*MI*/0, /*Predicate*/GIPFP_I64_Predicate_i64immSExt8, 14014 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID, 14015 // MIs[0] Operand 1 14016 // No operand predicates 14017 // (imm:{ *:[i64] })<<P:Predicate_i64immSExt8>>:$src => (MOV64ImmSExti8:{ *:[i64] } (imm:{ *:[i64] }):$src) 14018 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::MOV64ImmSExti8, 14019 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 14020 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // src 14021 GIR_EraseFromParent, /*InsnID*/0, 14022 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14023 // GIR_Coverage, 15512, 14024 GIR_Done, 14025 // Label 979: @32514 14026 GIM_Try, /*On fail goto*//*Label 980*/ 32538, // Rule ID 15513 // 14027 GIM_CheckI64ImmPredicate, /*MI*/0, /*Predicate*/GIPFP_I64_Predicate_i64immZExt32, 14028 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID, 14029 // MIs[0] Operand 1 14030 // No operand predicates 14031 // (imm:{ *:[i64] })<<P:Predicate_i64immZExt32>>:$src => (MOV32ri64:{ *:[i64] } (imm:{ *:[i64] }):$src) 14032 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::MOV32ri64, 14033 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 14034 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // src 14035 GIR_EraseFromParent, /*InsnID*/0, 14036 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14037 // GIR_Coverage, 15513, 14038 GIR_Done, 14039 // Label 980: @32538 14040 GIM_Try, /*On fail goto*//*Label 981*/ 32562, // Rule ID 22 // 14041 GIM_CheckI64ImmPredicate, /*MI*/0, /*Predicate*/GIPFP_I64_Predicate_i64immSExt32, 14042 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID, 14043 // MIs[0] Operand 1 14044 // No operand predicates 14045 // (imm:{ *:[i64] })<<P:Predicate_i64immSExt32>>:$src => (MOV64ri32:{ *:[i64] } (imm:{ *:[i64] }):$src) 14046 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::MOV64ri32, 14047 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 14048 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // src 14049 GIR_EraseFromParent, /*InsnID*/0, 14050 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14051 // GIR_Coverage, 22, 14052 GIR_Done, 14053 // Label 981: @32562 14054 GIM_Try, /*On fail goto*//*Label 982*/ 32583, // Rule ID 23 // 14055 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID, 14056 // MIs[0] Operand 1 14057 // No operand predicates 14058 // (imm:{ *:[i64] }):$src => (MOV64ri:{ *:[i64] } (imm:{ *:[i64] }):$src) 14059 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::MOV64ri, 14060 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 14061 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // src 14062 GIR_EraseFromParent, /*InsnID*/0, 14063 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14064 // GIR_Coverage, 23, 14065 GIR_Done, 14066 // Label 982: @32583 14067 GIM_Reject, 14068 // Label 971: @32584 14069 GIM_Reject, 14070 // Label 14: @32585 14071 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/3, 6, /*)*//*default:*//*Label 986*/ 32735, 14072 /*GILLT_s32*//*Label 983*/ 32594, 14073 /*GILLT_s64*//*Label 984*/ 32641, 14074 /*GILLT_s80*//*Label 985*/ 32688, 14075 // Label 983: @32594 14076 GIM_Try, /*On fail goto*//*Label 987*/ 32617, // Rule ID 848 // 14077 GIM_CheckFeatures, GIFBS_FPStackf32, 14078 GIM_CheckAPFloatImmPredicate, /*MI*/0, /*Predicate*/GIPFP_APFloat_Predicate_fpimm0, 14079 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::RFP32RegClassID, 14080 // MIs[0] Operand 1 14081 // No operand predicates 14082 // (fpimm:{ *:[f32] })<<P:Predicate_fpimm0>> => (LD_Fp032:{ *:[f32] }:{ *:[i16] }) 14083 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::LD_Fp032, 14084 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 14085 GIR_EraseFromParent, /*InsnID*/0, 14086 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14087 // GIR_Coverage, 848, 14088 GIR_Done, 14089 // Label 987: @32617 14090 GIM_Try, /*On fail goto*//*Label 988*/ 32640, // Rule ID 849 // 14091 GIM_CheckFeatures, GIFBS_FPStackf32, 14092 GIM_CheckAPFloatImmPredicate, /*MI*/0, /*Predicate*/GIPFP_APFloat_Predicate_fpimm1, 14093 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::RFP32RegClassID, 14094 // MIs[0] Operand 1 14095 // No operand predicates 14096 // (fpimm:{ *:[f32] })<<P:Predicate_fpimm1>> => (LD_Fp132:{ *:[f32] }:{ *:[i16] }) 14097 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::LD_Fp132, 14098 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 14099 GIR_EraseFromParent, /*InsnID*/0, 14100 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14101 // GIR_Coverage, 849, 14102 GIR_Done, 14103 // Label 988: @32640 14104 GIM_Reject, 14105 // Label 984: @32641 14106 GIM_Try, /*On fail goto*//*Label 989*/ 32664, // Rule ID 850 // 14107 GIM_CheckFeatures, GIFBS_FPStackf64, 14108 GIM_CheckAPFloatImmPredicate, /*MI*/0, /*Predicate*/GIPFP_APFloat_Predicate_fpimm0, 14109 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::RFP64RegClassID, 14110 // MIs[0] Operand 1 14111 // No operand predicates 14112 // (fpimm:{ *:[f64] })<<P:Predicate_fpimm0>> => (LD_Fp064:{ *:[f64] }:{ *:[i16] }) 14113 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::LD_Fp064, 14114 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 14115 GIR_EraseFromParent, /*InsnID*/0, 14116 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14117 // GIR_Coverage, 850, 14118 GIR_Done, 14119 // Label 989: @32664 14120 GIM_Try, /*On fail goto*//*Label 990*/ 32687, // Rule ID 851 // 14121 GIM_CheckFeatures, GIFBS_FPStackf64, 14122 GIM_CheckAPFloatImmPredicate, /*MI*/0, /*Predicate*/GIPFP_APFloat_Predicate_fpimm1, 14123 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::RFP64RegClassID, 14124 // MIs[0] Operand 1 14125 // No operand predicates 14126 // (fpimm:{ *:[f64] })<<P:Predicate_fpimm1>> => (LD_Fp164:{ *:[f64] }:{ *:[i16] }) 14127 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::LD_Fp164, 14128 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 14129 GIR_EraseFromParent, /*InsnID*/0, 14130 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14131 // GIR_Coverage, 851, 14132 GIR_Done, 14133 // Label 990: @32687 14134 GIM_Reject, 14135 // Label 985: @32688 14136 GIM_Try, /*On fail goto*//*Label 991*/ 32711, // Rule ID 852 // 14137 GIM_CheckFeatures, GIFBS_HasX87, 14138 GIM_CheckAPFloatImmPredicate, /*MI*/0, /*Predicate*/GIPFP_APFloat_Predicate_fpimm0, 14139 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::RFP80RegClassID, 14140 // MIs[0] Operand 1 14141 // No operand predicates 14142 // (fpimm:{ *:[f80] })<<P:Predicate_fpimm0>> => (LD_Fp080:{ *:[f80] }:{ *:[i16] }) 14143 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::LD_Fp080, 14144 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 14145 GIR_EraseFromParent, /*InsnID*/0, 14146 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14147 // GIR_Coverage, 852, 14148 GIR_Done, 14149 // Label 991: @32711 14150 GIM_Try, /*On fail goto*//*Label 992*/ 32734, // Rule ID 853 // 14151 GIM_CheckFeatures, GIFBS_HasX87, 14152 GIM_CheckAPFloatImmPredicate, /*MI*/0, /*Predicate*/GIPFP_APFloat_Predicate_fpimm1, 14153 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::RFP80RegClassID, 14154 // MIs[0] Operand 1 14155 // No operand predicates 14156 // (fpimm:{ *:[f80] })<<P:Predicate_fpimm1>> => (LD_Fp180:{ *:[f80] }:{ *:[i16] }) 14157 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::LD_Fp180, 14158 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 14159 GIR_EraseFromParent, /*InsnID*/0, 14160 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14161 // GIR_Coverage, 853, 14162 GIR_Done, 14163 // Label 992: @32734 14164 GIM_Reject, 14165 // Label 986: @32735 14166 GIM_Reject, 14167 // Label 15: @32736 14168 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/2, 25, /*)*//*default:*//*Label 1008*/ 33595, 14169 /*GILLT_s16*//*Label 993*/ 32765, 14170 /*GILLT_s32*//*Label 994*/ 32819, 14171 /*GILLT_s64*//*Label 995*/ 32862, 0, 0, 0, 14172 /*GILLT_v2s64*//*Label 996*/ 32928, 0, 14173 /*GILLT_v4s32*//*Label 997*/ 32952, 14174 /*GILLT_v4s64*//*Label 998*/ 32976, 0, 14175 /*GILLT_v8s16*//*Label 999*/ 33046, 14176 /*GILLT_v8s32*//*Label 1000*/ 33109, 14177 /*GILLT_v8s64*//*Label 1001*/ 33179, 0, 14178 /*GILLT_v16s8*//*Label 1002*/ 33249, 14179 /*GILLT_v16s16*//*Label 1003*/ 33312, 14180 /*GILLT_v16s32*//*Label 1004*/ 33430, 0, 14181 /*GILLT_v32s8*//*Label 1005*/ 33500, 14182 /*GILLT_v32s16*//*Label 1006*/ 33524, 0, 14183 /*GILLT_v64s8*//*Label 1007*/ 33571, 14184 // Label 993: @32765 14185 GIM_Try, /*On fail goto*//*Label 1009*/ 32818, // Rule ID 20888 // 14186 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s8, 14187 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID, 14188 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR8RegClassID, 14189 // (sext:{ *:[i16] } GR8:{ *:[i8] }:$src) => (EXTRACT_SUBREG:{ *:[i16] } (MOVSX32rr8:{ *:[i32] } GR8:{ *:[i8] }:$src), sub_16bit:{ *:[i32] }) 14190 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, 14191 GIR_BuildMI, /*InsnID*/1, /*Opcode*/X86::MOVSX32rr8, 14192 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 14193 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src 14194 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 14195 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 14196 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 14197 GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, X86::sub_16bit, 14198 GIR_EraseFromParent, /*InsnID*/0, 14199 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, X86::GR16RegClassID, 14200 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, X86::GR32RegClassID, 14201 // GIR_Coverage, 20888, 14202 GIR_Done, 14203 // Label 1009: @32818 14204 GIM_Reject, 14205 // Label 994: @32819 14206 GIM_Try, /*On fail goto*//*Label 1010*/ 32840, // Rule ID 417 // 14207 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s8, 14208 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID, 14209 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR8RegClassID, 14210 // (sext:{ *:[i32] } GR8:{ *:[i8] }:$src) => (MOVSX32rr8:{ *:[i32] } GR8:{ *:[i8] }:$src) 14211 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::MOVSX32rr8, 14212 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14213 // GIR_Coverage, 417, 14214 GIR_Done, 14215 // Label 1010: @32840 14216 GIM_Try, /*On fail goto*//*Label 1011*/ 32861, // Rule ID 419 // 14217 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16, 14218 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID, 14219 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR16RegClassID, 14220 // (sext:{ *:[i32] } GR16:{ *:[i16] }:$src) => (MOVSX32rr16:{ *:[i32] } GR16:{ *:[i16] }:$src) 14221 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::MOVSX32rr16, 14222 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14223 // GIR_Coverage, 419, 14224 GIR_Done, 14225 // Label 1011: @32861 14226 GIM_Reject, 14227 // Label 995: @32862 14228 GIM_Try, /*On fail goto*//*Label 1012*/ 32883, // Rule ID 425 // 14229 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s8, 14230 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID, 14231 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR8RegClassID, 14232 // (sext:{ *:[i64] } GR8:{ *:[i8] }:$src) => (MOVSX64rr8:{ *:[i64] } GR8:{ *:[i8] }:$src) 14233 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::MOVSX64rr8, 14234 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14235 // GIR_Coverage, 425, 14236 GIR_Done, 14237 // Label 1012: @32883 14238 GIM_Try, /*On fail goto*//*Label 1013*/ 32904, // Rule ID 427 // 14239 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16, 14240 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID, 14241 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR16RegClassID, 14242 // (sext:{ *:[i64] } GR16:{ *:[i16] }:$src) => (MOVSX64rr16:{ *:[i64] } GR16:{ *:[i16] }:$src) 14243 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::MOVSX64rr16, 14244 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14245 // GIR_Coverage, 427, 14246 GIR_Done, 14247 // Label 1013: @32904 14248 GIM_Try, /*On fail goto*//*Label 1014*/ 32927, // Rule ID 429 // 14249 GIM_CheckFeatures, GIFBS_In64BitMode, 14250 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 14251 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID, 14252 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR32RegClassID, 14253 // (sext:{ *:[i64] } GR32:{ *:[i32] }:$src) => (MOVSX64rr32:{ *:[i64] } GR32:{ *:[i32] }:$src) 14254 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::MOVSX64rr32, 14255 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14256 // GIR_Coverage, 429, 14257 GIR_Done, 14258 // Label 1014: @32927 14259 GIM_Reject, 14260 // Label 996: @32928 14261 GIM_Try, /*On fail goto*//*Label 1015*/ 32951, // Rule ID 12299 // 14262 GIM_CheckFeatures, GIFBS_HasDQI_HasVLX, 14263 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s1, 14264 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID, 14265 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VK2RegClassID, 14266 // (sext:{ *:[v2i64] } VK2:{ *:[v2i1] }:$src) => (VPMOVM2QZ128rr:{ *:[v2i64] } VK2:{ *:[v2i1] }:$src) 14267 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMOVM2QZ128rr, 14268 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14269 // GIR_Coverage, 12299, 14270 GIR_Done, 14271 // Label 1015: @32951 14272 GIM_Reject, 14273 // Label 997: @32952 14274 GIM_Try, /*On fail goto*//*Label 1016*/ 32975, // Rule ID 12296 // 14275 GIM_CheckFeatures, GIFBS_HasDQI_HasVLX, 14276 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s1, 14277 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID, 14278 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VK4RegClassID, 14279 // (sext:{ *:[v4i32] } VK4:{ *:[v4i1] }:$src) => (VPMOVM2DZ128rr:{ *:[v4i32] } VK4:{ *:[v4i1] }:$src) 14280 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMOVM2DZ128rr, 14281 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14282 // GIR_Coverage, 12296, 14283 GIR_Done, 14284 // Label 1016: @32975 14285 GIM_Reject, 14286 // Label 998: @32976 14287 GIM_Try, /*On fail goto*//*Label 1017*/ 32999, // Rule ID 12276 // 14288 GIM_CheckFeatures, GIFBS_HasAVX512_HasVLX, 14289 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, 14290 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID, 14291 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID, 14292 // (sext:{ *:[v4i64] } VR128X:{ *:[v4i32] }:$src) => (VPMOVSXDQZ256rr:{ *:[v4i64] } VR128X:{ *:[v4i32] }:$src) 14293 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMOVSXDQZ256rr, 14294 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14295 // GIR_Coverage, 12276, 14296 GIR_Done, 14297 // Label 1017: @32999 14298 GIM_Try, /*On fail goto*//*Label 1018*/ 33022, // Rule ID 12298 // 14299 GIM_CheckFeatures, GIFBS_HasDQI_HasVLX, 14300 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s1, 14301 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID, 14302 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VK4RegClassID, 14303 // (sext:{ *:[v4i64] } VK4:{ *:[v4i1] }:$src) => (VPMOVM2QZ256rr:{ *:[v4i64] } VK4:{ *:[v4i1] }:$src) 14304 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMOVM2QZ256rr, 14305 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14306 // GIR_Coverage, 12298, 14307 GIR_Done, 14308 // Label 1018: @33022 14309 GIM_Try, /*On fail goto*//*Label 1019*/ 33045, // Rule ID 16825 // 14310 GIM_CheckFeatures, GIFBS_HasAVX2_NoVLX, 14311 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, 14312 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID, 14313 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 14314 // (sext:{ *:[v4i64] } VR128:{ *:[v4i32] }:$src) => (VPMOVSXDQYrr:{ *:[v4i64] } VR128:{ *:[v4i32] }:$src) 14315 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMOVSXDQYrr, 14316 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14317 // GIR_Coverage, 16825, 14318 GIR_Done, 14319 // Label 1019: @33045 14320 GIM_Reject, 14321 // Label 999: @33046 14322 GIM_Try, /*On fail goto*//*Label 1020*/ 33108, 14323 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s1, 14324 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID, 14325 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VK8RegClassID, 14326 GIM_Try, /*On fail goto*//*Label 1021*/ 33071, // Rule ID 12293 // 14327 GIM_CheckFeatures, GIFBS_HasBWI_HasVLX, 14328 // (sext:{ *:[v8i16] } VK8:{ *:[v8i1] }:$src) => (VPMOVM2WZ128rr:{ *:[v8i16] } VK8:{ *:[v8i1] }:$src) 14329 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMOVM2WZ128rr, 14330 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14331 // GIR_Coverage, 12293, 14332 GIR_Done, 14333 // Label 1021: @33071 14334 GIM_Try, /*On fail goto*//*Label 1022*/ 33107, // Rule ID 20116 // 14335 GIM_CheckFeatures, GIFBS_HasDQI_HasVLX_NoBWI, 14336 // (sext:{ *:[v8i16] } VK8:{ *:[v8i1] }:$src) => (VPMOVDWZ256rr:{ *:[v8i16] } (VPMOVM2DZ256rr:{ *:[v8i32] } VK8:{ *:[v8i1] }:$src)) 14337 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s32, 14338 GIR_BuildMI, /*InsnID*/1, /*Opcode*/X86::VPMOVM2DZ256rr, 14339 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 14340 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src 14341 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 14342 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VPMOVDWZ256rr, 14343 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 14344 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 14345 GIR_EraseFromParent, /*InsnID*/0, 14346 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14347 // GIR_Coverage, 20116, 14348 GIR_Done, 14349 // Label 1022: @33107 14350 GIM_Reject, 14351 // Label 1020: @33108 14352 GIM_Reject, 14353 // Label 1000: @33109 14354 GIM_Try, /*On fail goto*//*Label 1023*/ 33132, // Rule ID 12240 // 14355 GIM_CheckFeatures, GIFBS_HasAVX512_HasVLX, 14356 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, 14357 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID, 14358 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID, 14359 // (sext:{ *:[v8i32] } VR128X:{ *:[v8i16] }:$src) => (VPMOVSXWDZ256rr:{ *:[v8i32] } VR128X:{ *:[v8i16] }:$src) 14360 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMOVSXWDZ256rr, 14361 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14362 // GIR_Coverage, 12240, 14363 GIR_Done, 14364 // Label 1023: @33132 14365 GIM_Try, /*On fail goto*//*Label 1024*/ 33155, // Rule ID 12295 // 14366 GIM_CheckFeatures, GIFBS_HasDQI_HasVLX, 14367 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s1, 14368 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID, 14369 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VK8RegClassID, 14370 // (sext:{ *:[v8i32] } VK8:{ *:[v8i1] }:$src) => (VPMOVM2DZ256rr:{ *:[v8i32] } VK8:{ *:[v8i1] }:$src) 14371 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMOVM2DZ256rr, 14372 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14373 // GIR_Coverage, 12295, 14374 GIR_Done, 14375 // Label 1024: @33155 14376 GIM_Try, /*On fail goto*//*Label 1025*/ 33178, // Rule ID 16823 // 14377 GIM_CheckFeatures, GIFBS_HasAVX2_NoVLX, 14378 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, 14379 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID, 14380 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 14381 // (sext:{ *:[v8i32] } VR128:{ *:[v8i16] }:$src) => (VPMOVSXWDYrr:{ *:[v8i32] } VR128:{ *:[v8i16] }:$src) 14382 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMOVSXWDYrr, 14383 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14384 // GIR_Coverage, 16823, 14385 GIR_Done, 14386 // Label 1025: @33178 14387 GIM_Reject, 14388 // Label 1001: @33179 14389 GIM_Try, /*On fail goto*//*Label 1026*/ 33202, // Rule ID 12264 // 14390 GIM_CheckFeatures, GIFBS_HasAVX512, 14391 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, 14392 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 14393 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID, 14394 // (sext:{ *:[v8i64] } VR128X:{ *:[v8i16] }:$src) => (VPMOVSXWQZrr:{ *:[v8i64] } VR128X:{ *:[v8i16] }:$src) 14395 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMOVSXWQZrr, 14396 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14397 // GIR_Coverage, 12264, 14398 GIR_Done, 14399 // Label 1026: @33202 14400 GIM_Try, /*On fail goto*//*Label 1027*/ 33225, // Rule ID 12282 // 14401 GIM_CheckFeatures, GIFBS_HasAVX512, 14402 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s32, 14403 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 14404 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID, 14405 // (sext:{ *:[v8i64] } VR256X:{ *:[v8i32] }:$src) => (VPMOVSXDQZrr:{ *:[v8i64] } VR256X:{ *:[v8i32] }:$src) 14406 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMOVSXDQZrr, 14407 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14408 // GIR_Coverage, 12282, 14409 GIR_Done, 14410 // Label 1027: @33225 14411 GIM_Try, /*On fail goto*//*Label 1028*/ 33248, // Rule ID 12297 // 14412 GIM_CheckFeatures, GIFBS_HasDQI, 14413 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s1, 14414 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 14415 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VK8RegClassID, 14416 // (sext:{ *:[v8i64] } VK8:{ *:[v8i1] }:$src) => (VPMOVM2QZrr:{ *:[v8i64] } VK8:{ *:[v8i1] }:$src) 14417 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMOVM2QZrr, 14418 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14419 // GIR_Coverage, 12297, 14420 GIR_Done, 14421 // Label 1028: @33248 14422 GIM_Reject, 14423 // Label 1002: @33249 14424 GIM_Try, /*On fail goto*//*Label 1029*/ 33311, 14425 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s1, 14426 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID, 14427 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VK16RegClassID, 14428 GIM_Try, /*On fail goto*//*Label 1030*/ 33274, // Rule ID 12290 // 14429 GIM_CheckFeatures, GIFBS_HasBWI_HasVLX, 14430 // (sext:{ *:[v16i8] } VK16:{ *:[v16i1] }:$src) => (VPMOVM2BZ128rr:{ *:[v16i8] } VK16:{ *:[v16i1] }:$src) 14431 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMOVM2BZ128rr, 14432 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14433 // GIR_Coverage, 12290, 14434 GIR_Done, 14435 // Label 1030: @33274 14436 GIM_Try, /*On fail goto*//*Label 1031*/ 33310, // Rule ID 20114 // 14437 GIM_CheckFeatures, GIFBS_HasDQI_NoBWI, 14438 // (sext:{ *:[v16i8] } VK16:{ *:[v16i1] }:$src) => (VPMOVDBZrr:{ *:[v16i8] } (VPMOVM2DZrr:{ *:[v16i32] } VK16:{ *:[v16i1] }:$src)) 14439 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s32, 14440 GIR_BuildMI, /*InsnID*/1, /*Opcode*/X86::VPMOVM2DZrr, 14441 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 14442 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src 14443 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 14444 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VPMOVDBZrr, 14445 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 14446 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 14447 GIR_EraseFromParent, /*InsnID*/0, 14448 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14449 // GIR_Coverage, 20114, 14450 GIR_Done, 14451 // Label 1031: @33310 14452 GIM_Reject, 14453 // Label 1029: @33311 14454 GIM_Reject, 14455 // Label 1003: @33312 14456 GIM_Try, /*On fail goto*//*Label 1032*/ 33335, // Rule ID 12186 // 14457 GIM_CheckFeatures, GIFBS_HasBWI_HasVLX, 14458 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, 14459 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID, 14460 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID, 14461 // (sext:{ *:[v16i16] } VR128X:{ *:[v16i8] }:$src) => (VPMOVSXBWZ256rr:{ *:[v16i16] } VR128X:{ *:[v16i8] }:$src) 14462 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMOVSXBWZ256rr, 14463 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14464 // GIR_Coverage, 12186, 14465 GIR_Done, 14466 // Label 1032: @33335 14467 GIM_Try, /*On fail goto*//*Label 1033*/ 33358, // Rule ID 12292 // 14468 GIM_CheckFeatures, GIFBS_HasBWI_HasVLX, 14469 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s1, 14470 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID, 14471 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VK16RegClassID, 14472 // (sext:{ *:[v16i16] } VK16:{ *:[v16i1] }:$src) => (VPMOVM2WZ256rr:{ *:[v16i16] } VK16:{ *:[v16i1] }:$src) 14473 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMOVM2WZ256rr, 14474 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14475 // GIR_Coverage, 12292, 14476 GIR_Done, 14477 // Label 1033: @33358 14478 GIM_Try, /*On fail goto*//*Label 1034*/ 33381, // Rule ID 16820 // 14479 GIM_CheckFeatures, GIFBS_HasAVX2_NoVLX_Or_NoBWI, 14480 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, 14481 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID, 14482 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 14483 // (sext:{ *:[v16i16] } VR128:{ *:[v16i8] }:$src) => (VPMOVSXBWYrr:{ *:[v16i16] } VR128:{ *:[v16i8] }:$src) 14484 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMOVSXBWYrr, 14485 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14486 // GIR_Coverage, 16820, 14487 GIR_Done, 14488 // Label 1034: @33381 14489 GIM_Try, /*On fail goto*//*Label 1035*/ 33429, // Rule ID 20115 // 14490 GIM_CheckFeatures, GIFBS_HasDQI_NoBWI, 14491 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s1, 14492 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID, 14493 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VK16RegClassID, 14494 // (sext:{ *:[v16i16] } VK16:{ *:[v16i1] }:$src) => (VPMOVDWZrr:{ *:[v16i16] } (VPMOVM2DZrr:{ *:[v16i32] } VK16:{ *:[v16i1] }:$src)) 14495 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s32, 14496 GIR_BuildMI, /*InsnID*/1, /*Opcode*/X86::VPMOVM2DZrr, 14497 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 14498 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src 14499 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 14500 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VPMOVDWZrr, 14501 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 14502 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 14503 GIR_EraseFromParent, /*InsnID*/0, 14504 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14505 // GIR_Coverage, 20115, 14506 GIR_Done, 14507 // Label 1035: @33429 14508 GIM_Reject, 14509 // Label 1004: @33430 14510 GIM_Try, /*On fail goto*//*Label 1036*/ 33453, // Rule ID 12210 // 14511 GIM_CheckFeatures, GIFBS_HasAVX512, 14512 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, 14513 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 14514 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID, 14515 // (sext:{ *:[v16i32] } VR128X:{ *:[v16i8] }:$src) => (VPMOVSXBDZrr:{ *:[v16i32] } VR128X:{ *:[v16i8] }:$src) 14516 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMOVSXBDZrr, 14517 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14518 // GIR_Coverage, 12210, 14519 GIR_Done, 14520 // Label 1036: @33453 14521 GIM_Try, /*On fail goto*//*Label 1037*/ 33476, // Rule ID 12246 // 14522 GIM_CheckFeatures, GIFBS_HasAVX512, 14523 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s16, 14524 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 14525 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID, 14526 // (sext:{ *:[v16i32] } VR256X:{ *:[v16i16] }:$src) => (VPMOVSXWDZrr:{ *:[v16i32] } VR256X:{ *:[v16i16] }:$src) 14527 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMOVSXWDZrr, 14528 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14529 // GIR_Coverage, 12246, 14530 GIR_Done, 14531 // Label 1037: @33476 14532 GIM_Try, /*On fail goto*//*Label 1038*/ 33499, // Rule ID 12294 // 14533 GIM_CheckFeatures, GIFBS_HasDQI, 14534 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s1, 14535 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 14536 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VK16RegClassID, 14537 // (sext:{ *:[v16i32] } VK16:{ *:[v16i1] }:$src) => (VPMOVM2DZrr:{ *:[v16i32] } VK16:{ *:[v16i1] }:$src) 14538 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMOVM2DZrr, 14539 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14540 // GIR_Coverage, 12294, 14541 GIR_Done, 14542 // Label 1038: @33499 14543 GIM_Reject, 14544 // Label 1005: @33500 14545 GIM_Try, /*On fail goto*//*Label 1039*/ 33523, // Rule ID 12289 // 14546 GIM_CheckFeatures, GIFBS_HasBWI_HasVLX, 14547 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v32s1, 14548 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID, 14549 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VK32RegClassID, 14550 // (sext:{ *:[v32i8] } VK32:{ *:[v32i1] }:$src) => (VPMOVM2BZ256rr:{ *:[v32i8] } VK32:{ *:[v32i1] }:$src) 14551 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMOVM2BZ256rr, 14552 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14553 // GIR_Coverage, 12289, 14554 GIR_Done, 14555 // Label 1039: @33523 14556 GIM_Reject, 14557 // Label 1006: @33524 14558 GIM_Try, /*On fail goto*//*Label 1040*/ 33547, // Rule ID 12192 // 14559 GIM_CheckFeatures, GIFBS_HasBWI, 14560 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v32s8, 14561 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 14562 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID, 14563 // (sext:{ *:[v32i16] } VR256X:{ *:[v32i8] }:$src) => (VPMOVSXBWZrr:{ *:[v32i16] } VR256X:{ *:[v32i8] }:$src) 14564 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMOVSXBWZrr, 14565 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14566 // GIR_Coverage, 12192, 14567 GIR_Done, 14568 // Label 1040: @33547 14569 GIM_Try, /*On fail goto*//*Label 1041*/ 33570, // Rule ID 12291 // 14570 GIM_CheckFeatures, GIFBS_HasBWI, 14571 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v32s1, 14572 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 14573 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VK32RegClassID, 14574 // (sext:{ *:[v32i16] } VK32:{ *:[v32i1] }:$src) => (VPMOVM2WZrr:{ *:[v32i16] } VK32:{ *:[v32i1] }:$src) 14575 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMOVM2WZrr, 14576 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14577 // GIR_Coverage, 12291, 14578 GIR_Done, 14579 // Label 1041: @33570 14580 GIM_Reject, 14581 // Label 1007: @33571 14582 GIM_Try, /*On fail goto*//*Label 1042*/ 33594, // Rule ID 12288 // 14583 GIM_CheckFeatures, GIFBS_HasBWI, 14584 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v64s1, 14585 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 14586 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VK64RegClassID, 14587 // (sext:{ *:[v64i8] } VK64:{ *:[v64i1] }:$src) => (VPMOVM2BZrr:{ *:[v64i8] } VK64:{ *:[v64i1] }:$src) 14588 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMOVM2BZrr, 14589 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14590 // GIR_Coverage, 12288, 14591 GIR_Done, 14592 // Label 1042: @33594 14593 GIM_Reject, 14594 // Label 1008: @33595 14595 GIM_Reject, 14596 // Label 16: @33596 14597 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/2, 23, /*)*//*default:*//*Label 1052*/ 34383, 14598 /*GILLT_s16*//*Label 1043*/ 33623, 14599 /*GILLT_s32*//*Label 1044*/ 33677, 14600 /*GILLT_s64*//*Label 1045*/ 33808, 0, 0, 0, 0, 0, 0, 14601 /*GILLT_v4s64*//*Label 1046*/ 34127, 0, 0, 14602 /*GILLT_v8s32*//*Label 1047*/ 34173, 14603 /*GILLT_v8s64*//*Label 1048*/ 34219, 0, 0, 14604 /*GILLT_v16s16*//*Label 1049*/ 34266, 14605 /*GILLT_v16s32*//*Label 1050*/ 34312, 0, 0, 14606 /*GILLT_v32s16*//*Label 1051*/ 34359, 14607 // Label 1043: @33623 14608 GIM_Try, /*On fail goto*//*Label 1053*/ 33676, // Rule ID 20890 // 14609 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s8, 14610 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID, 14611 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR8RegClassID, 14612 // (zext:{ *:[i16] } GR8:{ *:[i8] }:$src) => (EXTRACT_SUBREG:{ *:[i16] } (MOVZX32rr8:{ *:[i32] } GR8:{ *:[i8] }:$src), sub_16bit:{ *:[i32] }) 14613 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, 14614 GIR_BuildMI, /*InsnID*/1, /*Opcode*/X86::MOVZX32rr8, 14615 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 14616 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src 14617 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 14618 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 14619 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 14620 GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, X86::sub_16bit, 14621 GIR_EraseFromParent, /*InsnID*/0, 14622 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, X86::GR16RegClassID, 14623 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, X86::GR32RegClassID, 14624 // GIR_Coverage, 20890, 14625 GIR_Done, 14626 // Label 1053: @33676 14627 GIM_Reject, 14628 // Label 1044: @33677 14629 GIM_Try, /*On fail goto*//*Label 1054*/ 33720, // Rule ID 17874 // 14630 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16, 14631 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID, 14632 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 14633 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_BITCAST, 14634 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s1, 14635 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::VK16RegClassID, 14636 GIM_CheckIsSafeToFold, /*InsnID*/1, 14637 // (zext:{ *:[i32] } (bitconvert:{ *:[i16] } VK16:{ *:[v16i1] }:$src)) => (KMOVWrk:{ *:[i32] } VK16:{ *:[v16i1] }:$src) 14638 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::KMOVWrk, 14639 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 14640 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src 14641 GIR_EraseFromParent, /*InsnID*/0, 14642 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14643 // GIR_Coverage, 17874, 14644 GIR_Done, 14645 // Label 1054: @33720 14646 GIM_Try, /*On fail goto*//*Label 1055*/ 33765, // Rule ID 17877 // 14647 GIM_CheckFeatures, GIFBS_HasDQI, 14648 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s8, 14649 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID, 14650 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 14651 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_BITCAST, 14652 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s1, 14653 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::VK8RegClassID, 14654 GIM_CheckIsSafeToFold, /*InsnID*/1, 14655 // (zext:{ *:[i32] } (bitconvert:{ *:[i8] } VK8:{ *:[v8i1] }:$src)) => (KMOVBrk:{ *:[i32] } VK8:{ *:[v8i1] }:$src) 14656 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::KMOVBrk, 14657 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 14658 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src 14659 GIR_EraseFromParent, /*InsnID*/0, 14660 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14661 // GIR_Coverage, 17877, 14662 GIR_Done, 14663 // Label 1055: @33765 14664 GIM_Try, /*On fail goto*//*Label 1056*/ 33786, // Rule ID 421 // 14665 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s8, 14666 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID, 14667 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR8RegClassID, 14668 // (zext:{ *:[i32] } GR8:{ *:[i8] }:$src) => (MOVZX32rr8:{ *:[i32] } GR8:{ *:[i8] }:$src) 14669 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::MOVZX32rr8, 14670 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14671 // GIR_Coverage, 421, 14672 GIR_Done, 14673 // Label 1056: @33786 14674 GIM_Try, /*On fail goto*//*Label 1057*/ 33807, // Rule ID 423 // 14675 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16, 14676 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID, 14677 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR16RegClassID, 14678 // (zext:{ *:[i32] } GR16:{ *:[i16] }:$src) => (MOVZX32rr16:{ *:[i32] } GR16:{ *:[i16] }:$src) 14679 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::MOVZX32rr16, 14680 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14681 // GIR_Coverage, 423, 14682 GIR_Done, 14683 // Label 1057: @33807 14684 GIM_Reject, 14685 // Label 1045: @33808 14686 GIM_Try, /*On fail goto*//*Label 1058*/ 33879, // Rule ID 17875 // 14687 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16, 14688 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID, 14689 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 14690 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_BITCAST, 14691 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s1, 14692 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::VK16RegClassID, 14693 GIM_CheckIsSafeToFold, /*InsnID*/1, 14694 // (zext:{ *:[i64] } (bitconvert:{ *:[i16] } VK16:{ *:[v16i1] }:$src)) => (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (KMOVWrk:{ *:[i32] } VK16:{ *:[v16i1] }:$src), sub_32bit:{ *:[i32] }) 14695 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, 14696 GIR_BuildMI, /*InsnID*/1, /*Opcode*/X86::KMOVWrk, 14697 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 14698 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // src 14699 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 14700 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::SUBREG_TO_REG, 14701 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 14702 GIR_AddImm, /*InsnID*/0, /*Imm*/0, 14703 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 14704 GIR_AddImm, /*InsnID*/0, /*Imm*/6, 14705 GIR_EraseFromParent, /*InsnID*/0, 14706 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, X86::GR64RegClassID, 14707 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, X86::GR32RegClassID, 14708 // GIR_Coverage, 17875, 14709 GIR_Done, 14710 // Label 1058: @33879 14711 GIM_Try, /*On fail goto*//*Label 1059*/ 33952, // Rule ID 17878 // 14712 GIM_CheckFeatures, GIFBS_HasDQI, 14713 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s8, 14714 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID, 14715 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 14716 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_BITCAST, 14717 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s1, 14718 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::VK8RegClassID, 14719 GIM_CheckIsSafeToFold, /*InsnID*/1, 14720 // (zext:{ *:[i64] } (bitconvert:{ *:[i8] } VK8:{ *:[v8i1] }:$src)) => (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (KMOVBrk:{ *:[i32] } VK8:{ *:[v8i1] }:$src), sub_32bit:{ *:[i32] }) 14721 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, 14722 GIR_BuildMI, /*InsnID*/1, /*Opcode*/X86::KMOVBrk, 14723 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 14724 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // src 14725 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 14726 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::SUBREG_TO_REG, 14727 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 14728 GIR_AddImm, /*InsnID*/0, /*Imm*/0, 14729 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 14730 GIR_AddImm, /*InsnID*/0, /*Imm*/6, 14731 GIR_EraseFromParent, /*InsnID*/0, 14732 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, X86::GR64RegClassID, 14733 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, X86::GR32RegClassID, 14734 // GIR_Coverage, 17878, 14735 GIR_Done, 14736 // Label 1059: @33952 14737 GIM_Try, /*On fail goto*//*Label 1060*/ 34010, // Rule ID 16113 // 14738 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s8, 14739 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID, 14740 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR8RegClassID, 14741 // (zext:{ *:[i64] } GR8:{ *:[i8] }:$src) => (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (MOVZX32rr8:{ *:[i32] } GR8:{ *:[i8] }:$src), sub_32bit:{ *:[i32] }) 14742 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, 14743 GIR_BuildMI, /*InsnID*/1, /*Opcode*/X86::MOVZX32rr8, 14744 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 14745 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src 14746 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 14747 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::SUBREG_TO_REG, 14748 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 14749 GIR_AddImm, /*InsnID*/0, /*Imm*/0, 14750 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 14751 GIR_AddImm, /*InsnID*/0, /*Imm*/6, 14752 GIR_EraseFromParent, /*InsnID*/0, 14753 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, X86::GR64RegClassID, 14754 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, X86::GR32RegClassID, 14755 // GIR_Coverage, 16113, 14756 GIR_Done, 14757 // Label 1060: @34010 14758 GIM_Try, /*On fail goto*//*Label 1061*/ 34068, // Rule ID 16115 // 14759 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16, 14760 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID, 14761 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR16RegClassID, 14762 // (zext:{ *:[i64] } GR16:{ *:[i16] }:$src) => (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (MOVZX32rr16:{ *:[i32] } GR16:{ *:[i16] }:$src), sub_32bit:{ *:[i32] }) 14763 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, 14764 GIR_BuildMI, /*InsnID*/1, /*Opcode*/X86::MOVZX32rr16, 14765 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 14766 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src 14767 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 14768 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::SUBREG_TO_REG, 14769 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 14770 GIR_AddImm, /*InsnID*/0, /*Imm*/0, 14771 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 14772 GIR_AddImm, /*InsnID*/0, /*Imm*/6, 14773 GIR_EraseFromParent, /*InsnID*/0, 14774 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, X86::GR64RegClassID, 14775 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, X86::GR32RegClassID, 14776 // GIR_Coverage, 16115, 14777 GIR_Done, 14778 // Label 1061: @34068 14779 GIM_Try, /*On fail goto*//*Label 1062*/ 34126, // Rule ID 16117 // 14780 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 14781 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID, 14782 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR32RegClassID, 14783 // (zext:{ *:[i64] } GR32:{ *:[i32] }:$src) => (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (MOV32rr:{ *:[i32] } GR32:{ *:[i32] }:$src), sub_32bit:{ *:[i32] }) 14784 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, 14785 GIR_BuildMI, /*InsnID*/1, /*Opcode*/X86::MOV32rr, 14786 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 14787 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src 14788 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 14789 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::SUBREG_TO_REG, 14790 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 14791 GIR_AddImm, /*InsnID*/0, /*Imm*/0, 14792 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 14793 GIR_AddImm, /*InsnID*/0, /*Imm*/6, 14794 GIR_EraseFromParent, /*InsnID*/0, 14795 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, X86::GR64RegClassID, 14796 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, X86::GR32RegClassID, 14797 // GIR_Coverage, 16117, 14798 GIR_Done, 14799 // Label 1062: @34126 14800 GIM_Reject, 14801 // Label 1046: @34127 14802 GIM_Try, /*On fail goto*//*Label 1063*/ 34172, 14803 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, 14804 GIM_Try, /*On fail goto*//*Label 1064*/ 34152, // Rule ID 12168 // 14805 GIM_CheckFeatures, GIFBS_HasAVX512_HasVLX, 14806 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID, 14807 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID, 14808 // (zext:{ *:[v4i64] } VR128X:{ *:[v4i32] }:$src) => (VPMOVZXDQZ256rr:{ *:[v4i64] } VR128X:{ *:[v4i32] }:$src) 14809 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMOVZXDQZ256rr, 14810 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14811 // GIR_Coverage, 12168, 14812 GIR_Done, 14813 // Label 1064: @34152 14814 GIM_Try, /*On fail goto*//*Label 1065*/ 34171, // Rule ID 16848 // 14815 GIM_CheckFeatures, GIFBS_HasAVX2_NoVLX, 14816 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID, 14817 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 14818 // (zext:{ *:[v4i64] } VR128:{ *:[v4i32] }:$src) => (VPMOVZXDQYrr:{ *:[v4i64] } VR128:{ *:[v4i32] }:$src) 14819 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMOVZXDQYrr, 14820 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14821 // GIR_Coverage, 16848, 14822 GIR_Done, 14823 // Label 1065: @34171 14824 GIM_Reject, 14825 // Label 1063: @34172 14826 GIM_Reject, 14827 // Label 1047: @34173 14828 GIM_Try, /*On fail goto*//*Label 1066*/ 34218, 14829 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, 14830 GIM_Try, /*On fail goto*//*Label 1067*/ 34198, // Rule ID 12132 // 14831 GIM_CheckFeatures, GIFBS_HasAVX512_HasVLX, 14832 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID, 14833 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID, 14834 // (zext:{ *:[v8i32] } VR128X:{ *:[v8i16] }:$src) => (VPMOVZXWDZ256rr:{ *:[v8i32] } VR128X:{ *:[v8i16] }:$src) 14835 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMOVZXWDZ256rr, 14836 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14837 // GIR_Coverage, 12132, 14838 GIR_Done, 14839 // Label 1067: @34198 14840 GIM_Try, /*On fail goto*//*Label 1068*/ 34217, // Rule ID 16846 // 14841 GIM_CheckFeatures, GIFBS_HasAVX2_NoVLX, 14842 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID, 14843 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 14844 // (zext:{ *:[v8i32] } VR128:{ *:[v8i16] }:$src) => (VPMOVZXWDYrr:{ *:[v8i32] } VR128:{ *:[v8i16] }:$src) 14845 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMOVZXWDYrr, 14846 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14847 // GIR_Coverage, 16846, 14848 GIR_Done, 14849 // Label 1068: @34217 14850 GIM_Reject, 14851 // Label 1066: @34218 14852 GIM_Reject, 14853 // Label 1048: @34219 14854 GIM_Try, /*On fail goto*//*Label 1069*/ 34242, // Rule ID 12156 // 14855 GIM_CheckFeatures, GIFBS_HasAVX512, 14856 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, 14857 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 14858 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID, 14859 // (zext:{ *:[v8i64] } VR128X:{ *:[v8i16] }:$src) => (VPMOVZXWQZrr:{ *:[v8i64] } VR128X:{ *:[v8i16] }:$src) 14860 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMOVZXWQZrr, 14861 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14862 // GIR_Coverage, 12156, 14863 GIR_Done, 14864 // Label 1069: @34242 14865 GIM_Try, /*On fail goto*//*Label 1070*/ 34265, // Rule ID 12174 // 14866 GIM_CheckFeatures, GIFBS_HasAVX512, 14867 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s32, 14868 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 14869 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID, 14870 // (zext:{ *:[v8i64] } VR256X:{ *:[v8i32] }:$src) => (VPMOVZXDQZrr:{ *:[v8i64] } VR256X:{ *:[v8i32] }:$src) 14871 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMOVZXDQZrr, 14872 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14873 // GIR_Coverage, 12174, 14874 GIR_Done, 14875 // Label 1070: @34265 14876 GIM_Reject, 14877 // Label 1049: @34266 14878 GIM_Try, /*On fail goto*//*Label 1071*/ 34311, 14879 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, 14880 GIM_Try, /*On fail goto*//*Label 1072*/ 34291, // Rule ID 12078 // 14881 GIM_CheckFeatures, GIFBS_HasBWI_HasVLX, 14882 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID, 14883 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID, 14884 // (zext:{ *:[v16i16] } VR128X:{ *:[v16i8] }:$src) => (VPMOVZXBWZ256rr:{ *:[v16i16] } VR128X:{ *:[v16i8] }:$src) 14885 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMOVZXBWZ256rr, 14886 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14887 // GIR_Coverage, 12078, 14888 GIR_Done, 14889 // Label 1072: @34291 14890 GIM_Try, /*On fail goto*//*Label 1073*/ 34310, // Rule ID 16843 // 14891 GIM_CheckFeatures, GIFBS_HasAVX2_NoVLX_Or_NoBWI, 14892 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID, 14893 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 14894 // (zext:{ *:[v16i16] } VR128:{ *:[v16i8] }:$src) => (VPMOVZXBWYrr:{ *:[v16i16] } VR128:{ *:[v16i8] }:$src) 14895 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMOVZXBWYrr, 14896 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14897 // GIR_Coverage, 16843, 14898 GIR_Done, 14899 // Label 1073: @34310 14900 GIM_Reject, 14901 // Label 1071: @34311 14902 GIM_Reject, 14903 // Label 1050: @34312 14904 GIM_Try, /*On fail goto*//*Label 1074*/ 34335, // Rule ID 12102 // 14905 GIM_CheckFeatures, GIFBS_HasAVX512, 14906 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, 14907 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 14908 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID, 14909 // (zext:{ *:[v16i32] } VR128X:{ *:[v16i8] }:$src) => (VPMOVZXBDZrr:{ *:[v16i32] } VR128X:{ *:[v16i8] }:$src) 14910 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMOVZXBDZrr, 14911 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14912 // GIR_Coverage, 12102, 14913 GIR_Done, 14914 // Label 1074: @34335 14915 GIM_Try, /*On fail goto*//*Label 1075*/ 34358, // Rule ID 12138 // 14916 GIM_CheckFeatures, GIFBS_HasAVX512, 14917 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s16, 14918 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 14919 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID, 14920 // (zext:{ *:[v16i32] } VR256X:{ *:[v16i16] }:$src) => (VPMOVZXWDZrr:{ *:[v16i32] } VR256X:{ *:[v16i16] }:$src) 14921 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMOVZXWDZrr, 14922 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14923 // GIR_Coverage, 12138, 14924 GIR_Done, 14925 // Label 1075: @34358 14926 GIM_Reject, 14927 // Label 1051: @34359 14928 GIM_Try, /*On fail goto*//*Label 1076*/ 34382, // Rule ID 12084 // 14929 GIM_CheckFeatures, GIFBS_HasBWI, 14930 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v32s8, 14931 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 14932 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID, 14933 // (zext:{ *:[v32i16] } VR256X:{ *:[v32i8] }:$src) => (VPMOVZXBWZrr:{ *:[v32i16] } VR256X:{ *:[v32i8] }:$src) 14934 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMOVZXBWZrr, 14935 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14936 // GIR_Coverage, 12084, 14937 GIR_Done, 14938 // Label 1076: @34382 14939 GIM_Reject, 14940 // Label 1052: @34383 14941 GIM_Reject, 14942 // Label 17: @34384 14943 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 5, /*)*//*default:*//*Label 1081*/ 34976, 14944 /*GILLT_s8*//*Label 1077*/ 34394, 14945 /*GILLT_s16*//*Label 1078*/ 34503, 14946 /*GILLT_s32*//*Label 1079*/ 34612, 14947 /*GILLT_s64*//*Label 1080*/ 34794, 14948 // Label 1077: @34394 14949 GIM_Try, /*On fail goto*//*Label 1082*/ 34502, 14950 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s8, 14951 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s8, 14952 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR8RegClassID, 14953 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR8RegClassID, 14954 GIM_Try, /*On fail goto*//*Label 1083*/ 34438, // Rule ID 20915 // 14955 GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 1, 14956 // (shl:{ *:[i8] } GR8:{ *:[i8] }:$src1, 1:{ *:[i8] }) => (ADD8rr:{ *:[i8] }:{ *:[i32] } GR8:{ *:[i8] }:$src1, GR8:{ *:[i8] }:$src1) 14957 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::ADD8rr, 14958 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 14959 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 14960 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 14961 GIR_EraseFromParent, /*InsnID*/0, 14962 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14963 // GIR_Coverage, 20915, 14964 GIR_Done, 14965 // Label 1083: @34438 14966 GIM_Try, /*On fail goto*//*Label 1084*/ 34468, // Rule ID 467 // 14967 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 14968 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 14969 // MIs[1] Operand 1 14970 // No operand predicates 14971 GIM_CheckIsSafeToFold, /*InsnID*/1, 14972 // (shl:{ *:[i8] } GR8:{ *:[i8] }:$src1, (imm:{ *:[i8] }):$src2) => (SHL8ri:{ *:[i8] }:{ *:[i32] } GR8:{ *:[i8] }:$src1, (imm:{ *:[i8] }):$src2) 14973 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SHL8ri, 14974 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 14975 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 14976 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // src2 14977 GIR_EraseFromParent, /*InsnID*/0, 14978 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14979 // GIR_Coverage, 467, 14980 GIR_Done, 14981 // Label 1084: @34468 14982 GIM_Try, /*On fail goto*//*Label 1085*/ 34501, // Rule ID 463 // 14983 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::GR8_ABCD_LRegClassID, 14984 // (shl:{ *:[i8] } GR8:{ *:[i8] }:$src1, CL:{ *:[i8] }) => (SHL8rCL:{ *:[i8] }:{ *:[i32] } GR8:{ *:[i8] }:$src1) 14985 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, 14986 GIR_AddRegister, /*InsnID*/1, X86::CL, /*AddRegisterRegFlags*/RegState::Define, 14987 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // CL 14988 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SHL8rCL, 14989 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 14990 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 14991 GIR_EraseFromParent, /*InsnID*/0, 14992 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14993 // GIR_Coverage, 463, 14994 GIR_Done, 14995 // Label 1085: @34501 14996 GIM_Reject, 14997 // Label 1082: @34502 14998 GIM_Reject, 14999 // Label 1078: @34503 15000 GIM_Try, /*On fail goto*//*Label 1086*/ 34611, 15001 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16, 15002 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s8, 15003 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR16RegClassID, 15004 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR16RegClassID, 15005 GIM_Try, /*On fail goto*//*Label 1087*/ 34547, // Rule ID 20916 // 15006 GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 1, 15007 // (shl:{ *:[i16] } GR16:{ *:[i16] }:$src1, 1:{ *:[i8] }) => (ADD16rr:{ *:[i16] }:{ *:[i32] } GR16:{ *:[i16] }:$src1, GR16:{ *:[i16] }:$src1) 15008 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::ADD16rr, 15009 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 15010 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 15011 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 15012 GIR_EraseFromParent, /*InsnID*/0, 15013 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15014 // GIR_Coverage, 20916, 15015 GIR_Done, 15016 // Label 1087: @34547 15017 GIM_Try, /*On fail goto*//*Label 1088*/ 34577, // Rule ID 468 // 15018 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 15019 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 15020 // MIs[1] Operand 1 15021 // No operand predicates 15022 GIM_CheckIsSafeToFold, /*InsnID*/1, 15023 // (shl:{ *:[i16] } GR16:{ *:[i16] }:$src1, (imm:{ *:[i8] }):$src2) => (SHL16ri:{ *:[i16] }:{ *:[i32] } GR16:{ *:[i16] }:$src1, (imm:{ *:[i8] }):$src2) 15024 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SHL16ri, 15025 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 15026 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 15027 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // src2 15028 GIR_EraseFromParent, /*InsnID*/0, 15029 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15030 // GIR_Coverage, 468, 15031 GIR_Done, 15032 // Label 1088: @34577 15033 GIM_Try, /*On fail goto*//*Label 1089*/ 34610, // Rule ID 464 // 15034 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::GR8_ABCD_LRegClassID, 15035 // (shl:{ *:[i16] } GR16:{ *:[i16] }:$src1, CL:{ *:[i8] }) => (SHL16rCL:{ *:[i16] }:{ *:[i32] } GR16:{ *:[i16] }:$src1) 15036 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, 15037 GIR_AddRegister, /*InsnID*/1, X86::CL, /*AddRegisterRegFlags*/RegState::Define, 15038 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // CL 15039 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SHL16rCL, 15040 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 15041 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 15042 GIR_EraseFromParent, /*InsnID*/0, 15043 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15044 // GIR_Coverage, 464, 15045 GIR_Done, 15046 // Label 1089: @34610 15047 GIM_Reject, 15048 // Label 1086: @34611 15049 GIM_Reject, 15050 // Label 1079: @34612 15051 GIM_Try, /*On fail goto*//*Label 1090*/ 34793, 15052 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 15053 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s8, 15054 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID, 15055 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR32RegClassID, 15056 GIM_Try, /*On fail goto*//*Label 1091*/ 34656, // Rule ID 20917 // 15057 GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 1, 15058 // (shl:{ *:[i32] } GR32:{ *:[i32] }:$src1, 1:{ *:[i8] }) => (ADD32rr:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src1, GR32:{ *:[i32] }:$src1) 15059 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::ADD32rr, 15060 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 15061 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 15062 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 15063 GIR_EraseFromParent, /*InsnID*/0, 15064 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15065 // GIR_Coverage, 20917, 15066 GIR_Done, 15067 // Label 1091: @34656 15068 GIM_Try, /*On fail goto*//*Label 1092*/ 34686, // Rule ID 469 // 15069 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 15070 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 15071 // MIs[1] Operand 1 15072 // No operand predicates 15073 GIM_CheckIsSafeToFold, /*InsnID*/1, 15074 // (shl:{ *:[i32] } GR32:{ *:[i32] }:$src1, (imm:{ *:[i8] }):$src2) => (SHL32ri:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src1, (imm:{ *:[i8] }):$src2) 15075 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SHL32ri, 15076 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 15077 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 15078 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // src2 15079 GIR_EraseFromParent, /*InsnID*/0, 15080 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15081 // GIR_Coverage, 469, 15082 GIR_Done, 15083 // Label 1092: @34686 15084 GIM_Try, /*On fail goto*//*Label 1093*/ 34759, // Rule ID 16147 // 15085 GIM_CheckFeatures, GIFBS_HasBMI2, 15086 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::GR8RegClassID, 15087 // (shl:{ *:[i32] } GR32:{ *:[i32] }:$src1, GR8:{ *:[i8] }:$src2) => (SHLX32rr:{ *:[i32] } GR32:{ *:[i32] }:$src1, (INSERT_SUBREG:{ *:[i32] } (IMPLICIT_DEF:{ *:[i32] }), GR8:{ *:[i8] }:$src2, sub_8bit:{ *:[i32] })) 15088 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, 15089 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, 15090 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, 15091 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 15092 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 15093 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, 15094 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 15095 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, 15096 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // src2 15097 GIR_AddImm, /*InsnID*/1, /*Imm*/1, 15098 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID, 15099 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID, 15100 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, X86::GR8RegClassID, 15101 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SHLX32rr, 15102 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 15103 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 15104 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 15105 GIR_EraseFromParent, /*InsnID*/0, 15106 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15107 // GIR_Coverage, 16147, 15108 GIR_Done, 15109 // Label 1093: @34759 15110 GIM_Try, /*On fail goto*//*Label 1094*/ 34792, // Rule ID 465 // 15111 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::GR8_ABCD_LRegClassID, 15112 // (shl:{ *:[i32] } GR32:{ *:[i32] }:$src1, CL:{ *:[i8] }) => (SHL32rCL:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src1) 15113 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, 15114 GIR_AddRegister, /*InsnID*/1, X86::CL, /*AddRegisterRegFlags*/RegState::Define, 15115 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // CL 15116 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SHL32rCL, 15117 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 15118 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 15119 GIR_EraseFromParent, /*InsnID*/0, 15120 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15121 // GIR_Coverage, 465, 15122 GIR_Done, 15123 // Label 1094: @34792 15124 GIM_Reject, 15125 // Label 1090: @34793 15126 GIM_Reject, 15127 // Label 1080: @34794 15128 GIM_Try, /*On fail goto*//*Label 1095*/ 34975, 15129 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 15130 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s8, 15131 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID, 15132 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR64RegClassID, 15133 GIM_Try, /*On fail goto*//*Label 1096*/ 34838, // Rule ID 20918 // 15134 GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 1, 15135 // (shl:{ *:[i64] } GR64:{ *:[i64] }:$src1, 1:{ *:[i8] }) => (ADD64rr:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src1, GR64:{ *:[i64] }:$src1) 15136 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::ADD64rr, 15137 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 15138 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 15139 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 15140 GIR_EraseFromParent, /*InsnID*/0, 15141 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15142 // GIR_Coverage, 20918, 15143 GIR_Done, 15144 // Label 1096: @34838 15145 GIM_Try, /*On fail goto*//*Label 1097*/ 34868, // Rule ID 470 // 15146 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 15147 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 15148 // MIs[1] Operand 1 15149 // No operand predicates 15150 GIM_CheckIsSafeToFold, /*InsnID*/1, 15151 // (shl:{ *:[i64] } GR64:{ *:[i64] }:$src1, (imm:{ *:[i8] }):$src2) => (SHL64ri:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src1, (imm:{ *:[i8] }):$src2) 15152 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SHL64ri, 15153 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 15154 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 15155 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // src2 15156 GIR_EraseFromParent, /*InsnID*/0, 15157 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15158 // GIR_Coverage, 470, 15159 GIR_Done, 15160 // Label 1097: @34868 15161 GIM_Try, /*On fail goto*//*Label 1098*/ 34941, // Rule ID 16148 // 15162 GIM_CheckFeatures, GIFBS_HasBMI2, 15163 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::GR8RegClassID, 15164 // (shl:{ *:[i64] } GR64:{ *:[i64] }:$src1, GR8:{ *:[i8] }:$src2) => (SHLX64rr:{ *:[i64] } GR64:{ *:[i64] }:$src1, (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), GR8:{ *:[i8] }:$src2, sub_8bit:{ *:[i32] })) 15165 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, 15166 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, 15167 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, 15168 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 15169 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 15170 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, 15171 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 15172 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, 15173 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // src2 15174 GIR_AddImm, /*InsnID*/1, /*Imm*/1, 15175 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, X86::GR64_with_sub_8bitRegClassID, 15176 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, X86::GR64_with_sub_8bitRegClassID, 15177 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, X86::GR8RegClassID, 15178 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SHLX64rr, 15179 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 15180 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 15181 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 15182 GIR_EraseFromParent, /*InsnID*/0, 15183 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15184 // GIR_Coverage, 16148, 15185 GIR_Done, 15186 // Label 1098: @34941 15187 GIM_Try, /*On fail goto*//*Label 1099*/ 34974, // Rule ID 466 // 15188 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::GR8_ABCD_LRegClassID, 15189 // (shl:{ *:[i64] } GR64:{ *:[i64] }:$src1, CL:{ *:[i8] }) => (SHL64rCL:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src1) 15190 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, 15191 GIR_AddRegister, /*InsnID*/1, X86::CL, /*AddRegisterRegFlags*/RegState::Define, 15192 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // CL 15193 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SHL64rCL, 15194 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 15195 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 15196 GIR_EraseFromParent, /*InsnID*/0, 15197 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15198 // GIR_Coverage, 466, 15199 GIR_Done, 15200 // Label 1099: @34974 15201 GIM_Reject, 15202 // Label 1095: @34975 15203 GIM_Reject, 15204 // Label 1081: @34976 15205 GIM_Reject, 15206 // Label 18: @34977 15207 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 5, /*)*//*default:*//*Label 1104*/ 35553, 15208 /*GILLT_s8*//*Label 1100*/ 34987, 15209 /*GILLT_s16*//*Label 1101*/ 35092, 15210 /*GILLT_s32*//*Label 1102*/ 35197, 15211 /*GILLT_s64*//*Label 1103*/ 35375, 15212 // Label 1100: @34987 15213 GIM_Try, /*On fail goto*//*Label 1105*/ 35091, 15214 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s8, 15215 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s8, 15216 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR8RegClassID, 15217 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR8RegClassID, 15218 GIM_Try, /*On fail goto*//*Label 1106*/ 35027, // Rule ID 491 // 15219 GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 1, 15220 // (srl:{ *:[i8] } GR8:{ *:[i8] }:$src1, 1:{ *:[i8] }) => (SHR8r1:{ *:[i8] }:{ *:[i32] } GR8:{ *:[i8] }:$src1) 15221 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SHR8r1, 15222 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 15223 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 15224 GIR_EraseFromParent, /*InsnID*/0, 15225 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15226 // GIR_Coverage, 491, 15227 GIR_Done, 15228 // Label 1106: @35027 15229 GIM_Try, /*On fail goto*//*Label 1107*/ 35057, // Rule ID 487 // 15230 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 15231 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 15232 // MIs[1] Operand 1 15233 // No operand predicates 15234 GIM_CheckIsSafeToFold, /*InsnID*/1, 15235 // (srl:{ *:[i8] } GR8:{ *:[i8] }:$src1, (imm:{ *:[i8] }):$src2) => (SHR8ri:{ *:[i8] }:{ *:[i32] } GR8:{ *:[i8] }:$src1, (imm:{ *:[i8] }):$src2) 15236 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SHR8ri, 15237 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 15238 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 15239 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // src2 15240 GIR_EraseFromParent, /*InsnID*/0, 15241 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15242 // GIR_Coverage, 487, 15243 GIR_Done, 15244 // Label 1107: @35057 15245 GIM_Try, /*On fail goto*//*Label 1108*/ 35090, // Rule ID 483 // 15246 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::GR8_ABCD_LRegClassID, 15247 // (srl:{ *:[i8] } GR8:{ *:[i8] }:$src1, CL:{ *:[i8] }) => (SHR8rCL:{ *:[i8] }:{ *:[i32] } GR8:{ *:[i8] }:$src1) 15248 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, 15249 GIR_AddRegister, /*InsnID*/1, X86::CL, /*AddRegisterRegFlags*/RegState::Define, 15250 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // CL 15251 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SHR8rCL, 15252 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 15253 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 15254 GIR_EraseFromParent, /*InsnID*/0, 15255 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15256 // GIR_Coverage, 483, 15257 GIR_Done, 15258 // Label 1108: @35090 15259 GIM_Reject, 15260 // Label 1105: @35091 15261 GIM_Reject, 15262 // Label 1101: @35092 15263 GIM_Try, /*On fail goto*//*Label 1109*/ 35196, 15264 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16, 15265 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s8, 15266 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR16RegClassID, 15267 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR16RegClassID, 15268 GIM_Try, /*On fail goto*//*Label 1110*/ 35132, // Rule ID 492 // 15269 GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 1, 15270 // (srl:{ *:[i16] } GR16:{ *:[i16] }:$src1, 1:{ *:[i8] }) => (SHR16r1:{ *:[i16] }:{ *:[i32] } GR16:{ *:[i16] }:$src1) 15271 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SHR16r1, 15272 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 15273 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 15274 GIR_EraseFromParent, /*InsnID*/0, 15275 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15276 // GIR_Coverage, 492, 15277 GIR_Done, 15278 // Label 1110: @35132 15279 GIM_Try, /*On fail goto*//*Label 1111*/ 35162, // Rule ID 488 // 15280 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 15281 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 15282 // MIs[1] Operand 1 15283 // No operand predicates 15284 GIM_CheckIsSafeToFold, /*InsnID*/1, 15285 // (srl:{ *:[i16] } GR16:{ *:[i16] }:$src1, (imm:{ *:[i8] }):$src2) => (SHR16ri:{ *:[i16] }:{ *:[i32] } GR16:{ *:[i16] }:$src1, (imm:{ *:[i8] }):$src2) 15286 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SHR16ri, 15287 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 15288 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 15289 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // src2 15290 GIR_EraseFromParent, /*InsnID*/0, 15291 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15292 // GIR_Coverage, 488, 15293 GIR_Done, 15294 // Label 1111: @35162 15295 GIM_Try, /*On fail goto*//*Label 1112*/ 35195, // Rule ID 484 // 15296 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::GR8_ABCD_LRegClassID, 15297 // (srl:{ *:[i16] } GR16:{ *:[i16] }:$src1, CL:{ *:[i8] }) => (SHR16rCL:{ *:[i16] }:{ *:[i32] } GR16:{ *:[i16] }:$src1) 15298 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, 15299 GIR_AddRegister, /*InsnID*/1, X86::CL, /*AddRegisterRegFlags*/RegState::Define, 15300 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // CL 15301 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SHR16rCL, 15302 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 15303 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 15304 GIR_EraseFromParent, /*InsnID*/0, 15305 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15306 // GIR_Coverage, 484, 15307 GIR_Done, 15308 // Label 1112: @35195 15309 GIM_Reject, 15310 // Label 1109: @35196 15311 GIM_Reject, 15312 // Label 1102: @35197 15313 GIM_Try, /*On fail goto*//*Label 1113*/ 35374, 15314 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 15315 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s8, 15316 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID, 15317 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR32RegClassID, 15318 GIM_Try, /*On fail goto*//*Label 1114*/ 35237, // Rule ID 493 // 15319 GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 1, 15320 // (srl:{ *:[i32] } GR32:{ *:[i32] }:$src1, 1:{ *:[i8] }) => (SHR32r1:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src1) 15321 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SHR32r1, 15322 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 15323 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 15324 GIR_EraseFromParent, /*InsnID*/0, 15325 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15326 // GIR_Coverage, 493, 15327 GIR_Done, 15328 // Label 1114: @35237 15329 GIM_Try, /*On fail goto*//*Label 1115*/ 35267, // Rule ID 489 // 15330 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 15331 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 15332 // MIs[1] Operand 1 15333 // No operand predicates 15334 GIM_CheckIsSafeToFold, /*InsnID*/1, 15335 // (srl:{ *:[i32] } GR32:{ *:[i32] }:$src1, (imm:{ *:[i8] }):$src2) => (SHR32ri:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src1, (imm:{ *:[i8] }):$src2) 15336 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SHR32ri, 15337 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 15338 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 15339 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // src2 15340 GIR_EraseFromParent, /*InsnID*/0, 15341 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15342 // GIR_Coverage, 489, 15343 GIR_Done, 15344 // Label 1115: @35267 15345 GIM_Try, /*On fail goto*//*Label 1116*/ 35340, // Rule ID 16145 // 15346 GIM_CheckFeatures, GIFBS_HasBMI2, 15347 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::GR8RegClassID, 15348 // (srl:{ *:[i32] } GR32:{ *:[i32] }:$src1, GR8:{ *:[i8] }:$src2) => (SHRX32rr:{ *:[i32] } GR32:{ *:[i32] }:$src1, (INSERT_SUBREG:{ *:[i32] } (IMPLICIT_DEF:{ *:[i32] }), GR8:{ *:[i8] }:$src2, sub_8bit:{ *:[i32] })) 15349 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, 15350 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, 15351 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, 15352 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 15353 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 15354 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, 15355 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 15356 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, 15357 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // src2 15358 GIR_AddImm, /*InsnID*/1, /*Imm*/1, 15359 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID, 15360 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID, 15361 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, X86::GR8RegClassID, 15362 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SHRX32rr, 15363 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 15364 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 15365 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 15366 GIR_EraseFromParent, /*InsnID*/0, 15367 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15368 // GIR_Coverage, 16145, 15369 GIR_Done, 15370 // Label 1116: @35340 15371 GIM_Try, /*On fail goto*//*Label 1117*/ 35373, // Rule ID 485 // 15372 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::GR8_ABCD_LRegClassID, 15373 // (srl:{ *:[i32] } GR32:{ *:[i32] }:$src1, CL:{ *:[i8] }) => (SHR32rCL:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src1) 15374 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, 15375 GIR_AddRegister, /*InsnID*/1, X86::CL, /*AddRegisterRegFlags*/RegState::Define, 15376 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // CL 15377 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SHR32rCL, 15378 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 15379 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 15380 GIR_EraseFromParent, /*InsnID*/0, 15381 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15382 // GIR_Coverage, 485, 15383 GIR_Done, 15384 // Label 1117: @35373 15385 GIM_Reject, 15386 // Label 1113: @35374 15387 GIM_Reject, 15388 // Label 1103: @35375 15389 GIM_Try, /*On fail goto*//*Label 1118*/ 35552, 15390 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 15391 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s8, 15392 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID, 15393 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR64RegClassID, 15394 GIM_Try, /*On fail goto*//*Label 1119*/ 35415, // Rule ID 494 // 15395 GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 1, 15396 // (srl:{ *:[i64] } GR64:{ *:[i64] }:$src1, 1:{ *:[i8] }) => (SHR64r1:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src1) 15397 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SHR64r1, 15398 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 15399 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 15400 GIR_EraseFromParent, /*InsnID*/0, 15401 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15402 // GIR_Coverage, 494, 15403 GIR_Done, 15404 // Label 1119: @35415 15405 GIM_Try, /*On fail goto*//*Label 1120*/ 35445, // Rule ID 490 // 15406 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 15407 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 15408 // MIs[1] Operand 1 15409 // No operand predicates 15410 GIM_CheckIsSafeToFold, /*InsnID*/1, 15411 // (srl:{ *:[i64] } GR64:{ *:[i64] }:$src1, (imm:{ *:[i8] }):$src2) => (SHR64ri:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src1, (imm:{ *:[i8] }):$src2) 15412 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SHR64ri, 15413 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 15414 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 15415 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // src2 15416 GIR_EraseFromParent, /*InsnID*/0, 15417 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15418 // GIR_Coverage, 490, 15419 GIR_Done, 15420 // Label 1120: @35445 15421 GIM_Try, /*On fail goto*//*Label 1121*/ 35518, // Rule ID 16146 // 15422 GIM_CheckFeatures, GIFBS_HasBMI2, 15423 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::GR8RegClassID, 15424 // (srl:{ *:[i64] } GR64:{ *:[i64] }:$src1, GR8:{ *:[i8] }:$src2) => (SHRX64rr:{ *:[i64] } GR64:{ *:[i64] }:$src1, (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), GR8:{ *:[i8] }:$src2, sub_8bit:{ *:[i32] })) 15425 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, 15426 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, 15427 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, 15428 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 15429 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 15430 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, 15431 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 15432 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, 15433 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // src2 15434 GIR_AddImm, /*InsnID*/1, /*Imm*/1, 15435 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, X86::GR64_with_sub_8bitRegClassID, 15436 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, X86::GR64_with_sub_8bitRegClassID, 15437 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, X86::GR8RegClassID, 15438 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SHRX64rr, 15439 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 15440 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 15441 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 15442 GIR_EraseFromParent, /*InsnID*/0, 15443 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15444 // GIR_Coverage, 16146, 15445 GIR_Done, 15446 // Label 1121: @35518 15447 GIM_Try, /*On fail goto*//*Label 1122*/ 35551, // Rule ID 486 // 15448 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::GR8_ABCD_LRegClassID, 15449 // (srl:{ *:[i64] } GR64:{ *:[i64] }:$src1, CL:{ *:[i8] }) => (SHR64rCL:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src1) 15450 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, 15451 GIR_AddRegister, /*InsnID*/1, X86::CL, /*AddRegisterRegFlags*/RegState::Define, 15452 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // CL 15453 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SHR64rCL, 15454 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 15455 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 15456 GIR_EraseFromParent, /*InsnID*/0, 15457 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15458 // GIR_Coverage, 486, 15459 GIR_Done, 15460 // Label 1122: @35551 15461 GIM_Reject, 15462 // Label 1118: @35552 15463 GIM_Reject, 15464 // Label 1104: @35553 15465 GIM_Reject, 15466 // Label 19: @35554 15467 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 5, /*)*//*default:*//*Label 1127*/ 36130, 15468 /*GILLT_s8*//*Label 1123*/ 35564, 15469 /*GILLT_s16*//*Label 1124*/ 35669, 15470 /*GILLT_s32*//*Label 1125*/ 35774, 15471 /*GILLT_s64*//*Label 1126*/ 35952, 15472 // Label 1123: @35564 15473 GIM_Try, /*On fail goto*//*Label 1128*/ 35668, 15474 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s8, 15475 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s8, 15476 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR8RegClassID, 15477 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR8RegClassID, 15478 GIM_Try, /*On fail goto*//*Label 1129*/ 35604, // Rule ID 515 // 15479 GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 1, 15480 // (sra:{ *:[i8] } GR8:{ *:[i8] }:$src1, 1:{ *:[i8] }) => (SAR8r1:{ *:[i8] }:{ *:[i32] } GR8:{ *:[i8] }:$src1) 15481 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SAR8r1, 15482 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 15483 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 15484 GIR_EraseFromParent, /*InsnID*/0, 15485 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15486 // GIR_Coverage, 515, 15487 GIR_Done, 15488 // Label 1129: @35604 15489 GIM_Try, /*On fail goto*//*Label 1130*/ 35634, // Rule ID 511 // 15490 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 15491 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 15492 // MIs[1] Operand 1 15493 // No operand predicates 15494 GIM_CheckIsSafeToFold, /*InsnID*/1, 15495 // (sra:{ *:[i8] } GR8:{ *:[i8] }:$src1, (imm:{ *:[i8] }):$src2) => (SAR8ri:{ *:[i8] }:{ *:[i32] } GR8:{ *:[i8] }:$src1, (imm:{ *:[i8] }):$src2) 15496 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SAR8ri, 15497 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 15498 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 15499 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // src2 15500 GIR_EraseFromParent, /*InsnID*/0, 15501 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15502 // GIR_Coverage, 511, 15503 GIR_Done, 15504 // Label 1130: @35634 15505 GIM_Try, /*On fail goto*//*Label 1131*/ 35667, // Rule ID 507 // 15506 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::GR8_ABCD_LRegClassID, 15507 // (sra:{ *:[i8] } GR8:{ *:[i8] }:$src1, CL:{ *:[i8] }) => (SAR8rCL:{ *:[i8] }:{ *:[i32] } GR8:{ *:[i8] }:$src1) 15508 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, 15509 GIR_AddRegister, /*InsnID*/1, X86::CL, /*AddRegisterRegFlags*/RegState::Define, 15510 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // CL 15511 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SAR8rCL, 15512 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 15513 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 15514 GIR_EraseFromParent, /*InsnID*/0, 15515 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15516 // GIR_Coverage, 507, 15517 GIR_Done, 15518 // Label 1131: @35667 15519 GIM_Reject, 15520 // Label 1128: @35668 15521 GIM_Reject, 15522 // Label 1124: @35669 15523 GIM_Try, /*On fail goto*//*Label 1132*/ 35773, 15524 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16, 15525 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s8, 15526 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR16RegClassID, 15527 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR16RegClassID, 15528 GIM_Try, /*On fail goto*//*Label 1133*/ 35709, // Rule ID 516 // 15529 GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 1, 15530 // (sra:{ *:[i16] } GR16:{ *:[i16] }:$src1, 1:{ *:[i8] }) => (SAR16r1:{ *:[i16] }:{ *:[i32] } GR16:{ *:[i16] }:$src1) 15531 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SAR16r1, 15532 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 15533 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 15534 GIR_EraseFromParent, /*InsnID*/0, 15535 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15536 // GIR_Coverage, 516, 15537 GIR_Done, 15538 // Label 1133: @35709 15539 GIM_Try, /*On fail goto*//*Label 1134*/ 35739, // Rule ID 512 // 15540 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 15541 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 15542 // MIs[1] Operand 1 15543 // No operand predicates 15544 GIM_CheckIsSafeToFold, /*InsnID*/1, 15545 // (sra:{ *:[i16] } GR16:{ *:[i16] }:$src1, (imm:{ *:[i8] }):$src2) => (SAR16ri:{ *:[i16] }:{ *:[i32] } GR16:{ *:[i16] }:$src1, (imm:{ *:[i8] }):$src2) 15546 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SAR16ri, 15547 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 15548 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 15549 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // src2 15550 GIR_EraseFromParent, /*InsnID*/0, 15551 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15552 // GIR_Coverage, 512, 15553 GIR_Done, 15554 // Label 1134: @35739 15555 GIM_Try, /*On fail goto*//*Label 1135*/ 35772, // Rule ID 508 // 15556 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::GR8_ABCD_LRegClassID, 15557 // (sra:{ *:[i16] } GR16:{ *:[i16] }:$src1, CL:{ *:[i8] }) => (SAR16rCL:{ *:[i16] }:{ *:[i32] } GR16:{ *:[i16] }:$src1) 15558 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, 15559 GIR_AddRegister, /*InsnID*/1, X86::CL, /*AddRegisterRegFlags*/RegState::Define, 15560 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // CL 15561 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SAR16rCL, 15562 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 15563 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 15564 GIR_EraseFromParent, /*InsnID*/0, 15565 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15566 // GIR_Coverage, 508, 15567 GIR_Done, 15568 // Label 1135: @35772 15569 GIM_Reject, 15570 // Label 1132: @35773 15571 GIM_Reject, 15572 // Label 1125: @35774 15573 GIM_Try, /*On fail goto*//*Label 1136*/ 35951, 15574 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 15575 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s8, 15576 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID, 15577 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR32RegClassID, 15578 GIM_Try, /*On fail goto*//*Label 1137*/ 35814, // Rule ID 517 // 15579 GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 1, 15580 // (sra:{ *:[i32] } GR32:{ *:[i32] }:$src1, 1:{ *:[i8] }) => (SAR32r1:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src1) 15581 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SAR32r1, 15582 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 15583 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 15584 GIR_EraseFromParent, /*InsnID*/0, 15585 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15586 // GIR_Coverage, 517, 15587 GIR_Done, 15588 // Label 1137: @35814 15589 GIM_Try, /*On fail goto*//*Label 1138*/ 35844, // Rule ID 513 // 15590 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 15591 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 15592 // MIs[1] Operand 1 15593 // No operand predicates 15594 GIM_CheckIsSafeToFold, /*InsnID*/1, 15595 // (sra:{ *:[i32] } GR32:{ *:[i32] }:$src1, (imm:{ *:[i8] }):$src2) => (SAR32ri:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src1, (imm:{ *:[i8] }):$src2) 15596 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SAR32ri, 15597 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 15598 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 15599 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // src2 15600 GIR_EraseFromParent, /*InsnID*/0, 15601 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15602 // GIR_Coverage, 513, 15603 GIR_Done, 15604 // Label 1138: @35844 15605 GIM_Try, /*On fail goto*//*Label 1139*/ 35917, // Rule ID 16143 // 15606 GIM_CheckFeatures, GIFBS_HasBMI2, 15607 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::GR8RegClassID, 15608 // (sra:{ *:[i32] } GR32:{ *:[i32] }:$src1, GR8:{ *:[i8] }:$src2) => (SARX32rr:{ *:[i32] } GR32:{ *:[i32] }:$src1, (INSERT_SUBREG:{ *:[i32] } (IMPLICIT_DEF:{ *:[i32] }), GR8:{ *:[i8] }:$src2, sub_8bit:{ *:[i32] })) 15609 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, 15610 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, 15611 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, 15612 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 15613 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 15614 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, 15615 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 15616 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, 15617 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // src2 15618 GIR_AddImm, /*InsnID*/1, /*Imm*/1, 15619 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID, 15620 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID, 15621 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, X86::GR8RegClassID, 15622 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SARX32rr, 15623 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 15624 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 15625 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 15626 GIR_EraseFromParent, /*InsnID*/0, 15627 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15628 // GIR_Coverage, 16143, 15629 GIR_Done, 15630 // Label 1139: @35917 15631 GIM_Try, /*On fail goto*//*Label 1140*/ 35950, // Rule ID 509 // 15632 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::GR8_ABCD_LRegClassID, 15633 // (sra:{ *:[i32] } GR32:{ *:[i32] }:$src1, CL:{ *:[i8] }) => (SAR32rCL:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src1) 15634 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, 15635 GIR_AddRegister, /*InsnID*/1, X86::CL, /*AddRegisterRegFlags*/RegState::Define, 15636 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // CL 15637 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SAR32rCL, 15638 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 15639 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 15640 GIR_EraseFromParent, /*InsnID*/0, 15641 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15642 // GIR_Coverage, 509, 15643 GIR_Done, 15644 // Label 1140: @35950 15645 GIM_Reject, 15646 // Label 1136: @35951 15647 GIM_Reject, 15648 // Label 1126: @35952 15649 GIM_Try, /*On fail goto*//*Label 1141*/ 36129, 15650 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 15651 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s8, 15652 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID, 15653 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR64RegClassID, 15654 GIM_Try, /*On fail goto*//*Label 1142*/ 35992, // Rule ID 518 // 15655 GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 1, 15656 // (sra:{ *:[i64] } GR64:{ *:[i64] }:$src1, 1:{ *:[i8] }) => (SAR64r1:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src1) 15657 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SAR64r1, 15658 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 15659 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 15660 GIR_EraseFromParent, /*InsnID*/0, 15661 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15662 // GIR_Coverage, 518, 15663 GIR_Done, 15664 // Label 1142: @35992 15665 GIM_Try, /*On fail goto*//*Label 1143*/ 36022, // Rule ID 514 // 15666 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 15667 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 15668 // MIs[1] Operand 1 15669 // No operand predicates 15670 GIM_CheckIsSafeToFold, /*InsnID*/1, 15671 // (sra:{ *:[i64] } GR64:{ *:[i64] }:$src1, (imm:{ *:[i8] }):$src2) => (SAR64ri:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src1, (imm:{ *:[i8] }):$src2) 15672 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SAR64ri, 15673 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 15674 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 15675 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // src2 15676 GIR_EraseFromParent, /*InsnID*/0, 15677 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15678 // GIR_Coverage, 514, 15679 GIR_Done, 15680 // Label 1143: @36022 15681 GIM_Try, /*On fail goto*//*Label 1144*/ 36095, // Rule ID 16144 // 15682 GIM_CheckFeatures, GIFBS_HasBMI2, 15683 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::GR8RegClassID, 15684 // (sra:{ *:[i64] } GR64:{ *:[i64] }:$src1, GR8:{ *:[i8] }:$src2) => (SARX64rr:{ *:[i64] } GR64:{ *:[i64] }:$src1, (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), GR8:{ *:[i8] }:$src2, sub_8bit:{ *:[i32] })) 15685 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, 15686 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, 15687 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, 15688 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 15689 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 15690 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, 15691 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 15692 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, 15693 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // src2 15694 GIR_AddImm, /*InsnID*/1, /*Imm*/1, 15695 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, X86::GR64_with_sub_8bitRegClassID, 15696 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, X86::GR64_with_sub_8bitRegClassID, 15697 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, X86::GR8RegClassID, 15698 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SARX64rr, 15699 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 15700 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 15701 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 15702 GIR_EraseFromParent, /*InsnID*/0, 15703 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15704 // GIR_Coverage, 16144, 15705 GIR_Done, 15706 // Label 1144: @36095 15707 GIM_Try, /*On fail goto*//*Label 1145*/ 36128, // Rule ID 510 // 15708 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::GR8_ABCD_LRegClassID, 15709 // (sra:{ *:[i64] } GR64:{ *:[i64] }:$src1, CL:{ *:[i8] }) => (SAR64rCL:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src1) 15710 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, 15711 GIR_AddRegister, /*InsnID*/1, X86::CL, /*AddRegisterRegFlags*/RegState::Define, 15712 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // CL 15713 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SAR64rCL, 15714 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 15715 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 15716 GIR_EraseFromParent, /*InsnID*/0, 15717 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15718 // GIR_Coverage, 510, 15719 GIR_Done, 15720 // Label 1145: @36128 15721 GIM_Reject, 15722 // Label 1141: @36129 15723 GIM_Reject, 15724 // Label 1127: @36130 15725 GIM_Reject, 15726 // Label 20: @36131 15727 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/3, 5, /*)*//*default:*//*Label 1148*/ 36337, 15728 /*GILLT_s32*//*Label 1146*/ 36139, 15729 /*GILLT_s64*//*Label 1147*/ 36238, 15730 // Label 1146: @36139 15731 GIM_Try, /*On fail goto*//*Label 1149*/ 36237, 15732 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 15733 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 15734 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s8, 15735 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID, 15736 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR32RegClassID, 15737 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::GR32RegClassID, 15738 GIM_Try, /*On fail goto*//*Label 1150*/ 36199, // Rule ID 587 // 15739 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] 15740 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 15741 // MIs[1] Operand 1 15742 // No operand predicates 15743 GIM_CheckIsSafeToFold, /*InsnID*/1, 15744 // (fshl:{ *:[i32] } GR32:{ *:[i32] }:$src1, GR32:{ *:[i32] }:$src2, (imm:{ *:[i8] }):$src3) => (SHLD32rri8:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src1, GR32:{ *:[i32] }:$src2, (imm:{ *:[i8] }):$src3) 15745 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SHLD32rri8, 15746 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 15747 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 15748 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src2 15749 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // src3 15750 GIR_EraseFromParent, /*InsnID*/0, 15751 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15752 // GIR_Coverage, 587, 15753 GIR_Done, 15754 // Label 1150: @36199 15755 GIM_Try, /*On fail goto*//*Label 1151*/ 36236, // Rule ID 581 // 15756 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::GR8_ABCD_LRegClassID, 15757 // (fshl:{ *:[i32] } GR32:{ *:[i32] }:$src1, GR32:{ *:[i32] }:$src2, CL:{ *:[i8] }) => (SHLD32rrCL:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src1, GR32:{ *:[i32] }:$src2) 15758 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, 15759 GIR_AddRegister, /*InsnID*/1, X86::CL, /*AddRegisterRegFlags*/RegState::Define, 15760 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // CL 15761 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SHLD32rrCL, 15762 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 15763 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 15764 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src2 15765 GIR_EraseFromParent, /*InsnID*/0, 15766 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15767 // GIR_Coverage, 581, 15768 GIR_Done, 15769 // Label 1151: @36236 15770 GIM_Reject, 15771 // Label 1149: @36237 15772 GIM_Reject, 15773 // Label 1147: @36238 15774 GIM_Try, /*On fail goto*//*Label 1152*/ 36336, 15775 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 15776 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 15777 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s8, 15778 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID, 15779 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR64RegClassID, 15780 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::GR64RegClassID, 15781 GIM_Try, /*On fail goto*//*Label 1153*/ 36298, // Rule ID 589 // 15782 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] 15783 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 15784 // MIs[1] Operand 1 15785 // No operand predicates 15786 GIM_CheckIsSafeToFold, /*InsnID*/1, 15787 // (fshl:{ *:[i64] } GR64:{ *:[i64] }:$src1, GR64:{ *:[i64] }:$src2, (imm:{ *:[i8] }):$src3) => (SHLD64rri8:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src1, GR64:{ *:[i64] }:$src2, (imm:{ *:[i8] }):$src3) 15788 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SHLD64rri8, 15789 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 15790 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 15791 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src2 15792 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // src3 15793 GIR_EraseFromParent, /*InsnID*/0, 15794 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15795 // GIR_Coverage, 589, 15796 GIR_Done, 15797 // Label 1153: @36298 15798 GIM_Try, /*On fail goto*//*Label 1154*/ 36335, // Rule ID 583 // 15799 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::GR8_ABCD_LRegClassID, 15800 // (fshl:{ *:[i64] } GR64:{ *:[i64] }:$src1, GR64:{ *:[i64] }:$src2, CL:{ *:[i8] }) => (SHLD64rrCL:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src1, GR64:{ *:[i64] }:$src2) 15801 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, 15802 GIR_AddRegister, /*InsnID*/1, X86::CL, /*AddRegisterRegFlags*/RegState::Define, 15803 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // CL 15804 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SHLD64rrCL, 15805 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 15806 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 15807 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src2 15808 GIR_EraseFromParent, /*InsnID*/0, 15809 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15810 // GIR_Coverage, 583, 15811 GIR_Done, 15812 // Label 1154: @36335 15813 GIM_Reject, 15814 // Label 1152: @36336 15815 GIM_Reject, 15816 // Label 1148: @36337 15817 GIM_Reject, 15818 // Label 21: @36338 15819 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/3, 5, /*)*//*default:*//*Label 1157*/ 36544, 15820 /*GILLT_s32*//*Label 1155*/ 36346, 15821 /*GILLT_s64*//*Label 1156*/ 36445, 15822 // Label 1155: @36346 15823 GIM_Try, /*On fail goto*//*Label 1158*/ 36444, 15824 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 15825 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 15826 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s8, 15827 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID, 15828 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR32RegClassID, 15829 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::GR32RegClassID, 15830 GIM_Try, /*On fail goto*//*Label 1159*/ 36406, // Rule ID 588 // 15831 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] 15832 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 15833 // MIs[1] Operand 1 15834 // No operand predicates 15835 GIM_CheckIsSafeToFold, /*InsnID*/1, 15836 // (fshr:{ *:[i32] } GR32:{ *:[i32] }:$src2, GR32:{ *:[i32] }:$src1, (imm:{ *:[i8] }):$src3) => (SHRD32rri8:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src1, GR32:{ *:[i32] }:$src2, (imm:{ *:[i8] }):$src3) 15837 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SHRD32rri8, 15838 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 15839 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 15840 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src2 15841 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // src3 15842 GIR_EraseFromParent, /*InsnID*/0, 15843 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15844 // GIR_Coverage, 588, 15845 GIR_Done, 15846 // Label 1159: @36406 15847 GIM_Try, /*On fail goto*//*Label 1160*/ 36443, // Rule ID 582 // 15848 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::GR8_ABCD_LRegClassID, 15849 // (fshr:{ *:[i32] } GR32:{ *:[i32] }:$src2, GR32:{ *:[i32] }:$src1, CL:{ *:[i8] }) => (SHRD32rrCL:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src1, GR32:{ *:[i32] }:$src2) 15850 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, 15851 GIR_AddRegister, /*InsnID*/1, X86::CL, /*AddRegisterRegFlags*/RegState::Define, 15852 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // CL 15853 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SHRD32rrCL, 15854 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 15855 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 15856 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src2 15857 GIR_EraseFromParent, /*InsnID*/0, 15858 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15859 // GIR_Coverage, 582, 15860 GIR_Done, 15861 // Label 1160: @36443 15862 GIM_Reject, 15863 // Label 1158: @36444 15864 GIM_Reject, 15865 // Label 1156: @36445 15866 GIM_Try, /*On fail goto*//*Label 1161*/ 36543, 15867 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 15868 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 15869 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s8, 15870 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID, 15871 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR64RegClassID, 15872 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::GR64RegClassID, 15873 GIM_Try, /*On fail goto*//*Label 1162*/ 36505, // Rule ID 590 // 15874 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] 15875 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 15876 // MIs[1] Operand 1 15877 // No operand predicates 15878 GIM_CheckIsSafeToFold, /*InsnID*/1, 15879 // (fshr:{ *:[i64] } GR64:{ *:[i64] }:$src2, GR64:{ *:[i64] }:$src1, (imm:{ *:[i8] }):$src3) => (SHRD64rri8:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src1, GR64:{ *:[i64] }:$src2, (imm:{ *:[i8] }):$src3) 15880 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SHRD64rri8, 15881 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 15882 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 15883 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src2 15884 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // src3 15885 GIR_EraseFromParent, /*InsnID*/0, 15886 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15887 // GIR_Coverage, 590, 15888 GIR_Done, 15889 // Label 1162: @36505 15890 GIM_Try, /*On fail goto*//*Label 1163*/ 36542, // Rule ID 584 // 15891 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::GR8_ABCD_LRegClassID, 15892 // (fshr:{ *:[i64] } GR64:{ *:[i64] }:$src2, GR64:{ *:[i64] }:$src1, CL:{ *:[i8] }) => (SHRD64rrCL:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src1, GR64:{ *:[i64] }:$src2) 15893 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, 15894 GIR_AddRegister, /*InsnID*/1, X86::CL, /*AddRegisterRegFlags*/RegState::Define, 15895 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // CL 15896 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SHRD64rrCL, 15897 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 15898 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 15899 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src2 15900 GIR_EraseFromParent, /*InsnID*/0, 15901 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15902 // GIR_Coverage, 584, 15903 GIR_Done, 15904 // Label 1163: @36542 15905 GIM_Reject, 15906 // Label 1161: @36543 15907 GIM_Reject, 15908 // Label 1157: @36544 15909 GIM_Reject, 15910 // Label 22: @36545 15911 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 20, /*)*//*default:*//*Label 1174*/ 38006, 15912 /*GILLT_s8*//*Label 1164*/ 36570, 15913 /*GILLT_s16*//*Label 1165*/ 36697, 15914 /*GILLT_s32*//*Label 1166*/ 36824, 15915 /*GILLT_s64*//*Label 1167*/ 37015, 0, 0, 0, 15916 /*GILLT_v2s64*//*Label 1168*/ 37206, 0, 15917 /*GILLT_v4s32*//*Label 1169*/ 37390, 15918 /*GILLT_v4s64*//*Label 1170*/ 37574, 0, 0, 15919 /*GILLT_v8s32*//*Label 1171*/ 37758, 15920 /*GILLT_v8s64*//*Label 1172*/ 37942, 0, 0, 0, 15921 /*GILLT_v16s32*//*Label 1173*/ 37974, 15922 // Label 1164: @36570 15923 GIM_Try, /*On fail goto*//*Label 1175*/ 36696, 15924 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s8, 15925 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s8, 15926 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR8RegClassID, 15927 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR8RegClassID, 15928 GIM_Try, /*On fail goto*//*Label 1176*/ 36610, // Rule ID 563 // 15929 GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 1, 15930 // (rotr:{ *:[i8] } GR8:{ *:[i8] }:$src1, 1:{ *:[i8] }) => (ROR8r1:{ *:[i8] }:{ *:[i32] } GR8:{ *:[i8] }:$src1) 15931 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::ROR8r1, 15932 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 15933 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 15934 GIR_EraseFromParent, /*InsnID*/0, 15935 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15936 // GIR_Coverage, 563, 15937 GIR_Done, 15938 // Label 1176: @36610 15939 GIM_Try, /*On fail goto*//*Label 1177*/ 36632, // Rule ID 16123 // 15940 GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 7, 15941 // (rotr:{ *:[i8] } GR8:{ *:[i8] }:$src1, 7:{ *:[i8] }) => (ROL8r1:{ *:[i8] }:{ *:[i32] } GR8:{ *:[i8] }:$src1) 15942 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::ROL8r1, 15943 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 15944 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 15945 GIR_EraseFromParent, /*InsnID*/0, 15946 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15947 // GIR_Coverage, 16123, 15948 GIR_Done, 15949 // Label 1177: @36632 15950 GIM_Try, /*On fail goto*//*Label 1178*/ 36662, // Rule ID 559 // 15951 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 15952 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 15953 // MIs[1] Operand 1 15954 // No operand predicates 15955 GIM_CheckIsSafeToFold, /*InsnID*/1, 15956 // (rotr:{ *:[i8] } GR8:{ *:[i8] }:$src1, (imm:{ *:[i8] }):$src2) => (ROR8ri:{ *:[i8] }:{ *:[i32] } GR8:{ *:[i8] }:$src1, (imm:{ *:[i8] }):$src2) 15957 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::ROR8ri, 15958 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 15959 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 15960 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // src2 15961 GIR_EraseFromParent, /*InsnID*/0, 15962 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15963 // GIR_Coverage, 559, 15964 GIR_Done, 15965 // Label 1178: @36662 15966 GIM_Try, /*On fail goto*//*Label 1179*/ 36695, // Rule ID 555 // 15967 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::GR8_ABCD_LRegClassID, 15968 // (rotr:{ *:[i8] } GR8:{ *:[i8] }:$src1, CL:{ *:[i8] }) => (ROR8rCL:{ *:[i8] }:{ *:[i32] } GR8:{ *:[i8] }:$src1) 15969 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, 15970 GIR_AddRegister, /*InsnID*/1, X86::CL, /*AddRegisterRegFlags*/RegState::Define, 15971 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // CL 15972 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::ROR8rCL, 15973 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 15974 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 15975 GIR_EraseFromParent, /*InsnID*/0, 15976 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15977 // GIR_Coverage, 555, 15978 GIR_Done, 15979 // Label 1179: @36695 15980 GIM_Reject, 15981 // Label 1175: @36696 15982 GIM_Reject, 15983 // Label 1165: @36697 15984 GIM_Try, /*On fail goto*//*Label 1180*/ 36823, 15985 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16, 15986 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s8, 15987 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR16RegClassID, 15988 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR16RegClassID, 15989 GIM_Try, /*On fail goto*//*Label 1181*/ 36737, // Rule ID 564 // 15990 GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 1, 15991 // (rotr:{ *:[i16] } GR16:{ *:[i16] }:$src1, 1:{ *:[i8] }) => (ROR16r1:{ *:[i16] }:{ *:[i32] } GR16:{ *:[i16] }:$src1) 15992 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::ROR16r1, 15993 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 15994 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 15995 GIR_EraseFromParent, /*InsnID*/0, 15996 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15997 // GIR_Coverage, 564, 15998 GIR_Done, 15999 // Label 1181: @36737 16000 GIM_Try, /*On fail goto*//*Label 1182*/ 36759, // Rule ID 16124 // 16001 GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 15, 16002 // (rotr:{ *:[i16] } GR16:{ *:[i16] }:$src1, 15:{ *:[i8] }) => (ROL16r1:{ *:[i16] }:{ *:[i32] } GR16:{ *:[i16] }:$src1) 16003 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::ROL16r1, 16004 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 16005 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 16006 GIR_EraseFromParent, /*InsnID*/0, 16007 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16008 // GIR_Coverage, 16124, 16009 GIR_Done, 16010 // Label 1182: @36759 16011 GIM_Try, /*On fail goto*//*Label 1183*/ 36789, // Rule ID 560 // 16012 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 16013 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 16014 // MIs[1] Operand 1 16015 // No operand predicates 16016 GIM_CheckIsSafeToFold, /*InsnID*/1, 16017 // (rotr:{ *:[i16] } GR16:{ *:[i16] }:$src1, (imm:{ *:[i8] }):$src2) => (ROR16ri:{ *:[i16] }:{ *:[i32] } GR16:{ *:[i16] }:$src1, (imm:{ *:[i8] }):$src2) 16018 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::ROR16ri, 16019 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 16020 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 16021 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // src2 16022 GIR_EraseFromParent, /*InsnID*/0, 16023 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16024 // GIR_Coverage, 560, 16025 GIR_Done, 16026 // Label 1183: @36789 16027 GIM_Try, /*On fail goto*//*Label 1184*/ 36822, // Rule ID 556 // 16028 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::GR8_ABCD_LRegClassID, 16029 // (rotr:{ *:[i16] } GR16:{ *:[i16] }:$src1, CL:{ *:[i8] }) => (ROR16rCL:{ *:[i16] }:{ *:[i32] } GR16:{ *:[i16] }:$src1) 16030 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, 16031 GIR_AddRegister, /*InsnID*/1, X86::CL, /*AddRegisterRegFlags*/RegState::Define, 16032 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // CL 16033 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::ROR16rCL, 16034 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 16035 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 16036 GIR_EraseFromParent, /*InsnID*/0, 16037 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16038 // GIR_Coverage, 556, 16039 GIR_Done, 16040 // Label 1184: @36822 16041 GIM_Reject, 16042 // Label 1180: @36823 16043 GIM_Reject, 16044 // Label 1166: @36824 16045 GIM_Try, /*On fail goto*//*Label 1185*/ 37014, 16046 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 16047 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s8, 16048 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID, 16049 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR32RegClassID, 16050 GIM_Try, /*On fail goto*//*Label 1186*/ 36874, // Rule ID 16135 // 16051 GIM_CheckFeatures, GIFBS_HasBMI2, 16052 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 16053 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 16054 // MIs[1] Operand 1 16055 // No operand predicates 16056 GIM_CheckIsSafeToFold, /*InsnID*/1, 16057 // (rotr:{ *:[i32] } GR32:{ *:[i32] }:$src, (imm:{ *:[i8] }):$shamt) => (RORX32ri:{ *:[i32] } GR32:{ *:[i32] }:$src, (imm:{ *:[i8] }):$shamt) 16058 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::RORX32ri, 16059 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 16060 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 16061 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt 16062 GIR_EraseFromParent, /*InsnID*/0, 16063 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16064 // GIR_Coverage, 16135, 16065 GIR_Done, 16066 // Label 1186: @36874 16067 GIM_Try, /*On fail goto*//*Label 1187*/ 36906, // Rule ID 605 // 16068 GIM_CheckFeatures, GIFBS_HasFastSHLDRotate, 16069 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 16070 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 16071 // MIs[1] Operand 1 16072 // No operand predicates 16073 GIM_CheckIsSafeToFold, /*InsnID*/1, 16074 // (rotr:{ *:[i32] } GR32:{ *:[i32] }:$src1, (imm:{ *:[i8] }):$shamt) => (SHRDROT32ri:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src1, (imm:{ *:[i8] }):$shamt) 16075 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SHRDROT32ri, 16076 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 16077 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 16078 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt 16079 GIR_EraseFromParent, /*InsnID*/0, 16080 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16081 // GIR_Coverage, 605, 16082 GIR_Done, 16083 // Label 1187: @36906 16084 GIM_Try, /*On fail goto*//*Label 1188*/ 36928, // Rule ID 565 // 16085 GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 1, 16086 // (rotr:{ *:[i32] } GR32:{ *:[i32] }:$src1, 1:{ *:[i8] }) => (ROR32r1:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src1) 16087 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::ROR32r1, 16088 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 16089 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 16090 GIR_EraseFromParent, /*InsnID*/0, 16091 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16092 // GIR_Coverage, 565, 16093 GIR_Done, 16094 // Label 1188: @36928 16095 GIM_Try, /*On fail goto*//*Label 1189*/ 36950, // Rule ID 16125 // 16096 GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 31, 16097 // (rotr:{ *:[i32] } GR32:{ *:[i32] }:$src1, 31:{ *:[i8] }) => (ROL32r1:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src1) 16098 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::ROL32r1, 16099 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 16100 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 16101 GIR_EraseFromParent, /*InsnID*/0, 16102 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16103 // GIR_Coverage, 16125, 16104 GIR_Done, 16105 // Label 1189: @36950 16106 GIM_Try, /*On fail goto*//*Label 1190*/ 36980, // Rule ID 561 // 16107 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 16108 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 16109 // MIs[1] Operand 1 16110 // No operand predicates 16111 GIM_CheckIsSafeToFold, /*InsnID*/1, 16112 // (rotr:{ *:[i32] } GR32:{ *:[i32] }:$src1, (imm:{ *:[i8] }):$src2) => (ROR32ri:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src1, (imm:{ *:[i8] }):$src2) 16113 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::ROR32ri, 16114 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 16115 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 16116 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // src2 16117 GIR_EraseFromParent, /*InsnID*/0, 16118 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16119 // GIR_Coverage, 561, 16120 GIR_Done, 16121 // Label 1190: @36980 16122 GIM_Try, /*On fail goto*//*Label 1191*/ 37013, // Rule ID 557 // 16123 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::GR8_ABCD_LRegClassID, 16124 // (rotr:{ *:[i32] } GR32:{ *:[i32] }:$src1, CL:{ *:[i8] }) => (ROR32rCL:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src1) 16125 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, 16126 GIR_AddRegister, /*InsnID*/1, X86::CL, /*AddRegisterRegFlags*/RegState::Define, 16127 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // CL 16128 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::ROR32rCL, 16129 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 16130 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 16131 GIR_EraseFromParent, /*InsnID*/0, 16132 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16133 // GIR_Coverage, 557, 16134 GIR_Done, 16135 // Label 1191: @37013 16136 GIM_Reject, 16137 // Label 1185: @37014 16138 GIM_Reject, 16139 // Label 1167: @37015 16140 GIM_Try, /*On fail goto*//*Label 1192*/ 37205, 16141 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 16142 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s8, 16143 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID, 16144 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR64RegClassID, 16145 GIM_Try, /*On fail goto*//*Label 1193*/ 37065, // Rule ID 16136 // 16146 GIM_CheckFeatures, GIFBS_HasBMI2, 16147 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 16148 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 16149 // MIs[1] Operand 1 16150 // No operand predicates 16151 GIM_CheckIsSafeToFold, /*InsnID*/1, 16152 // (rotr:{ *:[i64] } GR64:{ *:[i64] }:$src, (imm:{ *:[i8] }):$shamt) => (RORX64ri:{ *:[i64] } GR64:{ *:[i64] }:$src, (imm:{ *:[i8] }):$shamt) 16153 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::RORX64ri, 16154 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 16155 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 16156 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt 16157 GIR_EraseFromParent, /*InsnID*/0, 16158 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16159 // GIR_Coverage, 16136, 16160 GIR_Done, 16161 // Label 1193: @37065 16162 GIM_Try, /*On fail goto*//*Label 1194*/ 37097, // Rule ID 606 // 16163 GIM_CheckFeatures, GIFBS_HasFastSHLDRotate, 16164 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 16165 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 16166 // MIs[1] Operand 1 16167 // No operand predicates 16168 GIM_CheckIsSafeToFold, /*InsnID*/1, 16169 // (rotr:{ *:[i64] } GR64:{ *:[i64] }:$src1, (imm:{ *:[i8] }):$shamt) => (SHRDROT64ri:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src1, (imm:{ *:[i8] }):$shamt) 16170 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SHRDROT64ri, 16171 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 16172 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 16173 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt 16174 GIR_EraseFromParent, /*InsnID*/0, 16175 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16176 // GIR_Coverage, 606, 16177 GIR_Done, 16178 // Label 1194: @37097 16179 GIM_Try, /*On fail goto*//*Label 1195*/ 37119, // Rule ID 566 // 16180 GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 1, 16181 // (rotr:{ *:[i64] } GR64:{ *:[i64] }:$src1, 1:{ *:[i8] }) => (ROR64r1:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src1) 16182 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::ROR64r1, 16183 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 16184 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 16185 GIR_EraseFromParent, /*InsnID*/0, 16186 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16187 // GIR_Coverage, 566, 16188 GIR_Done, 16189 // Label 1195: @37119 16190 GIM_Try, /*On fail goto*//*Label 1196*/ 37141, // Rule ID 16126 // 16191 GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 63, 16192 // (rotr:{ *:[i64] } GR64:{ *:[i64] }:$src1, 63:{ *:[i8] }) => (ROL64r1:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src1) 16193 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::ROL64r1, 16194 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 16195 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 16196 GIR_EraseFromParent, /*InsnID*/0, 16197 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16198 // GIR_Coverage, 16126, 16199 GIR_Done, 16200 // Label 1196: @37141 16201 GIM_Try, /*On fail goto*//*Label 1197*/ 37171, // Rule ID 562 // 16202 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 16203 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 16204 // MIs[1] Operand 1 16205 // No operand predicates 16206 GIM_CheckIsSafeToFold, /*InsnID*/1, 16207 // (rotr:{ *:[i64] } GR64:{ *:[i64] }:$src1, (imm:{ *:[i8] }):$src2) => (ROR64ri:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src1, (imm:{ *:[i8] }):$src2) 16208 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::ROR64ri, 16209 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 16210 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 16211 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // src2 16212 GIR_EraseFromParent, /*InsnID*/0, 16213 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16214 // GIR_Coverage, 562, 16215 GIR_Done, 16216 // Label 1197: @37171 16217 GIM_Try, /*On fail goto*//*Label 1198*/ 37204, // Rule ID 558 // 16218 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::GR8_ABCD_LRegClassID, 16219 // (rotr:{ *:[i64] } GR64:{ *:[i64] }:$src1, CL:{ *:[i8] }) => (ROR64rCL:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src1) 16220 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, 16221 GIR_AddRegister, /*InsnID*/1, X86::CL, /*AddRegisterRegFlags*/RegState::Define, 16222 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // CL 16223 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::ROR64rCL, 16224 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 16225 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 16226 GIR_EraseFromParent, /*InsnID*/0, 16227 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16228 // GIR_Coverage, 558, 16229 GIR_Done, 16230 // Label 1198: @37204 16231 GIM_Reject, 16232 // Label 1192: @37205 16233 GIM_Reject, 16234 // Label 1168: @37206 16235 GIM_Try, /*On fail goto*//*Label 1199*/ 37389, 16236 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, 16237 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 16238 GIM_Try, /*On fail goto*//*Label 1200*/ 37239, // Rule ID 7575 // 16239 GIM_CheckFeatures, GIFBS_HasAVX512_HasVLX, 16240 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID, 16241 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID, 16242 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128XRegClassID, 16243 // (rotr:{ *:[v2i64] } VR128X:{ *:[v2i64] }:$src1, VR128X:{ *:[v2i64] }:$src2) => (VPRORVQZ128rr:{ *:[v2i64] } VR128X:{ *:[v2i64] }:$src1, VR128X:{ *:[v2i64] }:$src2) 16244 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPRORVQZ128rr, 16245 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16246 // GIR_Coverage, 7575, 16247 GIR_Done, 16248 // Label 1200: @37239 16249 GIM_Try, /*On fail goto*//*Label 1201*/ 37388, // Rule ID 19289 // 16250 GIM_CheckFeatures, GIFBS_HasAVX512_NoVLX, 16251 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 16252 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID, 16253 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128XRegClassID, 16254 // (rotr:{ *:[v2i64] } VR128X:{ *:[v2i64] }:$src1, VR128X:{ *:[v2i64] }:$src2) => (EXTRACT_SUBREG:{ *:[v2i64] } (VPRORVQZrr:{ *:[v8i64] } (INSERT_SUBREG:{ *:[v8i64] } (IMPLICIT_DEF:{ *:[v8i64] }), VR128X:{ *:[v2i64] }:$src1, sub_xmm:{ *:[i32] }), (INSERT_SUBREG:{ *:[v8i64] } (IMPLICIT_DEF:{ *:[v8i64] }), VR128X:{ *:[v2i64] }:$src2, sub_xmm:{ *:[i32] })), sub_xmm:{ *:[i32] }) 16255 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s64, 16256 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s64, 16257 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v8s64, 16258 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v8s64, 16259 GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v8s64, 16260 GIR_BuildMI, /*InsnID*/5, /*Opcode*/TargetOpcode::IMPLICIT_DEF, 16261 GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/RegState::Define, 16262 GIR_ConstrainSelectedInstOperands, /*InsnID*/5, 16263 GIR_BuildMI, /*InsnID*/4, /*Opcode*/TargetOpcode::INSERT_SUBREG, 16264 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define, 16265 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/4, /*TempRegFlags*/0, 16266 GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/2, // src2 16267 GIR_AddImm, /*InsnID*/4, /*Imm*/9, 16268 GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, X86::VR512RegClassID, 16269 GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/1, X86::VR512RegClassID, 16270 GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/2, X86::VR128XRegClassID, 16271 GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::IMPLICIT_DEF, 16272 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, 16273 GIR_ConstrainSelectedInstOperands, /*InsnID*/3, 16274 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::INSERT_SUBREG, 16275 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 16276 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/2, /*TempRegFlags*/0, 16277 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src1 16278 GIR_AddImm, /*InsnID*/2, /*Imm*/9, 16279 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, X86::VR512RegClassID, 16280 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, X86::VR512RegClassID, 16281 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, X86::VR128XRegClassID, 16282 GIR_BuildMI, /*InsnID*/1, /*Opcode*/X86::VPRORVQZrr, 16283 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 16284 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, 16285 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/3, /*TempRegFlags*/0, 16286 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 16287 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 16288 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 16289 GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, X86::sub_xmm, 16290 GIR_EraseFromParent, /*InsnID*/0, 16291 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, X86::FR16XRegClassID, 16292 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, X86::VR512RegClassID, 16293 // GIR_Coverage, 19289, 16294 GIR_Done, 16295 // Label 1201: @37388 16296 GIM_Reject, 16297 // Label 1199: @37389 16298 GIM_Reject, 16299 // Label 1169: @37390 16300 GIM_Try, /*On fail goto*//*Label 1202*/ 37573, 16301 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, 16302 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 16303 GIM_Try, /*On fail goto*//*Label 1203*/ 37423, // Rule ID 7548 // 16304 GIM_CheckFeatures, GIFBS_HasAVX512_HasVLX, 16305 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID, 16306 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID, 16307 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128XRegClassID, 16308 // (rotr:{ *:[v4i32] } VR128X:{ *:[v4i32] }:$src1, VR128X:{ *:[v4i32] }:$src2) => (VPRORVDZ128rr:{ *:[v4i32] } VR128X:{ *:[v4i32] }:$src1, VR128X:{ *:[v4i32] }:$src2) 16309 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPRORVDZ128rr, 16310 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16311 // GIR_Coverage, 7548, 16312 GIR_Done, 16313 // Label 1203: @37423 16314 GIM_Try, /*On fail goto*//*Label 1204*/ 37572, // Rule ID 19291 // 16315 GIM_CheckFeatures, GIFBS_HasAVX512_NoVLX, 16316 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 16317 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID, 16318 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128XRegClassID, 16319 // (rotr:{ *:[v4i32] } VR128X:{ *:[v4i32] }:$src1, VR128X:{ *:[v4i32] }:$src2) => (EXTRACT_SUBREG:{ *:[v4i32] } (VPRORVDZrr:{ *:[v16i32] } (INSERT_SUBREG:{ *:[v16i32] } (IMPLICIT_DEF:{ *:[v16i32] }), VR128X:{ *:[v4i32] }:$src1, sub_xmm:{ *:[i32] }), (INSERT_SUBREG:{ *:[v16i32] } (IMPLICIT_DEF:{ *:[v16i32] }), VR128X:{ *:[v4i32] }:$src2, sub_xmm:{ *:[i32] })), sub_xmm:{ *:[i32] }) 16320 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s32, 16321 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s32, 16322 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s32, 16323 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v16s32, 16324 GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v16s32, 16325 GIR_BuildMI, /*InsnID*/5, /*Opcode*/TargetOpcode::IMPLICIT_DEF, 16326 GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/RegState::Define, 16327 GIR_ConstrainSelectedInstOperands, /*InsnID*/5, 16328 GIR_BuildMI, /*InsnID*/4, /*Opcode*/TargetOpcode::INSERT_SUBREG, 16329 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define, 16330 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/4, /*TempRegFlags*/0, 16331 GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/2, // src2 16332 GIR_AddImm, /*InsnID*/4, /*Imm*/9, 16333 GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, X86::VR512RegClassID, 16334 GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/1, X86::VR512RegClassID, 16335 GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/2, X86::VR128XRegClassID, 16336 GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::IMPLICIT_DEF, 16337 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, 16338 GIR_ConstrainSelectedInstOperands, /*InsnID*/3, 16339 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::INSERT_SUBREG, 16340 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 16341 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/2, /*TempRegFlags*/0, 16342 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src1 16343 GIR_AddImm, /*InsnID*/2, /*Imm*/9, 16344 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, X86::VR512RegClassID, 16345 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, X86::VR512RegClassID, 16346 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, X86::VR128XRegClassID, 16347 GIR_BuildMI, /*InsnID*/1, /*Opcode*/X86::VPRORVDZrr, 16348 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 16349 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, 16350 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/3, /*TempRegFlags*/0, 16351 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 16352 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 16353 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 16354 GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, X86::sub_xmm, 16355 GIR_EraseFromParent, /*InsnID*/0, 16356 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, X86::FR16XRegClassID, 16357 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, X86::VR512RegClassID, 16358 // GIR_Coverage, 19291, 16359 GIR_Done, 16360 // Label 1204: @37572 16361 GIM_Reject, 16362 // Label 1202: @37573 16363 GIM_Reject, 16364 // Label 1170: @37574 16365 GIM_Try, /*On fail goto*//*Label 1205*/ 37757, 16366 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s64, 16367 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s64, 16368 GIM_Try, /*On fail goto*//*Label 1206*/ 37607, // Rule ID 7566 // 16369 GIM_CheckFeatures, GIFBS_HasAVX512_HasVLX, 16370 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID, 16371 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID, 16372 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256XRegClassID, 16373 // (rotr:{ *:[v4i64] } VR256X:{ *:[v4i64] }:$src1, VR256X:{ *:[v4i64] }:$src2) => (VPRORVQZ256rr:{ *:[v4i64] } VR256X:{ *:[v4i64] }:$src1, VR256X:{ *:[v4i64] }:$src2) 16374 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPRORVQZ256rr, 16375 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16376 // GIR_Coverage, 7566, 16377 GIR_Done, 16378 // Label 1206: @37607 16379 GIM_Try, /*On fail goto*//*Label 1207*/ 37756, // Rule ID 19290 // 16380 GIM_CheckFeatures, GIFBS_HasAVX512_NoVLX, 16381 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 16382 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID, 16383 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256XRegClassID, 16384 // (rotr:{ *:[v4i64] } VR256X:{ *:[v4i64] }:$src1, VR256X:{ *:[v4i64] }:$src2) => (EXTRACT_SUBREG:{ *:[v4i64] } (VPRORVQZrr:{ *:[v8i64] } (INSERT_SUBREG:{ *:[v8i64] } (IMPLICIT_DEF:{ *:[v8i64] }), VR256X:{ *:[v4i64] }:$src1, sub_ymm:{ *:[i32] }), (INSERT_SUBREG:{ *:[v8i64] } (IMPLICIT_DEF:{ *:[v8i64] }), VR256X:{ *:[v4i64] }:$src2, sub_ymm:{ *:[i32] })), sub_ymm:{ *:[i32] }) 16385 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s64, 16386 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s64, 16387 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v8s64, 16388 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v8s64, 16389 GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v8s64, 16390 GIR_BuildMI, /*InsnID*/5, /*Opcode*/TargetOpcode::IMPLICIT_DEF, 16391 GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/RegState::Define, 16392 GIR_ConstrainSelectedInstOperands, /*InsnID*/5, 16393 GIR_BuildMI, /*InsnID*/4, /*Opcode*/TargetOpcode::INSERT_SUBREG, 16394 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define, 16395 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/4, /*TempRegFlags*/0, 16396 GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/2, // src2 16397 GIR_AddImm, /*InsnID*/4, /*Imm*/10, 16398 GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, X86::VR512RegClassID, 16399 GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/1, X86::VR512RegClassID, 16400 GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/2, X86::VR256XRegClassID, 16401 GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::IMPLICIT_DEF, 16402 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, 16403 GIR_ConstrainSelectedInstOperands, /*InsnID*/3, 16404 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::INSERT_SUBREG, 16405 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 16406 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/2, /*TempRegFlags*/0, 16407 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src1 16408 GIR_AddImm, /*InsnID*/2, /*Imm*/10, 16409 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, X86::VR512RegClassID, 16410 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, X86::VR512RegClassID, 16411 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, X86::VR256XRegClassID, 16412 GIR_BuildMI, /*InsnID*/1, /*Opcode*/X86::VPRORVQZrr, 16413 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 16414 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, 16415 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/3, /*TempRegFlags*/0, 16416 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 16417 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 16418 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 16419 GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, X86::sub_ymm, 16420 GIR_EraseFromParent, /*InsnID*/0, 16421 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, X86::VR256XRegClassID, 16422 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, X86::VR512RegClassID, 16423 // GIR_Coverage, 19290, 16424 GIR_Done, 16425 // Label 1207: @37756 16426 GIM_Reject, 16427 // Label 1205: @37757 16428 GIM_Reject, 16429 // Label 1171: @37758 16430 GIM_Try, /*On fail goto*//*Label 1208*/ 37941, 16431 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s32, 16432 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s32, 16433 GIM_Try, /*On fail goto*//*Label 1209*/ 37791, // Rule ID 7539 // 16434 GIM_CheckFeatures, GIFBS_HasAVX512_HasVLX, 16435 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID, 16436 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID, 16437 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256XRegClassID, 16438 // (rotr:{ *:[v8i32] } VR256X:{ *:[v8i32] }:$src1, VR256X:{ *:[v8i32] }:$src2) => (VPRORVDZ256rr:{ *:[v8i32] } VR256X:{ *:[v8i32] }:$src1, VR256X:{ *:[v8i32] }:$src2) 16439 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPRORVDZ256rr, 16440 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16441 // GIR_Coverage, 7539, 16442 GIR_Done, 16443 // Label 1209: @37791 16444 GIM_Try, /*On fail goto*//*Label 1210*/ 37940, // Rule ID 19292 // 16445 GIM_CheckFeatures, GIFBS_HasAVX512_NoVLX, 16446 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 16447 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID, 16448 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256XRegClassID, 16449 // (rotr:{ *:[v8i32] } VR256X:{ *:[v8i32] }:$src1, VR256X:{ *:[v8i32] }:$src2) => (EXTRACT_SUBREG:{ *:[v8i32] } (VPRORVDZrr:{ *:[v16i32] } (INSERT_SUBREG:{ *:[v16i32] } (IMPLICIT_DEF:{ *:[v16i32] }), VR256X:{ *:[v8i32] }:$src1, sub_ymm:{ *:[i32] }), (INSERT_SUBREG:{ *:[v16i32] } (IMPLICIT_DEF:{ *:[v16i32] }), VR256X:{ *:[v8i32] }:$src2, sub_ymm:{ *:[i32] })), sub_ymm:{ *:[i32] }) 16450 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s32, 16451 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s32, 16452 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s32, 16453 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v16s32, 16454 GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v16s32, 16455 GIR_BuildMI, /*InsnID*/5, /*Opcode*/TargetOpcode::IMPLICIT_DEF, 16456 GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/RegState::Define, 16457 GIR_ConstrainSelectedInstOperands, /*InsnID*/5, 16458 GIR_BuildMI, /*InsnID*/4, /*Opcode*/TargetOpcode::INSERT_SUBREG, 16459 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define, 16460 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/4, /*TempRegFlags*/0, 16461 GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/2, // src2 16462 GIR_AddImm, /*InsnID*/4, /*Imm*/10, 16463 GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, X86::VR512RegClassID, 16464 GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/1, X86::VR512RegClassID, 16465 GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/2, X86::VR256XRegClassID, 16466 GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::IMPLICIT_DEF, 16467 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, 16468 GIR_ConstrainSelectedInstOperands, /*InsnID*/3, 16469 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::INSERT_SUBREG, 16470 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 16471 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/2, /*TempRegFlags*/0, 16472 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src1 16473 GIR_AddImm, /*InsnID*/2, /*Imm*/10, 16474 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, X86::VR512RegClassID, 16475 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, X86::VR512RegClassID, 16476 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, X86::VR256XRegClassID, 16477 GIR_BuildMI, /*InsnID*/1, /*Opcode*/X86::VPRORVDZrr, 16478 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 16479 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, 16480 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/3, /*TempRegFlags*/0, 16481 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 16482 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 16483 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 16484 GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, X86::sub_ymm, 16485 GIR_EraseFromParent, /*InsnID*/0, 16486 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, X86::VR256XRegClassID, 16487 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, X86::VR512RegClassID, 16488 // GIR_Coverage, 19292, 16489 GIR_Done, 16490 // Label 1210: @37940 16491 GIM_Reject, 16492 // Label 1208: @37941 16493 GIM_Reject, 16494 // Label 1172: @37942 16495 GIM_Try, /*On fail goto*//*Label 1211*/ 37973, // Rule ID 7557 // 16496 GIM_CheckFeatures, GIFBS_HasAVX512, 16497 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s64, 16498 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s64, 16499 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 16500 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR512RegClassID, 16501 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR512RegClassID, 16502 // (rotr:{ *:[v8i64] } VR512:{ *:[v8i64] }:$src1, VR512:{ *:[v8i64] }:$src2) => (VPRORVQZrr:{ *:[v8i64] } VR512:{ *:[v8i64] }:$src1, VR512:{ *:[v8i64] }:$src2) 16503 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPRORVQZrr, 16504 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16505 // GIR_Coverage, 7557, 16506 GIR_Done, 16507 // Label 1211: @37973 16508 GIM_Reject, 16509 // Label 1173: @37974 16510 GIM_Try, /*On fail goto*//*Label 1212*/ 38005, // Rule ID 7530 // 16511 GIM_CheckFeatures, GIFBS_HasAVX512, 16512 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s32, 16513 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s32, 16514 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 16515 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR512RegClassID, 16516 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR512RegClassID, 16517 // (rotr:{ *:[v16i32] } VR512:{ *:[v16i32] }:$src1, VR512:{ *:[v16i32] }:$src2) => (VPRORVDZrr:{ *:[v16i32] } VR512:{ *:[v16i32] }:$src1, VR512:{ *:[v16i32] }:$src2) 16518 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPRORVDZrr, 16519 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16520 // GIR_Coverage, 7530, 16521 GIR_Done, 16522 // Label 1212: @38005 16523 GIM_Reject, 16524 // Label 1174: @38006 16525 GIM_Reject, 16526 // Label 23: @38007 16527 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 20, /*)*//*default:*//*Label 1225*/ 39514, 16528 /*GILLT_s8*//*Label 1213*/ 38032, 16529 /*GILLT_s16*//*Label 1214*/ 38159, 16530 /*GILLT_s32*//*Label 1215*/ 38286, 16531 /*GILLT_s64*//*Label 1216*/ 38445, 0, 0, 0, 16532 /*GILLT_v2s64*//*Label 1217*/ 38604, 0, 16533 /*GILLT_v4s32*//*Label 1218*/ 38811, 16534 /*GILLT_v4s64*//*Label 1219*/ 39018, 0, 16535 /*GILLT_v8s16*//*Label 1220*/ 39202, 16536 /*GILLT_v8s32*//*Label 1221*/ 39234, 16537 /*GILLT_v8s64*//*Label 1222*/ 39418, 0, 16538 /*GILLT_v16s8*//*Label 1223*/ 39450, 0, 16539 /*GILLT_v16s32*//*Label 1224*/ 39482, 16540 // Label 1213: @38032 16541 GIM_Try, /*On fail goto*//*Label 1226*/ 38158, 16542 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s8, 16543 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s8, 16544 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR8RegClassID, 16545 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR8RegClassID, 16546 GIM_Try, /*On fail goto*//*Label 1227*/ 38072, // Rule ID 539 // 16547 GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 1, 16548 // (rotl:{ *:[i8] } GR8:{ *:[i8] }:$src1, 1:{ *:[i8] }) => (ROL8r1:{ *:[i8] }:{ *:[i32] } GR8:{ *:[i8] }:$src1) 16549 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::ROL8r1, 16550 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 16551 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 16552 GIR_EraseFromParent, /*InsnID*/0, 16553 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16554 // GIR_Coverage, 539, 16555 GIR_Done, 16556 // Label 1227: @38072 16557 GIM_Try, /*On fail goto*//*Label 1228*/ 38094, // Rule ID 16119 // 16558 GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 7, 16559 // (rotl:{ *:[i8] } GR8:{ *:[i8] }:$src1, 7:{ *:[i8] }) => (ROR8r1:{ *:[i8] }:{ *:[i32] } GR8:{ *:[i8] }:$src1) 16560 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::ROR8r1, 16561 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 16562 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 16563 GIR_EraseFromParent, /*InsnID*/0, 16564 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16565 // GIR_Coverage, 16119, 16566 GIR_Done, 16567 // Label 1228: @38094 16568 GIM_Try, /*On fail goto*//*Label 1229*/ 38124, // Rule ID 535 // 16569 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 16570 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 16571 // MIs[1] Operand 1 16572 // No operand predicates 16573 GIM_CheckIsSafeToFold, /*InsnID*/1, 16574 // (rotl:{ *:[i8] } GR8:{ *:[i8] }:$src1, (imm:{ *:[i8] }):$src2) => (ROL8ri:{ *:[i8] }:{ *:[i32] } GR8:{ *:[i8] }:$src1, (imm:{ *:[i8] }):$src2) 16575 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::ROL8ri, 16576 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 16577 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 16578 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // src2 16579 GIR_EraseFromParent, /*InsnID*/0, 16580 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16581 // GIR_Coverage, 535, 16582 GIR_Done, 16583 // Label 1229: @38124 16584 GIM_Try, /*On fail goto*//*Label 1230*/ 38157, // Rule ID 531 // 16585 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::GR8_ABCD_LRegClassID, 16586 // (rotl:{ *:[i8] } GR8:{ *:[i8] }:$src1, CL:{ *:[i8] }) => (ROL8rCL:{ *:[i8] }:{ *:[i32] } GR8:{ *:[i8] }:$src1) 16587 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, 16588 GIR_AddRegister, /*InsnID*/1, X86::CL, /*AddRegisterRegFlags*/RegState::Define, 16589 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // CL 16590 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::ROL8rCL, 16591 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 16592 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 16593 GIR_EraseFromParent, /*InsnID*/0, 16594 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16595 // GIR_Coverage, 531, 16596 GIR_Done, 16597 // Label 1230: @38157 16598 GIM_Reject, 16599 // Label 1226: @38158 16600 GIM_Reject, 16601 // Label 1214: @38159 16602 GIM_Try, /*On fail goto*//*Label 1231*/ 38285, 16603 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16, 16604 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s8, 16605 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR16RegClassID, 16606 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR16RegClassID, 16607 GIM_Try, /*On fail goto*//*Label 1232*/ 38199, // Rule ID 540 // 16608 GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 1, 16609 // (rotl:{ *:[i16] } GR16:{ *:[i16] }:$src1, 1:{ *:[i8] }) => (ROL16r1:{ *:[i16] }:{ *:[i32] } GR16:{ *:[i16] }:$src1) 16610 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::ROL16r1, 16611 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 16612 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 16613 GIR_EraseFromParent, /*InsnID*/0, 16614 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16615 // GIR_Coverage, 540, 16616 GIR_Done, 16617 // Label 1232: @38199 16618 GIM_Try, /*On fail goto*//*Label 1233*/ 38221, // Rule ID 16120 // 16619 GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 15, 16620 // (rotl:{ *:[i16] } GR16:{ *:[i16] }:$src1, 15:{ *:[i8] }) => (ROR16r1:{ *:[i16] }:{ *:[i32] } GR16:{ *:[i16] }:$src1) 16621 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::ROR16r1, 16622 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 16623 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 16624 GIR_EraseFromParent, /*InsnID*/0, 16625 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16626 // GIR_Coverage, 16120, 16627 GIR_Done, 16628 // Label 1233: @38221 16629 GIM_Try, /*On fail goto*//*Label 1234*/ 38251, // Rule ID 536 // 16630 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 16631 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 16632 // MIs[1] Operand 1 16633 // No operand predicates 16634 GIM_CheckIsSafeToFold, /*InsnID*/1, 16635 // (rotl:{ *:[i16] } GR16:{ *:[i16] }:$src1, (imm:{ *:[i8] }):$src2) => (ROL16ri:{ *:[i16] }:{ *:[i32] } GR16:{ *:[i16] }:$src1, (imm:{ *:[i8] }):$src2) 16636 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::ROL16ri, 16637 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 16638 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 16639 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // src2 16640 GIR_EraseFromParent, /*InsnID*/0, 16641 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16642 // GIR_Coverage, 536, 16643 GIR_Done, 16644 // Label 1234: @38251 16645 GIM_Try, /*On fail goto*//*Label 1235*/ 38284, // Rule ID 532 // 16646 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::GR8_ABCD_LRegClassID, 16647 // (rotl:{ *:[i16] } GR16:{ *:[i16] }:$src1, CL:{ *:[i8] }) => (ROL16rCL:{ *:[i16] }:{ *:[i32] } GR16:{ *:[i16] }:$src1) 16648 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, 16649 GIR_AddRegister, /*InsnID*/1, X86::CL, /*AddRegisterRegFlags*/RegState::Define, 16650 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // CL 16651 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::ROL16rCL, 16652 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 16653 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 16654 GIR_EraseFromParent, /*InsnID*/0, 16655 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16656 // GIR_Coverage, 532, 16657 GIR_Done, 16658 // Label 1235: @38284 16659 GIM_Reject, 16660 // Label 1231: @38285 16661 GIM_Reject, 16662 // Label 1215: @38286 16663 GIM_Try, /*On fail goto*//*Label 1236*/ 38444, 16664 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 16665 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s8, 16666 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID, 16667 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR32RegClassID, 16668 GIM_Try, /*On fail goto*//*Label 1237*/ 38336, // Rule ID 603 // 16669 GIM_CheckFeatures, GIFBS_HasFastSHLDRotate, 16670 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 16671 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 16672 // MIs[1] Operand 1 16673 // No operand predicates 16674 GIM_CheckIsSafeToFold, /*InsnID*/1, 16675 // (rotl:{ *:[i32] } GR32:{ *:[i32] }:$src1, (imm:{ *:[i8] }):$shamt) => (SHLDROT32ri:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src1, (imm:{ *:[i8] }):$shamt) 16676 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SHLDROT32ri, 16677 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 16678 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 16679 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt 16680 GIR_EraseFromParent, /*InsnID*/0, 16681 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16682 // GIR_Coverage, 603, 16683 GIR_Done, 16684 // Label 1237: @38336 16685 GIM_Try, /*On fail goto*//*Label 1238*/ 38358, // Rule ID 541 // 16686 GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 1, 16687 // (rotl:{ *:[i32] } GR32:{ *:[i32] }:$src1, 1:{ *:[i8] }) => (ROL32r1:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src1) 16688 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::ROL32r1, 16689 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 16690 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 16691 GIR_EraseFromParent, /*InsnID*/0, 16692 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16693 // GIR_Coverage, 541, 16694 GIR_Done, 16695 // Label 1238: @38358 16696 GIM_Try, /*On fail goto*//*Label 1239*/ 38380, // Rule ID 16121 // 16697 GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 31, 16698 // (rotl:{ *:[i32] } GR32:{ *:[i32] }:$src1, 31:{ *:[i8] }) => (ROR32r1:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src1) 16699 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::ROR32r1, 16700 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 16701 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 16702 GIR_EraseFromParent, /*InsnID*/0, 16703 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16704 // GIR_Coverage, 16121, 16705 GIR_Done, 16706 // Label 1239: @38380 16707 GIM_Try, /*On fail goto*//*Label 1240*/ 38410, // Rule ID 537 // 16708 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 16709 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 16710 // MIs[1] Operand 1 16711 // No operand predicates 16712 GIM_CheckIsSafeToFold, /*InsnID*/1, 16713 // (rotl:{ *:[i32] } GR32:{ *:[i32] }:$src1, (imm:{ *:[i8] }):$src2) => (ROL32ri:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src1, (imm:{ *:[i8] }):$src2) 16714 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::ROL32ri, 16715 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 16716 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 16717 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // src2 16718 GIR_EraseFromParent, /*InsnID*/0, 16719 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16720 // GIR_Coverage, 537, 16721 GIR_Done, 16722 // Label 1240: @38410 16723 GIM_Try, /*On fail goto*//*Label 1241*/ 38443, // Rule ID 533 // 16724 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::GR8_ABCD_LRegClassID, 16725 // (rotl:{ *:[i32] } GR32:{ *:[i32] }:$src1, CL:{ *:[i8] }) => (ROL32rCL:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src1) 16726 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, 16727 GIR_AddRegister, /*InsnID*/1, X86::CL, /*AddRegisterRegFlags*/RegState::Define, 16728 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // CL 16729 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::ROL32rCL, 16730 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 16731 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 16732 GIR_EraseFromParent, /*InsnID*/0, 16733 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16734 // GIR_Coverage, 533, 16735 GIR_Done, 16736 // Label 1241: @38443 16737 GIM_Reject, 16738 // Label 1236: @38444 16739 GIM_Reject, 16740 // Label 1216: @38445 16741 GIM_Try, /*On fail goto*//*Label 1242*/ 38603, 16742 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 16743 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s8, 16744 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID, 16745 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR64RegClassID, 16746 GIM_Try, /*On fail goto*//*Label 1243*/ 38495, // Rule ID 604 // 16747 GIM_CheckFeatures, GIFBS_HasFastSHLDRotate, 16748 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 16749 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 16750 // MIs[1] Operand 1 16751 // No operand predicates 16752 GIM_CheckIsSafeToFold, /*InsnID*/1, 16753 // (rotl:{ *:[i64] } GR64:{ *:[i64] }:$src1, (imm:{ *:[i8] }):$shamt) => (SHLDROT64ri:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src1, (imm:{ *:[i8] }):$shamt) 16754 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SHLDROT64ri, 16755 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 16756 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 16757 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt 16758 GIR_EraseFromParent, /*InsnID*/0, 16759 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16760 // GIR_Coverage, 604, 16761 GIR_Done, 16762 // Label 1243: @38495 16763 GIM_Try, /*On fail goto*//*Label 1244*/ 38517, // Rule ID 542 // 16764 GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 1, 16765 // (rotl:{ *:[i64] } GR64:{ *:[i64] }:$src1, 1:{ *:[i8] }) => (ROL64r1:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src1) 16766 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::ROL64r1, 16767 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 16768 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 16769 GIR_EraseFromParent, /*InsnID*/0, 16770 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16771 // GIR_Coverage, 542, 16772 GIR_Done, 16773 // Label 1244: @38517 16774 GIM_Try, /*On fail goto*//*Label 1245*/ 38539, // Rule ID 16122 // 16775 GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 63, 16776 // (rotl:{ *:[i64] } GR64:{ *:[i64] }:$src1, 63:{ *:[i8] }) => (ROR64r1:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src1) 16777 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::ROR64r1, 16778 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 16779 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 16780 GIR_EraseFromParent, /*InsnID*/0, 16781 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16782 // GIR_Coverage, 16122, 16783 GIR_Done, 16784 // Label 1245: @38539 16785 GIM_Try, /*On fail goto*//*Label 1246*/ 38569, // Rule ID 538 // 16786 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 16787 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 16788 // MIs[1] Operand 1 16789 // No operand predicates 16790 GIM_CheckIsSafeToFold, /*InsnID*/1, 16791 // (rotl:{ *:[i64] } GR64:{ *:[i64] }:$src1, (imm:{ *:[i8] }):$src2) => (ROL64ri:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src1, (imm:{ *:[i8] }):$src2) 16792 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::ROL64ri, 16793 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 16794 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 16795 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // src2 16796 GIR_EraseFromParent, /*InsnID*/0, 16797 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16798 // GIR_Coverage, 538, 16799 GIR_Done, 16800 // Label 1246: @38569 16801 GIM_Try, /*On fail goto*//*Label 1247*/ 38602, // Rule ID 534 // 16802 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::GR8_ABCD_LRegClassID, 16803 // (rotl:{ *:[i64] } GR64:{ *:[i64] }:$src1, CL:{ *:[i8] }) => (ROL64rCL:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src1) 16804 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, 16805 GIR_AddRegister, /*InsnID*/1, X86::CL, /*AddRegisterRegFlags*/RegState::Define, 16806 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // CL 16807 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::ROL64rCL, 16808 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 16809 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 16810 GIR_EraseFromParent, /*InsnID*/0, 16811 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16812 // GIR_Coverage, 534, 16813 GIR_Done, 16814 // Label 1247: @38602 16815 GIM_Reject, 16816 // Label 1242: @38603 16817 GIM_Reject, 16818 // Label 1217: @38604 16819 GIM_Try, /*On fail goto*//*Label 1248*/ 38810, 16820 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, 16821 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 16822 GIM_Try, /*On fail goto*//*Label 1249*/ 38637, // Rule ID 1313 // 16823 GIM_CheckFeatures, GIFBS_HasXOP, 16824 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 16825 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 16826 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 16827 // (rotl:{ *:[v2i64] } VR128:{ *:[v2i64] }:$src1, VR128:{ *:[v2i64] }:$src2) => (VPROTQrr:{ *:[v2i64] } VR128:{ *:[v2i64] }:$src1, VR128:{ *:[v2i64] }:$src2) 16828 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPROTQrr, 16829 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16830 // GIR_Coverage, 1313, 16831 GIR_Done, 16832 // Label 1249: @38637 16833 GIM_Try, /*On fail goto*//*Label 1250*/ 38660, // Rule ID 7629 // 16834 GIM_CheckFeatures, GIFBS_HasAVX512_HasVLX, 16835 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID, 16836 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID, 16837 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128XRegClassID, 16838 // (rotl:{ *:[v2i64] } VR128X:{ *:[v2i64] }:$src1, VR128X:{ *:[v2i64] }:$src2) => (VPROLVQZ128rr:{ *:[v2i64] } VR128X:{ *:[v2i64] }:$src1, VR128X:{ *:[v2i64] }:$src2) 16839 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPROLVQZ128rr, 16840 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16841 // GIR_Coverage, 7629, 16842 GIR_Done, 16843 // Label 1250: @38660 16844 GIM_Try, /*On fail goto*//*Label 1251*/ 38809, // Rule ID 19281 // 16845 GIM_CheckFeatures, GIFBS_HasAVX512_NoVLX, 16846 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 16847 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID, 16848 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128XRegClassID, 16849 // (rotl:{ *:[v2i64] } VR128X:{ *:[v2i64] }:$src1, VR128X:{ *:[v2i64] }:$src2) => (EXTRACT_SUBREG:{ *:[v2i64] } (VPROLVQZrr:{ *:[v8i64] } (INSERT_SUBREG:{ *:[v8i64] } (IMPLICIT_DEF:{ *:[v8i64] }), VR128X:{ *:[v2i64] }:$src1, sub_xmm:{ *:[i32] }), (INSERT_SUBREG:{ *:[v8i64] } (IMPLICIT_DEF:{ *:[v8i64] }), VR128X:{ *:[v2i64] }:$src2, sub_xmm:{ *:[i32] })), sub_xmm:{ *:[i32] }) 16850 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s64, 16851 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s64, 16852 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v8s64, 16853 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v8s64, 16854 GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v8s64, 16855 GIR_BuildMI, /*InsnID*/5, /*Opcode*/TargetOpcode::IMPLICIT_DEF, 16856 GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/RegState::Define, 16857 GIR_ConstrainSelectedInstOperands, /*InsnID*/5, 16858 GIR_BuildMI, /*InsnID*/4, /*Opcode*/TargetOpcode::INSERT_SUBREG, 16859 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define, 16860 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/4, /*TempRegFlags*/0, 16861 GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/2, // src2 16862 GIR_AddImm, /*InsnID*/4, /*Imm*/9, 16863 GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, X86::VR512RegClassID, 16864 GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/1, X86::VR512RegClassID, 16865 GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/2, X86::VR128XRegClassID, 16866 GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::IMPLICIT_DEF, 16867 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, 16868 GIR_ConstrainSelectedInstOperands, /*InsnID*/3, 16869 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::INSERT_SUBREG, 16870 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 16871 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/2, /*TempRegFlags*/0, 16872 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src1 16873 GIR_AddImm, /*InsnID*/2, /*Imm*/9, 16874 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, X86::VR512RegClassID, 16875 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, X86::VR512RegClassID, 16876 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, X86::VR128XRegClassID, 16877 GIR_BuildMI, /*InsnID*/1, /*Opcode*/X86::VPROLVQZrr, 16878 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 16879 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, 16880 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/3, /*TempRegFlags*/0, 16881 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 16882 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 16883 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 16884 GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, X86::sub_xmm, 16885 GIR_EraseFromParent, /*InsnID*/0, 16886 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, X86::FR16XRegClassID, 16887 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, X86::VR512RegClassID, 16888 // GIR_Coverage, 19281, 16889 GIR_Done, 16890 // Label 1251: @38809 16891 GIM_Reject, 16892 // Label 1248: @38810 16893 GIM_Reject, 16894 // Label 1218: @38811 16895 GIM_Try, /*On fail goto*//*Label 1252*/ 39017, 16896 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, 16897 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 16898 GIM_Try, /*On fail goto*//*Label 1253*/ 38844, // Rule ID 1310 // 16899 GIM_CheckFeatures, GIFBS_HasXOP, 16900 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 16901 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 16902 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 16903 // (rotl:{ *:[v4i32] } VR128:{ *:[v4i32] }:$src1, VR128:{ *:[v4i32] }:$src2) => (VPROTDrr:{ *:[v4i32] } VR128:{ *:[v4i32] }:$src1, VR128:{ *:[v4i32] }:$src2) 16904 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPROTDrr, 16905 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16906 // GIR_Coverage, 1310, 16907 GIR_Done, 16908 // Label 1253: @38844 16909 GIM_Try, /*On fail goto*//*Label 1254*/ 38867, // Rule ID 7602 // 16910 GIM_CheckFeatures, GIFBS_HasAVX512_HasVLX, 16911 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID, 16912 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID, 16913 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128XRegClassID, 16914 // (rotl:{ *:[v4i32] } VR128X:{ *:[v4i32] }:$src1, VR128X:{ *:[v4i32] }:$src2) => (VPROLVDZ128rr:{ *:[v4i32] } VR128X:{ *:[v4i32] }:$src1, VR128X:{ *:[v4i32] }:$src2) 16915 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPROLVDZ128rr, 16916 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16917 // GIR_Coverage, 7602, 16918 GIR_Done, 16919 // Label 1254: @38867 16920 GIM_Try, /*On fail goto*//*Label 1255*/ 39016, // Rule ID 19283 // 16921 GIM_CheckFeatures, GIFBS_HasAVX512_NoVLX, 16922 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 16923 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID, 16924 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128XRegClassID, 16925 // (rotl:{ *:[v4i32] } VR128X:{ *:[v4i32] }:$src1, VR128X:{ *:[v4i32] }:$src2) => (EXTRACT_SUBREG:{ *:[v4i32] } (VPROLVDZrr:{ *:[v16i32] } (INSERT_SUBREG:{ *:[v16i32] } (IMPLICIT_DEF:{ *:[v16i32] }), VR128X:{ *:[v4i32] }:$src1, sub_xmm:{ *:[i32] }), (INSERT_SUBREG:{ *:[v16i32] } (IMPLICIT_DEF:{ *:[v16i32] }), VR128X:{ *:[v4i32] }:$src2, sub_xmm:{ *:[i32] })), sub_xmm:{ *:[i32] }) 16926 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s32, 16927 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s32, 16928 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s32, 16929 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v16s32, 16930 GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v16s32, 16931 GIR_BuildMI, /*InsnID*/5, /*Opcode*/TargetOpcode::IMPLICIT_DEF, 16932 GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/RegState::Define, 16933 GIR_ConstrainSelectedInstOperands, /*InsnID*/5, 16934 GIR_BuildMI, /*InsnID*/4, /*Opcode*/TargetOpcode::INSERT_SUBREG, 16935 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define, 16936 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/4, /*TempRegFlags*/0, 16937 GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/2, // src2 16938 GIR_AddImm, /*InsnID*/4, /*Imm*/9, 16939 GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, X86::VR512RegClassID, 16940 GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/1, X86::VR512RegClassID, 16941 GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/2, X86::VR128XRegClassID, 16942 GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::IMPLICIT_DEF, 16943 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, 16944 GIR_ConstrainSelectedInstOperands, /*InsnID*/3, 16945 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::INSERT_SUBREG, 16946 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 16947 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/2, /*TempRegFlags*/0, 16948 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src1 16949 GIR_AddImm, /*InsnID*/2, /*Imm*/9, 16950 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, X86::VR512RegClassID, 16951 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, X86::VR512RegClassID, 16952 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, X86::VR128XRegClassID, 16953 GIR_BuildMI, /*InsnID*/1, /*Opcode*/X86::VPROLVDZrr, 16954 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 16955 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, 16956 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/3, /*TempRegFlags*/0, 16957 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 16958 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 16959 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 16960 GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, X86::sub_xmm, 16961 GIR_EraseFromParent, /*InsnID*/0, 16962 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, X86::FR16XRegClassID, 16963 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, X86::VR512RegClassID, 16964 // GIR_Coverage, 19283, 16965 GIR_Done, 16966 // Label 1255: @39016 16967 GIM_Reject, 16968 // Label 1252: @39017 16969 GIM_Reject, 16970 // Label 1219: @39018 16971 GIM_Try, /*On fail goto*//*Label 1256*/ 39201, 16972 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s64, 16973 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s64, 16974 GIM_Try, /*On fail goto*//*Label 1257*/ 39051, // Rule ID 7620 // 16975 GIM_CheckFeatures, GIFBS_HasAVX512_HasVLX, 16976 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID, 16977 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID, 16978 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256XRegClassID, 16979 // (rotl:{ *:[v4i64] } VR256X:{ *:[v4i64] }:$src1, VR256X:{ *:[v4i64] }:$src2) => (VPROLVQZ256rr:{ *:[v4i64] } VR256X:{ *:[v4i64] }:$src1, VR256X:{ *:[v4i64] }:$src2) 16980 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPROLVQZ256rr, 16981 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16982 // GIR_Coverage, 7620, 16983 GIR_Done, 16984 // Label 1257: @39051 16985 GIM_Try, /*On fail goto*//*Label 1258*/ 39200, // Rule ID 19282 // 16986 GIM_CheckFeatures, GIFBS_HasAVX512_NoVLX, 16987 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 16988 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID, 16989 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256XRegClassID, 16990 // (rotl:{ *:[v4i64] } VR256X:{ *:[v4i64] }:$src1, VR256X:{ *:[v4i64] }:$src2) => (EXTRACT_SUBREG:{ *:[v4i64] } (VPROLVQZrr:{ *:[v8i64] } (INSERT_SUBREG:{ *:[v8i64] } (IMPLICIT_DEF:{ *:[v8i64] }), VR256X:{ *:[v4i64] }:$src1, sub_ymm:{ *:[i32] }), (INSERT_SUBREG:{ *:[v8i64] } (IMPLICIT_DEF:{ *:[v8i64] }), VR256X:{ *:[v4i64] }:$src2, sub_ymm:{ *:[i32] })), sub_ymm:{ *:[i32] }) 16991 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s64, 16992 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s64, 16993 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v8s64, 16994 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v8s64, 16995 GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v8s64, 16996 GIR_BuildMI, /*InsnID*/5, /*Opcode*/TargetOpcode::IMPLICIT_DEF, 16997 GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/RegState::Define, 16998 GIR_ConstrainSelectedInstOperands, /*InsnID*/5, 16999 GIR_BuildMI, /*InsnID*/4, /*Opcode*/TargetOpcode::INSERT_SUBREG, 17000 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define, 17001 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/4, /*TempRegFlags*/0, 17002 GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/2, // src2 17003 GIR_AddImm, /*InsnID*/4, /*Imm*/10, 17004 GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, X86::VR512RegClassID, 17005 GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/1, X86::VR512RegClassID, 17006 GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/2, X86::VR256XRegClassID, 17007 GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::IMPLICIT_DEF, 17008 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, 17009 GIR_ConstrainSelectedInstOperands, /*InsnID*/3, 17010 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::INSERT_SUBREG, 17011 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 17012 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/2, /*TempRegFlags*/0, 17013 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src1 17014 GIR_AddImm, /*InsnID*/2, /*Imm*/10, 17015 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, X86::VR512RegClassID, 17016 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, X86::VR512RegClassID, 17017 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, X86::VR256XRegClassID, 17018 GIR_BuildMI, /*InsnID*/1, /*Opcode*/X86::VPROLVQZrr, 17019 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 17020 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, 17021 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/3, /*TempRegFlags*/0, 17022 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 17023 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 17024 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 17025 GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, X86::sub_ymm, 17026 GIR_EraseFromParent, /*InsnID*/0, 17027 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, X86::VR256XRegClassID, 17028 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, X86::VR512RegClassID, 17029 // GIR_Coverage, 19282, 17030 GIR_Done, 17031 // Label 1258: @39200 17032 GIM_Reject, 17033 // Label 1256: @39201 17034 GIM_Reject, 17035 // Label 1220: @39202 17036 GIM_Try, /*On fail goto*//*Label 1259*/ 39233, // Rule ID 1316 // 17037 GIM_CheckFeatures, GIFBS_HasXOP, 17038 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, 17039 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 17040 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 17041 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 17042 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 17043 // (rotl:{ *:[v8i16] } VR128:{ *:[v8i16] }:$src1, VR128:{ *:[v8i16] }:$src2) => (VPROTWrr:{ *:[v8i16] } VR128:{ *:[v8i16] }:$src1, VR128:{ *:[v8i16] }:$src2) 17044 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPROTWrr, 17045 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 17046 // GIR_Coverage, 1316, 17047 GIR_Done, 17048 // Label 1259: @39233 17049 GIM_Reject, 17050 // Label 1221: @39234 17051 GIM_Try, /*On fail goto*//*Label 1260*/ 39417, 17052 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s32, 17053 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s32, 17054 GIM_Try, /*On fail goto*//*Label 1261*/ 39267, // Rule ID 7593 // 17055 GIM_CheckFeatures, GIFBS_HasAVX512_HasVLX, 17056 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID, 17057 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID, 17058 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256XRegClassID, 17059 // (rotl:{ *:[v8i32] } VR256X:{ *:[v8i32] }:$src1, VR256X:{ *:[v8i32] }:$src2) => (VPROLVDZ256rr:{ *:[v8i32] } VR256X:{ *:[v8i32] }:$src1, VR256X:{ *:[v8i32] }:$src2) 17060 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPROLVDZ256rr, 17061 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 17062 // GIR_Coverage, 7593, 17063 GIR_Done, 17064 // Label 1261: @39267 17065 GIM_Try, /*On fail goto*//*Label 1262*/ 39416, // Rule ID 19284 // 17066 GIM_CheckFeatures, GIFBS_HasAVX512_NoVLX, 17067 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 17068 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID, 17069 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256XRegClassID, 17070 // (rotl:{ *:[v8i32] } VR256X:{ *:[v8i32] }:$src1, VR256X:{ *:[v8i32] }:$src2) => (EXTRACT_SUBREG:{ *:[v8i32] } (VPROLVDZrr:{ *:[v16i32] } (INSERT_SUBREG:{ *:[v16i32] } (IMPLICIT_DEF:{ *:[v16i32] }), VR256X:{ *:[v8i32] }:$src1, sub_ymm:{ *:[i32] }), (INSERT_SUBREG:{ *:[v16i32] } (IMPLICIT_DEF:{ *:[v16i32] }), VR256X:{ *:[v8i32] }:$src2, sub_ymm:{ *:[i32] })), sub_ymm:{ *:[i32] }) 17071 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s32, 17072 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s32, 17073 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s32, 17074 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v16s32, 17075 GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v16s32, 17076 GIR_BuildMI, /*InsnID*/5, /*Opcode*/TargetOpcode::IMPLICIT_DEF, 17077 GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/RegState::Define, 17078 GIR_ConstrainSelectedInstOperands, /*InsnID*/5, 17079 GIR_BuildMI, /*InsnID*/4, /*Opcode*/TargetOpcode::INSERT_SUBREG, 17080 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define, 17081 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/4, /*TempRegFlags*/0, 17082 GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/2, // src2 17083 GIR_AddImm, /*InsnID*/4, /*Imm*/10, 17084 GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, X86::VR512RegClassID, 17085 GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/1, X86::VR512RegClassID, 17086 GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/2, X86::VR256XRegClassID, 17087 GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::IMPLICIT_DEF, 17088 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, 17089 GIR_ConstrainSelectedInstOperands, /*InsnID*/3, 17090 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::INSERT_SUBREG, 17091 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 17092 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/2, /*TempRegFlags*/0, 17093 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src1 17094 GIR_AddImm, /*InsnID*/2, /*Imm*/10, 17095 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, X86::VR512RegClassID, 17096 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, X86::VR512RegClassID, 17097 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, X86::VR256XRegClassID, 17098 GIR_BuildMI, /*InsnID*/1, /*Opcode*/X86::VPROLVDZrr, 17099 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 17100 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, 17101 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/3, /*TempRegFlags*/0, 17102 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 17103 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 17104 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 17105 GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, X86::sub_ymm, 17106 GIR_EraseFromParent, /*InsnID*/0, 17107 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, X86::VR256XRegClassID, 17108 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, X86::VR512RegClassID, 17109 // GIR_Coverage, 19284, 17110 GIR_Done, 17111 // Label 1262: @39416 17112 GIM_Reject, 17113 // Label 1260: @39417 17114 GIM_Reject, 17115 // Label 1222: @39418 17116 GIM_Try, /*On fail goto*//*Label 1263*/ 39449, // Rule ID 7611 // 17117 GIM_CheckFeatures, GIFBS_HasAVX512, 17118 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s64, 17119 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s64, 17120 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 17121 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR512RegClassID, 17122 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR512RegClassID, 17123 // (rotl:{ *:[v8i64] } VR512:{ *:[v8i64] }:$src1, VR512:{ *:[v8i64] }:$src2) => (VPROLVQZrr:{ *:[v8i64] } VR512:{ *:[v8i64] }:$src1, VR512:{ *:[v8i64] }:$src2) 17124 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPROLVQZrr, 17125 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 17126 // GIR_Coverage, 7611, 17127 GIR_Done, 17128 // Label 1263: @39449 17129 GIM_Reject, 17130 // Label 1223: @39450 17131 GIM_Try, /*On fail goto*//*Label 1264*/ 39481, // Rule ID 1307 // 17132 GIM_CheckFeatures, GIFBS_HasXOP, 17133 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, 17134 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, 17135 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 17136 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 17137 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 17138 // (rotl:{ *:[v16i8] } VR128:{ *:[v16i8] }:$src1, VR128:{ *:[v16i8] }:$src2) => (VPROTBrr:{ *:[v16i8] } VR128:{ *:[v16i8] }:$src1, VR128:{ *:[v16i8] }:$src2) 17139 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPROTBrr, 17140 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 17141 // GIR_Coverage, 1307, 17142 GIR_Done, 17143 // Label 1264: @39481 17144 GIM_Reject, 17145 // Label 1224: @39482 17146 GIM_Try, /*On fail goto*//*Label 1265*/ 39513, // Rule ID 7584 // 17147 GIM_CheckFeatures, GIFBS_HasAVX512, 17148 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s32, 17149 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s32, 17150 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 17151 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR512RegClassID, 17152 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR512RegClassID, 17153 // (rotl:{ *:[v16i32] } VR512:{ *:[v16i32] }:$src1, VR512:{ *:[v16i32] }:$src2) => (VPROLVDZrr:{ *:[v16i32] } VR512:{ *:[v16i32] }:$src1, VR512:{ *:[v16i32] }:$src2) 17154 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPROLVDZrr, 17155 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 17156 // GIR_Coverage, 7584, 17157 GIR_Done, 17158 // Label 1265: @39513 17159 GIM_Reject, 17160 // Label 1225: @39514 17161 GIM_Reject, 17162 // Label 24: @39515 17163 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/7, 24, /*)*//*default:*//*Label 1272*/ 41071, 17164 /*GILLT_v2s1*//*Label 1266*/ 39538, 0, 17165 /*GILLT_v4s1*//*Label 1267*/ 39689, 0, 0, 17166 /*GILLT_v8s1*//*Label 1268*/ 40024, 0, 0, 0, 17167 /*GILLT_v16s1*//*Label 1269*/ 40411, 0, 0, 0, 17168 /*GILLT_v32s1*//*Label 1270*/ 40798, 0, 0, 17169 /*GILLT_v64s1*//*Label 1271*/ 41018, 17170 // Label 1266: @39538 17171 GIM_Try, /*On fail goto*//*Label 1273*/ 39688, 17172 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 17173 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, 17174 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VK2RegClassID, 17175 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SGT, 17176 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::VR128XRegClassID, 17177 GIM_Try, /*On fail goto*//*Label 1274*/ 39592, // Rule ID 12311 // 17178 GIM_CheckFeatures, GIFBS_HasDQI_HasVLX, 17179 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 17180 GIM_CheckOpcodeIsEither, /*MI*/1, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, 17181 GIM_CheckIsBuildVectorAllZeros, /*MI*/1, 17182 GIM_CheckIsSafeToFold, /*InsnID*/1, 17183 // (setcc:{ *:[v2i1] } immAllZerosV:{ *:[v2i64] }, VR128X:{ *:[v2i64] }:$src, SETGT:{ *:[Other] }) => (VPMOVQ2MZ128rr:{ *:[v2i1] } VR128X:{ *:[v2i64] }:$src) 17184 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VPMOVQ2MZ128rr, 17185 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 17186 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src 17187 GIR_EraseFromParent, /*InsnID*/0, 17188 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 17189 // GIR_Coverage, 12311, 17190 GIR_Done, 17191 // Label 1274: @39592 17192 GIM_Try, /*On fail goto*//*Label 1275*/ 39687, // Rule ID 20113 // 17193 GIM_CheckFeatures, GIFBS_HasDQI_NoVLX, 17194 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 17195 GIM_CheckOpcodeIsEither, /*MI*/1, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, 17196 GIM_CheckIsBuildVectorAllZeros, /*MI*/1, 17197 GIM_CheckIsSafeToFold, /*InsnID*/1, 17198 // (setcc:{ *:[v2i1] } immAllZerosV:{ *:[v2i64] }, VR128X:{ *:[v2i64] }:$src, SETGT:{ *:[Other] }) => (COPY_TO_REGCLASS:{ *:[v2i1] } (VPMOVQ2MZrr:{ *:[v8i1] } (INSERT_SUBREG:{ *:[v8i64] } (IMPLICIT_DEF:{ *:[v8i64] }), VR128X:{ *:[v2i64] }:$src, sub_xmm:{ *:[i32] })), VK2:{ *:[i32] }) 17199 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s1, 17200 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s64, 17201 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v8s64, 17202 GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::IMPLICIT_DEF, 17203 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, 17204 GIR_ConstrainSelectedInstOperands, /*InsnID*/3, 17205 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::INSERT_SUBREG, 17206 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 17207 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/2, /*TempRegFlags*/0, 17208 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // src 17209 GIR_AddImm, /*InsnID*/2, /*Imm*/9, 17210 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, X86::VR512RegClassID, 17211 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, X86::VR512RegClassID, 17212 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, X86::VR128XRegClassID, 17213 GIR_BuildMI, /*InsnID*/1, /*Opcode*/X86::VPMOVQ2MZrr, 17214 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 17215 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, 17216 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 17217 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 17218 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 17219 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 17220 GIR_EraseFromParent, /*InsnID*/0, 17221 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, X86::VK2RegClassID, 17222 // GIR_Coverage, 20113, 17223 GIR_Done, 17224 // Label 1275: @39687 17225 GIM_Reject, 17226 // Label 1273: @39688 17227 GIM_Reject, 17228 // Label 1267: @39689 17229 GIM_Try, /*On fail goto*//*Label 1276*/ 39741, // Rule ID 12308 // 17230 GIM_CheckFeatures, GIFBS_HasDQI_HasVLX, 17231 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 17232 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, 17233 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VK4RegClassID, 17234 // MIs[0] Operand 1 17235 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SGT, 17236 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 17237 GIM_CheckOpcodeIsEither, /*MI*/1, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, 17238 GIM_CheckIsBuildVectorAllZeros, /*MI*/1, 17239 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::VR128XRegClassID, 17240 GIM_CheckIsSafeToFold, /*InsnID*/1, 17241 // (setcc:{ *:[v4i1] } immAllZerosV:{ *:[v4i32] }, VR128X:{ *:[v4i32] }:$src, SETGT:{ *:[Other] }) => (VPMOVD2MZ128rr:{ *:[v4i1] } VR128X:{ *:[v4i32] }:$src) 17242 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VPMOVD2MZ128rr, 17243 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 17244 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src 17245 GIR_EraseFromParent, /*InsnID*/0, 17246 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 17247 // GIR_Coverage, 12308, 17248 GIR_Done, 17249 // Label 1276: @39741 17250 GIM_Try, /*On fail goto*//*Label 1277*/ 39793, // Rule ID 12310 // 17251 GIM_CheckFeatures, GIFBS_HasDQI_HasVLX, 17252 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s64, 17253 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s64, 17254 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VK4RegClassID, 17255 // MIs[0] Operand 1 17256 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SGT, 17257 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 17258 GIM_CheckOpcodeIsEither, /*MI*/1, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, 17259 GIM_CheckIsBuildVectorAllZeros, /*MI*/1, 17260 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::VR256XRegClassID, 17261 GIM_CheckIsSafeToFold, /*InsnID*/1, 17262 // (setcc:{ *:[v4i1] } immAllZerosV:{ *:[v4i64] }, VR256X:{ *:[v4i64] }:$src, SETGT:{ *:[Other] }) => (VPMOVQ2MZ256rr:{ *:[v4i1] } VR256X:{ *:[v4i64] }:$src) 17263 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VPMOVQ2MZ256rr, 17264 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 17265 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src 17266 GIR_EraseFromParent, /*InsnID*/0, 17267 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 17268 // GIR_Coverage, 12310, 17269 GIR_Done, 17270 // Label 1277: @39793 17271 GIM_Try, /*On fail goto*//*Label 1278*/ 39908, // Rule ID 20111 // 17272 GIM_CheckFeatures, GIFBS_HasDQI_NoVLX, 17273 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 17274 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, 17275 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VK4RegClassID, 17276 // MIs[0] Operand 1 17277 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SGT, 17278 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 17279 GIM_CheckOpcodeIsEither, /*MI*/1, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, 17280 GIM_CheckIsBuildVectorAllZeros, /*MI*/1, 17281 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::VR128XRegClassID, 17282 GIM_CheckIsSafeToFold, /*InsnID*/1, 17283 // (setcc:{ *:[v4i1] } immAllZerosV:{ *:[v4i32] }, VR128X:{ *:[v4i32] }:$src, SETGT:{ *:[Other] }) => (COPY_TO_REGCLASS:{ *:[v4i1] } (VPMOVD2MZrr:{ *:[v16i1] } (INSERT_SUBREG:{ *:[v16i32] } (IMPLICIT_DEF:{ *:[v16i32] }), VR128X:{ *:[v4i32] }:$src, sub_xmm:{ *:[i32] })), VK4:{ *:[i32] }) 17284 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s1, 17285 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s32, 17286 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s32, 17287 GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::IMPLICIT_DEF, 17288 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, 17289 GIR_ConstrainSelectedInstOperands, /*InsnID*/3, 17290 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::INSERT_SUBREG, 17291 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 17292 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/2, /*TempRegFlags*/0, 17293 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // src 17294 GIR_AddImm, /*InsnID*/2, /*Imm*/9, 17295 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, X86::VR512RegClassID, 17296 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, X86::VR512RegClassID, 17297 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, X86::VR128XRegClassID, 17298 GIR_BuildMI, /*InsnID*/1, /*Opcode*/X86::VPMOVD2MZrr, 17299 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 17300 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, 17301 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 17302 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 17303 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 17304 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 17305 GIR_EraseFromParent, /*InsnID*/0, 17306 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, X86::VK4RegClassID, 17307 // GIR_Coverage, 20111, 17308 GIR_Done, 17309 // Label 1278: @39908 17310 GIM_Try, /*On fail goto*//*Label 1279*/ 40023, // Rule ID 20112 // 17311 GIM_CheckFeatures, GIFBS_HasDQI_NoVLX, 17312 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s64, 17313 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s64, 17314 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VK4RegClassID, 17315 // MIs[0] Operand 1 17316 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SGT, 17317 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 17318 GIM_CheckOpcodeIsEither, /*MI*/1, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, 17319 GIM_CheckIsBuildVectorAllZeros, /*MI*/1, 17320 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::VR256XRegClassID, 17321 GIM_CheckIsSafeToFold, /*InsnID*/1, 17322 // (setcc:{ *:[v4i1] } immAllZerosV:{ *:[v4i64] }, VR256X:{ *:[v4i64] }:$src, SETGT:{ *:[Other] }) => (COPY_TO_REGCLASS:{ *:[v4i1] } (VPMOVQ2MZrr:{ *:[v8i1] } (INSERT_SUBREG:{ *:[v8i64] } (IMPLICIT_DEF:{ *:[v8i64] }), VR256X:{ *:[v4i64] }:$src, sub_ymm:{ *:[i32] })), VK4:{ *:[i32] }) 17323 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s1, 17324 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s64, 17325 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v8s64, 17326 GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::IMPLICIT_DEF, 17327 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, 17328 GIR_ConstrainSelectedInstOperands, /*InsnID*/3, 17329 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::INSERT_SUBREG, 17330 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 17331 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/2, /*TempRegFlags*/0, 17332 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // src 17333 GIR_AddImm, /*InsnID*/2, /*Imm*/10, 17334 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, X86::VR512RegClassID, 17335 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, X86::VR512RegClassID, 17336 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, X86::VR256XRegClassID, 17337 GIR_BuildMI, /*InsnID*/1, /*Opcode*/X86::VPMOVQ2MZrr, 17338 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 17339 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, 17340 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 17341 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 17342 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 17343 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 17344 GIR_EraseFromParent, /*InsnID*/0, 17345 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, X86::VK4RegClassID, 17346 // GIR_Coverage, 20112, 17347 GIR_Done, 17348 // Label 1279: @40023 17349 GIM_Reject, 17350 // Label 1268: @40024 17351 GIM_Try, /*On fail goto*//*Label 1280*/ 40076, // Rule ID 12305 // 17352 GIM_CheckFeatures, GIFBS_HasBWI_HasVLX, 17353 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 17354 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, 17355 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VK8RegClassID, 17356 // MIs[0] Operand 1 17357 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SGT, 17358 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 17359 GIM_CheckOpcodeIsEither, /*MI*/1, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, 17360 GIM_CheckIsBuildVectorAllZeros, /*MI*/1, 17361 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::VR128XRegClassID, 17362 GIM_CheckIsSafeToFold, /*InsnID*/1, 17363 // (setcc:{ *:[v8i1] } immAllZerosV:{ *:[v8i16] }, VR128X:{ *:[v8i16] }:$src, SETGT:{ *:[Other] }) => (VPMOVW2MZ128rr:{ *:[v8i1] } VR128X:{ *:[v8i16] }:$src) 17364 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VPMOVW2MZ128rr, 17365 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 17366 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src 17367 GIR_EraseFromParent, /*InsnID*/0, 17368 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 17369 // GIR_Coverage, 12305, 17370 GIR_Done, 17371 // Label 1280: @40076 17372 GIM_Try, /*On fail goto*//*Label 1281*/ 40128, // Rule ID 12307 // 17373 GIM_CheckFeatures, GIFBS_HasDQI_HasVLX, 17374 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s32, 17375 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s32, 17376 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VK8RegClassID, 17377 // MIs[0] Operand 1 17378 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SGT, 17379 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 17380 GIM_CheckOpcodeIsEither, /*MI*/1, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, 17381 GIM_CheckIsBuildVectorAllZeros, /*MI*/1, 17382 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::VR256XRegClassID, 17383 GIM_CheckIsSafeToFold, /*InsnID*/1, 17384 // (setcc:{ *:[v8i1] } immAllZerosV:{ *:[v8i32] }, VR256X:{ *:[v8i32] }:$src, SETGT:{ *:[Other] }) => (VPMOVD2MZ256rr:{ *:[v8i1] } VR256X:{ *:[v8i32] }:$src) 17385 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VPMOVD2MZ256rr, 17386 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 17387 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src 17388 GIR_EraseFromParent, /*InsnID*/0, 17389 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 17390 // GIR_Coverage, 12307, 17391 GIR_Done, 17392 // Label 1281: @40128 17393 GIM_Try, /*On fail goto*//*Label 1282*/ 40180, // Rule ID 12309 // 17394 GIM_CheckFeatures, GIFBS_HasDQI, 17395 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s64, 17396 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s64, 17397 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VK8RegClassID, 17398 // MIs[0] Operand 1 17399 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SGT, 17400 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 17401 GIM_CheckOpcodeIsEither, /*MI*/1, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, 17402 GIM_CheckIsBuildVectorAllZeros, /*MI*/1, 17403 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::VR512RegClassID, 17404 GIM_CheckIsSafeToFold, /*InsnID*/1, 17405 // (setcc:{ *:[v8i1] } immAllZerosV:{ *:[v8i64] }, VR512:{ *:[v8i64] }:$src, SETGT:{ *:[Other] }) => (VPMOVQ2MZrr:{ *:[v8i1] } VR512:{ *:[v8i64] }:$src) 17406 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VPMOVQ2MZrr, 17407 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 17408 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src 17409 GIR_EraseFromParent, /*InsnID*/0, 17410 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 17411 // GIR_Coverage, 12309, 17412 GIR_Done, 17413 // Label 1282: @40180 17414 GIM_Try, /*On fail goto*//*Label 1283*/ 40295, // Rule ID 20109 // 17415 GIM_CheckFeatures, GIFBS_HasBWI_NoVLX, 17416 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 17417 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, 17418 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VK8RegClassID, 17419 // MIs[0] Operand 1 17420 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SGT, 17421 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 17422 GIM_CheckOpcodeIsEither, /*MI*/1, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, 17423 GIM_CheckIsBuildVectorAllZeros, /*MI*/1, 17424 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::VR128XRegClassID, 17425 GIM_CheckIsSafeToFold, /*InsnID*/1, 17426 // (setcc:{ *:[v8i1] } immAllZerosV:{ *:[v8i16] }, VR128X:{ *:[v8i16] }:$src, SETGT:{ *:[Other] }) => (COPY_TO_REGCLASS:{ *:[v8i1] } (VPMOVW2MZrr:{ *:[v32i1] } (INSERT_SUBREG:{ *:[v32i16] } (IMPLICIT_DEF:{ *:[v32i16] }), VR128X:{ *:[v8i16] }:$src, sub_xmm:{ *:[i32] })), VK8:{ *:[i32] }) 17427 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v32s1, 17428 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v32s16, 17429 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v32s16, 17430 GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::IMPLICIT_DEF, 17431 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, 17432 GIR_ConstrainSelectedInstOperands, /*InsnID*/3, 17433 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::INSERT_SUBREG, 17434 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 17435 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/2, /*TempRegFlags*/0, 17436 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // src 17437 GIR_AddImm, /*InsnID*/2, /*Imm*/9, 17438 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, X86::VR512RegClassID, 17439 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, X86::VR512RegClassID, 17440 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, X86::VR128XRegClassID, 17441 GIR_BuildMI, /*InsnID*/1, /*Opcode*/X86::VPMOVW2MZrr, 17442 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 17443 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, 17444 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 17445 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 17446 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 17447 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 17448 GIR_EraseFromParent, /*InsnID*/0, 17449 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, X86::VK8RegClassID, 17450 // GIR_Coverage, 20109, 17451 GIR_Done, 17452 // Label 1283: @40295 17453 GIM_Try, /*On fail goto*//*Label 1284*/ 40410, // Rule ID 20110 // 17454 GIM_CheckFeatures, GIFBS_HasDQI_NoVLX, 17455 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s32, 17456 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s32, 17457 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VK8RegClassID, 17458 // MIs[0] Operand 1 17459 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SGT, 17460 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 17461 GIM_CheckOpcodeIsEither, /*MI*/1, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, 17462 GIM_CheckIsBuildVectorAllZeros, /*MI*/1, 17463 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::VR256XRegClassID, 17464 GIM_CheckIsSafeToFold, /*InsnID*/1, 17465 // (setcc:{ *:[v8i1] } immAllZerosV:{ *:[v8i32] }, VR256X:{ *:[v8i32] }:$src, SETGT:{ *:[Other] }) => (COPY_TO_REGCLASS:{ *:[v8i1] } (VPMOVD2MZrr:{ *:[v16i1] } (INSERT_SUBREG:{ *:[v16i32] } (IMPLICIT_DEF:{ *:[v16i32] }), VR256X:{ *:[v8i32] }:$src, sub_ymm:{ *:[i32] })), VK8:{ *:[i32] }) 17466 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s1, 17467 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s32, 17468 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s32, 17469 GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::IMPLICIT_DEF, 17470 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, 17471 GIR_ConstrainSelectedInstOperands, /*InsnID*/3, 17472 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::INSERT_SUBREG, 17473 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 17474 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/2, /*TempRegFlags*/0, 17475 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // src 17476 GIR_AddImm, /*InsnID*/2, /*Imm*/10, 17477 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, X86::VR512RegClassID, 17478 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, X86::VR512RegClassID, 17479 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, X86::VR256XRegClassID, 17480 GIR_BuildMI, /*InsnID*/1, /*Opcode*/X86::VPMOVD2MZrr, 17481 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 17482 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, 17483 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 17484 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 17485 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 17486 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 17487 GIR_EraseFromParent, /*InsnID*/0, 17488 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, X86::VK8RegClassID, 17489 // GIR_Coverage, 20110, 17490 GIR_Done, 17491 // Label 1284: @40410 17492 GIM_Reject, 17493 // Label 1269: @40411 17494 GIM_Try, /*On fail goto*//*Label 1285*/ 40463, // Rule ID 12302 // 17495 GIM_CheckFeatures, GIFBS_HasBWI_HasVLX, 17496 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, 17497 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, 17498 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VK16RegClassID, 17499 // MIs[0] Operand 1 17500 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SGT, 17501 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 17502 GIM_CheckOpcodeIsEither, /*MI*/1, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, 17503 GIM_CheckIsBuildVectorAllZeros, /*MI*/1, 17504 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::VR128XRegClassID, 17505 GIM_CheckIsSafeToFold, /*InsnID*/1, 17506 // (setcc:{ *:[v16i1] } immAllZerosV:{ *:[v16i8] }, VR128X:{ *:[v16i8] }:$src, SETGT:{ *:[Other] }) => (VPMOVB2MZ128rr:{ *:[v16i1] } VR128X:{ *:[v16i8] }:$src) 17507 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VPMOVB2MZ128rr, 17508 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 17509 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src 17510 GIR_EraseFromParent, /*InsnID*/0, 17511 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 17512 // GIR_Coverage, 12302, 17513 GIR_Done, 17514 // Label 1285: @40463 17515 GIM_Try, /*On fail goto*//*Label 1286*/ 40515, // Rule ID 12304 // 17516 GIM_CheckFeatures, GIFBS_HasBWI_HasVLX, 17517 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s16, 17518 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s16, 17519 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VK16RegClassID, 17520 // MIs[0] Operand 1 17521 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SGT, 17522 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 17523 GIM_CheckOpcodeIsEither, /*MI*/1, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, 17524 GIM_CheckIsBuildVectorAllZeros, /*MI*/1, 17525 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::VR256XRegClassID, 17526 GIM_CheckIsSafeToFold, /*InsnID*/1, 17527 // (setcc:{ *:[v16i1] } immAllZerosV:{ *:[v16i16] }, VR256X:{ *:[v16i16] }:$src, SETGT:{ *:[Other] }) => (VPMOVW2MZ256rr:{ *:[v16i1] } VR256X:{ *:[v16i16] }:$src) 17528 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VPMOVW2MZ256rr, 17529 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 17530 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src 17531 GIR_EraseFromParent, /*InsnID*/0, 17532 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 17533 // GIR_Coverage, 12304, 17534 GIR_Done, 17535 // Label 1286: @40515 17536 GIM_Try, /*On fail goto*//*Label 1287*/ 40567, // Rule ID 12306 // 17537 GIM_CheckFeatures, GIFBS_HasDQI, 17538 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s32, 17539 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s32, 17540 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VK16RegClassID, 17541 // MIs[0] Operand 1 17542 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SGT, 17543 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 17544 GIM_CheckOpcodeIsEither, /*MI*/1, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, 17545 GIM_CheckIsBuildVectorAllZeros, /*MI*/1, 17546 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::VR512RegClassID, 17547 GIM_CheckIsSafeToFold, /*InsnID*/1, 17548 // (setcc:{ *:[v16i1] } immAllZerosV:{ *:[v16i32] }, VR512:{ *:[v16i32] }:$src, SETGT:{ *:[Other] }) => (VPMOVD2MZrr:{ *:[v16i1] } VR512:{ *:[v16i32] }:$src) 17549 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VPMOVD2MZrr, 17550 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 17551 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src 17552 GIR_EraseFromParent, /*InsnID*/0, 17553 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 17554 // GIR_Coverage, 12306, 17555 GIR_Done, 17556 // Label 1287: @40567 17557 GIM_Try, /*On fail goto*//*Label 1288*/ 40682, // Rule ID 20107 // 17558 GIM_CheckFeatures, GIFBS_HasBWI_NoVLX, 17559 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, 17560 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, 17561 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VK16RegClassID, 17562 // MIs[0] Operand 1 17563 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SGT, 17564 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 17565 GIM_CheckOpcodeIsEither, /*MI*/1, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, 17566 GIM_CheckIsBuildVectorAllZeros, /*MI*/1, 17567 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::VR128XRegClassID, 17568 GIM_CheckIsSafeToFold, /*InsnID*/1, 17569 // (setcc:{ *:[v16i1] } immAllZerosV:{ *:[v16i8] }, VR128X:{ *:[v16i8] }:$src, SETGT:{ *:[Other] }) => (COPY_TO_REGCLASS:{ *:[v16i1] } (VPMOVB2MZrr:{ *:[v64i1] } (INSERT_SUBREG:{ *:[v64i8] } (IMPLICIT_DEF:{ *:[v64i8] }), VR128X:{ *:[v16i8] }:$src, sub_xmm:{ *:[i32] })), VK16:{ *:[i32] }) 17570 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v64s1, 17571 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v64s8, 17572 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v64s8, 17573 GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::IMPLICIT_DEF, 17574 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, 17575 GIR_ConstrainSelectedInstOperands, /*InsnID*/3, 17576 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::INSERT_SUBREG, 17577 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 17578 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/2, /*TempRegFlags*/0, 17579 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // src 17580 GIR_AddImm, /*InsnID*/2, /*Imm*/9, 17581 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, X86::VR512RegClassID, 17582 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, X86::VR512RegClassID, 17583 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, X86::VR128XRegClassID, 17584 GIR_BuildMI, /*InsnID*/1, /*Opcode*/X86::VPMOVB2MZrr, 17585 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 17586 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, 17587 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 17588 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 17589 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 17590 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 17591 GIR_EraseFromParent, /*InsnID*/0, 17592 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, X86::VK16RegClassID, 17593 // GIR_Coverage, 20107, 17594 GIR_Done, 17595 // Label 1288: @40682 17596 GIM_Try, /*On fail goto*//*Label 1289*/ 40797, // Rule ID 20108 // 17597 GIM_CheckFeatures, GIFBS_HasBWI_NoVLX, 17598 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s16, 17599 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s16, 17600 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VK16RegClassID, 17601 // MIs[0] Operand 1 17602 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SGT, 17603 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 17604 GIM_CheckOpcodeIsEither, /*MI*/1, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, 17605 GIM_CheckIsBuildVectorAllZeros, /*MI*/1, 17606 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::VR256XRegClassID, 17607 GIM_CheckIsSafeToFold, /*InsnID*/1, 17608 // (setcc:{ *:[v16i1] } immAllZerosV:{ *:[v16i16] }, VR256X:{ *:[v16i16] }:$src, SETGT:{ *:[Other] }) => (COPY_TO_REGCLASS:{ *:[v16i1] } (VPMOVW2MZrr:{ *:[v32i1] } (INSERT_SUBREG:{ *:[v32i16] } (IMPLICIT_DEF:{ *:[v32i16] }), VR256X:{ *:[v16i16] }:$src, sub_ymm:{ *:[i32] })), VK16:{ *:[i32] }) 17609 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v32s1, 17610 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v32s16, 17611 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v32s16, 17612 GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::IMPLICIT_DEF, 17613 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, 17614 GIR_ConstrainSelectedInstOperands, /*InsnID*/3, 17615 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::INSERT_SUBREG, 17616 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 17617 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/2, /*TempRegFlags*/0, 17618 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // src 17619 GIR_AddImm, /*InsnID*/2, /*Imm*/10, 17620 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, X86::VR512RegClassID, 17621 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, X86::VR512RegClassID, 17622 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, X86::VR256XRegClassID, 17623 GIR_BuildMI, /*InsnID*/1, /*Opcode*/X86::VPMOVW2MZrr, 17624 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 17625 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, 17626 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 17627 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 17628 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 17629 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 17630 GIR_EraseFromParent, /*InsnID*/0, 17631 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, X86::VK16RegClassID, 17632 // GIR_Coverage, 20108, 17633 GIR_Done, 17634 // Label 1289: @40797 17635 GIM_Reject, 17636 // Label 1270: @40798 17637 GIM_Try, /*On fail goto*//*Label 1290*/ 40850, // Rule ID 12301 // 17638 GIM_CheckFeatures, GIFBS_HasBWI_HasVLX, 17639 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v32s8, 17640 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v32s8, 17641 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VK32RegClassID, 17642 // MIs[0] Operand 1 17643 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SGT, 17644 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 17645 GIM_CheckOpcodeIsEither, /*MI*/1, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, 17646 GIM_CheckIsBuildVectorAllZeros, /*MI*/1, 17647 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::VR256XRegClassID, 17648 GIM_CheckIsSafeToFold, /*InsnID*/1, 17649 // (setcc:{ *:[v32i1] } immAllZerosV:{ *:[v32i8] }, VR256X:{ *:[v32i8] }:$src, SETGT:{ *:[Other] }) => (VPMOVB2MZ256rr:{ *:[v32i1] } VR256X:{ *:[v32i8] }:$src) 17650 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VPMOVB2MZ256rr, 17651 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 17652 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src 17653 GIR_EraseFromParent, /*InsnID*/0, 17654 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 17655 // GIR_Coverage, 12301, 17656 GIR_Done, 17657 // Label 1290: @40850 17658 GIM_Try, /*On fail goto*//*Label 1291*/ 40902, // Rule ID 12303 // 17659 GIM_CheckFeatures, GIFBS_HasBWI, 17660 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v32s16, 17661 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v32s16, 17662 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VK32RegClassID, 17663 // MIs[0] Operand 1 17664 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SGT, 17665 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 17666 GIM_CheckOpcodeIsEither, /*MI*/1, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, 17667 GIM_CheckIsBuildVectorAllZeros, /*MI*/1, 17668 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::VR512RegClassID, 17669 GIM_CheckIsSafeToFold, /*InsnID*/1, 17670 // (setcc:{ *:[v32i1] } immAllZerosV:{ *:[v32i16] }, VR512:{ *:[v32i16] }:$src, SETGT:{ *:[Other] }) => (VPMOVW2MZrr:{ *:[v32i1] } VR512:{ *:[v32i16] }:$src) 17671 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VPMOVW2MZrr, 17672 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 17673 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src 17674 GIR_EraseFromParent, /*InsnID*/0, 17675 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 17676 // GIR_Coverage, 12303, 17677 GIR_Done, 17678 // Label 1291: @40902 17679 GIM_Try, /*On fail goto*//*Label 1292*/ 41017, // Rule ID 20106 // 17680 GIM_CheckFeatures, GIFBS_HasBWI_NoVLX, 17681 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v32s8, 17682 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v32s8, 17683 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VK32RegClassID, 17684 // MIs[0] Operand 1 17685 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SGT, 17686 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 17687 GIM_CheckOpcodeIsEither, /*MI*/1, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, 17688 GIM_CheckIsBuildVectorAllZeros, /*MI*/1, 17689 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::VR256XRegClassID, 17690 GIM_CheckIsSafeToFold, /*InsnID*/1, 17691 // (setcc:{ *:[v32i1] } immAllZerosV:{ *:[v32i8] }, VR256X:{ *:[v32i8] }:$src, SETGT:{ *:[Other] }) => (COPY_TO_REGCLASS:{ *:[v32i1] } (VPMOVB2MZrr:{ *:[v64i1] } (INSERT_SUBREG:{ *:[v64i8] } (IMPLICIT_DEF:{ *:[v64i8] }), VR256X:{ *:[v32i8] }:$src, sub_ymm:{ *:[i32] })), VK32:{ *:[i32] }) 17692 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v64s1, 17693 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v64s8, 17694 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v64s8, 17695 GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::IMPLICIT_DEF, 17696 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, 17697 GIR_ConstrainSelectedInstOperands, /*InsnID*/3, 17698 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::INSERT_SUBREG, 17699 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 17700 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/2, /*TempRegFlags*/0, 17701 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // src 17702 GIR_AddImm, /*InsnID*/2, /*Imm*/10, 17703 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, X86::VR512RegClassID, 17704 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, X86::VR512RegClassID, 17705 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, X86::VR256XRegClassID, 17706 GIR_BuildMI, /*InsnID*/1, /*Opcode*/X86::VPMOVB2MZrr, 17707 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 17708 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, 17709 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 17710 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 17711 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 17712 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 17713 GIR_EraseFromParent, /*InsnID*/0, 17714 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, X86::VK32RegClassID, 17715 // GIR_Coverage, 20106, 17716 GIR_Done, 17717 // Label 1292: @41017 17718 GIM_Reject, 17719 // Label 1271: @41018 17720 GIM_Try, /*On fail goto*//*Label 1293*/ 41070, // Rule ID 12300 // 17721 GIM_CheckFeatures, GIFBS_HasBWI, 17722 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v64s8, 17723 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v64s8, 17724 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VK64RegClassID, 17725 // MIs[0] Operand 1 17726 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SGT, 17727 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 17728 GIM_CheckOpcodeIsEither, /*MI*/1, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, 17729 GIM_CheckIsBuildVectorAllZeros, /*MI*/1, 17730 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::VR512RegClassID, 17731 GIM_CheckIsSafeToFold, /*InsnID*/1, 17732 // (setcc:{ *:[v64i1] } immAllZerosV:{ *:[v64i8] }, VR512:{ *:[v64i8] }:$src, SETGT:{ *:[Other] }) => (VPMOVB2MZrr:{ *:[v64i1] } VR512:{ *:[v64i8] }:$src) 17733 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VPMOVB2MZrr, 17734 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 17735 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src 17736 GIR_EraseFromParent, /*InsnID*/0, 17737 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 17738 // GIR_Coverage, 12300, 17739 GIR_Done, 17740 // Label 1293: @41070 17741 GIM_Reject, 17742 // Label 1272: @41071 17743 GIM_Reject, 17744 // Label 25: @41072 17745 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/13, 23, /*)*//*default:*//*Label 1297*/ 41259, 17746 /*GILLT_v8s16*//*Label 1294*/ 41088, 0, 0, 0, 0, 17747 /*GILLT_v16s16*//*Label 1295*/ 41169, 0, 0, 0, 17748 /*GILLT_v32s16*//*Label 1296*/ 41227, 17749 // Label 1294: @41088 17750 GIM_Try, /*On fail goto*//*Label 1298*/ 41168, 17751 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, 17752 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 17753 GIM_Try, /*On fail goto*//*Label 1299*/ 41121, // Rule ID 2268 // 17754 GIM_CheckFeatures, GIFBS_HasAVX_NoVLX_Or_NoBWI, 17755 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 17756 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 17757 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 17758 // (mulhu:{ *:[v8i16] } VR128:{ *:[v8i16] }:$src1, VR128:{ *:[v8i16] }:$src2) => (VPMULHUWrr:{ *:[v8i16] } VR128:{ *:[v8i16] }:$src1, VR128:{ *:[v8i16] }:$src2) 17759 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMULHUWrr, 17760 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 17761 // GIR_Coverage, 2268, 17762 GIR_Done, 17763 // Label 1299: @41121 17764 GIM_Try, /*On fail goto*//*Label 1300*/ 41144, // Rule ID 2270 // 17765 GIM_CheckFeatures, GIFBS_UseSSE2, 17766 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 17767 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 17768 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 17769 // (mulhu:{ *:[v8i16] } VR128:{ *:[v8i16] }:$src1, VR128:{ *:[v8i16] }:$src2) => (PMULHUWrr:{ *:[v8i16] } VR128:{ *:[v8i16] }:$src1, VR128:{ *:[v8i16] }:$src2) 17770 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::PMULHUWrr, 17771 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 17772 // GIR_Coverage, 2270, 17773 GIR_Done, 17774 // Label 1300: @41144 17775 GIM_Try, /*On fail goto*//*Label 1301*/ 41167, // Rule ID 4698 // 17776 GIM_CheckFeatures, GIFBS_HasBWI_HasVLX, 17777 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID, 17778 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID, 17779 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128XRegClassID, 17780 // (mulhu:{ *:[v8i16] } VR128X:{ *:[v8i16] }:$src1, VR128X:{ *:[v8i16] }:$src2) => (VPMULHUWZ128rr:{ *:[v8i16] } VR128X:{ *:[v8i16] }:$src1, VR128X:{ *:[v8i16] }:$src2) 17781 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMULHUWZ128rr, 17782 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 17783 // GIR_Coverage, 4698, 17784 GIR_Done, 17785 // Label 1301: @41167 17786 GIM_Reject, 17787 // Label 1298: @41168 17788 GIM_Reject, 17789 // Label 1295: @41169 17790 GIM_Try, /*On fail goto*//*Label 1302*/ 41226, 17791 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s16, 17792 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s16, 17793 GIM_Try, /*On fail goto*//*Label 1303*/ 41202, // Rule ID 2272 // 17794 GIM_CheckFeatures, GIFBS_HasAVX2_NoVLX_Or_NoBWI, 17795 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID, 17796 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256RegClassID, 17797 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256RegClassID, 17798 // (mulhu:{ *:[v16i16] } VR256:{ *:[v16i16] }:$src1, VR256:{ *:[v16i16] }:$src2) => (VPMULHUWYrr:{ *:[v16i16] } VR256:{ *:[v16i16] }:$src1, VR256:{ *:[v16i16] }:$src2) 17799 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMULHUWYrr, 17800 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 17801 // GIR_Coverage, 2272, 17802 GIR_Done, 17803 // Label 1303: @41202 17804 GIM_Try, /*On fail goto*//*Label 1304*/ 41225, // Rule ID 4692 // 17805 GIM_CheckFeatures, GIFBS_HasBWI_HasVLX, 17806 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID, 17807 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID, 17808 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256XRegClassID, 17809 // (mulhu:{ *:[v16i16] } VR256X:{ *:[v16i16] }:$src1, VR256X:{ *:[v16i16] }:$src2) => (VPMULHUWZ256rr:{ *:[v16i16] } VR256X:{ *:[v16i16] }:$src1, VR256X:{ *:[v16i16] }:$src2) 17810 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMULHUWZ256rr, 17811 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 17812 // GIR_Coverage, 4692, 17813 GIR_Done, 17814 // Label 1304: @41225 17815 GIM_Reject, 17816 // Label 1302: @41226 17817 GIM_Reject, 17818 // Label 1296: @41227 17819 GIM_Try, /*On fail goto*//*Label 1305*/ 41258, // Rule ID 4686 // 17820 GIM_CheckFeatures, GIFBS_HasBWI, 17821 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v32s16, 17822 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v32s16, 17823 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 17824 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR512RegClassID, 17825 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR512RegClassID, 17826 // (mulhu:{ *:[v32i16] } VR512:{ *:[v32i16] }:$src1, VR512:{ *:[v32i16] }:$src2) => (VPMULHUWZrr:{ *:[v32i16] } VR512:{ *:[v32i16] }:$src1, VR512:{ *:[v32i16] }:$src2) 17827 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMULHUWZrr, 17828 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 17829 // GIR_Coverage, 4686, 17830 GIR_Done, 17831 // Label 1305: @41258 17832 GIM_Reject, 17833 // Label 1297: @41259 17834 GIM_Reject, 17835 // Label 26: @41260 17836 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/13, 23, /*)*//*default:*//*Label 1309*/ 41447, 17837 /*GILLT_v8s16*//*Label 1306*/ 41276, 0, 0, 0, 0, 17838 /*GILLT_v16s16*//*Label 1307*/ 41357, 0, 0, 0, 17839 /*GILLT_v32s16*//*Label 1308*/ 41415, 17840 // Label 1306: @41276 17841 GIM_Try, /*On fail goto*//*Label 1310*/ 41356, 17842 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, 17843 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 17844 GIM_Try, /*On fail goto*//*Label 1311*/ 41309, // Rule ID 2274 // 17845 GIM_CheckFeatures, GIFBS_HasAVX_NoVLX_Or_NoBWI, 17846 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 17847 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 17848 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 17849 // (mulhs:{ *:[v8i16] } VR128:{ *:[v8i16] }:$src1, VR128:{ *:[v8i16] }:$src2) => (VPMULHWrr:{ *:[v8i16] } VR128:{ *:[v8i16] }:$src1, VR128:{ *:[v8i16] }:$src2) 17850 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMULHWrr, 17851 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 17852 // GIR_Coverage, 2274, 17853 GIR_Done, 17854 // Label 1311: @41309 17855 GIM_Try, /*On fail goto*//*Label 1312*/ 41332, // Rule ID 2276 // 17856 GIM_CheckFeatures, GIFBS_UseSSE2, 17857 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 17858 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 17859 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 17860 // (mulhs:{ *:[v8i16] } VR128:{ *:[v8i16] }:$src1, VR128:{ *:[v8i16] }:$src2) => (PMULHWrr:{ *:[v8i16] } VR128:{ *:[v8i16] }:$src1, VR128:{ *:[v8i16] }:$src2) 17861 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::PMULHWrr, 17862 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 17863 // GIR_Coverage, 2276, 17864 GIR_Done, 17865 // Label 1312: @41332 17866 GIM_Try, /*On fail goto*//*Label 1313*/ 41355, // Rule ID 4680 // 17867 GIM_CheckFeatures, GIFBS_HasBWI_HasVLX, 17868 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID, 17869 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID, 17870 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128XRegClassID, 17871 // (mulhs:{ *:[v8i16] } VR128X:{ *:[v8i16] }:$src1, VR128X:{ *:[v8i16] }:$src2) => (VPMULHWZ128rr:{ *:[v8i16] } VR128X:{ *:[v8i16] }:$src1, VR128X:{ *:[v8i16] }:$src2) 17872 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMULHWZ128rr, 17873 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 17874 // GIR_Coverage, 4680, 17875 GIR_Done, 17876 // Label 1313: @41355 17877 GIM_Reject, 17878 // Label 1310: @41356 17879 GIM_Reject, 17880 // Label 1307: @41357 17881 GIM_Try, /*On fail goto*//*Label 1314*/ 41414, 17882 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s16, 17883 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s16, 17884 GIM_Try, /*On fail goto*//*Label 1315*/ 41390, // Rule ID 2278 // 17885 GIM_CheckFeatures, GIFBS_HasAVX2_NoVLX_Or_NoBWI, 17886 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID, 17887 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256RegClassID, 17888 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256RegClassID, 17889 // (mulhs:{ *:[v16i16] } VR256:{ *:[v16i16] }:$src1, VR256:{ *:[v16i16] }:$src2) => (VPMULHWYrr:{ *:[v16i16] } VR256:{ *:[v16i16] }:$src1, VR256:{ *:[v16i16] }:$src2) 17890 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMULHWYrr, 17891 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 17892 // GIR_Coverage, 2278, 17893 GIR_Done, 17894 // Label 1315: @41390 17895 GIM_Try, /*On fail goto*//*Label 1316*/ 41413, // Rule ID 4674 // 17896 GIM_CheckFeatures, GIFBS_HasBWI_HasVLX, 17897 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID, 17898 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID, 17899 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256XRegClassID, 17900 // (mulhs:{ *:[v16i16] } VR256X:{ *:[v16i16] }:$src1, VR256X:{ *:[v16i16] }:$src2) => (VPMULHWZ256rr:{ *:[v16i16] } VR256X:{ *:[v16i16] }:$src1, VR256X:{ *:[v16i16] }:$src2) 17901 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMULHWZ256rr, 17902 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 17903 // GIR_Coverage, 4674, 17904 GIR_Done, 17905 // Label 1316: @41413 17906 GIM_Reject, 17907 // Label 1314: @41414 17908 GIM_Reject, 17909 // Label 1308: @41415 17910 GIM_Try, /*On fail goto*//*Label 1317*/ 41446, // Rule ID 4668 // 17911 GIM_CheckFeatures, GIFBS_HasBWI, 17912 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v32s16, 17913 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v32s16, 17914 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 17915 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR512RegClassID, 17916 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR512RegClassID, 17917 // (mulhs:{ *:[v32i16] } VR512:{ *:[v32i16] }:$src1, VR512:{ *:[v32i16] }:$src2) => (VPMULHWZrr:{ *:[v32i16] } VR512:{ *:[v32i16] }:$src1, VR512:{ *:[v32i16] }:$src2) 17918 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMULHWZrr, 17919 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 17920 // GIR_Coverage, 4668, 17921 GIR_Done, 17922 // Label 1317: @41446 17923 GIM_Reject, 17924 // Label 1309: @41447 17925 GIM_Reject, 17926 // Label 27: @41448 17927 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/13, 25, /*)*//*default:*//*Label 1324*/ 41808, 17928 /*GILLT_v8s16*//*Label 1318*/ 41466, 0, 0, 0, 17929 /*GILLT_v16s8*//*Label 1319*/ 41547, 17930 /*GILLT_v16s16*//*Label 1320*/ 41628, 0, 0, 17931 /*GILLT_v32s8*//*Label 1321*/ 41686, 17932 /*GILLT_v32s16*//*Label 1322*/ 41744, 0, 17933 /*GILLT_v64s8*//*Label 1323*/ 41776, 17934 // Label 1318: @41466 17935 GIM_Try, /*On fail goto*//*Label 1325*/ 41546, 17936 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, 17937 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 17938 GIM_Try, /*On fail goto*//*Label 1326*/ 41499, // Rule ID 2256 // 17939 GIM_CheckFeatures, GIFBS_HasAVX_NoVLX_Or_NoBWI, 17940 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 17941 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 17942 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 17943 // (uaddsat:{ *:[v8i16] } VR128:{ *:[v8i16] }:$src1, VR128:{ *:[v8i16] }:$src2) => (VPADDUSWrr:{ *:[v8i16] } VR128:{ *:[v8i16] }:$src1, VR128:{ *:[v8i16] }:$src2) 17944 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPADDUSWrr, 17945 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 17946 // GIR_Coverage, 2256, 17947 GIR_Done, 17948 // Label 1326: @41499 17949 GIM_Try, /*On fail goto*//*Label 1327*/ 41522, // Rule ID 2258 // 17950 GIM_CheckFeatures, GIFBS_UseSSE2, 17951 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 17952 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 17953 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 17954 // (uaddsat:{ *:[v8i16] } VR128:{ *:[v8i16] }:$src1, VR128:{ *:[v8i16] }:$src2) => (PADDUSWrr:{ *:[v8i16] } VR128:{ *:[v8i16] }:$src1, VR128:{ *:[v8i16] }:$src2) 17955 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::PADDUSWrr, 17956 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 17957 // GIR_Coverage, 2258, 17958 GIR_Done, 17959 // Label 1327: @41522 17960 GIM_Try, /*On fail goto*//*Label 1328*/ 41545, // Rule ID 4536 // 17961 GIM_CheckFeatures, GIFBS_HasBWI_HasVLX, 17962 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID, 17963 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID, 17964 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128XRegClassID, 17965 // (uaddsat:{ *:[v8i16] } VR128X:{ *:[v8i16] }:$src1, VR128X:{ *:[v8i16] }:$src2) => (VPADDUSWZ128rr:{ *:[v8i16] } VR128X:{ *:[v8i16] }:$src1, VR128X:{ *:[v8i16] }:$src2) 17966 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPADDUSWZ128rr, 17967 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 17968 // GIR_Coverage, 4536, 17969 GIR_Done, 17970 // Label 1328: @41545 17971 GIM_Reject, 17972 // Label 1325: @41546 17973 GIM_Reject, 17974 // Label 1319: @41547 17975 GIM_Try, /*On fail goto*//*Label 1329*/ 41627, 17976 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, 17977 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, 17978 GIM_Try, /*On fail goto*//*Label 1330*/ 41580, // Rule ID 2250 // 17979 GIM_CheckFeatures, GIFBS_HasAVX_NoVLX_Or_NoBWI, 17980 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 17981 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 17982 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 17983 // (uaddsat:{ *:[v16i8] } VR128:{ *:[v16i8] }:$src1, VR128:{ *:[v16i8] }:$src2) => (VPADDUSBrr:{ *:[v16i8] } VR128:{ *:[v16i8] }:$src1, VR128:{ *:[v16i8] }:$src2) 17984 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPADDUSBrr, 17985 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 17986 // GIR_Coverage, 2250, 17987 GIR_Done, 17988 // Label 1330: @41580 17989 GIM_Try, /*On fail goto*//*Label 1331*/ 41603, // Rule ID 2252 // 17990 GIM_CheckFeatures, GIFBS_UseSSE2, 17991 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 17992 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 17993 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 17994 // (uaddsat:{ *:[v16i8] } VR128:{ *:[v16i8] }:$src1, VR128:{ *:[v16i8] }:$src2) => (PADDUSBrr:{ *:[v16i8] } VR128:{ *:[v16i8] }:$src1, VR128:{ *:[v16i8] }:$src2) 17995 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::PADDUSBrr, 17996 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 17997 // GIR_Coverage, 2252, 17998 GIR_Done, 17999 // Label 1331: @41603 18000 GIM_Try, /*On fail goto*//*Label 1332*/ 41626, // Rule ID 4554 // 18001 GIM_CheckFeatures, GIFBS_HasBWI_HasVLX, 18002 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID, 18003 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID, 18004 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128XRegClassID, 18005 // (uaddsat:{ *:[v16i8] } VR128X:{ *:[v16i8] }:$src1, VR128X:{ *:[v16i8] }:$src2) => (VPADDUSBZ128rr:{ *:[v16i8] } VR128X:{ *:[v16i8] }:$src1, VR128X:{ *:[v16i8] }:$src2) 18006 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPADDUSBZ128rr, 18007 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 18008 // GIR_Coverage, 4554, 18009 GIR_Done, 18010 // Label 1332: @41626 18011 GIM_Reject, 18012 // Label 1329: @41627 18013 GIM_Reject, 18014 // Label 1320: @41628 18015 GIM_Try, /*On fail goto*//*Label 1333*/ 41685, 18016 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s16, 18017 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s16, 18018 GIM_Try, /*On fail goto*//*Label 1334*/ 41661, // Rule ID 2260 // 18019 GIM_CheckFeatures, GIFBS_HasAVX2_NoVLX_Or_NoBWI, 18020 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID, 18021 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256RegClassID, 18022 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256RegClassID, 18023 // (uaddsat:{ *:[v16i16] } VR256:{ *:[v16i16] }:$src1, VR256:{ *:[v16i16] }:$src2) => (VPADDUSWYrr:{ *:[v16i16] } VR256:{ *:[v16i16] }:$src1, VR256:{ *:[v16i16] }:$src2) 18024 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPADDUSWYrr, 18025 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 18026 // GIR_Coverage, 2260, 18027 GIR_Done, 18028 // Label 1334: @41661 18029 GIM_Try, /*On fail goto*//*Label 1335*/ 41684, // Rule ID 4530 // 18030 GIM_CheckFeatures, GIFBS_HasBWI_HasVLX, 18031 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID, 18032 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID, 18033 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256XRegClassID, 18034 // (uaddsat:{ *:[v16i16] } VR256X:{ *:[v16i16] }:$src1, VR256X:{ *:[v16i16] }:$src2) => (VPADDUSWZ256rr:{ *:[v16i16] } VR256X:{ *:[v16i16] }:$src1, VR256X:{ *:[v16i16] }:$src2) 18035 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPADDUSWZ256rr, 18036 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 18037 // GIR_Coverage, 4530, 18038 GIR_Done, 18039 // Label 1335: @41684 18040 GIM_Reject, 18041 // Label 1333: @41685 18042 GIM_Reject, 18043 // Label 1321: @41686 18044 GIM_Try, /*On fail goto*//*Label 1336*/ 41743, 18045 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v32s8, 18046 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v32s8, 18047 GIM_Try, /*On fail goto*//*Label 1337*/ 41719, // Rule ID 2254 // 18048 GIM_CheckFeatures, GIFBS_HasAVX2_NoVLX_Or_NoBWI, 18049 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID, 18050 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256RegClassID, 18051 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256RegClassID, 18052 // (uaddsat:{ *:[v32i8] } VR256:{ *:[v32i8] }:$src1, VR256:{ *:[v32i8] }:$src2) => (VPADDUSBYrr:{ *:[v32i8] } VR256:{ *:[v32i8] }:$src1, VR256:{ *:[v32i8] }:$src2) 18053 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPADDUSBYrr, 18054 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 18055 // GIR_Coverage, 2254, 18056 GIR_Done, 18057 // Label 1337: @41719 18058 GIM_Try, /*On fail goto*//*Label 1338*/ 41742, // Rule ID 4548 // 18059 GIM_CheckFeatures, GIFBS_HasBWI_HasVLX, 18060 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID, 18061 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID, 18062 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256XRegClassID, 18063 // (uaddsat:{ *:[v32i8] } VR256X:{ *:[v32i8] }:$src1, VR256X:{ *:[v32i8] }:$src2) => (VPADDUSBZ256rr:{ *:[v32i8] } VR256X:{ *:[v32i8] }:$src1, VR256X:{ *:[v32i8] }:$src2) 18064 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPADDUSBZ256rr, 18065 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 18066 // GIR_Coverage, 4548, 18067 GIR_Done, 18068 // Label 1338: @41742 18069 GIM_Reject, 18070 // Label 1336: @41743 18071 GIM_Reject, 18072 // Label 1322: @41744 18073 GIM_Try, /*On fail goto*//*Label 1339*/ 41775, // Rule ID 4524 // 18074 GIM_CheckFeatures, GIFBS_HasBWI, 18075 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v32s16, 18076 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v32s16, 18077 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 18078 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR512RegClassID, 18079 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR512RegClassID, 18080 // (uaddsat:{ *:[v32i16] } VR512:{ *:[v32i16] }:$src1, VR512:{ *:[v32i16] }:$src2) => (VPADDUSWZrr:{ *:[v32i16] } VR512:{ *:[v32i16] }:$src1, VR512:{ *:[v32i16] }:$src2) 18081 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPADDUSWZrr, 18082 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 18083 // GIR_Coverage, 4524, 18084 GIR_Done, 18085 // Label 1339: @41775 18086 GIM_Reject, 18087 // Label 1323: @41776 18088 GIM_Try, /*On fail goto*//*Label 1340*/ 41807, // Rule ID 4542 // 18089 GIM_CheckFeatures, GIFBS_HasBWI, 18090 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v64s8, 18091 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v64s8, 18092 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 18093 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR512RegClassID, 18094 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR512RegClassID, 18095 // (uaddsat:{ *:[v64i8] } VR512:{ *:[v64i8] }:$src1, VR512:{ *:[v64i8] }:$src2) => (VPADDUSBZrr:{ *:[v64i8] } VR512:{ *:[v64i8] }:$src1, VR512:{ *:[v64i8] }:$src2) 18096 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPADDUSBZrr, 18097 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 18098 // GIR_Coverage, 4542, 18099 GIR_Done, 18100 // Label 1340: @41807 18101 GIM_Reject, 18102 // Label 1324: @41808 18103 GIM_Reject, 18104 // Label 28: @41809 18105 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/13, 25, /*)*//*default:*//*Label 1347*/ 42169, 18106 /*GILLT_v8s16*//*Label 1341*/ 41827, 0, 0, 0, 18107 /*GILLT_v16s8*//*Label 1342*/ 41908, 18108 /*GILLT_v16s16*//*Label 1343*/ 41989, 0, 0, 18109 /*GILLT_v32s8*//*Label 1344*/ 42047, 18110 /*GILLT_v32s16*//*Label 1345*/ 42105, 0, 18111 /*GILLT_v64s8*//*Label 1346*/ 42137, 18112 // Label 1341: @41827 18113 GIM_Try, /*On fail goto*//*Label 1348*/ 41907, 18114 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, 18115 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 18116 GIM_Try, /*On fail goto*//*Label 1349*/ 41860, // Rule ID 2244 // 18117 GIM_CheckFeatures, GIFBS_HasAVX_NoVLX_Or_NoBWI, 18118 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 18119 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 18120 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 18121 // (saddsat:{ *:[v8i16] } VR128:{ *:[v8i16] }:$src1, VR128:{ *:[v8i16] }:$src2) => (VPADDSWrr:{ *:[v8i16] } VR128:{ *:[v8i16] }:$src1, VR128:{ *:[v8i16] }:$src2) 18122 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPADDSWrr, 18123 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 18124 // GIR_Coverage, 2244, 18125 GIR_Done, 18126 // Label 1349: @41860 18127 GIM_Try, /*On fail goto*//*Label 1350*/ 41883, // Rule ID 2246 // 18128 GIM_CheckFeatures, GIFBS_UseSSE2, 18129 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 18130 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 18131 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 18132 // (saddsat:{ *:[v8i16] } VR128:{ *:[v8i16] }:$src1, VR128:{ *:[v8i16] }:$src2) => (PADDSWrr:{ *:[v8i16] } VR128:{ *:[v8i16] }:$src1, VR128:{ *:[v8i16] }:$src2) 18133 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::PADDSWrr, 18134 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 18135 // GIR_Coverage, 2246, 18136 GIR_Done, 18137 // Label 1350: @41883 18138 GIM_Try, /*On fail goto*//*Label 1351*/ 41906, // Rule ID 4464 // 18139 GIM_CheckFeatures, GIFBS_HasBWI_HasVLX, 18140 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID, 18141 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID, 18142 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128XRegClassID, 18143 // (saddsat:{ *:[v8i16] } VR128X:{ *:[v8i16] }:$src1, VR128X:{ *:[v8i16] }:$src2) => (VPADDSWZ128rr:{ *:[v8i16] } VR128X:{ *:[v8i16] }:$src1, VR128X:{ *:[v8i16] }:$src2) 18144 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPADDSWZ128rr, 18145 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 18146 // GIR_Coverage, 4464, 18147 GIR_Done, 18148 // Label 1351: @41906 18149 GIM_Reject, 18150 // Label 1348: @41907 18151 GIM_Reject, 18152 // Label 1342: @41908 18153 GIM_Try, /*On fail goto*//*Label 1352*/ 41988, 18154 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, 18155 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, 18156 GIM_Try, /*On fail goto*//*Label 1353*/ 41941, // Rule ID 2238 // 18157 GIM_CheckFeatures, GIFBS_HasAVX_NoVLX_Or_NoBWI, 18158 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 18159 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 18160 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 18161 // (saddsat:{ *:[v16i8] } VR128:{ *:[v16i8] }:$src1, VR128:{ *:[v16i8] }:$src2) => (VPADDSBrr:{ *:[v16i8] } VR128:{ *:[v16i8] }:$src1, VR128:{ *:[v16i8] }:$src2) 18162 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPADDSBrr, 18163 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 18164 // GIR_Coverage, 2238, 18165 GIR_Done, 18166 // Label 1353: @41941 18167 GIM_Try, /*On fail goto*//*Label 1354*/ 41964, // Rule ID 2240 // 18168 GIM_CheckFeatures, GIFBS_UseSSE2, 18169 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 18170 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 18171 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 18172 // (saddsat:{ *:[v16i8] } VR128:{ *:[v16i8] }:$src1, VR128:{ *:[v16i8] }:$src2) => (PADDSBrr:{ *:[v16i8] } VR128:{ *:[v16i8] }:$src1, VR128:{ *:[v16i8] }:$src2) 18173 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::PADDSBrr, 18174 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 18175 // GIR_Coverage, 2240, 18176 GIR_Done, 18177 // Label 1354: @41964 18178 GIM_Try, /*On fail goto*//*Label 1355*/ 41987, // Rule ID 4482 // 18179 GIM_CheckFeatures, GIFBS_HasBWI_HasVLX, 18180 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID, 18181 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID, 18182 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128XRegClassID, 18183 // (saddsat:{ *:[v16i8] } VR128X:{ *:[v16i8] }:$src1, VR128X:{ *:[v16i8] }:$src2) => (VPADDSBZ128rr:{ *:[v16i8] } VR128X:{ *:[v16i8] }:$src1, VR128X:{ *:[v16i8] }:$src2) 18184 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPADDSBZ128rr, 18185 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 18186 // GIR_Coverage, 4482, 18187 GIR_Done, 18188 // Label 1355: @41987 18189 GIM_Reject, 18190 // Label 1352: @41988 18191 GIM_Reject, 18192 // Label 1343: @41989 18193 GIM_Try, /*On fail goto*//*Label 1356*/ 42046, 18194 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s16, 18195 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s16, 18196 GIM_Try, /*On fail goto*//*Label 1357*/ 42022, // Rule ID 2248 // 18197 GIM_CheckFeatures, GIFBS_HasAVX2_NoVLX_Or_NoBWI, 18198 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID, 18199 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256RegClassID, 18200 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256RegClassID, 18201 // (saddsat:{ *:[v16i16] } VR256:{ *:[v16i16] }:$src1, VR256:{ *:[v16i16] }:$src2) => (VPADDSWYrr:{ *:[v16i16] } VR256:{ *:[v16i16] }:$src1, VR256:{ *:[v16i16] }:$src2) 18202 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPADDSWYrr, 18203 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 18204 // GIR_Coverage, 2248, 18205 GIR_Done, 18206 // Label 1357: @42022 18207 GIM_Try, /*On fail goto*//*Label 1358*/ 42045, // Rule ID 4458 // 18208 GIM_CheckFeatures, GIFBS_HasBWI_HasVLX, 18209 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID, 18210 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID, 18211 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256XRegClassID, 18212 // (saddsat:{ *:[v16i16] } VR256X:{ *:[v16i16] }:$src1, VR256X:{ *:[v16i16] }:$src2) => (VPADDSWZ256rr:{ *:[v16i16] } VR256X:{ *:[v16i16] }:$src1, VR256X:{ *:[v16i16] }:$src2) 18213 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPADDSWZ256rr, 18214 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 18215 // GIR_Coverage, 4458, 18216 GIR_Done, 18217 // Label 1358: @42045 18218 GIM_Reject, 18219 // Label 1356: @42046 18220 GIM_Reject, 18221 // Label 1344: @42047 18222 GIM_Try, /*On fail goto*//*Label 1359*/ 42104, 18223 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v32s8, 18224 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v32s8, 18225 GIM_Try, /*On fail goto*//*Label 1360*/ 42080, // Rule ID 2242 // 18226 GIM_CheckFeatures, GIFBS_HasAVX2_NoVLX_Or_NoBWI, 18227 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID, 18228 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256RegClassID, 18229 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256RegClassID, 18230 // (saddsat:{ *:[v32i8] } VR256:{ *:[v32i8] }:$src1, VR256:{ *:[v32i8] }:$src2) => (VPADDSBYrr:{ *:[v32i8] } VR256:{ *:[v32i8] }:$src1, VR256:{ *:[v32i8] }:$src2) 18231 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPADDSBYrr, 18232 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 18233 // GIR_Coverage, 2242, 18234 GIR_Done, 18235 // Label 1360: @42080 18236 GIM_Try, /*On fail goto*//*Label 1361*/ 42103, // Rule ID 4476 // 18237 GIM_CheckFeatures, GIFBS_HasBWI_HasVLX, 18238 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID, 18239 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID, 18240 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256XRegClassID, 18241 // (saddsat:{ *:[v32i8] } VR256X:{ *:[v32i8] }:$src1, VR256X:{ *:[v32i8] }:$src2) => (VPADDSBZ256rr:{ *:[v32i8] } VR256X:{ *:[v32i8] }:$src1, VR256X:{ *:[v32i8] }:$src2) 18242 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPADDSBZ256rr, 18243 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 18244 // GIR_Coverage, 4476, 18245 GIR_Done, 18246 // Label 1361: @42103 18247 GIM_Reject, 18248 // Label 1359: @42104 18249 GIM_Reject, 18250 // Label 1345: @42105 18251 GIM_Try, /*On fail goto*//*Label 1362*/ 42136, // Rule ID 4452 // 18252 GIM_CheckFeatures, GIFBS_HasBWI, 18253 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v32s16, 18254 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v32s16, 18255 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 18256 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR512RegClassID, 18257 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR512RegClassID, 18258 // (saddsat:{ *:[v32i16] } VR512:{ *:[v32i16] }:$src1, VR512:{ *:[v32i16] }:$src2) => (VPADDSWZrr:{ *:[v32i16] } VR512:{ *:[v32i16] }:$src1, VR512:{ *:[v32i16] }:$src2) 18259 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPADDSWZrr, 18260 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 18261 // GIR_Coverage, 4452, 18262 GIR_Done, 18263 // Label 1362: @42136 18264 GIM_Reject, 18265 // Label 1346: @42137 18266 GIM_Try, /*On fail goto*//*Label 1363*/ 42168, // Rule ID 4470 // 18267 GIM_CheckFeatures, GIFBS_HasBWI, 18268 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v64s8, 18269 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v64s8, 18270 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 18271 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR512RegClassID, 18272 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR512RegClassID, 18273 // (saddsat:{ *:[v64i8] } VR512:{ *:[v64i8] }:$src1, VR512:{ *:[v64i8] }:$src2) => (VPADDSBZrr:{ *:[v64i8] } VR512:{ *:[v64i8] }:$src1, VR512:{ *:[v64i8] }:$src2) 18274 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPADDSBZrr, 18275 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 18276 // GIR_Coverage, 4470, 18277 GIR_Done, 18278 // Label 1363: @42168 18279 GIM_Reject, 18280 // Label 1347: @42169 18281 GIM_Reject, 18282 // Label 29: @42170 18283 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/13, 25, /*)*//*default:*//*Label 1370*/ 42530, 18284 /*GILLT_v8s16*//*Label 1364*/ 42188, 0, 0, 0, 18285 /*GILLT_v16s8*//*Label 1365*/ 42269, 18286 /*GILLT_v16s16*//*Label 1366*/ 42350, 0, 0, 18287 /*GILLT_v32s8*//*Label 1367*/ 42408, 18288 /*GILLT_v32s16*//*Label 1368*/ 42466, 0, 18289 /*GILLT_v64s8*//*Label 1369*/ 42498, 18290 // Label 1364: @42188 18291 GIM_Try, /*On fail goto*//*Label 1371*/ 42268, 18292 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, 18293 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 18294 GIM_Try, /*On fail goto*//*Label 1372*/ 42221, // Rule ID 2322 // 18295 GIM_CheckFeatures, GIFBS_HasAVX_NoVLX_Or_NoBWI, 18296 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 18297 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 18298 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 18299 // (usubsat:{ *:[v8i16] } VR128:{ *:[v8i16] }:$src1, VR128:{ *:[v8i16] }:$src2) => (VPSUBUSWrr:{ *:[v8i16] } VR128:{ *:[v8i16] }:$src1, VR128:{ *:[v8i16] }:$src2) 18300 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPSUBUSWrr, 18301 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 18302 // GIR_Coverage, 2322, 18303 GIR_Done, 18304 // Label 1372: @42221 18305 GIM_Try, /*On fail goto*//*Label 1373*/ 42244, // Rule ID 2324 // 18306 GIM_CheckFeatures, GIFBS_UseSSE2, 18307 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 18308 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 18309 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 18310 // (usubsat:{ *:[v8i16] } VR128:{ *:[v8i16] }:$src1, VR128:{ *:[v8i16] }:$src2) => (PSUBUSWrr:{ *:[v8i16] } VR128:{ *:[v8i16] }:$src1, VR128:{ *:[v8i16] }:$src2) 18311 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::PSUBUSWrr, 18312 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 18313 // GIR_Coverage, 2324, 18314 GIR_Done, 18315 // Label 1373: @42244 18316 GIM_Try, /*On fail goto*//*Label 1374*/ 42267, // Rule ID 4572 // 18317 GIM_CheckFeatures, GIFBS_HasBWI_HasVLX, 18318 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID, 18319 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID, 18320 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128XRegClassID, 18321 // (usubsat:{ *:[v8i16] } VR128X:{ *:[v8i16] }:$src1, VR128X:{ *:[v8i16] }:$src2) => (VPSUBUSWZ128rr:{ *:[v8i16] } VR128X:{ *:[v8i16] }:$src1, VR128X:{ *:[v8i16] }:$src2) 18322 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPSUBUSWZ128rr, 18323 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 18324 // GIR_Coverage, 4572, 18325 GIR_Done, 18326 // Label 1374: @42267 18327 GIM_Reject, 18328 // Label 1371: @42268 18329 GIM_Reject, 18330 // Label 1365: @42269 18331 GIM_Try, /*On fail goto*//*Label 1375*/ 42349, 18332 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, 18333 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, 18334 GIM_Try, /*On fail goto*//*Label 1376*/ 42302, // Rule ID 2316 // 18335 GIM_CheckFeatures, GIFBS_HasAVX_NoVLX_Or_NoBWI, 18336 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 18337 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 18338 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 18339 // (usubsat:{ *:[v16i8] } VR128:{ *:[v16i8] }:$src1, VR128:{ *:[v16i8] }:$src2) => (VPSUBUSBrr:{ *:[v16i8] } VR128:{ *:[v16i8] }:$src1, VR128:{ *:[v16i8] }:$src2) 18340 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPSUBUSBrr, 18341 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 18342 // GIR_Coverage, 2316, 18343 GIR_Done, 18344 // Label 1376: @42302 18345 GIM_Try, /*On fail goto*//*Label 1377*/ 42325, // Rule ID 2318 // 18346 GIM_CheckFeatures, GIFBS_UseSSE2, 18347 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 18348 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 18349 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 18350 // (usubsat:{ *:[v16i8] } VR128:{ *:[v16i8] }:$src1, VR128:{ *:[v16i8] }:$src2) => (PSUBUSBrr:{ *:[v16i8] } VR128:{ *:[v16i8] }:$src1, VR128:{ *:[v16i8] }:$src2) 18351 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::PSUBUSBrr, 18352 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 18353 // GIR_Coverage, 2318, 18354 GIR_Done, 18355 // Label 1377: @42325 18356 GIM_Try, /*On fail goto*//*Label 1378*/ 42348, // Rule ID 4590 // 18357 GIM_CheckFeatures, GIFBS_HasBWI_HasVLX, 18358 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID, 18359 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID, 18360 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128XRegClassID, 18361 // (usubsat:{ *:[v16i8] } VR128X:{ *:[v16i8] }:$src1, VR128X:{ *:[v16i8] }:$src2) => (VPSUBUSBZ128rr:{ *:[v16i8] } VR128X:{ *:[v16i8] }:$src1, VR128X:{ *:[v16i8] }:$src2) 18362 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPSUBUSBZ128rr, 18363 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 18364 // GIR_Coverage, 4590, 18365 GIR_Done, 18366 // Label 1378: @42348 18367 GIM_Reject, 18368 // Label 1375: @42349 18369 GIM_Reject, 18370 // Label 1366: @42350 18371 GIM_Try, /*On fail goto*//*Label 1379*/ 42407, 18372 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s16, 18373 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s16, 18374 GIM_Try, /*On fail goto*//*Label 1380*/ 42383, // Rule ID 2326 // 18375 GIM_CheckFeatures, GIFBS_HasAVX2_NoVLX_Or_NoBWI, 18376 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID, 18377 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256RegClassID, 18378 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256RegClassID, 18379 // (usubsat:{ *:[v16i16] } VR256:{ *:[v16i16] }:$src1, VR256:{ *:[v16i16] }:$src2) => (VPSUBUSWYrr:{ *:[v16i16] } VR256:{ *:[v16i16] }:$src1, VR256:{ *:[v16i16] }:$src2) 18380 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPSUBUSWYrr, 18381 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 18382 // GIR_Coverage, 2326, 18383 GIR_Done, 18384 // Label 1380: @42383 18385 GIM_Try, /*On fail goto*//*Label 1381*/ 42406, // Rule ID 4566 // 18386 GIM_CheckFeatures, GIFBS_HasBWI_HasVLX, 18387 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID, 18388 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID, 18389 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256XRegClassID, 18390 // (usubsat:{ *:[v16i16] } VR256X:{ *:[v16i16] }:$src1, VR256X:{ *:[v16i16] }:$src2) => (VPSUBUSWZ256rr:{ *:[v16i16] } VR256X:{ *:[v16i16] }:$src1, VR256X:{ *:[v16i16] }:$src2) 18391 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPSUBUSWZ256rr, 18392 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 18393 // GIR_Coverage, 4566, 18394 GIR_Done, 18395 // Label 1381: @42406 18396 GIM_Reject, 18397 // Label 1379: @42407 18398 GIM_Reject, 18399 // Label 1367: @42408 18400 GIM_Try, /*On fail goto*//*Label 1382*/ 42465, 18401 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v32s8, 18402 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v32s8, 18403 GIM_Try, /*On fail goto*//*Label 1383*/ 42441, // Rule ID 2320 // 18404 GIM_CheckFeatures, GIFBS_HasAVX2_NoVLX_Or_NoBWI, 18405 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID, 18406 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256RegClassID, 18407 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256RegClassID, 18408 // (usubsat:{ *:[v32i8] } VR256:{ *:[v32i8] }:$src1, VR256:{ *:[v32i8] }:$src2) => (VPSUBUSBYrr:{ *:[v32i8] } VR256:{ *:[v32i8] }:$src1, VR256:{ *:[v32i8] }:$src2) 18409 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPSUBUSBYrr, 18410 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 18411 // GIR_Coverage, 2320, 18412 GIR_Done, 18413 // Label 1383: @42441 18414 GIM_Try, /*On fail goto*//*Label 1384*/ 42464, // Rule ID 4584 // 18415 GIM_CheckFeatures, GIFBS_HasBWI_HasVLX, 18416 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID, 18417 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID, 18418 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256XRegClassID, 18419 // (usubsat:{ *:[v32i8] } VR256X:{ *:[v32i8] }:$src1, VR256X:{ *:[v32i8] }:$src2) => (VPSUBUSBZ256rr:{ *:[v32i8] } VR256X:{ *:[v32i8] }:$src1, VR256X:{ *:[v32i8] }:$src2) 18420 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPSUBUSBZ256rr, 18421 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 18422 // GIR_Coverage, 4584, 18423 GIR_Done, 18424 // Label 1384: @42464 18425 GIM_Reject, 18426 // Label 1382: @42465 18427 GIM_Reject, 18428 // Label 1368: @42466 18429 GIM_Try, /*On fail goto*//*Label 1385*/ 42497, // Rule ID 4560 // 18430 GIM_CheckFeatures, GIFBS_HasBWI, 18431 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v32s16, 18432 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v32s16, 18433 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 18434 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR512RegClassID, 18435 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR512RegClassID, 18436 // (usubsat:{ *:[v32i16] } VR512:{ *:[v32i16] }:$src1, VR512:{ *:[v32i16] }:$src2) => (VPSUBUSWZrr:{ *:[v32i16] } VR512:{ *:[v32i16] }:$src1, VR512:{ *:[v32i16] }:$src2) 18437 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPSUBUSWZrr, 18438 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 18439 // GIR_Coverage, 4560, 18440 GIR_Done, 18441 // Label 1385: @42497 18442 GIM_Reject, 18443 // Label 1369: @42498 18444 GIM_Try, /*On fail goto*//*Label 1386*/ 42529, // Rule ID 4578 // 18445 GIM_CheckFeatures, GIFBS_HasBWI, 18446 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v64s8, 18447 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v64s8, 18448 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 18449 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR512RegClassID, 18450 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR512RegClassID, 18451 // (usubsat:{ *:[v64i8] } VR512:{ *:[v64i8] }:$src1, VR512:{ *:[v64i8] }:$src2) => (VPSUBUSBZrr:{ *:[v64i8] } VR512:{ *:[v64i8] }:$src1, VR512:{ *:[v64i8] }:$src2) 18452 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPSUBUSBZrr, 18453 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 18454 // GIR_Coverage, 4578, 18455 GIR_Done, 18456 // Label 1386: @42529 18457 GIM_Reject, 18458 // Label 1370: @42530 18459 GIM_Reject, 18460 // Label 30: @42531 18461 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/13, 25, /*)*//*default:*//*Label 1393*/ 42891, 18462 /*GILLT_v8s16*//*Label 1387*/ 42549, 0, 0, 0, 18463 /*GILLT_v16s8*//*Label 1388*/ 42630, 18464 /*GILLT_v16s16*//*Label 1389*/ 42711, 0, 0, 18465 /*GILLT_v32s8*//*Label 1390*/ 42769, 18466 /*GILLT_v32s16*//*Label 1391*/ 42827, 0, 18467 /*GILLT_v64s8*//*Label 1392*/ 42859, 18468 // Label 1387: @42549 18469 GIM_Try, /*On fail goto*//*Label 1394*/ 42629, 18470 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, 18471 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 18472 GIM_Try, /*On fail goto*//*Label 1395*/ 42582, // Rule ID 2310 // 18473 GIM_CheckFeatures, GIFBS_HasAVX_NoVLX_Or_NoBWI, 18474 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 18475 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 18476 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 18477 // (ssubsat:{ *:[v8i16] } VR128:{ *:[v8i16] }:$src1, VR128:{ *:[v8i16] }:$src2) => (VPSUBSWrr:{ *:[v8i16] } VR128:{ *:[v8i16] }:$src1, VR128:{ *:[v8i16] }:$src2) 18478 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPSUBSWrr, 18479 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 18480 // GIR_Coverage, 2310, 18481 GIR_Done, 18482 // Label 1395: @42582 18483 GIM_Try, /*On fail goto*//*Label 1396*/ 42605, // Rule ID 2312 // 18484 GIM_CheckFeatures, GIFBS_UseSSE2, 18485 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 18486 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 18487 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 18488 // (ssubsat:{ *:[v8i16] } VR128:{ *:[v8i16] }:$src1, VR128:{ *:[v8i16] }:$src2) => (PSUBSWrr:{ *:[v8i16] } VR128:{ *:[v8i16] }:$src1, VR128:{ *:[v8i16] }:$src2) 18489 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::PSUBSWrr, 18490 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 18491 // GIR_Coverage, 2312, 18492 GIR_Done, 18493 // Label 1396: @42605 18494 GIM_Try, /*On fail goto*//*Label 1397*/ 42628, // Rule ID 4500 // 18495 GIM_CheckFeatures, GIFBS_HasBWI_HasVLX, 18496 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID, 18497 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID, 18498 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128XRegClassID, 18499 // (ssubsat:{ *:[v8i16] } VR128X:{ *:[v8i16] }:$src1, VR128X:{ *:[v8i16] }:$src2) => (VPSUBSWZ128rr:{ *:[v8i16] } VR128X:{ *:[v8i16] }:$src1, VR128X:{ *:[v8i16] }:$src2) 18500 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPSUBSWZ128rr, 18501 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 18502 // GIR_Coverage, 4500, 18503 GIR_Done, 18504 // Label 1397: @42628 18505 GIM_Reject, 18506 // Label 1394: @42629 18507 GIM_Reject, 18508 // Label 1388: @42630 18509 GIM_Try, /*On fail goto*//*Label 1398*/ 42710, 18510 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, 18511 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, 18512 GIM_Try, /*On fail goto*//*Label 1399*/ 42663, // Rule ID 2304 // 18513 GIM_CheckFeatures, GIFBS_HasAVX_NoVLX_Or_NoBWI, 18514 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 18515 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 18516 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 18517 // (ssubsat:{ *:[v16i8] } VR128:{ *:[v16i8] }:$src1, VR128:{ *:[v16i8] }:$src2) => (VPSUBSBrr:{ *:[v16i8] } VR128:{ *:[v16i8] }:$src1, VR128:{ *:[v16i8] }:$src2) 18518 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPSUBSBrr, 18519 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 18520 // GIR_Coverage, 2304, 18521 GIR_Done, 18522 // Label 1399: @42663 18523 GIM_Try, /*On fail goto*//*Label 1400*/ 42686, // Rule ID 2306 // 18524 GIM_CheckFeatures, GIFBS_UseSSE2, 18525 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 18526 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 18527 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 18528 // (ssubsat:{ *:[v16i8] } VR128:{ *:[v16i8] }:$src1, VR128:{ *:[v16i8] }:$src2) => (PSUBSBrr:{ *:[v16i8] } VR128:{ *:[v16i8] }:$src1, VR128:{ *:[v16i8] }:$src2) 18529 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::PSUBSBrr, 18530 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 18531 // GIR_Coverage, 2306, 18532 GIR_Done, 18533 // Label 1400: @42686 18534 GIM_Try, /*On fail goto*//*Label 1401*/ 42709, // Rule ID 4518 // 18535 GIM_CheckFeatures, GIFBS_HasBWI_HasVLX, 18536 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID, 18537 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID, 18538 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128XRegClassID, 18539 // (ssubsat:{ *:[v16i8] } VR128X:{ *:[v16i8] }:$src1, VR128X:{ *:[v16i8] }:$src2) => (VPSUBSBZ128rr:{ *:[v16i8] } VR128X:{ *:[v16i8] }:$src1, VR128X:{ *:[v16i8] }:$src2) 18540 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPSUBSBZ128rr, 18541 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 18542 // GIR_Coverage, 4518, 18543 GIR_Done, 18544 // Label 1401: @42709 18545 GIM_Reject, 18546 // Label 1398: @42710 18547 GIM_Reject, 18548 // Label 1389: @42711 18549 GIM_Try, /*On fail goto*//*Label 1402*/ 42768, 18550 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s16, 18551 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s16, 18552 GIM_Try, /*On fail goto*//*Label 1403*/ 42744, // Rule ID 2314 // 18553 GIM_CheckFeatures, GIFBS_HasAVX2_NoVLX_Or_NoBWI, 18554 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID, 18555 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256RegClassID, 18556 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256RegClassID, 18557 // (ssubsat:{ *:[v16i16] } VR256:{ *:[v16i16] }:$src1, VR256:{ *:[v16i16] }:$src2) => (VPSUBSWYrr:{ *:[v16i16] } VR256:{ *:[v16i16] }:$src1, VR256:{ *:[v16i16] }:$src2) 18558 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPSUBSWYrr, 18559 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 18560 // GIR_Coverage, 2314, 18561 GIR_Done, 18562 // Label 1403: @42744 18563 GIM_Try, /*On fail goto*//*Label 1404*/ 42767, // Rule ID 4494 // 18564 GIM_CheckFeatures, GIFBS_HasBWI_HasVLX, 18565 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID, 18566 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID, 18567 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256XRegClassID, 18568 // (ssubsat:{ *:[v16i16] } VR256X:{ *:[v16i16] }:$src1, VR256X:{ *:[v16i16] }:$src2) => (VPSUBSWZ256rr:{ *:[v16i16] } VR256X:{ *:[v16i16] }:$src1, VR256X:{ *:[v16i16] }:$src2) 18569 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPSUBSWZ256rr, 18570 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 18571 // GIR_Coverage, 4494, 18572 GIR_Done, 18573 // Label 1404: @42767 18574 GIM_Reject, 18575 // Label 1402: @42768 18576 GIM_Reject, 18577 // Label 1390: @42769 18578 GIM_Try, /*On fail goto*//*Label 1405*/ 42826, 18579 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v32s8, 18580 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v32s8, 18581 GIM_Try, /*On fail goto*//*Label 1406*/ 42802, // Rule ID 2308 // 18582 GIM_CheckFeatures, GIFBS_HasAVX2_NoVLX_Or_NoBWI, 18583 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID, 18584 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256RegClassID, 18585 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256RegClassID, 18586 // (ssubsat:{ *:[v32i8] } VR256:{ *:[v32i8] }:$src1, VR256:{ *:[v32i8] }:$src2) => (VPSUBSBYrr:{ *:[v32i8] } VR256:{ *:[v32i8] }:$src1, VR256:{ *:[v32i8] }:$src2) 18587 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPSUBSBYrr, 18588 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 18589 // GIR_Coverage, 2308, 18590 GIR_Done, 18591 // Label 1406: @42802 18592 GIM_Try, /*On fail goto*//*Label 1407*/ 42825, // Rule ID 4512 // 18593 GIM_CheckFeatures, GIFBS_HasBWI_HasVLX, 18594 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID, 18595 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID, 18596 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256XRegClassID, 18597 // (ssubsat:{ *:[v32i8] } VR256X:{ *:[v32i8] }:$src1, VR256X:{ *:[v32i8] }:$src2) => (VPSUBSBZ256rr:{ *:[v32i8] } VR256X:{ *:[v32i8] }:$src1, VR256X:{ *:[v32i8] }:$src2) 18598 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPSUBSBZ256rr, 18599 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 18600 // GIR_Coverage, 4512, 18601 GIR_Done, 18602 // Label 1407: @42825 18603 GIM_Reject, 18604 // Label 1405: @42826 18605 GIM_Reject, 18606 // Label 1391: @42827 18607 GIM_Try, /*On fail goto*//*Label 1408*/ 42858, // Rule ID 4488 // 18608 GIM_CheckFeatures, GIFBS_HasBWI, 18609 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v32s16, 18610 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v32s16, 18611 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 18612 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR512RegClassID, 18613 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR512RegClassID, 18614 // (ssubsat:{ *:[v32i16] } VR512:{ *:[v32i16] }:$src1, VR512:{ *:[v32i16] }:$src2) => (VPSUBSWZrr:{ *:[v32i16] } VR512:{ *:[v32i16] }:$src1, VR512:{ *:[v32i16] }:$src2) 18615 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPSUBSWZrr, 18616 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 18617 // GIR_Coverage, 4488, 18618 GIR_Done, 18619 // Label 1408: @42858 18620 GIM_Reject, 18621 // Label 1392: @42859 18622 GIM_Try, /*On fail goto*//*Label 1409*/ 42890, // Rule ID 4506 // 18623 GIM_CheckFeatures, GIFBS_HasBWI, 18624 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v64s8, 18625 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v64s8, 18626 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 18627 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR512RegClassID, 18628 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR512RegClassID, 18629 // (ssubsat:{ *:[v64i8] } VR512:{ *:[v64i8] }:$src1, VR512:{ *:[v64i8] }:$src2) => (VPSUBSBZrr:{ *:[v64i8] } VR512:{ *:[v64i8] }:$src1, VR512:{ *:[v64i8] }:$src2) 18630 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPSUBSBZrr, 18631 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 18632 // GIR_Coverage, 4506, 18633 GIR_Done, 18634 // Label 1409: @42890 18635 GIM_Reject, 18636 // Label 1393: @42891 18637 GIM_Reject, 18638 // Label 31: @42892 18639 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/2, 23, /*)*//*default:*//*Label 1423*/ 43713, 18640 /*GILLT_s16*//*Label 1410*/ 42919, 18641 /*GILLT_s32*//*Label 1411*/ 42954, 18642 /*GILLT_s64*//*Label 1412*/ 43073, 18643 /*GILLT_s80*//*Label 1413*/ 43192, 0, 0, 18644 /*GILLT_v2s64*//*Label 1414*/ 43230, 0, 18645 /*GILLT_v4s32*//*Label 1415*/ 43320, 18646 /*GILLT_v4s64*//*Label 1416*/ 43410, 0, 18647 /*GILLT_v8s16*//*Label 1417*/ 43474, 18648 /*GILLT_v8s32*//*Label 1418*/ 43509, 18649 /*GILLT_v8s64*//*Label 1419*/ 43573, 0, 0, 18650 /*GILLT_v16s16*//*Label 1420*/ 43608, 18651 /*GILLT_v16s32*//*Label 1421*/ 43643, 0, 0, 18652 /*GILLT_v32s16*//*Label 1422*/ 43678, 18653 // Label 1410: @42919 18654 GIM_Try, /*On fail goto*//*Label 1424*/ 42953, // Rule ID 5592 // 18655 GIM_CheckFeatures, GIFBS_HasFP16, 18656 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16, 18657 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16, 18658 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::FR16XRegClassID, 18659 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::FR16XRegClassID, 18660 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::FR16XRegClassID, 18661 // (fadd:{ *:[f16] } FR16X:{ *:[f16] }:$src1, FR16X:{ *:[f16] }:$src2) => (VADDSHZrr:{ *:[f16] } FR16X:{ *:[f16] }:$src1, FR16X:{ *:[f16] }:$src2) 18662 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VADDSHZrr, 18663 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 18664 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 18665 // GIR_Coverage, 5592, 18666 GIR_Done, 18667 // Label 1424: @42953 18668 GIM_Reject, 18669 // Label 1411: @42954 18670 GIM_Try, /*On fail goto*//*Label 1425*/ 43072, 18671 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 18672 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 18673 GIM_Try, /*On fail goto*//*Label 1426*/ 42993, // Rule ID 621 // 18674 GIM_CheckFeatures, GIFBS_FPStackf32, 18675 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::RFP32RegClassID, 18676 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::RFP32RegClassID, 18677 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::RFP32RegClassID, 18678 // (fadd:{ *:[f32] } RFP32:{ *:[f32] }:$src1, RFP32:{ *:[f32] }:$src2) => (ADD_Fp32:{ *:[f32] }:{ *:[i16] } RFP32:{ *:[f32] }:$src1, RFP32:{ *:[f32] }:$src2) 18679 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::ADD_Fp32, 18680 GIR_AddImplicitDef, /*InsnID*/0, X86::FPSW, 18681 GIR_AddImplicitUse, /*InsnID*/0, X86::FPCW, 18682 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 18683 // GIR_Coverage, 621, 18684 GIR_Done, 18685 // Label 1426: @42993 18686 GIM_Try, /*On fail goto*//*Label 1427*/ 43019, // Rule ID 1891 // 18687 GIM_CheckFeatures, GIFBS_UseAVX, 18688 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::FR32RegClassID, 18689 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::FR32RegClassID, 18690 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::FR32RegClassID, 18691 // (fadd:{ *:[f32] } FR32:{ *:[f32] }:$src1, FR32:{ *:[f32] }:$src2) => (VADDSSrr:{ *:[f32] } FR32:{ *:[f32] }:$src1, FR32:{ *:[f32] }:$src2) 18692 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VADDSSrr, 18693 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 18694 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 18695 // GIR_Coverage, 1891, 18696 GIR_Done, 18697 // Label 1427: @43019 18698 GIM_Try, /*On fail goto*//*Label 1428*/ 43045, // Rule ID 1899 // 18699 GIM_CheckFeatures, GIFBS_UseSSE1, 18700 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::FR32RegClassID, 18701 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::FR32RegClassID, 18702 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::FR32RegClassID, 18703 // (fadd:{ *:[f32] } FR32:{ *:[f32] }:$src1, FR32:{ *:[f32] }:$src2) => (ADDSSrr:{ *:[f32] } FR32:{ *:[f32] }:$src1, FR32:{ *:[f32] }:$src2) 18704 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::ADDSSrr, 18705 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 18706 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 18707 // GIR_Coverage, 1899, 18708 GIR_Done, 18709 // Label 1428: @43045 18710 GIM_Try, /*On fail goto*//*Label 1429*/ 43071, // Rule ID 5554 // 18711 GIM_CheckFeatures, GIFBS_HasAVX512, 18712 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::FR32XRegClassID, 18713 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::FR32XRegClassID, 18714 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::FR32XRegClassID, 18715 // (fadd:{ *:[f32] } FR32X:{ *:[f32] }:$src1, FR32X:{ *:[f32] }:$src2) => (VADDSSZrr:{ *:[f32] } FR32X:{ *:[f32] }:$src1, FR32X:{ *:[f32] }:$src2) 18716 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VADDSSZrr, 18717 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 18718 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 18719 // GIR_Coverage, 5554, 18720 GIR_Done, 18721 // Label 1429: @43071 18722 GIM_Reject, 18723 // Label 1425: @43072 18724 GIM_Reject, 18725 // Label 1412: @43073 18726 GIM_Try, /*On fail goto*//*Label 1430*/ 43191, 18727 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 18728 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 18729 GIM_Try, /*On fail goto*//*Label 1431*/ 43112, // Rule ID 623 // 18730 GIM_CheckFeatures, GIFBS_FPStackf64, 18731 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::RFP64RegClassID, 18732 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::RFP64RegClassID, 18733 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::RFP64RegClassID, 18734 // (fadd:{ *:[f64] } RFP64:{ *:[f64] }:$src1, RFP64:{ *:[f64] }:$src2) => (ADD_Fp64:{ *:[f64] }:{ *:[i16] } RFP64:{ *:[f64] }:$src1, RFP64:{ *:[f64] }:$src2) 18735 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::ADD_Fp64, 18736 GIR_AddImplicitDef, /*InsnID*/0, X86::FPSW, 18737 GIR_AddImplicitUse, /*InsnID*/0, X86::FPCW, 18738 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 18739 // GIR_Coverage, 623, 18740 GIR_Done, 18741 // Label 1431: @43112 18742 GIM_Try, /*On fail goto*//*Label 1432*/ 43138, // Rule ID 1895 // 18743 GIM_CheckFeatures, GIFBS_UseAVX, 18744 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::FR64RegClassID, 18745 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::FR64RegClassID, 18746 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::FR64RegClassID, 18747 // (fadd:{ *:[f64] } FR64:{ *:[f64] }:$src1, FR64:{ *:[f64] }:$src2) => (VADDSDrr:{ *:[f64] } FR64:{ *:[f64] }:$src1, FR64:{ *:[f64] }:$src2) 18748 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VADDSDrr, 18749 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 18750 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 18751 // GIR_Coverage, 1895, 18752 GIR_Done, 18753 // Label 1432: @43138 18754 GIM_Try, /*On fail goto*//*Label 1433*/ 43164, // Rule ID 1903 // 18755 GIM_CheckFeatures, GIFBS_UseSSE2, 18756 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::FR64RegClassID, 18757 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::FR64RegClassID, 18758 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::FR64RegClassID, 18759 // (fadd:{ *:[f64] } FR64:{ *:[f64] }:$src1, FR64:{ *:[f64] }:$src2) => (ADDSDrr:{ *:[f64] } FR64:{ *:[f64] }:$src1, FR64:{ *:[f64] }:$src2) 18760 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::ADDSDrr, 18761 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 18762 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 18763 // GIR_Coverage, 1903, 18764 GIR_Done, 18765 // Label 1433: @43164 18766 GIM_Try, /*On fail goto*//*Label 1434*/ 43190, // Rule ID 5573 // 18767 GIM_CheckFeatures, GIFBS_HasAVX512, 18768 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::FR64XRegClassID, 18769 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::FR64XRegClassID, 18770 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::FR64XRegClassID, 18771 // (fadd:{ *:[f64] } FR64X:{ *:[f64] }:$src1, FR64X:{ *:[f64] }:$src2) => (VADDSDZrr:{ *:[f64] } FR64X:{ *:[f64] }:$src1, FR64X:{ *:[f64] }:$src2) 18772 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VADDSDZrr, 18773 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 18774 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 18775 // GIR_Coverage, 5573, 18776 GIR_Done, 18777 // Label 1434: @43190 18778 GIM_Reject, 18779 // Label 1430: @43191 18780 GIM_Reject, 18781 // Label 1413: @43192 18782 GIM_Try, /*On fail goto*//*Label 1435*/ 43229, // Rule ID 625 // 18783 GIM_CheckFeatures, GIFBS_HasX87, 18784 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s80, 18785 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s80, 18786 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::RFP80RegClassID, 18787 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::RFP80RegClassID, 18788 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::RFP80RegClassID, 18789 // (fadd:{ *:[f80] } RFP80:{ *:[f80] }:$src1, RFP80:{ *:[f80] }:$src2) => (ADD_Fp80:{ *:[f80] }:{ *:[i16] } RFP80:{ *:[f80] }:$src1, RFP80:{ *:[f80] }:$src2) 18790 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::ADD_Fp80, 18791 GIR_AddImplicitDef, /*InsnID*/0, X86::FPSW, 18792 GIR_AddImplicitUse, /*InsnID*/0, X86::FPCW, 18793 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 18794 // GIR_Coverage, 625, 18795 GIR_Done, 18796 // Label 1435: @43229 18797 GIM_Reject, 18798 // Label 1414: @43230 18799 GIM_Try, /*On fail goto*//*Label 1436*/ 43319, 18800 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, 18801 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 18802 GIM_Try, /*On fail goto*//*Label 1437*/ 43266, // Rule ID 1871 // 18803 GIM_CheckFeatures, GIFBS_HasAVX_NoVLX, 18804 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 18805 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 18806 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 18807 // (fadd:{ *:[v2f64] } VR128:{ *:[v2f64] }:$src1, VR128:{ *:[v2f64] }:$src2) => (VADDPDrr:{ *:[v2f64] } VR128:{ *:[v2f64] }:$src1, VR128:{ *:[v2f64] }:$src2) 18808 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VADDPDrr, 18809 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 18810 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 18811 // GIR_Coverage, 1871, 18812 GIR_Done, 18813 // Label 1437: @43266 18814 GIM_Try, /*On fail goto*//*Label 1438*/ 43292, // Rule ID 1887 // 18815 GIM_CheckFeatures, GIFBS_UseSSE2, 18816 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 18817 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 18818 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 18819 // (fadd:{ *:[v2f64] } VR128:{ *:[v2f64] }:$src1, VR128:{ *:[v2f64] }:$src2) => (ADDPDrr:{ *:[v2f64] } VR128:{ *:[v2f64] }:$src1, VR128:{ *:[v2f64] }:$src2) 18820 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::ADDPDrr, 18821 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 18822 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 18823 // GIR_Coverage, 1887, 18824 GIR_Done, 18825 // Label 1438: @43292 18826 GIM_Try, /*On fail goto*//*Label 1439*/ 43318, // Rule ID 5932 // 18827 GIM_CheckFeatures, GIFBS_HasAVX512_HasVLX, 18828 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID, 18829 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID, 18830 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128XRegClassID, 18831 // (fadd:{ *:[v2f64] } VR128X:{ *:[v2f64] }:$src1, VR128X:{ *:[v2f64] }:$src2) => (VADDPDZ128rr:{ *:[v2f64] } VR128X:{ *:[v2f64] }:$src1, VR128X:{ *:[v2f64] }:$src2) 18832 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VADDPDZ128rr, 18833 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 18834 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 18835 // GIR_Coverage, 5932, 18836 GIR_Done, 18837 // Label 1439: @43318 18838 GIM_Reject, 18839 // Label 1436: @43319 18840 GIM_Reject, 18841 // Label 1415: @43320 18842 GIM_Try, /*On fail goto*//*Label 1440*/ 43409, 18843 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, 18844 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 18845 GIM_Try, /*On fail goto*//*Label 1441*/ 43356, // Rule ID 1867 // 18846 GIM_CheckFeatures, GIFBS_HasAVX_NoVLX, 18847 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 18848 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 18849 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 18850 // (fadd:{ *:[v4f32] } VR128:{ *:[v4f32] }:$src1, VR128:{ *:[v4f32] }:$src2) => (VADDPSrr:{ *:[v4f32] } VR128:{ *:[v4f32] }:$src1, VR128:{ *:[v4f32] }:$src2) 18851 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VADDPSrr, 18852 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 18853 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 18854 // GIR_Coverage, 1867, 18855 GIR_Done, 18856 // Label 1441: @43356 18857 GIM_Try, /*On fail goto*//*Label 1442*/ 43382, // Rule ID 1883 // 18858 GIM_CheckFeatures, GIFBS_UseSSE1, 18859 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 18860 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 18861 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 18862 // (fadd:{ *:[v4f32] } VR128:{ *:[v4f32] }:$src1, VR128:{ *:[v4f32] }:$src2) => (ADDPSrr:{ *:[v4f32] } VR128:{ *:[v4f32] }:$src1, VR128:{ *:[v4f32] }:$src2) 18863 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::ADDPSrr, 18864 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 18865 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 18866 // GIR_Coverage, 1883, 18867 GIR_Done, 18868 // Label 1442: @43382 18869 GIM_Try, /*On fail goto*//*Label 1443*/ 43408, // Rule ID 5908 // 18870 GIM_CheckFeatures, GIFBS_HasAVX512_HasVLX, 18871 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID, 18872 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID, 18873 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128XRegClassID, 18874 // (fadd:{ *:[v4f32] } VR128X:{ *:[v4f32] }:$src1, VR128X:{ *:[v4f32] }:$src2) => (VADDPSZ128rr:{ *:[v4f32] } VR128X:{ *:[v4f32] }:$src1, VR128X:{ *:[v4f32] }:$src2) 18875 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VADDPSZ128rr, 18876 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 18877 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 18878 // GIR_Coverage, 5908, 18879 GIR_Done, 18880 // Label 1443: @43408 18881 GIM_Reject, 18882 // Label 1440: @43409 18883 GIM_Reject, 18884 // Label 1416: @43410 18885 GIM_Try, /*On fail goto*//*Label 1444*/ 43473, 18886 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s64, 18887 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s64, 18888 GIM_Try, /*On fail goto*//*Label 1445*/ 43446, // Rule ID 1879 // 18889 GIM_CheckFeatures, GIFBS_HasAVX_NoVLX, 18890 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID, 18891 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256RegClassID, 18892 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256RegClassID, 18893 // (fadd:{ *:[v4f64] } VR256:{ *:[v4f64] }:$src1, VR256:{ *:[v4f64] }:$src2) => (VADDPDYrr:{ *:[v4f64] } VR256:{ *:[v4f64] }:$src1, VR256:{ *:[v4f64] }:$src2) 18894 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VADDPDYrr, 18895 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 18896 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 18897 // GIR_Coverage, 1879, 18898 GIR_Done, 18899 // Label 1445: @43446 18900 GIM_Try, /*On fail goto*//*Label 1446*/ 43472, // Rule ID 5944 // 18901 GIM_CheckFeatures, GIFBS_HasAVX512_HasVLX, 18902 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID, 18903 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID, 18904 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256XRegClassID, 18905 // (fadd:{ *:[v4f64] } VR256X:{ *:[v4f64] }:$src1, VR256X:{ *:[v4f64] }:$src2) => (VADDPDZ256rr:{ *:[v4f64] } VR256X:{ *:[v4f64] }:$src1, VR256X:{ *:[v4f64] }:$src2) 18906 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VADDPDZ256rr, 18907 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 18908 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 18909 // GIR_Coverage, 5944, 18910 GIR_Done, 18911 // Label 1446: @43472 18912 GIM_Reject, 18913 // Label 1444: @43473 18914 GIM_Reject, 18915 // Label 1417: @43474 18916 GIM_Try, /*On fail goto*//*Label 1447*/ 43508, // Rule ID 5968 // 18917 GIM_CheckFeatures, GIFBS_HasFP16_HasVLX, 18918 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, 18919 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 18920 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID, 18921 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID, 18922 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128XRegClassID, 18923 // (fadd:{ *:[v8f16] } VR128X:{ *:[v8f16] }:$src1, VR128X:{ *:[v8f16] }:$src2) => (VADDPHZ128rr:{ *:[v8f16] } VR128X:{ *:[v8f16] }:$src1, VR128X:{ *:[v8f16] }:$src2) 18924 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VADDPHZ128rr, 18925 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 18926 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 18927 // GIR_Coverage, 5968, 18928 GIR_Done, 18929 // Label 1447: @43508 18930 GIM_Reject, 18931 // Label 1418: @43509 18932 GIM_Try, /*On fail goto*//*Label 1448*/ 43572, 18933 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s32, 18934 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s32, 18935 GIM_Try, /*On fail goto*//*Label 1449*/ 43545, // Rule ID 1875 // 18936 GIM_CheckFeatures, GIFBS_HasAVX_NoVLX, 18937 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID, 18938 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256RegClassID, 18939 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256RegClassID, 18940 // (fadd:{ *:[v8f32] } VR256:{ *:[v8f32] }:$src1, VR256:{ *:[v8f32] }:$src2) => (VADDPSYrr:{ *:[v8f32] } VR256:{ *:[v8f32] }:$src1, VR256:{ *:[v8f32] }:$src2) 18941 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VADDPSYrr, 18942 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 18943 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 18944 // GIR_Coverage, 1875, 18945 GIR_Done, 18946 // Label 1449: @43545 18947 GIM_Try, /*On fail goto*//*Label 1450*/ 43571, // Rule ID 5920 // 18948 GIM_CheckFeatures, GIFBS_HasAVX512_HasVLX, 18949 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID, 18950 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID, 18951 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256XRegClassID, 18952 // (fadd:{ *:[v8f32] } VR256X:{ *:[v8f32] }:$src1, VR256X:{ *:[v8f32] }:$src2) => (VADDPSZ256rr:{ *:[v8f32] } VR256X:{ *:[v8f32] }:$src1, VR256X:{ *:[v8f32] }:$src2) 18953 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VADDPSZ256rr, 18954 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 18955 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 18956 // GIR_Coverage, 5920, 18957 GIR_Done, 18958 // Label 1450: @43571 18959 GIM_Reject, 18960 // Label 1448: @43572 18961 GIM_Reject, 18962 // Label 1419: @43573 18963 GIM_Try, /*On fail goto*//*Label 1451*/ 43607, // Rule ID 5896 // 18964 GIM_CheckFeatures, GIFBS_HasAVX512, 18965 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s64, 18966 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s64, 18967 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 18968 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR512RegClassID, 18969 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR512RegClassID, 18970 // (fadd:{ *:[v8f64] } VR512:{ *:[v8f64] }:$src1, VR512:{ *:[v8f64] }:$src2) => (VADDPDZrr:{ *:[v8f64] } VR512:{ *:[v8f64] }:$src1, VR512:{ *:[v8f64] }:$src2) 18971 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VADDPDZrr, 18972 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 18973 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 18974 // GIR_Coverage, 5896, 18975 GIR_Done, 18976 // Label 1451: @43607 18977 GIM_Reject, 18978 // Label 1420: @43608 18979 GIM_Try, /*On fail goto*//*Label 1452*/ 43642, // Rule ID 5980 // 18980 GIM_CheckFeatures, GIFBS_HasFP16_HasVLX, 18981 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s16, 18982 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s16, 18983 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID, 18984 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID, 18985 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256XRegClassID, 18986 // (fadd:{ *:[v16f16] } VR256X:{ *:[v16f16] }:$src1, VR256X:{ *:[v16f16] }:$src2) => (VADDPHZ256rr:{ *:[v16f16] } VR256X:{ *:[v16f16] }:$src1, VR256X:{ *:[v16f16] }:$src2) 18987 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VADDPHZ256rr, 18988 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 18989 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 18990 // GIR_Coverage, 5980, 18991 GIR_Done, 18992 // Label 1452: @43642 18993 GIM_Reject, 18994 // Label 1421: @43643 18995 GIM_Try, /*On fail goto*//*Label 1453*/ 43677, // Rule ID 5884 // 18996 GIM_CheckFeatures, GIFBS_HasAVX512, 18997 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s32, 18998 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s32, 18999 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 19000 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR512RegClassID, 19001 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR512RegClassID, 19002 // (fadd:{ *:[v16f32] } VR512:{ *:[v16f32] }:$src1, VR512:{ *:[v16f32] }:$src2) => (VADDPSZrr:{ *:[v16f32] } VR512:{ *:[v16f32] }:$src1, VR512:{ *:[v16f32] }:$src2) 19003 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VADDPSZrr, 19004 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 19005 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 19006 // GIR_Coverage, 5884, 19007 GIR_Done, 19008 // Label 1453: @43677 19009 GIM_Reject, 19010 // Label 1422: @43678 19011 GIM_Try, /*On fail goto*//*Label 1454*/ 43712, // Rule ID 5956 // 19012 GIM_CheckFeatures, GIFBS_HasFP16, 19013 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v32s16, 19014 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v32s16, 19015 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 19016 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR512RegClassID, 19017 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR512RegClassID, 19018 // (fadd:{ *:[v32f16] } VR512:{ *:[v32f16] }:$src1, VR512:{ *:[v32f16] }:$src2) => (VADDPHZrr:{ *:[v32f16] } VR512:{ *:[v32f16] }:$src1, VR512:{ *:[v32f16] }:$src2) 19019 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VADDPHZrr, 19020 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 19021 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 19022 // GIR_Coverage, 5956, 19023 GIR_Done, 19024 // Label 1454: @43712 19025 GIM_Reject, 19026 // Label 1423: @43713 19027 GIM_Reject, 19028 // Label 32: @43714 19029 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/2, 23, /*)*//*default:*//*Label 1468*/ 44535, 19030 /*GILLT_s16*//*Label 1455*/ 43741, 19031 /*GILLT_s32*//*Label 1456*/ 43776, 19032 /*GILLT_s64*//*Label 1457*/ 43895, 19033 /*GILLT_s80*//*Label 1458*/ 44014, 0, 0, 19034 /*GILLT_v2s64*//*Label 1459*/ 44052, 0, 19035 /*GILLT_v4s32*//*Label 1460*/ 44142, 19036 /*GILLT_v4s64*//*Label 1461*/ 44232, 0, 19037 /*GILLT_v8s16*//*Label 1462*/ 44296, 19038 /*GILLT_v8s32*//*Label 1463*/ 44331, 19039 /*GILLT_v8s64*//*Label 1464*/ 44395, 0, 0, 19040 /*GILLT_v16s16*//*Label 1465*/ 44430, 19041 /*GILLT_v16s32*//*Label 1466*/ 44465, 0, 0, 19042 /*GILLT_v32s16*//*Label 1467*/ 44500, 19043 // Label 1455: @43741 19044 GIM_Try, /*On fail goto*//*Label 1469*/ 43775, // Rule ID 5706 // 19045 GIM_CheckFeatures, GIFBS_HasFP16, 19046 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16, 19047 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16, 19048 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::FR16XRegClassID, 19049 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::FR16XRegClassID, 19050 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::FR16XRegClassID, 19051 // (fsub:{ *:[f16] } FR16X:{ *:[f16] }:$src1, FR16X:{ *:[f16] }:$src2) => (VSUBSHZrr:{ *:[f16] } FR16X:{ *:[f16] }:$src1, FR16X:{ *:[f16] }:$src2) 19052 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VSUBSHZrr, 19053 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 19054 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 19055 // GIR_Coverage, 5706, 19056 GIR_Done, 19057 // Label 1469: @43775 19058 GIM_Reject, 19059 // Label 1456: @43776 19060 GIM_Try, /*On fail goto*//*Label 1470*/ 43894, 19061 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 19062 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 19063 GIM_Try, /*On fail goto*//*Label 1471*/ 43815, // Rule ID 627 // 19064 GIM_CheckFeatures, GIFBS_FPStackf32, 19065 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::RFP32RegClassID, 19066 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::RFP32RegClassID, 19067 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::RFP32RegClassID, 19068 // (fsub:{ *:[f32] } RFP32:{ *:[f32] }:$src1, RFP32:{ *:[f32] }:$src2) => (SUB_Fp32:{ *:[f32] }:{ *:[i16] } RFP32:{ *:[f32] }:$src1, RFP32:{ *:[f32] }:$src2) 19069 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::SUB_Fp32, 19070 GIR_AddImplicitDef, /*InsnID*/0, X86::FPSW, 19071 GIR_AddImplicitUse, /*InsnID*/0, X86::FPCW, 19072 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 19073 // GIR_Coverage, 627, 19074 GIR_Done, 19075 // Label 1471: @43815 19076 GIM_Try, /*On fail goto*//*Label 1472*/ 43841, // Rule ID 1971 // 19077 GIM_CheckFeatures, GIFBS_UseAVX, 19078 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::FR32RegClassID, 19079 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::FR32RegClassID, 19080 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::FR32RegClassID, 19081 // (fsub:{ *:[f32] } FR32:{ *:[f32] }:$src1, FR32:{ *:[f32] }:$src2) => (VSUBSSrr:{ *:[f32] } FR32:{ *:[f32] }:$src1, FR32:{ *:[f32] }:$src2) 19082 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VSUBSSrr, 19083 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 19084 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 19085 // GIR_Coverage, 1971, 19086 GIR_Done, 19087 // Label 1472: @43841 19088 GIM_Try, /*On fail goto*//*Label 1473*/ 43867, // Rule ID 1979 // 19089 GIM_CheckFeatures, GIFBS_UseSSE1, 19090 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::FR32RegClassID, 19091 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::FR32RegClassID, 19092 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::FR32RegClassID, 19093 // (fsub:{ *:[f32] } FR32:{ *:[f32] }:$src1, FR32:{ *:[f32] }:$src2) => (SUBSSrr:{ *:[f32] } FR32:{ *:[f32] }:$src1, FR32:{ *:[f32] }:$src2) 19094 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::SUBSSrr, 19095 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 19096 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 19097 // GIR_Coverage, 1979, 19098 GIR_Done, 19099 // Label 1473: @43867 19100 GIM_Try, /*On fail goto*//*Label 1474*/ 43893, // Rule ID 5668 // 19101 GIM_CheckFeatures, GIFBS_HasAVX512, 19102 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::FR32XRegClassID, 19103 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::FR32XRegClassID, 19104 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::FR32XRegClassID, 19105 // (fsub:{ *:[f32] } FR32X:{ *:[f32] }:$src1, FR32X:{ *:[f32] }:$src2) => (VSUBSSZrr:{ *:[f32] } FR32X:{ *:[f32] }:$src1, FR32X:{ *:[f32] }:$src2) 19106 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VSUBSSZrr, 19107 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 19108 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 19109 // GIR_Coverage, 5668, 19110 GIR_Done, 19111 // Label 1474: @43893 19112 GIM_Reject, 19113 // Label 1470: @43894 19114 GIM_Reject, 19115 // Label 1457: @43895 19116 GIM_Try, /*On fail goto*//*Label 1475*/ 44013, 19117 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 19118 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 19119 GIM_Try, /*On fail goto*//*Label 1476*/ 43934, // Rule ID 629 // 19120 GIM_CheckFeatures, GIFBS_FPStackf64, 19121 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::RFP64RegClassID, 19122 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::RFP64RegClassID, 19123 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::RFP64RegClassID, 19124 // (fsub:{ *:[f64] } RFP64:{ *:[f64] }:$src1, RFP64:{ *:[f64] }:$src2) => (SUB_Fp64:{ *:[f64] }:{ *:[i16] } RFP64:{ *:[f64] }:$src1, RFP64:{ *:[f64] }:$src2) 19125 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::SUB_Fp64, 19126 GIR_AddImplicitDef, /*InsnID*/0, X86::FPSW, 19127 GIR_AddImplicitUse, /*InsnID*/0, X86::FPCW, 19128 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 19129 // GIR_Coverage, 629, 19130 GIR_Done, 19131 // Label 1476: @43934 19132 GIM_Try, /*On fail goto*//*Label 1477*/ 43960, // Rule ID 1975 // 19133 GIM_CheckFeatures, GIFBS_UseAVX, 19134 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::FR64RegClassID, 19135 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::FR64RegClassID, 19136 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::FR64RegClassID, 19137 // (fsub:{ *:[f64] } FR64:{ *:[f64] }:$src1, FR64:{ *:[f64] }:$src2) => (VSUBSDrr:{ *:[f64] } FR64:{ *:[f64] }:$src1, FR64:{ *:[f64] }:$src2) 19138 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VSUBSDrr, 19139 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 19140 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 19141 // GIR_Coverage, 1975, 19142 GIR_Done, 19143 // Label 1477: @43960 19144 GIM_Try, /*On fail goto*//*Label 1478*/ 43986, // Rule ID 1983 // 19145 GIM_CheckFeatures, GIFBS_UseSSE2, 19146 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::FR64RegClassID, 19147 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::FR64RegClassID, 19148 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::FR64RegClassID, 19149 // (fsub:{ *:[f64] } FR64:{ *:[f64] }:$src1, FR64:{ *:[f64] }:$src2) => (SUBSDrr:{ *:[f64] } FR64:{ *:[f64] }:$src1, FR64:{ *:[f64] }:$src2) 19150 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::SUBSDrr, 19151 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 19152 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 19153 // GIR_Coverage, 1983, 19154 GIR_Done, 19155 // Label 1478: @43986 19156 GIM_Try, /*On fail goto*//*Label 1479*/ 44012, // Rule ID 5687 // 19157 GIM_CheckFeatures, GIFBS_HasAVX512, 19158 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::FR64XRegClassID, 19159 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::FR64XRegClassID, 19160 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::FR64XRegClassID, 19161 // (fsub:{ *:[f64] } FR64X:{ *:[f64] }:$src1, FR64X:{ *:[f64] }:$src2) => (VSUBSDZrr:{ *:[f64] } FR64X:{ *:[f64] }:$src1, FR64X:{ *:[f64] }:$src2) 19162 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VSUBSDZrr, 19163 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 19164 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 19165 // GIR_Coverage, 5687, 19166 GIR_Done, 19167 // Label 1479: @44012 19168 GIM_Reject, 19169 // Label 1475: @44013 19170 GIM_Reject, 19171 // Label 1458: @44014 19172 GIM_Try, /*On fail goto*//*Label 1480*/ 44051, // Rule ID 631 // 19173 GIM_CheckFeatures, GIFBS_HasX87, 19174 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s80, 19175 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s80, 19176 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::RFP80RegClassID, 19177 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::RFP80RegClassID, 19178 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::RFP80RegClassID, 19179 // (fsub:{ *:[f80] } RFP80:{ *:[f80] }:$src1, RFP80:{ *:[f80] }:$src2) => (SUB_Fp80:{ *:[f80] }:{ *:[i16] } RFP80:{ *:[f80] }:$src1, RFP80:{ *:[f80] }:$src2) 19180 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::SUB_Fp80, 19181 GIR_AddImplicitDef, /*InsnID*/0, X86::FPSW, 19182 GIR_AddImplicitUse, /*InsnID*/0, X86::FPCW, 19183 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 19184 // GIR_Coverage, 631, 19185 GIR_Done, 19186 // Label 1480: @44051 19187 GIM_Reject, 19188 // Label 1459: @44052 19189 GIM_Try, /*On fail goto*//*Label 1481*/ 44141, 19190 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, 19191 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 19192 GIM_Try, /*On fail goto*//*Label 1482*/ 44088, // Rule ID 1951 // 19193 GIM_CheckFeatures, GIFBS_HasAVX_NoVLX, 19194 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 19195 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 19196 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 19197 // (fsub:{ *:[v2f64] } VR128:{ *:[v2f64] }:$src1, VR128:{ *:[v2f64] }:$src2) => (VSUBPDrr:{ *:[v2f64] } VR128:{ *:[v2f64] }:$src1, VR128:{ *:[v2f64] }:$src2) 19198 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VSUBPDrr, 19199 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 19200 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 19201 // GIR_Coverage, 1951, 19202 GIR_Done, 19203 // Label 1482: @44088 19204 GIM_Try, /*On fail goto*//*Label 1483*/ 44114, // Rule ID 1967 // 19205 GIM_CheckFeatures, GIFBS_UseSSE2, 19206 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 19207 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 19208 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 19209 // (fsub:{ *:[v2f64] } VR128:{ *:[v2f64] }:$src1, VR128:{ *:[v2f64] }:$src2) => (SUBPDrr:{ *:[v2f64] } VR128:{ *:[v2f64] }:$src1, VR128:{ *:[v2f64] }:$src2) 19210 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::SUBPDrr, 19211 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 19212 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 19213 // GIR_Coverage, 1967, 19214 GIR_Done, 19215 // Label 1483: @44114 19216 GIM_Try, /*On fail goto*//*Label 1484*/ 44140, // Rule ID 6166 // 19217 GIM_CheckFeatures, GIFBS_HasAVX512_HasVLX, 19218 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID, 19219 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID, 19220 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128XRegClassID, 19221 // (fsub:{ *:[v2f64] } VR128X:{ *:[v2f64] }:$src1, VR128X:{ *:[v2f64] }:$src2) => (VSUBPDZ128rr:{ *:[v2f64] } VR128X:{ *:[v2f64] }:$src1, VR128X:{ *:[v2f64] }:$src2) 19222 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VSUBPDZ128rr, 19223 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 19224 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 19225 // GIR_Coverage, 6166, 19226 GIR_Done, 19227 // Label 1484: @44140 19228 GIM_Reject, 19229 // Label 1481: @44141 19230 GIM_Reject, 19231 // Label 1460: @44142 19232 GIM_Try, /*On fail goto*//*Label 1485*/ 44231, 19233 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, 19234 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 19235 GIM_Try, /*On fail goto*//*Label 1486*/ 44178, // Rule ID 1947 // 19236 GIM_CheckFeatures, GIFBS_HasAVX_NoVLX, 19237 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 19238 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 19239 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 19240 // (fsub:{ *:[v4f32] } VR128:{ *:[v4f32] }:$src1, VR128:{ *:[v4f32] }:$src2) => (VSUBPSrr:{ *:[v4f32] } VR128:{ *:[v4f32] }:$src1, VR128:{ *:[v4f32] }:$src2) 19241 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VSUBPSrr, 19242 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 19243 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 19244 // GIR_Coverage, 1947, 19245 GIR_Done, 19246 // Label 1486: @44178 19247 GIM_Try, /*On fail goto*//*Label 1487*/ 44204, // Rule ID 1963 // 19248 GIM_CheckFeatures, GIFBS_UseSSE1, 19249 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 19250 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 19251 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 19252 // (fsub:{ *:[v4f32] } VR128:{ *:[v4f32] }:$src1, VR128:{ *:[v4f32] }:$src2) => (SUBPSrr:{ *:[v4f32] } VR128:{ *:[v4f32] }:$src1, VR128:{ *:[v4f32] }:$src2) 19253 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::SUBPSrr, 19254 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 19255 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 19256 // GIR_Coverage, 1963, 19257 GIR_Done, 19258 // Label 1487: @44204 19259 GIM_Try, /*On fail goto*//*Label 1488*/ 44230, // Rule ID 6142 // 19260 GIM_CheckFeatures, GIFBS_HasAVX512_HasVLX, 19261 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID, 19262 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID, 19263 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128XRegClassID, 19264 // (fsub:{ *:[v4f32] } VR128X:{ *:[v4f32] }:$src1, VR128X:{ *:[v4f32] }:$src2) => (VSUBPSZ128rr:{ *:[v4f32] } VR128X:{ *:[v4f32] }:$src1, VR128X:{ *:[v4f32] }:$src2) 19265 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VSUBPSZ128rr, 19266 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 19267 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 19268 // GIR_Coverage, 6142, 19269 GIR_Done, 19270 // Label 1488: @44230 19271 GIM_Reject, 19272 // Label 1485: @44231 19273 GIM_Reject, 19274 // Label 1461: @44232 19275 GIM_Try, /*On fail goto*//*Label 1489*/ 44295, 19276 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s64, 19277 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s64, 19278 GIM_Try, /*On fail goto*//*Label 1490*/ 44268, // Rule ID 1959 // 19279 GIM_CheckFeatures, GIFBS_HasAVX_NoVLX, 19280 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID, 19281 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256RegClassID, 19282 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256RegClassID, 19283 // (fsub:{ *:[v4f64] } VR256:{ *:[v4f64] }:$src1, VR256:{ *:[v4f64] }:$src2) => (VSUBPDYrr:{ *:[v4f64] } VR256:{ *:[v4f64] }:$src1, VR256:{ *:[v4f64] }:$src2) 19284 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VSUBPDYrr, 19285 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 19286 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 19287 // GIR_Coverage, 1959, 19288 GIR_Done, 19289 // Label 1490: @44268 19290 GIM_Try, /*On fail goto*//*Label 1491*/ 44294, // Rule ID 6178 // 19291 GIM_CheckFeatures, GIFBS_HasAVX512_HasVLX, 19292 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID, 19293 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID, 19294 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256XRegClassID, 19295 // (fsub:{ *:[v4f64] } VR256X:{ *:[v4f64] }:$src1, VR256X:{ *:[v4f64] }:$src2) => (VSUBPDZ256rr:{ *:[v4f64] } VR256X:{ *:[v4f64] }:$src1, VR256X:{ *:[v4f64] }:$src2) 19296 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VSUBPDZ256rr, 19297 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 19298 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 19299 // GIR_Coverage, 6178, 19300 GIR_Done, 19301 // Label 1491: @44294 19302 GIM_Reject, 19303 // Label 1489: @44295 19304 GIM_Reject, 19305 // Label 1462: @44296 19306 GIM_Try, /*On fail goto*//*Label 1492*/ 44330, // Rule ID 6202 // 19307 GIM_CheckFeatures, GIFBS_HasFP16_HasVLX, 19308 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, 19309 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 19310 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID, 19311 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID, 19312 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128XRegClassID, 19313 // (fsub:{ *:[v8f16] } VR128X:{ *:[v8f16] }:$src1, VR128X:{ *:[v8f16] }:$src2) => (VSUBPHZ128rr:{ *:[v8f16] } VR128X:{ *:[v8f16] }:$src1, VR128X:{ *:[v8f16] }:$src2) 19314 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VSUBPHZ128rr, 19315 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 19316 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 19317 // GIR_Coverage, 6202, 19318 GIR_Done, 19319 // Label 1492: @44330 19320 GIM_Reject, 19321 // Label 1463: @44331 19322 GIM_Try, /*On fail goto*//*Label 1493*/ 44394, 19323 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s32, 19324 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s32, 19325 GIM_Try, /*On fail goto*//*Label 1494*/ 44367, // Rule ID 1955 // 19326 GIM_CheckFeatures, GIFBS_HasAVX_NoVLX, 19327 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID, 19328 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256RegClassID, 19329 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256RegClassID, 19330 // (fsub:{ *:[v8f32] } VR256:{ *:[v8f32] }:$src1, VR256:{ *:[v8f32] }:$src2) => (VSUBPSYrr:{ *:[v8f32] } VR256:{ *:[v8f32] }:$src1, VR256:{ *:[v8f32] }:$src2) 19331 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VSUBPSYrr, 19332 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 19333 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 19334 // GIR_Coverage, 1955, 19335 GIR_Done, 19336 // Label 1494: @44367 19337 GIM_Try, /*On fail goto*//*Label 1495*/ 44393, // Rule ID 6154 // 19338 GIM_CheckFeatures, GIFBS_HasAVX512_HasVLX, 19339 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID, 19340 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID, 19341 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256XRegClassID, 19342 // (fsub:{ *:[v8f32] } VR256X:{ *:[v8f32] }:$src1, VR256X:{ *:[v8f32] }:$src2) => (VSUBPSZ256rr:{ *:[v8f32] } VR256X:{ *:[v8f32] }:$src1, VR256X:{ *:[v8f32] }:$src2) 19343 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VSUBPSZ256rr, 19344 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 19345 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 19346 // GIR_Coverage, 6154, 19347 GIR_Done, 19348 // Label 1495: @44393 19349 GIM_Reject, 19350 // Label 1493: @44394 19351 GIM_Reject, 19352 // Label 1464: @44395 19353 GIM_Try, /*On fail goto*//*Label 1496*/ 44429, // Rule ID 6130 // 19354 GIM_CheckFeatures, GIFBS_HasAVX512, 19355 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s64, 19356 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s64, 19357 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 19358 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR512RegClassID, 19359 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR512RegClassID, 19360 // (fsub:{ *:[v8f64] } VR512:{ *:[v8f64] }:$src1, VR512:{ *:[v8f64] }:$src2) => (VSUBPDZrr:{ *:[v8f64] } VR512:{ *:[v8f64] }:$src1, VR512:{ *:[v8f64] }:$src2) 19361 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VSUBPDZrr, 19362 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 19363 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 19364 // GIR_Coverage, 6130, 19365 GIR_Done, 19366 // Label 1496: @44429 19367 GIM_Reject, 19368 // Label 1465: @44430 19369 GIM_Try, /*On fail goto*//*Label 1497*/ 44464, // Rule ID 6214 // 19370 GIM_CheckFeatures, GIFBS_HasFP16_HasVLX, 19371 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s16, 19372 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s16, 19373 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID, 19374 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID, 19375 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256XRegClassID, 19376 // (fsub:{ *:[v16f16] } VR256X:{ *:[v16f16] }:$src1, VR256X:{ *:[v16f16] }:$src2) => (VSUBPHZ256rr:{ *:[v16f16] } VR256X:{ *:[v16f16] }:$src1, VR256X:{ *:[v16f16] }:$src2) 19377 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VSUBPHZ256rr, 19378 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 19379 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 19380 // GIR_Coverage, 6214, 19381 GIR_Done, 19382 // Label 1497: @44464 19383 GIM_Reject, 19384 // Label 1466: @44465 19385 GIM_Try, /*On fail goto*//*Label 1498*/ 44499, // Rule ID 6118 // 19386 GIM_CheckFeatures, GIFBS_HasAVX512, 19387 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s32, 19388 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s32, 19389 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 19390 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR512RegClassID, 19391 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR512RegClassID, 19392 // (fsub:{ *:[v16f32] } VR512:{ *:[v16f32] }:$src1, VR512:{ *:[v16f32] }:$src2) => (VSUBPSZrr:{ *:[v16f32] } VR512:{ *:[v16f32] }:$src1, VR512:{ *:[v16f32] }:$src2) 19393 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VSUBPSZrr, 19394 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 19395 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 19396 // GIR_Coverage, 6118, 19397 GIR_Done, 19398 // Label 1498: @44499 19399 GIM_Reject, 19400 // Label 1467: @44500 19401 GIM_Try, /*On fail goto*//*Label 1499*/ 44534, // Rule ID 6190 // 19402 GIM_CheckFeatures, GIFBS_HasFP16, 19403 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v32s16, 19404 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v32s16, 19405 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 19406 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR512RegClassID, 19407 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR512RegClassID, 19408 // (fsub:{ *:[v32f16] } VR512:{ *:[v32f16] }:$src1, VR512:{ *:[v32f16] }:$src2) => (VSUBPHZrr:{ *:[v32f16] } VR512:{ *:[v32f16] }:$src1, VR512:{ *:[v32f16] }:$src2) 19409 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VSUBPHZrr, 19410 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 19411 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 19412 // GIR_Coverage, 6190, 19413 GIR_Done, 19414 // Label 1499: @44534 19415 GIM_Reject, 19416 // Label 1468: @44535 19417 GIM_Reject, 19418 // Label 33: @44536 19419 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/2, 23, /*)*//*default:*//*Label 1513*/ 45357, 19420 /*GILLT_s16*//*Label 1500*/ 44563, 19421 /*GILLT_s32*//*Label 1501*/ 44598, 19422 /*GILLT_s64*//*Label 1502*/ 44717, 19423 /*GILLT_s80*//*Label 1503*/ 44836, 0, 0, 19424 /*GILLT_v2s64*//*Label 1504*/ 44874, 0, 19425 /*GILLT_v4s32*//*Label 1505*/ 44964, 19426 /*GILLT_v4s64*//*Label 1506*/ 45054, 0, 19427 /*GILLT_v8s16*//*Label 1507*/ 45118, 19428 /*GILLT_v8s32*//*Label 1508*/ 45153, 19429 /*GILLT_v8s64*//*Label 1509*/ 45217, 0, 0, 19430 /*GILLT_v16s16*//*Label 1510*/ 45252, 19431 /*GILLT_v16s32*//*Label 1511*/ 45287, 0, 0, 19432 /*GILLT_v32s16*//*Label 1512*/ 45322, 19433 // Label 1500: @44563 19434 GIM_Try, /*On fail goto*//*Label 1514*/ 44597, // Rule ID 5649 // 19435 GIM_CheckFeatures, GIFBS_HasFP16, 19436 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16, 19437 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16, 19438 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::FR16XRegClassID, 19439 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::FR16XRegClassID, 19440 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::FR16XRegClassID, 19441 // (fmul:{ *:[f16] } FR16X:{ *:[f16] }:$src1, FR16X:{ *:[f16] }:$src2) => (VMULSHZrr:{ *:[f16] } FR16X:{ *:[f16] }:$src1, FR16X:{ *:[f16] }:$src2) 19442 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VMULSHZrr, 19443 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 19444 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 19445 // GIR_Coverage, 5649, 19446 GIR_Done, 19447 // Label 1514: @44597 19448 GIM_Reject, 19449 // Label 1501: @44598 19450 GIM_Try, /*On fail goto*//*Label 1515*/ 44716, 19451 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 19452 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 19453 GIM_Try, /*On fail goto*//*Label 1516*/ 44637, // Rule ID 633 // 19454 GIM_CheckFeatures, GIFBS_FPStackf32, 19455 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::RFP32RegClassID, 19456 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::RFP32RegClassID, 19457 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::RFP32RegClassID, 19458 // (fmul:{ *:[f32] } RFP32:{ *:[f32] }:$src1, RFP32:{ *:[f32] }:$src2) => (MUL_Fp32:{ *:[f32] }:{ *:[i16] } RFP32:{ *:[f32] }:$src1, RFP32:{ *:[f32] }:$src2) 19459 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::MUL_Fp32, 19460 GIR_AddImplicitDef, /*InsnID*/0, X86::FPSW, 19461 GIR_AddImplicitUse, /*InsnID*/0, X86::FPCW, 19462 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 19463 // GIR_Coverage, 633, 19464 GIR_Done, 19465 // Label 1516: @44637 19466 GIM_Try, /*On fail goto*//*Label 1517*/ 44663, // Rule ID 1931 // 19467 GIM_CheckFeatures, GIFBS_UseAVX, 19468 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::FR32RegClassID, 19469 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::FR32RegClassID, 19470 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::FR32RegClassID, 19471 // (fmul:{ *:[f32] } FR32:{ *:[f32] }:$src1, FR32:{ *:[f32] }:$src2) => (VMULSSrr:{ *:[f32] } FR32:{ *:[f32] }:$src1, FR32:{ *:[f32] }:$src2) 19472 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VMULSSrr, 19473 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 19474 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 19475 // GIR_Coverage, 1931, 19476 GIR_Done, 19477 // Label 1517: @44663 19478 GIM_Try, /*On fail goto*//*Label 1518*/ 44689, // Rule ID 1939 // 19479 GIM_CheckFeatures, GIFBS_UseSSE1, 19480 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::FR32RegClassID, 19481 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::FR32RegClassID, 19482 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::FR32RegClassID, 19483 // (fmul:{ *:[f32] } FR32:{ *:[f32] }:$src1, FR32:{ *:[f32] }:$src2) => (MULSSrr:{ *:[f32] } FR32:{ *:[f32] }:$src1, FR32:{ *:[f32] }:$src2) 19484 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::MULSSrr, 19485 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 19486 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 19487 // GIR_Coverage, 1939, 19488 GIR_Done, 19489 // Label 1518: @44689 19490 GIM_Try, /*On fail goto*//*Label 1519*/ 44715, // Rule ID 5611 // 19491 GIM_CheckFeatures, GIFBS_HasAVX512, 19492 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::FR32XRegClassID, 19493 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::FR32XRegClassID, 19494 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::FR32XRegClassID, 19495 // (fmul:{ *:[f32] } FR32X:{ *:[f32] }:$src1, FR32X:{ *:[f32] }:$src2) => (VMULSSZrr:{ *:[f32] } FR32X:{ *:[f32] }:$src1, FR32X:{ *:[f32] }:$src2) 19496 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VMULSSZrr, 19497 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 19498 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 19499 // GIR_Coverage, 5611, 19500 GIR_Done, 19501 // Label 1519: @44715 19502 GIM_Reject, 19503 // Label 1515: @44716 19504 GIM_Reject, 19505 // Label 1502: @44717 19506 GIM_Try, /*On fail goto*//*Label 1520*/ 44835, 19507 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 19508 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 19509 GIM_Try, /*On fail goto*//*Label 1521*/ 44756, // Rule ID 635 // 19510 GIM_CheckFeatures, GIFBS_FPStackf64, 19511 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::RFP64RegClassID, 19512 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::RFP64RegClassID, 19513 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::RFP64RegClassID, 19514 // (fmul:{ *:[f64] } RFP64:{ *:[f64] }:$src1, RFP64:{ *:[f64] }:$src2) => (MUL_Fp64:{ *:[f64] }:{ *:[i16] } RFP64:{ *:[f64] }:$src1, RFP64:{ *:[f64] }:$src2) 19515 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::MUL_Fp64, 19516 GIR_AddImplicitDef, /*InsnID*/0, X86::FPSW, 19517 GIR_AddImplicitUse, /*InsnID*/0, X86::FPCW, 19518 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 19519 // GIR_Coverage, 635, 19520 GIR_Done, 19521 // Label 1521: @44756 19522 GIM_Try, /*On fail goto*//*Label 1522*/ 44782, // Rule ID 1935 // 19523 GIM_CheckFeatures, GIFBS_UseAVX, 19524 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::FR64RegClassID, 19525 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::FR64RegClassID, 19526 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::FR64RegClassID, 19527 // (fmul:{ *:[f64] } FR64:{ *:[f64] }:$src1, FR64:{ *:[f64] }:$src2) => (VMULSDrr:{ *:[f64] } FR64:{ *:[f64] }:$src1, FR64:{ *:[f64] }:$src2) 19528 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VMULSDrr, 19529 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 19530 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 19531 // GIR_Coverage, 1935, 19532 GIR_Done, 19533 // Label 1522: @44782 19534 GIM_Try, /*On fail goto*//*Label 1523*/ 44808, // Rule ID 1943 // 19535 GIM_CheckFeatures, GIFBS_UseSSE2, 19536 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::FR64RegClassID, 19537 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::FR64RegClassID, 19538 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::FR64RegClassID, 19539 // (fmul:{ *:[f64] } FR64:{ *:[f64] }:$src1, FR64:{ *:[f64] }:$src2) => (MULSDrr:{ *:[f64] } FR64:{ *:[f64] }:$src1, FR64:{ *:[f64] }:$src2) 19540 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::MULSDrr, 19541 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 19542 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 19543 // GIR_Coverage, 1943, 19544 GIR_Done, 19545 // Label 1523: @44808 19546 GIM_Try, /*On fail goto*//*Label 1524*/ 44834, // Rule ID 5630 // 19547 GIM_CheckFeatures, GIFBS_HasAVX512, 19548 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::FR64XRegClassID, 19549 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::FR64XRegClassID, 19550 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::FR64XRegClassID, 19551 // (fmul:{ *:[f64] } FR64X:{ *:[f64] }:$src1, FR64X:{ *:[f64] }:$src2) => (VMULSDZrr:{ *:[f64] } FR64X:{ *:[f64] }:$src1, FR64X:{ *:[f64] }:$src2) 19552 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VMULSDZrr, 19553 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 19554 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 19555 // GIR_Coverage, 5630, 19556 GIR_Done, 19557 // Label 1524: @44834 19558 GIM_Reject, 19559 // Label 1520: @44835 19560 GIM_Reject, 19561 // Label 1503: @44836 19562 GIM_Try, /*On fail goto*//*Label 1525*/ 44873, // Rule ID 637 // 19563 GIM_CheckFeatures, GIFBS_HasX87, 19564 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s80, 19565 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s80, 19566 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::RFP80RegClassID, 19567 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::RFP80RegClassID, 19568 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::RFP80RegClassID, 19569 // (fmul:{ *:[f80] } RFP80:{ *:[f80] }:$src1, RFP80:{ *:[f80] }:$src2) => (MUL_Fp80:{ *:[f80] }:{ *:[i16] } RFP80:{ *:[f80] }:$src1, RFP80:{ *:[f80] }:$src2) 19570 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::MUL_Fp80, 19571 GIR_AddImplicitDef, /*InsnID*/0, X86::FPSW, 19572 GIR_AddImplicitUse, /*InsnID*/0, X86::FPCW, 19573 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 19574 // GIR_Coverage, 637, 19575 GIR_Done, 19576 // Label 1525: @44873 19577 GIM_Reject, 19578 // Label 1504: @44874 19579 GIM_Try, /*On fail goto*//*Label 1526*/ 44963, 19580 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, 19581 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 19582 GIM_Try, /*On fail goto*//*Label 1527*/ 44910, // Rule ID 1911 // 19583 GIM_CheckFeatures, GIFBS_HasAVX_NoVLX, 19584 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 19585 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 19586 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 19587 // (fmul:{ *:[v2f64] } VR128:{ *:[v2f64] }:$src1, VR128:{ *:[v2f64] }:$src2) => (VMULPDrr:{ *:[v2f64] } VR128:{ *:[v2f64] }:$src1, VR128:{ *:[v2f64] }:$src2) 19588 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VMULPDrr, 19589 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 19590 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 19591 // GIR_Coverage, 1911, 19592 GIR_Done, 19593 // Label 1527: @44910 19594 GIM_Try, /*On fail goto*//*Label 1528*/ 44936, // Rule ID 1927 // 19595 GIM_CheckFeatures, GIFBS_UseSSE2, 19596 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 19597 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 19598 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 19599 // (fmul:{ *:[v2f64] } VR128:{ *:[v2f64] }:$src1, VR128:{ *:[v2f64] }:$src2) => (MULPDrr:{ *:[v2f64] } VR128:{ *:[v2f64] }:$src1, VR128:{ *:[v2f64] }:$src2) 19600 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::MULPDrr, 19601 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 19602 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 19603 // GIR_Coverage, 1927, 19604 GIR_Done, 19605 // Label 1528: @44936 19606 GIM_Try, /*On fail goto*//*Label 1529*/ 44962, // Rule ID 6049 // 19607 GIM_CheckFeatures, GIFBS_HasAVX512_HasVLX, 19608 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID, 19609 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID, 19610 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128XRegClassID, 19611 // (fmul:{ *:[v2f64] } VR128X:{ *:[v2f64] }:$src1, VR128X:{ *:[v2f64] }:$src2) => (VMULPDZ128rr:{ *:[v2f64] } VR128X:{ *:[v2f64] }:$src1, VR128X:{ *:[v2f64] }:$src2) 19612 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VMULPDZ128rr, 19613 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 19614 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 19615 // GIR_Coverage, 6049, 19616 GIR_Done, 19617 // Label 1529: @44962 19618 GIM_Reject, 19619 // Label 1526: @44963 19620 GIM_Reject, 19621 // Label 1505: @44964 19622 GIM_Try, /*On fail goto*//*Label 1530*/ 45053, 19623 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, 19624 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 19625 GIM_Try, /*On fail goto*//*Label 1531*/ 45000, // Rule ID 1907 // 19626 GIM_CheckFeatures, GIFBS_HasAVX_NoVLX, 19627 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 19628 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 19629 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 19630 // (fmul:{ *:[v4f32] } VR128:{ *:[v4f32] }:$src1, VR128:{ *:[v4f32] }:$src2) => (VMULPSrr:{ *:[v4f32] } VR128:{ *:[v4f32] }:$src1, VR128:{ *:[v4f32] }:$src2) 19631 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VMULPSrr, 19632 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 19633 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 19634 // GIR_Coverage, 1907, 19635 GIR_Done, 19636 // Label 1531: @45000 19637 GIM_Try, /*On fail goto*//*Label 1532*/ 45026, // Rule ID 1923 // 19638 GIM_CheckFeatures, GIFBS_UseSSE1, 19639 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 19640 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 19641 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 19642 // (fmul:{ *:[v4f32] } VR128:{ *:[v4f32] }:$src1, VR128:{ *:[v4f32] }:$src2) => (MULPSrr:{ *:[v4f32] } VR128:{ *:[v4f32] }:$src1, VR128:{ *:[v4f32] }:$src2) 19643 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::MULPSrr, 19644 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 19645 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 19646 // GIR_Coverage, 1923, 19647 GIR_Done, 19648 // Label 1532: @45026 19649 GIM_Try, /*On fail goto*//*Label 1533*/ 45052, // Rule ID 6025 // 19650 GIM_CheckFeatures, GIFBS_HasAVX512_HasVLX, 19651 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID, 19652 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID, 19653 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128XRegClassID, 19654 // (fmul:{ *:[v4f32] } VR128X:{ *:[v4f32] }:$src1, VR128X:{ *:[v4f32] }:$src2) => (VMULPSZ128rr:{ *:[v4f32] } VR128X:{ *:[v4f32] }:$src1, VR128X:{ *:[v4f32] }:$src2) 19655 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VMULPSZ128rr, 19656 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 19657 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 19658 // GIR_Coverage, 6025, 19659 GIR_Done, 19660 // Label 1533: @45052 19661 GIM_Reject, 19662 // Label 1530: @45053 19663 GIM_Reject, 19664 // Label 1506: @45054 19665 GIM_Try, /*On fail goto*//*Label 1534*/ 45117, 19666 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s64, 19667 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s64, 19668 GIM_Try, /*On fail goto*//*Label 1535*/ 45090, // Rule ID 1919 // 19669 GIM_CheckFeatures, GIFBS_HasAVX_NoVLX, 19670 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID, 19671 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256RegClassID, 19672 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256RegClassID, 19673 // (fmul:{ *:[v4f64] } VR256:{ *:[v4f64] }:$src1, VR256:{ *:[v4f64] }:$src2) => (VMULPDYrr:{ *:[v4f64] } VR256:{ *:[v4f64] }:$src1, VR256:{ *:[v4f64] }:$src2) 19674 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VMULPDYrr, 19675 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 19676 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 19677 // GIR_Coverage, 1919, 19678 GIR_Done, 19679 // Label 1535: @45090 19680 GIM_Try, /*On fail goto*//*Label 1536*/ 45116, // Rule ID 6061 // 19681 GIM_CheckFeatures, GIFBS_HasAVX512_HasVLX, 19682 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID, 19683 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID, 19684 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256XRegClassID, 19685 // (fmul:{ *:[v4f64] } VR256X:{ *:[v4f64] }:$src1, VR256X:{ *:[v4f64] }:$src2) => (VMULPDZ256rr:{ *:[v4f64] } VR256X:{ *:[v4f64] }:$src1, VR256X:{ *:[v4f64] }:$src2) 19686 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VMULPDZ256rr, 19687 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 19688 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 19689 // GIR_Coverage, 6061, 19690 GIR_Done, 19691 // Label 1536: @45116 19692 GIM_Reject, 19693 // Label 1534: @45117 19694 GIM_Reject, 19695 // Label 1507: @45118 19696 GIM_Try, /*On fail goto*//*Label 1537*/ 45152, // Rule ID 6085 // 19697 GIM_CheckFeatures, GIFBS_HasFP16_HasVLX, 19698 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, 19699 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 19700 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID, 19701 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID, 19702 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128XRegClassID, 19703 // (fmul:{ *:[v8f16] } VR128X:{ *:[v8f16] }:$src1, VR128X:{ *:[v8f16] }:$src2) => (VMULPHZ128rr:{ *:[v8f16] } VR128X:{ *:[v8f16] }:$src1, VR128X:{ *:[v8f16] }:$src2) 19704 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VMULPHZ128rr, 19705 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 19706 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 19707 // GIR_Coverage, 6085, 19708 GIR_Done, 19709 // Label 1537: @45152 19710 GIM_Reject, 19711 // Label 1508: @45153 19712 GIM_Try, /*On fail goto*//*Label 1538*/ 45216, 19713 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s32, 19714 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s32, 19715 GIM_Try, /*On fail goto*//*Label 1539*/ 45189, // Rule ID 1915 // 19716 GIM_CheckFeatures, GIFBS_HasAVX_NoVLX, 19717 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID, 19718 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256RegClassID, 19719 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256RegClassID, 19720 // (fmul:{ *:[v8f32] } VR256:{ *:[v8f32] }:$src1, VR256:{ *:[v8f32] }:$src2) => (VMULPSYrr:{ *:[v8f32] } VR256:{ *:[v8f32] }:$src1, VR256:{ *:[v8f32] }:$src2) 19721 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VMULPSYrr, 19722 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 19723 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 19724 // GIR_Coverage, 1915, 19725 GIR_Done, 19726 // Label 1539: @45189 19727 GIM_Try, /*On fail goto*//*Label 1540*/ 45215, // Rule ID 6037 // 19728 GIM_CheckFeatures, GIFBS_HasAVX512_HasVLX, 19729 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID, 19730 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID, 19731 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256XRegClassID, 19732 // (fmul:{ *:[v8f32] } VR256X:{ *:[v8f32] }:$src1, VR256X:{ *:[v8f32] }:$src2) => (VMULPSZ256rr:{ *:[v8f32] } VR256X:{ *:[v8f32] }:$src1, VR256X:{ *:[v8f32] }:$src2) 19733 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VMULPSZ256rr, 19734 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 19735 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 19736 // GIR_Coverage, 6037, 19737 GIR_Done, 19738 // Label 1540: @45215 19739 GIM_Reject, 19740 // Label 1538: @45216 19741 GIM_Reject, 19742 // Label 1509: @45217 19743 GIM_Try, /*On fail goto*//*Label 1541*/ 45251, // Rule ID 6013 // 19744 GIM_CheckFeatures, GIFBS_HasAVX512, 19745 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s64, 19746 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s64, 19747 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 19748 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR512RegClassID, 19749 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR512RegClassID, 19750 // (fmul:{ *:[v8f64] } VR512:{ *:[v8f64] }:$src1, VR512:{ *:[v8f64] }:$src2) => (VMULPDZrr:{ *:[v8f64] } VR512:{ *:[v8f64] }:$src1, VR512:{ *:[v8f64] }:$src2) 19751 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VMULPDZrr, 19752 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 19753 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 19754 // GIR_Coverage, 6013, 19755 GIR_Done, 19756 // Label 1541: @45251 19757 GIM_Reject, 19758 // Label 1510: @45252 19759 GIM_Try, /*On fail goto*//*Label 1542*/ 45286, // Rule ID 6097 // 19760 GIM_CheckFeatures, GIFBS_HasFP16_HasVLX, 19761 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s16, 19762 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s16, 19763 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID, 19764 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID, 19765 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256XRegClassID, 19766 // (fmul:{ *:[v16f16] } VR256X:{ *:[v16f16] }:$src1, VR256X:{ *:[v16f16] }:$src2) => (VMULPHZ256rr:{ *:[v16f16] } VR256X:{ *:[v16f16] }:$src1, VR256X:{ *:[v16f16] }:$src2) 19767 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VMULPHZ256rr, 19768 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 19769 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 19770 // GIR_Coverage, 6097, 19771 GIR_Done, 19772 // Label 1542: @45286 19773 GIM_Reject, 19774 // Label 1511: @45287 19775 GIM_Try, /*On fail goto*//*Label 1543*/ 45321, // Rule ID 6001 // 19776 GIM_CheckFeatures, GIFBS_HasAVX512, 19777 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s32, 19778 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s32, 19779 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 19780 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR512RegClassID, 19781 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR512RegClassID, 19782 // (fmul:{ *:[v16f32] } VR512:{ *:[v16f32] }:$src1, VR512:{ *:[v16f32] }:$src2) => (VMULPSZrr:{ *:[v16f32] } VR512:{ *:[v16f32] }:$src1, VR512:{ *:[v16f32] }:$src2) 19783 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VMULPSZrr, 19784 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 19785 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 19786 // GIR_Coverage, 6001, 19787 GIR_Done, 19788 // Label 1543: @45321 19789 GIM_Reject, 19790 // Label 1512: @45322 19791 GIM_Try, /*On fail goto*//*Label 1544*/ 45356, // Rule ID 6073 // 19792 GIM_CheckFeatures, GIFBS_HasFP16, 19793 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v32s16, 19794 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v32s16, 19795 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 19796 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR512RegClassID, 19797 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR512RegClassID, 19798 // (fmul:{ *:[v32f16] } VR512:{ *:[v32f16] }:$src1, VR512:{ *:[v32f16] }:$src2) => (VMULPHZrr:{ *:[v32f16] } VR512:{ *:[v32f16] }:$src1, VR512:{ *:[v32f16] }:$src2) 19799 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VMULPHZrr, 19800 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 19801 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 19802 // GIR_Coverage, 6073, 19803 GIR_Done, 19804 // Label 1544: @45356 19805 GIM_Reject, 19806 // Label 1513: @45357 19807 GIM_Reject, 19808 // Label 34: @45358 19809 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/2, 23, /*)*//*default:*//*Label 1557*/ 46531, 19810 /*GILLT_s16*//*Label 1545*/ 45385, 19811 /*GILLT_s32*//*Label 1546*/ 45442, 19812 /*GILLT_s64*//*Label 1547*/ 45576, 0, 0, 0, 19813 /*GILLT_v2s64*//*Label 1548*/ 45710, 0, 19814 /*GILLT_v4s32*//*Label 1549*/ 45844, 19815 /*GILLT_v4s64*//*Label 1550*/ 45978, 0, 19816 /*GILLT_v8s16*//*Label 1551*/ 46112, 19817 /*GILLT_v8s32*//*Label 1552*/ 46169, 19818 /*GILLT_v8s64*//*Label 1553*/ 46303, 0, 0, 19819 /*GILLT_v16s16*//*Label 1554*/ 46360, 19820 /*GILLT_v16s32*//*Label 1555*/ 46417, 0, 0, 19821 /*GILLT_v32s16*//*Label 1556*/ 46474, 19822 // Label 1545: @45385 19823 GIM_Try, /*On fail goto*//*Label 1558*/ 45441, // Rule ID 9724 // 19824 GIM_CheckFeatures, GIFBS_HasFP16, 19825 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16, 19826 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16, 19827 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s16, 19828 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::FR16XRegClassID, 19829 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::FR16XRegClassID, 19830 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::FR16XRegClassID, 19831 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::FR16XRegClassID, 19832 // (fma:{ *:[f16] } FR16X:{ *:[f16] }:$src2, FR16X:{ *:[f16] }:$src1, FR16X:{ *:[f16] }:$src3) => (VFMADD213SHZr:{ *:[f16] } FR16X:{ *:[f16] }:$src1, FR16X:{ *:[f16] }:$src2, FR16X:{ *:[f16] }:$src3) 19833 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VFMADD213SHZr, 19834 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 19835 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 19836 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src2 19837 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src3 19838 GIR_EraseFromParent, /*InsnID*/0, 19839 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 19840 // GIR_Coverage, 9724, 19841 GIR_Done, 19842 // Label 1558: @45441 19843 GIM_Reject, 19844 // Label 1546: @45442 19845 GIM_Try, /*On fail goto*//*Label 1559*/ 45575, 19846 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 19847 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 19848 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 19849 GIM_Try, /*On fail goto*//*Label 1560*/ 45500, // Rule ID 1030 // 19850 GIM_CheckFeatures, GIFBS_HasFMA_NoAVX512_NoFMA4, 19851 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::FR32RegClassID, 19852 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::FR32RegClassID, 19853 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::FR32RegClassID, 19854 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::FR32RegClassID, 19855 // (fma:{ *:[f32] } FR32:{ *:[f32] }:$src2, FR32:{ *:[f32] }:$src1, FR32:{ *:[f32] }:$src3) => (VFMADD213SSr:{ *:[f32] } FR32:{ *:[f32] }:$src1, FR32:{ *:[f32] }:$src2, FR32:{ *:[f32] }:$src3) 19856 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VFMADD213SSr, 19857 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 19858 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 19859 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src2 19860 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src3 19861 GIR_EraseFromParent, /*InsnID*/0, 19862 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 19863 // GIR_Coverage, 1030, 19864 GIR_Done, 19865 // Label 1560: @45500 19866 GIM_Try, /*On fail goto*//*Label 1561*/ 45530, // Rule ID 1094 // 19867 GIM_CheckFeatures, GIFBS_HasFMA4_NoAVX512, 19868 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::FR32RegClassID, 19869 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::FR32RegClassID, 19870 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::FR32RegClassID, 19871 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::FR32RegClassID, 19872 // (fma:{ *:[f32] } FR32:{ *:[f32] }:$src1, FR32:{ *:[f32] }:$src2, FR32:{ *:[f32] }:$src3) => (VFMADDSS4rr:{ *:[f32] } FR32:{ *:[f32] }:$src1, FR32:{ *:[f32] }:$src2, FR32:{ *:[f32] }:$src3) 19873 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VFMADDSS4rr, 19874 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 19875 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 19876 // GIR_Coverage, 1094, 19877 GIR_Done, 19878 // Label 1561: @45530 19879 GIM_Try, /*On fail goto*//*Label 1562*/ 45574, // Rule ID 9706 // 19880 GIM_CheckFeatures, GIFBS_HasAVX512, 19881 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::FR32XRegClassID, 19882 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::FR32XRegClassID, 19883 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::FR32XRegClassID, 19884 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::FR32XRegClassID, 19885 // (fma:{ *:[f32] } FR32X:{ *:[f32] }:$src2, FR32X:{ *:[f32] }:$src1, FR32X:{ *:[f32] }:$src3) => (VFMADD213SSZr:{ *:[f32] } FR32X:{ *:[f32] }:$src1, FR32X:{ *:[f32] }:$src2, FR32X:{ *:[f32] }:$src3) 19886 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VFMADD213SSZr, 19887 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 19888 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 19889 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src2 19890 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src3 19891 GIR_EraseFromParent, /*InsnID*/0, 19892 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 19893 // GIR_Coverage, 9706, 19894 GIR_Done, 19895 // Label 1562: @45574 19896 GIM_Reject, 19897 // Label 1559: @45575 19898 GIM_Reject, 19899 // Label 1547: @45576 19900 GIM_Try, /*On fail goto*//*Label 1563*/ 45709, 19901 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 19902 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 19903 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, 19904 GIM_Try, /*On fail goto*//*Label 1564*/ 45634, // Rule ID 1038 // 19905 GIM_CheckFeatures, GIFBS_HasFMA_NoAVX512_NoFMA4, 19906 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::FR64RegClassID, 19907 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::FR64RegClassID, 19908 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::FR64RegClassID, 19909 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::FR64RegClassID, 19910 // (fma:{ *:[f64] } FR64:{ *:[f64] }:$src2, FR64:{ *:[f64] }:$src1, FR64:{ *:[f64] }:$src3) => (VFMADD213SDr:{ *:[f64] } FR64:{ *:[f64] }:$src1, FR64:{ *:[f64] }:$src2, FR64:{ *:[f64] }:$src3) 19911 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VFMADD213SDr, 19912 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 19913 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 19914 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src2 19915 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src3 19916 GIR_EraseFromParent, /*InsnID*/0, 19917 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 19918 // GIR_Coverage, 1038, 19919 GIR_Done, 19920 // Label 1564: @45634 19921 GIM_Try, /*On fail goto*//*Label 1565*/ 45664, // Rule ID 1178 // 19922 GIM_CheckFeatures, GIFBS_HasFMA4_NoAVX512, 19923 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::FR64RegClassID, 19924 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::FR64RegClassID, 19925 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::FR64RegClassID, 19926 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::FR64RegClassID, 19927 // (fma:{ *:[f64] } FR64:{ *:[f64] }:$src1, FR64:{ *:[f64] }:$src2, FR64:{ *:[f64] }:$src3) => (VFMADDSD4rr:{ *:[f64] } FR64:{ *:[f64] }:$src1, FR64:{ *:[f64] }:$src2, FR64:{ *:[f64] }:$src3) 19928 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VFMADDSD4rr, 19929 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 19930 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 19931 // GIR_Coverage, 1178, 19932 GIR_Done, 19933 // Label 1565: @45664 19934 GIM_Try, /*On fail goto*//*Label 1566*/ 45708, // Rule ID 9715 // 19935 GIM_CheckFeatures, GIFBS_HasAVX512, 19936 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::FR64XRegClassID, 19937 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::FR64XRegClassID, 19938 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::FR64XRegClassID, 19939 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::FR64XRegClassID, 19940 // (fma:{ *:[f64] } FR64X:{ *:[f64] }:$src2, FR64X:{ *:[f64] }:$src1, FR64X:{ *:[f64] }:$src3) => (VFMADD213SDZr:{ *:[f64] } FR64X:{ *:[f64] }:$src1, FR64X:{ *:[f64] }:$src2, FR64X:{ *:[f64] }:$src3) 19941 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VFMADD213SDZr, 19942 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 19943 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 19944 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src2 19945 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src3 19946 GIR_EraseFromParent, /*InsnID*/0, 19947 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 19948 // GIR_Coverage, 9715, 19949 GIR_Done, 19950 // Label 1566: @45708 19951 GIM_Reject, 19952 // Label 1563: @45709 19953 GIM_Reject, 19954 // Label 1548: @45710 19955 GIM_Try, /*On fail goto*//*Label 1567*/ 45843, 19956 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, 19957 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 19958 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, 19959 GIM_Try, /*On fail goto*//*Label 1568*/ 45768, // Rule ID 918 // 19960 GIM_CheckFeatures, GIFBS_HasFMA_NoFMA4_NoVLX, 19961 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 19962 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 19963 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 19964 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::VR128RegClassID, 19965 // (fma:{ *:[v2f64] } VR128:{ *:[v2f64] }:$src2, VR128:{ *:[v2f64] }:$src1, VR128:{ *:[v2f64] }:$src3) => (VFMADD213PDr:{ *:[v2f64] } VR128:{ *:[v2f64] }:$src1, VR128:{ *:[v2f64] }:$src2, VR128:{ *:[v2f64] }:$src3) 19966 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VFMADD213PDr, 19967 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 19968 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 19969 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src2 19970 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src3 19971 GIR_EraseFromParent, /*InsnID*/0, 19972 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 19973 // GIR_Coverage, 918, 19974 GIR_Done, 19975 // Label 1568: @45768 19976 GIM_Try, /*On fail goto*//*Label 1569*/ 45798, // Rule ID 1202 // 19977 GIM_CheckFeatures, GIFBS_HasFMA4_NoVLX, 19978 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 19979 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 19980 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 19981 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::VR128RegClassID, 19982 // (fma:{ *:[v2f64] } VR128:{ *:[v2f64] }:$src1, VR128:{ *:[v2f64] }:$src2, VR128:{ *:[v2f64] }:$src3) => (VFMADDPD4rr:{ *:[v2f64] } VR128:{ *:[v2f64] }:$src1, VR128:{ *:[v2f64] }:$src2, VR128:{ *:[v2f64] }:$src3) 19983 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VFMADDPD4rr, 19984 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 19985 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 19986 // GIR_Coverage, 1202, 19987 GIR_Done, 19988 // Label 1569: @45798 19989 GIM_Try, /*On fail goto*//*Label 1570*/ 45842, // Rule ID 8083 // 19990 GIM_CheckFeatures, GIFBS_HasAVX512_HasVLX, 19991 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID, 19992 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID, 19993 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128XRegClassID, 19994 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::VR128XRegClassID, 19995 // (fma:{ *:[v2f64] } VR128X:{ *:[v2f64] }:$src2, VR128X:{ *:[v2f64] }:$src1, VR128X:{ *:[v2f64] }:$src3) => (VFMADD213PDZ128r:{ *:[v2f64] } VR128X:{ *:[v2f64] }:$src1, VR128X:{ *:[v2f64] }:$src2, VR128X:{ *:[v2f64] }:$src3) 19996 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VFMADD213PDZ128r, 19997 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 19998 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 19999 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src2 20000 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src3 20001 GIR_EraseFromParent, /*InsnID*/0, 20002 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 20003 // GIR_Coverage, 8083, 20004 GIR_Done, 20005 // Label 1570: @45842 20006 GIM_Reject, 20007 // Label 1567: @45843 20008 GIM_Reject, 20009 // Label 1549: @45844 20010 GIM_Try, /*On fail goto*//*Label 1571*/ 45977, 20011 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, 20012 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 20013 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, 20014 GIM_Try, /*On fail goto*//*Label 1572*/ 45902, // Rule ID 870 // 20015 GIM_CheckFeatures, GIFBS_HasFMA_NoFMA4_NoVLX, 20016 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 20017 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 20018 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 20019 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::VR128RegClassID, 20020 // (fma:{ *:[v4f32] } VR128:{ *:[v4f32] }:$src2, VR128:{ *:[v4f32] }:$src1, VR128:{ *:[v4f32] }:$src3) => (VFMADD213PSr:{ *:[v4f32] } VR128:{ *:[v4f32] }:$src1, VR128:{ *:[v4f32] }:$src2, VR128:{ *:[v4f32] }:$src3) 20021 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VFMADD213PSr, 20022 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 20023 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 20024 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src2 20025 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src3 20026 GIR_EraseFromParent, /*InsnID*/0, 20027 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 20028 // GIR_Coverage, 870, 20029 GIR_Done, 20030 // Label 1572: @45902 20031 GIM_Try, /*On fail goto*//*Label 1573*/ 45932, // Rule ID 1118 // 20032 GIM_CheckFeatures, GIFBS_HasFMA4_NoVLX, 20033 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 20034 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 20035 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 20036 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::VR128RegClassID, 20037 // (fma:{ *:[v4f32] } VR128:{ *:[v4f32] }:$src1, VR128:{ *:[v4f32] }:$src2, VR128:{ *:[v4f32] }:$src3) => (VFMADDPS4rr:{ *:[v4f32] } VR128:{ *:[v4f32] }:$src1, VR128:{ *:[v4f32] }:$src2, VR128:{ *:[v4f32] }:$src3) 20038 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VFMADDPS4rr, 20039 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 20040 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 20041 // GIR_Coverage, 1118, 20042 GIR_Done, 20043 // Label 1573: @45932 20044 GIM_Try, /*On fail goto*//*Label 1574*/ 45976, // Rule ID 8044 // 20045 GIM_CheckFeatures, GIFBS_HasAVX512_HasVLX, 20046 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID, 20047 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID, 20048 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128XRegClassID, 20049 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::VR128XRegClassID, 20050 // (fma:{ *:[v4f32] } VR128X:{ *:[v4f32] }:$src2, VR128X:{ *:[v4f32] }:$src1, VR128X:{ *:[v4f32] }:$src3) => (VFMADD213PSZ128r:{ *:[v4f32] } VR128X:{ *:[v4f32] }:$src1, VR128X:{ *:[v4f32] }:$src2, VR128X:{ *:[v4f32] }:$src3) 20051 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VFMADD213PSZ128r, 20052 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 20053 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 20054 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src2 20055 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src3 20056 GIR_EraseFromParent, /*InsnID*/0, 20057 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 20058 // GIR_Coverage, 8044, 20059 GIR_Done, 20060 // Label 1574: @45976 20061 GIM_Reject, 20062 // Label 1571: @45977 20063 GIM_Reject, 20064 // Label 1550: @45978 20065 GIM_Try, /*On fail goto*//*Label 1575*/ 46111, 20066 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s64, 20067 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s64, 20068 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s64, 20069 GIM_Try, /*On fail goto*//*Label 1576*/ 46036, // Rule ID 926 // 20070 GIM_CheckFeatures, GIFBS_HasFMA_NoFMA4_NoVLX, 20071 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID, 20072 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256RegClassID, 20073 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256RegClassID, 20074 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::VR256RegClassID, 20075 // (fma:{ *:[v4f64] } VR256:{ *:[v4f64] }:$src2, VR256:{ *:[v4f64] }:$src1, VR256:{ *:[v4f64] }:$src3) => (VFMADD213PDYr:{ *:[v4f64] } VR256:{ *:[v4f64] }:$src1, VR256:{ *:[v4f64] }:$src2, VR256:{ *:[v4f64] }:$src3) 20076 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VFMADD213PDYr, 20077 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 20078 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 20079 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src2 20080 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src3 20081 GIR_EraseFromParent, /*InsnID*/0, 20082 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 20083 // GIR_Coverage, 926, 20084 GIR_Done, 20085 // Label 1576: @46036 20086 GIM_Try, /*On fail goto*//*Label 1577*/ 46066, // Rule ID 1208 // 20087 GIM_CheckFeatures, GIFBS_HasFMA4_NoVLX, 20088 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID, 20089 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256RegClassID, 20090 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256RegClassID, 20091 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::VR256RegClassID, 20092 // (fma:{ *:[v4f64] } VR256:{ *:[v4f64] }:$src1, VR256:{ *:[v4f64] }:$src2, VR256:{ *:[v4f64] }:$src3) => (VFMADDPD4Yrr:{ *:[v4f64] } VR256:{ *:[v4f64] }:$src1, VR256:{ *:[v4f64] }:$src2, VR256:{ *:[v4f64] }:$src3) 20093 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VFMADDPD4Yrr, 20094 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 20095 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 20096 // GIR_Coverage, 1208, 20097 GIR_Done, 20098 // Label 1577: @46066 20099 GIM_Try, /*On fail goto*//*Label 1578*/ 46110, // Rule ID 8071 // 20100 GIM_CheckFeatures, GIFBS_HasAVX512_HasVLX, 20101 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID, 20102 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID, 20103 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256XRegClassID, 20104 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::VR256XRegClassID, 20105 // (fma:{ *:[v4f64] } VR256X:{ *:[v4f64] }:$src2, VR256X:{ *:[v4f64] }:$src1, VR256X:{ *:[v4f64] }:$src3) => (VFMADD213PDZ256r:{ *:[v4f64] } VR256X:{ *:[v4f64] }:$src1, VR256X:{ *:[v4f64] }:$src2, VR256X:{ *:[v4f64] }:$src3) 20106 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VFMADD213PDZ256r, 20107 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 20108 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 20109 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src2 20110 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src3 20111 GIR_EraseFromParent, /*InsnID*/0, 20112 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 20113 // GIR_Coverage, 8071, 20114 GIR_Done, 20115 // Label 1578: @46110 20116 GIM_Reject, 20117 // Label 1575: @46111 20118 GIM_Reject, 20119 // Label 1551: @46112 20120 GIM_Try, /*On fail goto*//*Label 1579*/ 46168, // Rule ID 8005 // 20121 GIM_CheckFeatures, GIFBS_HasFP16_HasVLX, 20122 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, 20123 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 20124 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, 20125 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID, 20126 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID, 20127 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128XRegClassID, 20128 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::VR128XRegClassID, 20129 // (fma:{ *:[v8f16] } VR128X:{ *:[v8f16] }:$src2, VR128X:{ *:[v8f16] }:$src1, VR128X:{ *:[v8f16] }:$src3) => (VFMADD213PHZ128r:{ *:[v8f16] } VR128X:{ *:[v8f16] }:$src1, VR128X:{ *:[v8f16] }:$src2, VR128X:{ *:[v8f16] }:$src3) 20130 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VFMADD213PHZ128r, 20131 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 20132 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 20133 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src2 20134 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src3 20135 GIR_EraseFromParent, /*InsnID*/0, 20136 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 20137 // GIR_Coverage, 8005, 20138 GIR_Done, 20139 // Label 1579: @46168 20140 GIM_Reject, 20141 // Label 1552: @46169 20142 GIM_Try, /*On fail goto*//*Label 1580*/ 46302, 20143 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s32, 20144 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s32, 20145 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s32, 20146 GIM_Try, /*On fail goto*//*Label 1581*/ 46227, // Rule ID 878 // 20147 GIM_CheckFeatures, GIFBS_HasFMA_NoFMA4_NoVLX, 20148 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID, 20149 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256RegClassID, 20150 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256RegClassID, 20151 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::VR256RegClassID, 20152 // (fma:{ *:[v8f32] } VR256:{ *:[v8f32] }:$src2, VR256:{ *:[v8f32] }:$src1, VR256:{ *:[v8f32] }:$src3) => (VFMADD213PSYr:{ *:[v8f32] } VR256:{ *:[v8f32] }:$src1, VR256:{ *:[v8f32] }:$src2, VR256:{ *:[v8f32] }:$src3) 20153 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VFMADD213PSYr, 20154 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 20155 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 20156 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src2 20157 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src3 20158 GIR_EraseFromParent, /*InsnID*/0, 20159 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 20160 // GIR_Coverage, 878, 20161 GIR_Done, 20162 // Label 1581: @46227 20163 GIM_Try, /*On fail goto*//*Label 1582*/ 46257, // Rule ID 1124 // 20164 GIM_CheckFeatures, GIFBS_HasFMA4_NoVLX, 20165 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID, 20166 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256RegClassID, 20167 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256RegClassID, 20168 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::VR256RegClassID, 20169 // (fma:{ *:[v8f32] } VR256:{ *:[v8f32] }:$src1, VR256:{ *:[v8f32] }:$src2, VR256:{ *:[v8f32] }:$src3) => (VFMADDPS4Yrr:{ *:[v8f32] } VR256:{ *:[v8f32] }:$src1, VR256:{ *:[v8f32] }:$src2, VR256:{ *:[v8f32] }:$src3) 20170 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VFMADDPS4Yrr, 20171 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 20172 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 20173 // GIR_Coverage, 1124, 20174 GIR_Done, 20175 // Label 1582: @46257 20176 GIM_Try, /*On fail goto*//*Label 1583*/ 46301, // Rule ID 8032 // 20177 GIM_CheckFeatures, GIFBS_HasAVX512_HasVLX, 20178 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID, 20179 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID, 20180 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256XRegClassID, 20181 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::VR256XRegClassID, 20182 // (fma:{ *:[v8f32] } VR256X:{ *:[v8f32] }:$src2, VR256X:{ *:[v8f32] }:$src1, VR256X:{ *:[v8f32] }:$src3) => (VFMADD213PSZ256r:{ *:[v8f32] } VR256X:{ *:[v8f32] }:$src1, VR256X:{ *:[v8f32] }:$src2, VR256X:{ *:[v8f32] }:$src3) 20183 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VFMADD213PSZ256r, 20184 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 20185 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 20186 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src2 20187 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src3 20188 GIR_EraseFromParent, /*InsnID*/0, 20189 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 20190 // GIR_Coverage, 8032, 20191 GIR_Done, 20192 // Label 1583: @46301 20193 GIM_Reject, 20194 // Label 1580: @46302 20195 GIM_Reject, 20196 // Label 1553: @46303 20197 GIM_Try, /*On fail goto*//*Label 1584*/ 46359, // Rule ID 8056 // 20198 GIM_CheckFeatures, GIFBS_HasAVX512, 20199 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s64, 20200 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s64, 20201 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s64, 20202 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 20203 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR512RegClassID, 20204 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR512RegClassID, 20205 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::VR512RegClassID, 20206 // (fma:{ *:[v8f64] } VR512:{ *:[v8f64] }:$src2, VR512:{ *:[v8f64] }:$src1, VR512:{ *:[v8f64] }:$src3) => (VFMADD213PDZr:{ *:[v8f64] } VR512:{ *:[v8f64] }:$src1, VR512:{ *:[v8f64] }:$src2, VR512:{ *:[v8f64] }:$src3) 20207 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VFMADD213PDZr, 20208 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 20209 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 20210 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src2 20211 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src3 20212 GIR_EraseFromParent, /*InsnID*/0, 20213 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 20214 // GIR_Coverage, 8056, 20215 GIR_Done, 20216 // Label 1584: @46359 20217 GIM_Reject, 20218 // Label 1554: @46360 20219 GIM_Try, /*On fail goto*//*Label 1585*/ 46416, // Rule ID 7993 // 20220 GIM_CheckFeatures, GIFBS_HasFP16_HasVLX, 20221 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s16, 20222 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s16, 20223 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s16, 20224 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID, 20225 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID, 20226 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256XRegClassID, 20227 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::VR256XRegClassID, 20228 // (fma:{ *:[v16f16] } VR256X:{ *:[v16f16] }:$src2, VR256X:{ *:[v16f16] }:$src1, VR256X:{ *:[v16f16] }:$src3) => (VFMADD213PHZ256r:{ *:[v16f16] } VR256X:{ *:[v16f16] }:$src1, VR256X:{ *:[v16f16] }:$src2, VR256X:{ *:[v16f16] }:$src3) 20229 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VFMADD213PHZ256r, 20230 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 20231 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 20232 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src2 20233 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src3 20234 GIR_EraseFromParent, /*InsnID*/0, 20235 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 20236 // GIR_Coverage, 7993, 20237 GIR_Done, 20238 // Label 1585: @46416 20239 GIM_Reject, 20240 // Label 1555: @46417 20241 GIM_Try, /*On fail goto*//*Label 1586*/ 46473, // Rule ID 8017 // 20242 GIM_CheckFeatures, GIFBS_HasAVX512, 20243 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s32, 20244 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s32, 20245 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s32, 20246 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 20247 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR512RegClassID, 20248 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR512RegClassID, 20249 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::VR512RegClassID, 20250 // (fma:{ *:[v16f32] } VR512:{ *:[v16f32] }:$src2, VR512:{ *:[v16f32] }:$src1, VR512:{ *:[v16f32] }:$src3) => (VFMADD213PSZr:{ *:[v16f32] } VR512:{ *:[v16f32] }:$src1, VR512:{ *:[v16f32] }:$src2, VR512:{ *:[v16f32] }:$src3) 20251 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VFMADD213PSZr, 20252 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 20253 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 20254 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src2 20255 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src3 20256 GIR_EraseFromParent, /*InsnID*/0, 20257 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 20258 // GIR_Coverage, 8017, 20259 GIR_Done, 20260 // Label 1586: @46473 20261 GIM_Reject, 20262 // Label 1556: @46474 20263 GIM_Try, /*On fail goto*//*Label 1587*/ 46530, // Rule ID 7978 // 20264 GIM_CheckFeatures, GIFBS_HasFP16, 20265 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v32s16, 20266 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v32s16, 20267 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v32s16, 20268 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 20269 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR512RegClassID, 20270 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR512RegClassID, 20271 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::VR512RegClassID, 20272 // (fma:{ *:[v32f16] } VR512:{ *:[v32f16] }:$src2, VR512:{ *:[v32f16] }:$src1, VR512:{ *:[v32f16] }:$src3) => (VFMADD213PHZr:{ *:[v32f16] } VR512:{ *:[v32f16] }:$src1, VR512:{ *:[v32f16] }:$src2, VR512:{ *:[v32f16] }:$src3) 20273 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VFMADD213PHZr, 20274 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 20275 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 20276 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src2 20277 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src3 20278 GIR_EraseFromParent, /*InsnID*/0, 20279 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 20280 // GIR_Coverage, 7978, 20281 GIR_Done, 20282 // Label 1587: @46530 20283 GIM_Reject, 20284 // Label 1557: @46531 20285 GIM_Reject, 20286 // Label 35: @46532 20287 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/2, 23, /*)*//*default:*//*Label 1601*/ 47353, 20288 /*GILLT_s16*//*Label 1588*/ 46559, 20289 /*GILLT_s32*//*Label 1589*/ 46594, 20290 /*GILLT_s64*//*Label 1590*/ 46713, 20291 /*GILLT_s80*//*Label 1591*/ 46832, 0, 0, 20292 /*GILLT_v2s64*//*Label 1592*/ 46870, 0, 20293 /*GILLT_v4s32*//*Label 1593*/ 46960, 20294 /*GILLT_v4s64*//*Label 1594*/ 47050, 0, 20295 /*GILLT_v8s16*//*Label 1595*/ 47114, 20296 /*GILLT_v8s32*//*Label 1596*/ 47149, 20297 /*GILLT_v8s64*//*Label 1597*/ 47213, 0, 0, 20298 /*GILLT_v16s16*//*Label 1598*/ 47248, 20299 /*GILLT_v16s32*//*Label 1599*/ 47283, 0, 0, 20300 /*GILLT_v32s16*//*Label 1600*/ 47318, 20301 // Label 1588: @46559 20302 GIM_Try, /*On fail goto*//*Label 1602*/ 46593, // Rule ID 5763 // 20303 GIM_CheckFeatures, GIFBS_HasFP16, 20304 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16, 20305 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16, 20306 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::FR16XRegClassID, 20307 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::FR16XRegClassID, 20308 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::FR16XRegClassID, 20309 // (fdiv:{ *:[f16] } FR16X:{ *:[f16] }:$src1, FR16X:{ *:[f16] }:$src2) => (VDIVSHZrr:{ *:[f16] } FR16X:{ *:[f16] }:$src1, FR16X:{ *:[f16] }:$src2) 20310 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VDIVSHZrr, 20311 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 20312 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 20313 // GIR_Coverage, 5763, 20314 GIR_Done, 20315 // Label 1602: @46593 20316 GIM_Reject, 20317 // Label 1589: @46594 20318 GIM_Try, /*On fail goto*//*Label 1603*/ 46712, 20319 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 20320 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 20321 GIM_Try, /*On fail goto*//*Label 1604*/ 46633, // Rule ID 639 // 20322 GIM_CheckFeatures, GIFBS_FPStackf32, 20323 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::RFP32RegClassID, 20324 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::RFP32RegClassID, 20325 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::RFP32RegClassID, 20326 // (fdiv:{ *:[f32] } RFP32:{ *:[f32] }:$src1, RFP32:{ *:[f32] }:$src2) => (DIV_Fp32:{ *:[f32] }:{ *:[i16] } RFP32:{ *:[f32] }:$src1, RFP32:{ *:[f32] }:$src2) 20327 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::DIV_Fp32, 20328 GIR_AddImplicitDef, /*InsnID*/0, X86::FPSW, 20329 GIR_AddImplicitUse, /*InsnID*/0, X86::FPCW, 20330 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 20331 // GIR_Coverage, 639, 20332 GIR_Done, 20333 // Label 1604: @46633 20334 GIM_Try, /*On fail goto*//*Label 1605*/ 46659, // Rule ID 2011 // 20335 GIM_CheckFeatures, GIFBS_UseAVX, 20336 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::FR32RegClassID, 20337 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::FR32RegClassID, 20338 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::FR32RegClassID, 20339 // (fdiv:{ *:[f32] } FR32:{ *:[f32] }:$src1, FR32:{ *:[f32] }:$src2) => (VDIVSSrr:{ *:[f32] } FR32:{ *:[f32] }:$src1, FR32:{ *:[f32] }:$src2) 20340 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VDIVSSrr, 20341 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 20342 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 20343 // GIR_Coverage, 2011, 20344 GIR_Done, 20345 // Label 1605: @46659 20346 GIM_Try, /*On fail goto*//*Label 1606*/ 46685, // Rule ID 2019 // 20347 GIM_CheckFeatures, GIFBS_UseSSE1, 20348 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::FR32RegClassID, 20349 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::FR32RegClassID, 20350 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::FR32RegClassID, 20351 // (fdiv:{ *:[f32] } FR32:{ *:[f32] }:$src1, FR32:{ *:[f32] }:$src2) => (DIVSSrr:{ *:[f32] } FR32:{ *:[f32] }:$src1, FR32:{ *:[f32] }:$src2) 20352 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::DIVSSrr, 20353 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 20354 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 20355 // GIR_Coverage, 2019, 20356 GIR_Done, 20357 // Label 1606: @46685 20358 GIM_Try, /*On fail goto*//*Label 1607*/ 46711, // Rule ID 5725 // 20359 GIM_CheckFeatures, GIFBS_HasAVX512, 20360 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::FR32XRegClassID, 20361 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::FR32XRegClassID, 20362 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::FR32XRegClassID, 20363 // (fdiv:{ *:[f32] } FR32X:{ *:[f32] }:$src1, FR32X:{ *:[f32] }:$src2) => (VDIVSSZrr:{ *:[f32] } FR32X:{ *:[f32] }:$src1, FR32X:{ *:[f32] }:$src2) 20364 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VDIVSSZrr, 20365 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 20366 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 20367 // GIR_Coverage, 5725, 20368 GIR_Done, 20369 // Label 1607: @46711 20370 GIM_Reject, 20371 // Label 1603: @46712 20372 GIM_Reject, 20373 // Label 1590: @46713 20374 GIM_Try, /*On fail goto*//*Label 1608*/ 46831, 20375 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 20376 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 20377 GIM_Try, /*On fail goto*//*Label 1609*/ 46752, // Rule ID 641 // 20378 GIM_CheckFeatures, GIFBS_FPStackf64, 20379 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::RFP64RegClassID, 20380 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::RFP64RegClassID, 20381 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::RFP64RegClassID, 20382 // (fdiv:{ *:[f64] } RFP64:{ *:[f64] }:$src1, RFP64:{ *:[f64] }:$src2) => (DIV_Fp64:{ *:[f64] }:{ *:[i16] } RFP64:{ *:[f64] }:$src1, RFP64:{ *:[f64] }:$src2) 20383 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::DIV_Fp64, 20384 GIR_AddImplicitDef, /*InsnID*/0, X86::FPSW, 20385 GIR_AddImplicitUse, /*InsnID*/0, X86::FPCW, 20386 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 20387 // GIR_Coverage, 641, 20388 GIR_Done, 20389 // Label 1609: @46752 20390 GIM_Try, /*On fail goto*//*Label 1610*/ 46778, // Rule ID 2015 // 20391 GIM_CheckFeatures, GIFBS_UseAVX, 20392 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::FR64RegClassID, 20393 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::FR64RegClassID, 20394 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::FR64RegClassID, 20395 // (fdiv:{ *:[f64] } FR64:{ *:[f64] }:$src1, FR64:{ *:[f64] }:$src2) => (VDIVSDrr:{ *:[f64] } FR64:{ *:[f64] }:$src1, FR64:{ *:[f64] }:$src2) 20396 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VDIVSDrr, 20397 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 20398 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 20399 // GIR_Coverage, 2015, 20400 GIR_Done, 20401 // Label 1610: @46778 20402 GIM_Try, /*On fail goto*//*Label 1611*/ 46804, // Rule ID 2023 // 20403 GIM_CheckFeatures, GIFBS_UseSSE2, 20404 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::FR64RegClassID, 20405 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::FR64RegClassID, 20406 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::FR64RegClassID, 20407 // (fdiv:{ *:[f64] } FR64:{ *:[f64] }:$src1, FR64:{ *:[f64] }:$src2) => (DIVSDrr:{ *:[f64] } FR64:{ *:[f64] }:$src1, FR64:{ *:[f64] }:$src2) 20408 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::DIVSDrr, 20409 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 20410 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 20411 // GIR_Coverage, 2023, 20412 GIR_Done, 20413 // Label 1611: @46804 20414 GIM_Try, /*On fail goto*//*Label 1612*/ 46830, // Rule ID 5744 // 20415 GIM_CheckFeatures, GIFBS_HasAVX512, 20416 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::FR64XRegClassID, 20417 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::FR64XRegClassID, 20418 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::FR64XRegClassID, 20419 // (fdiv:{ *:[f64] } FR64X:{ *:[f64] }:$src1, FR64X:{ *:[f64] }:$src2) => (VDIVSDZrr:{ *:[f64] } FR64X:{ *:[f64] }:$src1, FR64X:{ *:[f64] }:$src2) 20420 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VDIVSDZrr, 20421 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 20422 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 20423 // GIR_Coverage, 5744, 20424 GIR_Done, 20425 // Label 1612: @46830 20426 GIM_Reject, 20427 // Label 1608: @46831 20428 GIM_Reject, 20429 // Label 1591: @46832 20430 GIM_Try, /*On fail goto*//*Label 1613*/ 46869, // Rule ID 643 // 20431 GIM_CheckFeatures, GIFBS_HasX87, 20432 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s80, 20433 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s80, 20434 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::RFP80RegClassID, 20435 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::RFP80RegClassID, 20436 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::RFP80RegClassID, 20437 // (fdiv:{ *:[f80] } RFP80:{ *:[f80] }:$src1, RFP80:{ *:[f80] }:$src2) => (DIV_Fp80:{ *:[f80] }:{ *:[i16] } RFP80:{ *:[f80] }:$src1, RFP80:{ *:[f80] }:$src2) 20438 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::DIV_Fp80, 20439 GIR_AddImplicitDef, /*InsnID*/0, X86::FPSW, 20440 GIR_AddImplicitUse, /*InsnID*/0, X86::FPCW, 20441 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 20442 // GIR_Coverage, 643, 20443 GIR_Done, 20444 // Label 1613: @46869 20445 GIM_Reject, 20446 // Label 1592: @46870 20447 GIM_Try, /*On fail goto*//*Label 1614*/ 46959, 20448 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, 20449 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 20450 GIM_Try, /*On fail goto*//*Label 1615*/ 46906, // Rule ID 1991 // 20451 GIM_CheckFeatures, GIFBS_HasAVX_NoVLX, 20452 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 20453 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 20454 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 20455 // (fdiv:{ *:[v2f64] } VR128:{ *:[v2f64] }:$src1, VR128:{ *:[v2f64] }:$src2) => (VDIVPDrr:{ *:[v2f64] } VR128:{ *:[v2f64] }:$src1, VR128:{ *:[v2f64] }:$src2) 20456 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VDIVPDrr, 20457 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 20458 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 20459 // GIR_Coverage, 1991, 20460 GIR_Done, 20461 // Label 1615: @46906 20462 GIM_Try, /*On fail goto*//*Label 1616*/ 46932, // Rule ID 2007 // 20463 GIM_CheckFeatures, GIFBS_UseSSE2, 20464 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 20465 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 20466 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 20467 // (fdiv:{ *:[v2f64] } VR128:{ *:[v2f64] }:$src1, VR128:{ *:[v2f64] }:$src2) => (DIVPDrr:{ *:[v2f64] } VR128:{ *:[v2f64] }:$src1, VR128:{ *:[v2f64] }:$src2) 20468 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::DIVPDrr, 20469 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 20470 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 20471 // GIR_Coverage, 2007, 20472 GIR_Done, 20473 // Label 1616: @46932 20474 GIM_Try, /*On fail goto*//*Label 1617*/ 46958, // Rule ID 6283 // 20475 GIM_CheckFeatures, GIFBS_HasAVX512_HasVLX, 20476 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID, 20477 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID, 20478 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128XRegClassID, 20479 // (fdiv:{ *:[v2f64] } VR128X:{ *:[v2f64] }:$src1, VR128X:{ *:[v2f64] }:$src2) => (VDIVPDZ128rr:{ *:[v2f64] } VR128X:{ *:[v2f64] }:$src1, VR128X:{ *:[v2f64] }:$src2) 20480 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VDIVPDZ128rr, 20481 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 20482 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 20483 // GIR_Coverage, 6283, 20484 GIR_Done, 20485 // Label 1617: @46958 20486 GIM_Reject, 20487 // Label 1614: @46959 20488 GIM_Reject, 20489 // Label 1593: @46960 20490 GIM_Try, /*On fail goto*//*Label 1618*/ 47049, 20491 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, 20492 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 20493 GIM_Try, /*On fail goto*//*Label 1619*/ 46996, // Rule ID 1987 // 20494 GIM_CheckFeatures, GIFBS_HasAVX_NoVLX, 20495 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 20496 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 20497 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 20498 // (fdiv:{ *:[v4f32] } VR128:{ *:[v4f32] }:$src1, VR128:{ *:[v4f32] }:$src2) => (VDIVPSrr:{ *:[v4f32] } VR128:{ *:[v4f32] }:$src1, VR128:{ *:[v4f32] }:$src2) 20499 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VDIVPSrr, 20500 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 20501 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 20502 // GIR_Coverage, 1987, 20503 GIR_Done, 20504 // Label 1619: @46996 20505 GIM_Try, /*On fail goto*//*Label 1620*/ 47022, // Rule ID 2003 // 20506 GIM_CheckFeatures, GIFBS_UseSSE1, 20507 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 20508 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 20509 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 20510 // (fdiv:{ *:[v4f32] } VR128:{ *:[v4f32] }:$src1, VR128:{ *:[v4f32] }:$src2) => (DIVPSrr:{ *:[v4f32] } VR128:{ *:[v4f32] }:$src1, VR128:{ *:[v4f32] }:$src2) 20511 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::DIVPSrr, 20512 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 20513 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 20514 // GIR_Coverage, 2003, 20515 GIR_Done, 20516 // Label 1620: @47022 20517 GIM_Try, /*On fail goto*//*Label 1621*/ 47048, // Rule ID 6259 // 20518 GIM_CheckFeatures, GIFBS_HasAVX512_HasVLX, 20519 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID, 20520 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID, 20521 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128XRegClassID, 20522 // (fdiv:{ *:[v4f32] } VR128X:{ *:[v4f32] }:$src1, VR128X:{ *:[v4f32] }:$src2) => (VDIVPSZ128rr:{ *:[v4f32] } VR128X:{ *:[v4f32] }:$src1, VR128X:{ *:[v4f32] }:$src2) 20523 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VDIVPSZ128rr, 20524 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 20525 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 20526 // GIR_Coverage, 6259, 20527 GIR_Done, 20528 // Label 1621: @47048 20529 GIM_Reject, 20530 // Label 1618: @47049 20531 GIM_Reject, 20532 // Label 1594: @47050 20533 GIM_Try, /*On fail goto*//*Label 1622*/ 47113, 20534 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s64, 20535 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s64, 20536 GIM_Try, /*On fail goto*//*Label 1623*/ 47086, // Rule ID 1999 // 20537 GIM_CheckFeatures, GIFBS_HasAVX_NoVLX, 20538 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID, 20539 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256RegClassID, 20540 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256RegClassID, 20541 // (fdiv:{ *:[v4f64] } VR256:{ *:[v4f64] }:$src1, VR256:{ *:[v4f64] }:$src2) => (VDIVPDYrr:{ *:[v4f64] } VR256:{ *:[v4f64] }:$src1, VR256:{ *:[v4f64] }:$src2) 20542 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VDIVPDYrr, 20543 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 20544 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 20545 // GIR_Coverage, 1999, 20546 GIR_Done, 20547 // Label 1623: @47086 20548 GIM_Try, /*On fail goto*//*Label 1624*/ 47112, // Rule ID 6295 // 20549 GIM_CheckFeatures, GIFBS_HasAVX512_HasVLX, 20550 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID, 20551 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID, 20552 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256XRegClassID, 20553 // (fdiv:{ *:[v4f64] } VR256X:{ *:[v4f64] }:$src1, VR256X:{ *:[v4f64] }:$src2) => (VDIVPDZ256rr:{ *:[v4f64] } VR256X:{ *:[v4f64] }:$src1, VR256X:{ *:[v4f64] }:$src2) 20554 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VDIVPDZ256rr, 20555 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 20556 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 20557 // GIR_Coverage, 6295, 20558 GIR_Done, 20559 // Label 1624: @47112 20560 GIM_Reject, 20561 // Label 1622: @47113 20562 GIM_Reject, 20563 // Label 1595: @47114 20564 GIM_Try, /*On fail goto*//*Label 1625*/ 47148, // Rule ID 6319 // 20565 GIM_CheckFeatures, GIFBS_HasFP16_HasVLX, 20566 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, 20567 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 20568 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID, 20569 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID, 20570 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128XRegClassID, 20571 // (fdiv:{ *:[v8f16] } VR128X:{ *:[v8f16] }:$src1, VR128X:{ *:[v8f16] }:$src2) => (VDIVPHZ128rr:{ *:[v8f16] } VR128X:{ *:[v8f16] }:$src1, VR128X:{ *:[v8f16] }:$src2) 20572 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VDIVPHZ128rr, 20573 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 20574 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 20575 // GIR_Coverage, 6319, 20576 GIR_Done, 20577 // Label 1625: @47148 20578 GIM_Reject, 20579 // Label 1596: @47149 20580 GIM_Try, /*On fail goto*//*Label 1626*/ 47212, 20581 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s32, 20582 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s32, 20583 GIM_Try, /*On fail goto*//*Label 1627*/ 47185, // Rule ID 1995 // 20584 GIM_CheckFeatures, GIFBS_HasAVX_NoVLX, 20585 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID, 20586 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256RegClassID, 20587 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256RegClassID, 20588 // (fdiv:{ *:[v8f32] } VR256:{ *:[v8f32] }:$src1, VR256:{ *:[v8f32] }:$src2) => (VDIVPSYrr:{ *:[v8f32] } VR256:{ *:[v8f32] }:$src1, VR256:{ *:[v8f32] }:$src2) 20589 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VDIVPSYrr, 20590 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 20591 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 20592 // GIR_Coverage, 1995, 20593 GIR_Done, 20594 // Label 1627: @47185 20595 GIM_Try, /*On fail goto*//*Label 1628*/ 47211, // Rule ID 6271 // 20596 GIM_CheckFeatures, GIFBS_HasAVX512_HasVLX, 20597 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID, 20598 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID, 20599 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256XRegClassID, 20600 // (fdiv:{ *:[v8f32] } VR256X:{ *:[v8f32] }:$src1, VR256X:{ *:[v8f32] }:$src2) => (VDIVPSZ256rr:{ *:[v8f32] } VR256X:{ *:[v8f32] }:$src1, VR256X:{ *:[v8f32] }:$src2) 20601 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VDIVPSZ256rr, 20602 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 20603 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 20604 // GIR_Coverage, 6271, 20605 GIR_Done, 20606 // Label 1628: @47211 20607 GIM_Reject, 20608 // Label 1626: @47212 20609 GIM_Reject, 20610 // Label 1597: @47213 20611 GIM_Try, /*On fail goto*//*Label 1629*/ 47247, // Rule ID 6247 // 20612 GIM_CheckFeatures, GIFBS_HasAVX512, 20613 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s64, 20614 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s64, 20615 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 20616 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR512RegClassID, 20617 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR512RegClassID, 20618 // (fdiv:{ *:[v8f64] } VR512:{ *:[v8f64] }:$src1, VR512:{ *:[v8f64] }:$src2) => (VDIVPDZrr:{ *:[v8f64] } VR512:{ *:[v8f64] }:$src1, VR512:{ *:[v8f64] }:$src2) 20619 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VDIVPDZrr, 20620 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 20621 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 20622 // GIR_Coverage, 6247, 20623 GIR_Done, 20624 // Label 1629: @47247 20625 GIM_Reject, 20626 // Label 1598: @47248 20627 GIM_Try, /*On fail goto*//*Label 1630*/ 47282, // Rule ID 6331 // 20628 GIM_CheckFeatures, GIFBS_HasFP16_HasVLX, 20629 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s16, 20630 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s16, 20631 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID, 20632 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID, 20633 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256XRegClassID, 20634 // (fdiv:{ *:[v16f16] } VR256X:{ *:[v16f16] }:$src1, VR256X:{ *:[v16f16] }:$src2) => (VDIVPHZ256rr:{ *:[v16f16] } VR256X:{ *:[v16f16] }:$src1, VR256X:{ *:[v16f16] }:$src2) 20635 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VDIVPHZ256rr, 20636 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 20637 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 20638 // GIR_Coverage, 6331, 20639 GIR_Done, 20640 // Label 1630: @47282 20641 GIM_Reject, 20642 // Label 1599: @47283 20643 GIM_Try, /*On fail goto*//*Label 1631*/ 47317, // Rule ID 6235 // 20644 GIM_CheckFeatures, GIFBS_HasAVX512, 20645 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s32, 20646 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s32, 20647 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 20648 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR512RegClassID, 20649 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR512RegClassID, 20650 // (fdiv:{ *:[v16f32] } VR512:{ *:[v16f32] }:$src1, VR512:{ *:[v16f32] }:$src2) => (VDIVPSZrr:{ *:[v16f32] } VR512:{ *:[v16f32] }:$src1, VR512:{ *:[v16f32] }:$src2) 20651 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VDIVPSZrr, 20652 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 20653 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 20654 // GIR_Coverage, 6235, 20655 GIR_Done, 20656 // Label 1631: @47317 20657 GIM_Reject, 20658 // Label 1600: @47318 20659 GIM_Try, /*On fail goto*//*Label 1632*/ 47352, // Rule ID 6307 // 20660 GIM_CheckFeatures, GIFBS_HasFP16, 20661 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v32s16, 20662 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v32s16, 20663 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 20664 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR512RegClassID, 20665 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR512RegClassID, 20666 // (fdiv:{ *:[v32f16] } VR512:{ *:[v32f16] }:$src1, VR512:{ *:[v32f16] }:$src2) => (VDIVPHZrr:{ *:[v32f16] } VR512:{ *:[v32f16] }:$src1, VR512:{ *:[v32f16] }:$src2) 20667 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VDIVPHZrr, 20668 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 20669 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 20670 // GIR_Coverage, 6307, 20671 GIR_Done, 20672 // Label 1632: @47352 20673 GIM_Reject, 20674 // Label 1601: @47353 20675 GIM_Reject, 20676 // Label 36: @47354 20677 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/3, 6, /*)*//*default:*//*Label 1636*/ 47444, 20678 /*GILLT_s32*//*Label 1633*/ 47363, 20679 /*GILLT_s64*//*Label 1634*/ 47390, 20680 /*GILLT_s80*//*Label 1635*/ 47417, 20681 // Label 1633: @47363 20682 GIM_Try, /*On fail goto*//*Label 1637*/ 47389, // Rule ID 776 // 20683 GIM_CheckFeatures, GIFBS_FPStackf32, 20684 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 20685 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::RFP32RegClassID, 20686 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::RFP32RegClassID, 20687 // (fneg:{ *:[f32] } RFP32:{ *:[f32] }:$src) => (CHS_Fp32:{ *:[f32] }:{ *:[i16] } RFP32:{ *:[f32] }:$src) 20688 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::CHS_Fp32, 20689 GIR_AddImplicitDef, /*InsnID*/0, X86::FPSW, 20690 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 20691 // GIR_Coverage, 776, 20692 GIR_Done, 20693 // Label 1637: @47389 20694 GIM_Reject, 20695 // Label 1634: @47390 20696 GIM_Try, /*On fail goto*//*Label 1638*/ 47416, // Rule ID 777 // 20697 GIM_CheckFeatures, GIFBS_FPStackf64, 20698 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 20699 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::RFP64RegClassID, 20700 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::RFP64RegClassID, 20701 // (fneg:{ *:[f64] } RFP64:{ *:[f64] }:$src) => (CHS_Fp64:{ *:[f64] }:{ *:[i16] } RFP64:{ *:[f64] }:$src) 20702 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::CHS_Fp64, 20703 GIR_AddImplicitDef, /*InsnID*/0, X86::FPSW, 20704 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 20705 // GIR_Coverage, 777, 20706 GIR_Done, 20707 // Label 1638: @47416 20708 GIM_Reject, 20709 // Label 1635: @47417 20710 GIM_Try, /*On fail goto*//*Label 1639*/ 47443, // Rule ID 778 // 20711 GIM_CheckFeatures, GIFBS_HasX87, 20712 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s80, 20713 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::RFP80RegClassID, 20714 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::RFP80RegClassID, 20715 // (fneg:{ *:[f80] } RFP80:{ *:[f80] }:$src) => (CHS_Fp80:{ *:[f80] }:{ *:[i16] } RFP80:{ *:[f80] }:$src) 20716 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::CHS_Fp80, 20717 GIR_AddImplicitDef, /*InsnID*/0, X86::FPSW, 20718 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 20719 // GIR_Coverage, 778, 20720 GIR_Done, 20721 // Label 1639: @47443 20722 GIM_Reject, 20723 // Label 1636: @47444 20724 GIM_Reject, 20725 // Label 37: @47445 20726 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/3, 20, /*)*//*default:*//*Label 1647*/ 47923, 20727 /*GILLT_s32*//*Label 1640*/ 47468, 20728 /*GILLT_s64*//*Label 1641*/ 47517, 20729 /*GILLT_s80*//*Label 1642*/ 47713, 0, 0, 0, 0, 0, 20730 /*GILLT_v4s64*//*Label 1643*/ 47764, 0, 0, 20731 /*GILLT_v8s32*//*Label 1644*/ 47816, 20732 /*GILLT_v8s64*//*Label 1645*/ 47843, 0, 0, 0, 20733 /*GILLT_v16s32*//*Label 1646*/ 47896, 20734 // Label 1640: @47468 20735 GIM_Try, /*On fail goto*//*Label 1648*/ 47516, // Rule ID 19687 // 20736 GIM_CheckFeatures, GIFBS_HasFP16, 20737 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16, 20738 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::FR32XRegClassID, 20739 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::FR16XRegClassID, 20740 // (fpextend:{ *:[f32] } FR16X:{ *:[f16] }:$src) => (VCVTSH2SSZrr:{ *:[f32] } (IMPLICIT_DEF:{ *:[f32] }), FR16X:{ *:[f16] }:$src) 20741 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, 20742 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, 20743 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 20744 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 20745 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VCVTSH2SSZrr, 20746 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 20747 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 20748 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 20749 GIR_EraseFromParent, /*InsnID*/0, 20750 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 20751 // GIR_Coverage, 19687, 20752 GIR_Done, 20753 // Label 1648: @47516 20754 GIM_Reject, 20755 // Label 1641: @47517 20756 GIM_Try, /*On fail goto*//*Label 1649*/ 47543, // Rule ID 1624 // 20757 GIM_CheckFeatures, GIFBS_UseSSE2, 20758 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 20759 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::FR64RegClassID, 20760 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::FR32RegClassID, 20761 // (fpextend:{ *:[f64] } FR32:{ *:[f32] }:$src) => (CVTSS2SDrr:{ *:[f64] } FR32:{ *:[f32] }:$src) 20762 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::CVTSS2SDrr, 20763 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 20764 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 20765 // GIR_Coverage, 1624, 20766 GIR_Done, 20767 // Label 1649: @47543 20768 GIM_Try, /*On fail goto*//*Label 1650*/ 47568, // Rule ID 16182 // 20769 GIM_CheckFeatures, GIFBS_FPStackf32, 20770 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 20771 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::RFP64RegClassID, 20772 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::RFP32RegClassID, 20773 // (fpextend:{ *:[f64] } RFP32:{ *:[f32] }:$src) => (COPY_TO_REGCLASS:{ *:[f64] } RFP32:{ *:[f32] }:$src, RFP64:{ *:[i32] }) 20774 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, 20775 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, X86::RFP64RegClassID, 20776 // GIR_Coverage, 16182, 20777 GIR_Done, 20778 // Label 1650: @47568 20779 GIM_Try, /*On fail goto*//*Label 1651*/ 47616, // Rule ID 16455 // 20780 GIM_CheckFeatures, GIFBS_UseAVX, 20781 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 20782 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::FR64RegClassID, 20783 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::FR32RegClassID, 20784 // (fpextend:{ *:[f64] } FR32:{ *:[f32] }:$src) => (VCVTSS2SDrr:{ *:[f64] } (IMPLICIT_DEF:{ *:[f64] }), FR32:{ *:[f32] }:$src) 20785 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, 20786 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, 20787 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 20788 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 20789 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VCVTSS2SDrr, 20790 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 20791 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 20792 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 20793 GIR_EraseFromParent, /*InsnID*/0, 20794 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 20795 // GIR_Coverage, 16455, 20796 GIR_Done, 20797 // Label 1651: @47616 20798 GIM_Try, /*On fail goto*//*Label 1652*/ 47664, // Rule ID 19681 // 20799 GIM_CheckFeatures, GIFBS_HasAVX512, 20800 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 20801 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::FR64XRegClassID, 20802 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::FR32XRegClassID, 20803 // (fpextend:{ *:[f64] } FR32X:{ *:[f32] }:$src) => (VCVTSS2SDZrr:{ *:[f64] } (IMPLICIT_DEF:{ *:[f64] }), FR32X:{ *:[f32] }:$src) 20804 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, 20805 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, 20806 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 20807 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 20808 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VCVTSS2SDZrr, 20809 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 20810 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 20811 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 20812 GIR_EraseFromParent, /*InsnID*/0, 20813 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 20814 // GIR_Coverage, 19681, 20815 GIR_Done, 20816 // Label 1652: @47664 20817 GIM_Try, /*On fail goto*//*Label 1653*/ 47712, // Rule ID 19691 // 20818 GIM_CheckFeatures, GIFBS_HasFP16, 20819 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16, 20820 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::FR64XRegClassID, 20821 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::FR16XRegClassID, 20822 // (fpextend:{ *:[f64] } FR16X:{ *:[f16] }:$src) => (VCVTSH2SDZrr:{ *:[f64] } (IMPLICIT_DEF:{ *:[f64] }), FR16X:{ *:[f16] }:$src) 20823 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, 20824 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, 20825 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 20826 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 20827 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VCVTSH2SDZrr, 20828 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 20829 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 20830 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 20831 GIR_EraseFromParent, /*InsnID*/0, 20832 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 20833 // GIR_Coverage, 19691, 20834 GIR_Done, 20835 // Label 1653: @47712 20836 GIM_Reject, 20837 // Label 1642: @47713 20838 GIM_Try, /*On fail goto*//*Label 1654*/ 47738, // Rule ID 16184 // 20839 GIM_CheckFeatures, GIFBS_FPStackf32, 20840 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 20841 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::RFP80RegClassID, 20842 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::RFP32RegClassID, 20843 // (fpextend:{ *:[f80] } RFP32:{ *:[f32] }:$src) => (COPY_TO_REGCLASS:{ *:[f80] } RFP32:{ *:[f32] }:$src, RFP80:{ *:[i32] }) 20844 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, 20845 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, X86::RFP80RegClassID, 20846 // GIR_Coverage, 16184, 20847 GIR_Done, 20848 // Label 1654: @47738 20849 GIM_Try, /*On fail goto*//*Label 1655*/ 47763, // Rule ID 16186 // 20850 GIM_CheckFeatures, GIFBS_FPStackf64, 20851 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 20852 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::RFP80RegClassID, 20853 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::RFP64RegClassID, 20854 // (fpextend:{ *:[f80] } RFP64:{ *:[f64] }:$src) => (COPY_TO_REGCLASS:{ *:[f80] } RFP64:{ *:[f64] }:$src, RFP80:{ *:[i32] }) 20855 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, 20856 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, X86::RFP80RegClassID, 20857 // GIR_Coverage, 16186, 20858 GIR_Done, 20859 // Label 1655: @47763 20860 GIM_Reject, 20861 // Label 1643: @47764 20862 GIM_Try, /*On fail goto*//*Label 1656*/ 47815, 20863 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, 20864 GIM_Try, /*On fail goto*//*Label 1657*/ 47792, // Rule ID 1667 // 20865 GIM_CheckFeatures, GIFBS_HasAVX_NoVLX, 20866 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID, 20867 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 20868 // (fpextend:{ *:[v4f64] } VR128:{ *:[v4f32] }:$src) => (VCVTPS2PDYrr:{ *:[v4f64] } VR128:{ *:[v4f32] }:$src) 20869 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VCVTPS2PDYrr, 20870 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 20871 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 20872 // GIR_Coverage, 1667, 20873 GIR_Done, 20874 // Label 1657: @47792 20875 GIM_Try, /*On fail goto*//*Label 1658*/ 47814, // Rule ID 10148 // 20876 GIM_CheckFeatures, GIFBS_HasAVX512_HasVLX, 20877 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID, 20878 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID, 20879 // (fpextend:{ *:[v4f64] } VR128X:{ *:[v4f32] }:$src) => (VCVTPS2PDZ256rr:{ *:[v4f64] } VR128X:{ *:[v4f32] }:$src) 20880 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VCVTPS2PDZ256rr, 20881 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 20882 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 20883 // GIR_Coverage, 10148, 20884 GIR_Done, 20885 // Label 1658: @47814 20886 GIM_Reject, 20887 // Label 1656: @47815 20888 GIM_Reject, 20889 // Label 1644: @47816 20890 GIM_Try, /*On fail goto*//*Label 1659*/ 47842, // Rule ID 10211 // 20891 GIM_CheckFeatures, GIFBS_HasFP16_HasVLX, 20892 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, 20893 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID, 20894 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID, 20895 // (fpextend:{ *:[v8f32] } VR128X:{ *:[v8f16] }:$src) => (VCVTPH2PSXZ256rr:{ *:[v8f32] } VR128X:{ *:[v8f16] }:$src) 20896 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VCVTPH2PSXZ256rr, 20897 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 20898 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 20899 // GIR_Coverage, 10211, 20900 GIR_Done, 20901 // Label 1659: @47842 20902 GIM_Reject, 20903 // Label 1645: @47843 20904 GIM_Try, /*On fail goto*//*Label 1660*/ 47869, // Rule ID 10123 // 20905 GIM_CheckFeatures, GIFBS_HasAVX512, 20906 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s32, 20907 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 20908 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID, 20909 // (fpextend:{ *:[v8f64] } VR256X:{ *:[v8f32] }:$src) => (VCVTPS2PDZrr:{ *:[v8f64] } VR256X:{ *:[v8f32] }:$src) 20910 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VCVTPS2PDZrr, 20911 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 20912 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 20913 // GIR_Coverage, 10123, 20914 GIR_Done, 20915 // Label 1660: @47869 20916 GIM_Try, /*On fail goto*//*Label 1661*/ 47895, // Rule ID 10237 // 20917 GIM_CheckFeatures, GIFBS_HasFP16, 20918 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, 20919 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 20920 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID, 20921 // (fpextend:{ *:[v8f64] } VR128X:{ *:[v8f16] }:$src) => (VCVTPH2PDZrr:{ *:[v8f64] } VR128X:{ *:[v8f16] }:$src) 20922 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VCVTPH2PDZrr, 20923 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 20924 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 20925 // GIR_Coverage, 10237, 20926 GIR_Done, 20927 // Label 1661: @47895 20928 GIM_Reject, 20929 // Label 1646: @47896 20930 GIM_Try, /*On fail goto*//*Label 1662*/ 47922, // Rule ID 10186 // 20931 GIM_CheckFeatures, GIFBS_HasFP16, 20932 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s16, 20933 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 20934 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID, 20935 // (fpextend:{ *:[v16f32] } VR256X:{ *:[v16f16] }:$src) => (VCVTPH2PSXZrr:{ *:[v16f32] } VR256X:{ *:[v16f16] }:$src) 20936 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VCVTPH2PSXZrr, 20937 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 20938 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 20939 // GIR_Coverage, 10186, 20940 GIR_Done, 20941 // Label 1662: @47922 20942 GIM_Reject, 20943 // Label 1647: @47923 20944 GIM_Reject, 20945 // Label 38: @47924 20946 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/2, 5, /*)*//*default:*//*Label 1666*/ 48229, 20947 /*GILLT_s16*//*Label 1663*/ 47933, 20948 /*GILLT_s32*//*Label 1664*/ 48030, 20949 /*GILLT_s64*//*Label 1665*/ 48203, 20950 // Label 1663: @47933 20951 GIM_Try, /*On fail goto*//*Label 1667*/ 47981, // Rule ID 19695 // 20952 GIM_CheckFeatures, GIFBS_HasFP16, 20953 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 20954 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::FR16XRegClassID, 20955 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::FR32XRegClassID, 20956 // (fpround:{ *:[f16] } FR32X:{ *:[f32] }:$src) => (VCVTSS2SHZrr:{ *:[f16] } (IMPLICIT_DEF:{ *:[f16] }), FR32X:{ *:[f32] }:$src) 20957 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16, 20958 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, 20959 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 20960 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 20961 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VCVTSS2SHZrr, 20962 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 20963 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 20964 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 20965 GIR_EraseFromParent, /*InsnID*/0, 20966 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 20967 // GIR_Coverage, 19695, 20968 GIR_Done, 20969 // Label 1667: @47981 20970 GIM_Try, /*On fail goto*//*Label 1668*/ 48029, // Rule ID 19697 // 20971 GIM_CheckFeatures, GIFBS_HasFP16, 20972 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 20973 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::FR16XRegClassID, 20974 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::FR64XRegClassID, 20975 // (fpround:{ *:[f16] } FR64X:{ *:[f64] }:$src) => (VCVTSD2SHZrr:{ *:[f16] } (IMPLICIT_DEF:{ *:[f16] }), FR64X:{ *:[f64] }:$src) 20976 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16, 20977 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, 20978 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 20979 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 20980 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VCVTSD2SHZrr, 20981 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 20982 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 20983 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 20984 GIR_EraseFromParent, /*InsnID*/0, 20985 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 20986 // GIR_Coverage, 19697, 20987 GIR_Done, 20988 // Label 1668: @48029 20989 GIM_Reject, 20990 // Label 1664: @48030 20991 GIM_Try, /*On fail goto*//*Label 1669*/ 48056, // Rule ID 1612 // 20992 GIM_CheckFeatures, GIFBS_UseSSE2, 20993 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 20994 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::FR32RegClassID, 20995 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::FR64RegClassID, 20996 // (fpround:{ *:[f32] } FR64:{ *:[f64] }:$src) => (CVTSD2SSrr:{ *:[f32] } FR64:{ *:[f64] }:$src) 20997 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::CVTSD2SSrr, 20998 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 20999 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 21000 // GIR_Coverage, 1612, 21001 GIR_Done, 21002 // Label 1669: @48056 21003 GIM_Try, /*On fail goto*//*Label 1670*/ 48081, // Rule ID 16188 // 21004 GIM_CheckFeatures, GIFBS_FPStackf32, 21005 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 21006 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::RFP32RegClassID, 21007 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::RFP64RegClassID, 21008 // (fpround:{ *:[f32] } RFP64:{ *:[f64] }:$src) => (COPY_TO_REGCLASS:{ *:[f32] } RFP64:{ *:[f64] }:$src, RFP32:{ *:[i32] }) 21009 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, 21010 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, X86::RFP32RegClassID, 21011 // GIR_Coverage, 16188, 21012 GIR_Done, 21013 // Label 1670: @48081 21014 GIM_Try, /*On fail goto*//*Label 1671*/ 48106, // Rule ID 16190 // 21015 GIM_CheckFeatures, GIFBS_FPStackf32, 21016 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s80, 21017 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::RFP32RegClassID, 21018 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::RFP80RegClassID, 21019 // (fpround:{ *:[f32] } RFP80:{ *:[f80] }:$src) => (COPY_TO_REGCLASS:{ *:[f32] } RFP80:{ *:[f80] }:$src, RFP32:{ *:[i32] }) 21020 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, 21021 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, X86::RFP32RegClassID, 21022 // GIR_Coverage, 16190, 21023 GIR_Done, 21024 // Label 1671: @48106 21025 GIM_Try, /*On fail goto*//*Label 1672*/ 48154, // Rule ID 16453 // 21026 GIM_CheckFeatures, GIFBS_UseAVX, 21027 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 21028 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::FR32RegClassID, 21029 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::FR64RegClassID, 21030 // (fpround:{ *:[f32] } FR64:{ *:[f64] }:$src) => (VCVTSD2SSrr:{ *:[f32] } (IMPLICIT_DEF:{ *:[f32] }), FR64:{ *:[f64] }:$src) 21031 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, 21032 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, 21033 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 21034 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 21035 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VCVTSD2SSrr, 21036 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 21037 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 21038 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 21039 GIR_EraseFromParent, /*InsnID*/0, 21040 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 21041 // GIR_Coverage, 16453, 21042 GIR_Done, 21043 // Label 1672: @48154 21044 GIM_Try, /*On fail goto*//*Label 1673*/ 48202, // Rule ID 19685 // 21045 GIM_CheckFeatures, GIFBS_HasAVX512, 21046 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 21047 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::FR32XRegClassID, 21048 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::FR64XRegClassID, 21049 // (fpround:{ *:[f32] } FR64X:{ *:[f64] }:$src) => (VCVTSD2SSZrr:{ *:[f32] } (IMPLICIT_DEF:{ *:[f32] }), FR64X:{ *:[f64] }:$src) 21050 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, 21051 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, 21052 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 21053 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 21054 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VCVTSD2SSZrr, 21055 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 21056 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 21057 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 21058 GIR_EraseFromParent, /*InsnID*/0, 21059 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 21060 // GIR_Coverage, 19685, 21061 GIR_Done, 21062 // Label 1673: @48202 21063 GIM_Reject, 21064 // Label 1665: @48203 21065 GIM_Try, /*On fail goto*//*Label 1674*/ 48228, // Rule ID 16192 // 21066 GIM_CheckFeatures, GIFBS_FPStackf64, 21067 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s80, 21068 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::RFP64RegClassID, 21069 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::RFP80RegClassID, 21070 // (fpround:{ *:[f64] } RFP80:{ *:[f80] }:$src) => (COPY_TO_REGCLASS:{ *:[f64] } RFP80:{ *:[f80] }:$src, RFP64:{ *:[i32] }) 21071 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, 21072 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, X86::RFP64RegClassID, 21073 // GIR_Coverage, 16192, 21074 GIR_Done, 21075 // Label 1674: @48228 21076 GIM_Reject, 21077 // Label 1666: @48229 21078 GIM_Reject, 21079 // Label 39: @48230 21080 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/3, 11, /*)*//*default:*//*Label 1678*/ 48637, 21081 /*GILLT_s32*//*Label 1675*/ 48244, 21082 /*GILLT_s64*//*Label 1676*/ 48427, 0, 0, 0, 0, 0, 21083 /*GILLT_v4s32*//*Label 1677*/ 48610, 21084 // Label 1675: @48244 21085 GIM_Try, /*On fail goto*//*Label 1679*/ 48270, // Rule ID 1472 // 21086 GIM_CheckFeatures, GIFBS_UseAVX, 21087 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 21088 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID, 21089 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::FR32RegClassID, 21090 // (fp_to_sint:{ *:[i32] } FR32:{ *:[f32] }:$src) => (VCVTTSS2SIrr:{ *:[i32] } FR32:{ *:[f32] }:$src) 21091 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VCVTTSS2SIrr, 21092 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 21093 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 21094 // GIR_Coverage, 1472, 21095 GIR_Done, 21096 // Label 1679: @48270 21097 GIM_Try, /*On fail goto*//*Label 1680*/ 48296, // Rule ID 1480 // 21098 GIM_CheckFeatures, GIFBS_UseAVX, 21099 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 21100 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID, 21101 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::FR64RegClassID, 21102 // (fp_to_sint:{ *:[i32] } FR64:{ *:[f64] }:$src) => (VCVTTSD2SIrr:{ *:[i32] } FR64:{ *:[f64] }:$src) 21103 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VCVTTSD2SIrr, 21104 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 21105 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 21106 // GIR_Coverage, 1480, 21107 GIR_Done, 21108 // Label 1680: @48296 21109 GIM_Try, /*On fail goto*//*Label 1681*/ 48322, // Rule ID 1496 // 21110 GIM_CheckFeatures, GIFBS_UseSSE1, 21111 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 21112 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID, 21113 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::FR32RegClassID, 21114 // (fp_to_sint:{ *:[i32] } FR32:{ *:[f32] }:$src) => (CVTTSS2SIrr:{ *:[i32] } FR32:{ *:[f32] }:$src) 21115 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::CVTTSS2SIrr, 21116 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 21117 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 21118 // GIR_Coverage, 1496, 21119 GIR_Done, 21120 // Label 1681: @48322 21121 GIM_Try, /*On fail goto*//*Label 1682*/ 48348, // Rule ID 1504 // 21122 GIM_CheckFeatures, GIFBS_UseSSE2, 21123 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 21124 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID, 21125 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::FR64RegClassID, 21126 // (fp_to_sint:{ *:[i32] } FR64:{ *:[f64] }:$src) => (CVTTSD2SIrr:{ *:[i32] } FR64:{ *:[f64] }:$src) 21127 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::CVTTSD2SIrr, 21128 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 21129 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 21130 // GIR_Coverage, 1504, 21131 GIR_Done, 21132 // Label 1682: @48348 21133 GIM_Try, /*On fail goto*//*Label 1683*/ 48374, // Rule ID 9934 // 21134 GIM_CheckFeatures, GIFBS_HasAVX512, 21135 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 21136 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID, 21137 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::FR32XRegClassID, 21138 // (fp_to_sint:{ *:[i32] } FR32X:{ *:[f32] }:$src) => (VCVTTSS2SIZrr:{ *:[i32] } FR32X:{ *:[f32] }:$src) 21139 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VCVTTSS2SIZrr, 21140 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 21141 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 21142 // GIR_Coverage, 9934, 21143 GIR_Done, 21144 // Label 1683: @48374 21145 GIM_Try, /*On fail goto*//*Label 1684*/ 48400, // Rule ID 9952 // 21146 GIM_CheckFeatures, GIFBS_HasAVX512, 21147 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 21148 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID, 21149 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::FR64XRegClassID, 21150 // (fp_to_sint:{ *:[i32] } FR64X:{ *:[f64] }:$src) => (VCVTTSD2SIZrr:{ *:[i32] } FR64X:{ *:[f64] }:$src) 21151 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VCVTTSD2SIZrr, 21152 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 21153 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 21154 // GIR_Coverage, 9952, 21155 GIR_Done, 21156 // Label 1684: @48400 21157 GIM_Try, /*On fail goto*//*Label 1685*/ 48426, // Rule ID 14946 // 21158 GIM_CheckFeatures, GIFBS_HasFP16, 21159 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16, 21160 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID, 21161 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::FR16XRegClassID, 21162 // (fp_to_sint:{ *:[i32] } FR16X:{ *:[f16] }:$src) => (VCVTTSH2SIZrr:{ *:[i32] } FR16X:{ *:[f16] }:$src) 21163 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VCVTTSH2SIZrr, 21164 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 21165 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 21166 // GIR_Coverage, 14946, 21167 GIR_Done, 21168 // Label 1685: @48426 21169 GIM_Reject, 21170 // Label 1676: @48427 21171 GIM_Try, /*On fail goto*//*Label 1686*/ 48453, // Rule ID 1476 // 21172 GIM_CheckFeatures, GIFBS_UseAVX, 21173 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 21174 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID, 21175 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::FR32RegClassID, 21176 // (fp_to_sint:{ *:[i64] } FR32:{ *:[f32] }:$src) => (VCVTTSS2SI64rr:{ *:[i64] } FR32:{ *:[f32] }:$src) 21177 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VCVTTSS2SI64rr, 21178 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 21179 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 21180 // GIR_Coverage, 1476, 21181 GIR_Done, 21182 // Label 1686: @48453 21183 GIM_Try, /*On fail goto*//*Label 1687*/ 48479, // Rule ID 1484 // 21184 GIM_CheckFeatures, GIFBS_UseAVX, 21185 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 21186 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID, 21187 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::FR64RegClassID, 21188 // (fp_to_sint:{ *:[i64] } FR64:{ *:[f64] }:$src) => (VCVTTSD2SI64rr:{ *:[i64] } FR64:{ *:[f64] }:$src) 21189 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VCVTTSD2SI64rr, 21190 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 21191 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 21192 // GIR_Coverage, 1484, 21193 GIR_Done, 21194 // Label 1687: @48479 21195 GIM_Try, /*On fail goto*//*Label 1688*/ 48505, // Rule ID 1500 // 21196 GIM_CheckFeatures, GIFBS_UseSSE1, 21197 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 21198 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID, 21199 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::FR32RegClassID, 21200 // (fp_to_sint:{ *:[i64] } FR32:{ *:[f32] }:$src) => (CVTTSS2SI64rr:{ *:[i64] } FR32:{ *:[f32] }:$src) 21201 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::CVTTSS2SI64rr, 21202 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 21203 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 21204 // GIR_Coverage, 1500, 21205 GIR_Done, 21206 // Label 1688: @48505 21207 GIM_Try, /*On fail goto*//*Label 1689*/ 48531, // Rule ID 1508 // 21208 GIM_CheckFeatures, GIFBS_UseSSE2, 21209 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 21210 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID, 21211 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::FR64RegClassID, 21212 // (fp_to_sint:{ *:[i64] } FR64:{ *:[f64] }:$src) => (CVTTSD2SI64rr:{ *:[i64] } FR64:{ *:[f64] }:$src) 21213 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::CVTTSD2SI64rr, 21214 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 21215 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 21216 // GIR_Coverage, 1508, 21217 GIR_Done, 21218 // Label 1689: @48531 21219 GIM_Try, /*On fail goto*//*Label 1690*/ 48557, // Rule ID 9943 // 21220 GIM_CheckFeatures, GIFBS_HasAVX512, 21221 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 21222 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID, 21223 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::FR32XRegClassID, 21224 // (fp_to_sint:{ *:[i64] } FR32X:{ *:[f32] }:$src) => (VCVTTSS2SI64Zrr:{ *:[i64] } FR32X:{ *:[f32] }:$src) 21225 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VCVTTSS2SI64Zrr, 21226 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 21227 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 21228 // GIR_Coverage, 9943, 21229 GIR_Done, 21230 // Label 1690: @48557 21231 GIM_Try, /*On fail goto*//*Label 1691*/ 48583, // Rule ID 9961 // 21232 GIM_CheckFeatures, GIFBS_HasAVX512, 21233 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 21234 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID, 21235 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::FR64XRegClassID, 21236 // (fp_to_sint:{ *:[i64] } FR64X:{ *:[f64] }:$src) => (VCVTTSD2SI64Zrr:{ *:[i64] } FR64X:{ *:[f64] }:$src) 21237 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VCVTTSD2SI64Zrr, 21238 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 21239 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 21240 // GIR_Coverage, 9961, 21241 GIR_Done, 21242 // Label 1691: @48583 21243 GIM_Try, /*On fail goto*//*Label 1692*/ 48609, // Rule ID 14955 // 21244 GIM_CheckFeatures, GIFBS_HasFP16, 21245 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16, 21246 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID, 21247 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::FR16XRegClassID, 21248 // (fp_to_sint:{ *:[i64] } FR16X:{ *:[f16] }:$src) => (VCVTTSH2SI64Zrr:{ *:[i64] } FR16X:{ *:[f16] }:$src) 21249 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VCVTTSH2SI64Zrr, 21250 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 21251 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 21252 // GIR_Coverage, 14955, 21253 GIR_Done, 21254 // Label 1692: @48609 21255 GIM_Reject, 21256 // Label 1677: @48610 21257 GIM_Try, /*On fail goto*//*Label 1693*/ 48636, // Rule ID 16499 // 21258 GIM_CheckFeatures, GIFBS_HasAVX_NoVLX, 21259 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s64, 21260 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 21261 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256RegClassID, 21262 // (fp_to_sint:{ *:[v4i32] } VR256:{ *:[v4f64] }:$src) => (VCVTTPD2DQYrr:{ *:[v4i32] } VR256:{ *:[v4f64] }:$src) 21263 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VCVTTPD2DQYrr, 21264 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 21265 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 21266 // GIR_Coverage, 16499, 21267 GIR_Done, 21268 // Label 1693: @48636 21269 GIM_Reject, 21270 // Label 1678: @48637 21271 GIM_Reject, 21272 // Label 40: @48638 21273 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/3, 5, /*)*//*default:*//*Label 1696*/ 48804, 21274 /*GILLT_s32*//*Label 1694*/ 48646, 21275 /*GILLT_s64*//*Label 1695*/ 48725, 21276 // Label 1694: @48646 21277 GIM_Try, /*On fail goto*//*Label 1697*/ 48672, // Rule ID 9970 // 21278 GIM_CheckFeatures, GIFBS_HasAVX512, 21279 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 21280 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID, 21281 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::FR32XRegClassID, 21282 // (fp_to_uint:{ *:[i32] } FR32X:{ *:[f32] }:$src) => (VCVTTSS2USIZrr:{ *:[i32] } FR32X:{ *:[f32] }:$src) 21283 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VCVTTSS2USIZrr, 21284 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 21285 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 21286 // GIR_Coverage, 9970, 21287 GIR_Done, 21288 // Label 1697: @48672 21289 GIM_Try, /*On fail goto*//*Label 1698*/ 48698, // Rule ID 9988 // 21290 GIM_CheckFeatures, GIFBS_HasAVX512, 21291 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 21292 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID, 21293 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::FR64XRegClassID, 21294 // (fp_to_uint:{ *:[i32] } FR64X:{ *:[f64] }:$src) => (VCVTTSD2USIZrr:{ *:[i32] } FR64X:{ *:[f64] }:$src) 21295 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VCVTTSD2USIZrr, 21296 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 21297 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 21298 // GIR_Coverage, 9988, 21299 GIR_Done, 21300 // Label 1698: @48698 21301 GIM_Try, /*On fail goto*//*Label 1699*/ 48724, // Rule ID 14964 // 21302 GIM_CheckFeatures, GIFBS_HasFP16, 21303 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16, 21304 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID, 21305 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::FR16XRegClassID, 21306 // (fp_to_uint:{ *:[i32] } FR16X:{ *:[f16] }:$src) => (VCVTTSH2USIZrr:{ *:[i32] } FR16X:{ *:[f16] }:$src) 21307 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VCVTTSH2USIZrr, 21308 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 21309 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 21310 // GIR_Coverage, 14964, 21311 GIR_Done, 21312 // Label 1699: @48724 21313 GIM_Reject, 21314 // Label 1695: @48725 21315 GIM_Try, /*On fail goto*//*Label 1700*/ 48751, // Rule ID 9979 // 21316 GIM_CheckFeatures, GIFBS_HasAVX512, 21317 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 21318 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID, 21319 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::FR32XRegClassID, 21320 // (fp_to_uint:{ *:[i64] } FR32X:{ *:[f32] }:$src) => (VCVTTSS2USI64Zrr:{ *:[i64] } FR32X:{ *:[f32] }:$src) 21321 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VCVTTSS2USI64Zrr, 21322 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 21323 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 21324 // GIR_Coverage, 9979, 21325 GIR_Done, 21326 // Label 1700: @48751 21327 GIM_Try, /*On fail goto*//*Label 1701*/ 48777, // Rule ID 9997 // 21328 GIM_CheckFeatures, GIFBS_HasAVX512, 21329 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 21330 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID, 21331 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::FR64XRegClassID, 21332 // (fp_to_uint:{ *:[i64] } FR64X:{ *:[f64] }:$src) => (VCVTTSD2USI64Zrr:{ *:[i64] } FR64X:{ *:[f64] }:$src) 21333 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VCVTTSD2USI64Zrr, 21334 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 21335 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 21336 // GIR_Coverage, 9997, 21337 GIR_Done, 21338 // Label 1701: @48777 21339 GIM_Try, /*On fail goto*//*Label 1702*/ 48803, // Rule ID 14973 // 21340 GIM_CheckFeatures, GIFBS_HasFP16, 21341 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16, 21342 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID, 21343 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::FR16XRegClassID, 21344 // (fp_to_uint:{ *:[i64] } FR16X:{ *:[f16] }:$src) => (VCVTTSH2USI64Zrr:{ *:[i64] } FR16X:{ *:[f16] }:$src) 21345 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VCVTTSH2USI64Zrr, 21346 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 21347 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 21348 // GIR_Coverage, 14973, 21349 GIR_Done, 21350 // Label 1702: @48803 21351 GIM_Reject, 21352 // Label 1696: @48804 21353 GIM_Reject, 21354 // Label 41: @48805 21355 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/2, 23, /*)*//*default:*//*Label 1715*/ 49936, 21356 /*GILLT_s16*//*Label 1703*/ 48832, 21357 /*GILLT_s32*//*Label 1704*/ 48929, 21358 /*GILLT_s64*//*Label 1705*/ 49174, 0, 0, 0, 21359 /*GILLT_v2s64*//*Label 1706*/ 49416, 0, 21360 /*GILLT_v4s32*//*Label 1707*/ 49443, 21361 /*GILLT_v4s64*//*Label 1708*/ 49548, 0, 21362 /*GILLT_v8s16*//*Label 1709*/ 49621, 21363 /*GILLT_v8s32*//*Label 1710*/ 49700, 21364 /*GILLT_v8s64*//*Label 1711*/ 49779, 0, 0, 21365 /*GILLT_v16s16*//*Label 1712*/ 49829, 21366 /*GILLT_v16s32*//*Label 1713*/ 49882, 0, 0, 21367 /*GILLT_v32s16*//*Label 1714*/ 49909, 21368 // Label 1703: @48832 21369 GIM_Try, /*On fail goto*//*Label 1716*/ 48880, // Rule ID 20574 // 21370 GIM_CheckFeatures, GIFBS_HasFP16, 21371 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 21372 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::FR16XRegClassID, 21373 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR32RegClassID, 21374 // (sint_to_fp:{ *:[f16] } GR32:{ *:[i32] }:$src) => (VCVTSI2SHZrr:{ *:[f16] } (IMPLICIT_DEF:{ *:[f16] }), GR32:{ *:[i32] }:$src) 21375 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16, 21376 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, 21377 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 21378 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 21379 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VCVTSI2SHZrr, 21380 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 21381 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 21382 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 21383 GIR_EraseFromParent, /*InsnID*/0, 21384 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 21385 // GIR_Coverage, 20574, 21386 GIR_Done, 21387 // Label 1716: @48880 21388 GIM_Try, /*On fail goto*//*Label 1717*/ 48928, // Rule ID 20576 // 21389 GIM_CheckFeatures, GIFBS_HasFP16, 21390 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 21391 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::FR16XRegClassID, 21392 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR64RegClassID, 21393 // (sint_to_fp:{ *:[f16] } GR64:{ *:[i64] }:$src) => (VCVTSI642SHZrr:{ *:[f16] } (IMPLICIT_DEF:{ *:[f16] }), GR64:{ *:[i64] }:$src) 21394 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16, 21395 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, 21396 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 21397 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 21398 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VCVTSI642SHZrr, 21399 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 21400 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 21401 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 21402 GIR_EraseFromParent, /*InsnID*/0, 21403 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 21404 // GIR_Coverage, 20576, 21405 GIR_Done, 21406 // Label 1717: @48928 21407 GIM_Reject, 21408 // Label 1704: @48929 21409 GIM_Try, /*On fail goto*//*Label 1718*/ 48955, // Rule ID 1520 // 21410 GIM_CheckFeatures, GIFBS_UseSSE1, 21411 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 21412 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::FR32RegClassID, 21413 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR32RegClassID, 21414 // (sint_to_fp:{ *:[f32] } GR32:{ *:[i32] }:$src) => (CVTSI2SSrr:{ *:[f32] } GR32:{ *:[i32] }:$src) 21415 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::CVTSI2SSrr, 21416 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 21417 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 21418 // GIR_Coverage, 1520, 21419 GIR_Done, 21420 // Label 1718: @48955 21421 GIM_Try, /*On fail goto*//*Label 1719*/ 48981, // Rule ID 1524 // 21422 GIM_CheckFeatures, GIFBS_UseSSE1, 21423 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 21424 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::FR32RegClassID, 21425 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR64RegClassID, 21426 // (sint_to_fp:{ *:[f32] } GR64:{ *:[i64] }:$src) => (CVTSI642SSrr:{ *:[f32] } GR64:{ *:[i64] }:$src) 21427 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::CVTSI642SSrr, 21428 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 21429 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 21430 // GIR_Coverage, 1524, 21431 GIR_Done, 21432 // Label 1719: @48981 21433 GIM_Try, /*On fail goto*//*Label 1720*/ 49029, // Rule ID 16437 // 21434 GIM_CheckFeatures, GIFBS_UseAVX, 21435 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 21436 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::FR32RegClassID, 21437 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR32RegClassID, 21438 // (sint_to_fp:{ *:[f32] } GR32:{ *:[i32] }:$src) => (VCVTSI2SSrr:{ *:[f32] } (IMPLICIT_DEF:{ *:[f32] }), GR32:{ *:[i32] }:$src) 21439 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, 21440 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, 21441 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 21442 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 21443 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VCVTSI2SSrr, 21444 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 21445 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 21446 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 21447 GIR_EraseFromParent, /*InsnID*/0, 21448 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 21449 // GIR_Coverage, 16437, 21450 GIR_Done, 21451 // Label 1720: @49029 21452 GIM_Try, /*On fail goto*//*Label 1721*/ 49077, // Rule ID 16439 // 21453 GIM_CheckFeatures, GIFBS_UseAVX, 21454 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 21455 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::FR32RegClassID, 21456 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR64RegClassID, 21457 // (sint_to_fp:{ *:[f32] } GR64:{ *:[i64] }:$src) => (VCVTSI642SSrr:{ *:[f32] } (IMPLICIT_DEF:{ *:[f32] }), GR64:{ *:[i64] }:$src) 21458 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, 21459 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, 21460 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 21461 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 21462 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VCVTSI642SSrr, 21463 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 21464 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 21465 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 21466 GIR_EraseFromParent, /*InsnID*/0, 21467 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 21468 // GIR_Coverage, 16439, 21469 GIR_Done, 21470 // Label 1721: @49077 21471 GIM_Try, /*On fail goto*//*Label 1722*/ 49125, // Rule ID 19621 // 21472 GIM_CheckFeatures, GIFBS_HasAVX512, 21473 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 21474 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::FR32XRegClassID, 21475 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR32RegClassID, 21476 // (sint_to_fp:{ *:[f32] } GR32:{ *:[i32] }:$src) => (VCVTSI2SSZrr:{ *:[f32] } (IMPLICIT_DEF:{ *:[f32] }), GR32:{ *:[i32] }:$src) 21477 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, 21478 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, 21479 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 21480 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 21481 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VCVTSI2SSZrr, 21482 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 21483 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 21484 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 21485 GIR_EraseFromParent, /*InsnID*/0, 21486 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 21487 // GIR_Coverage, 19621, 21488 GIR_Done, 21489 // Label 1722: @49125 21490 GIM_Try, /*On fail goto*//*Label 1723*/ 49173, // Rule ID 19623 // 21491 GIM_CheckFeatures, GIFBS_HasAVX512, 21492 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 21493 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::FR32XRegClassID, 21494 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR64RegClassID, 21495 // (sint_to_fp:{ *:[f32] } GR64:{ *:[i64] }:$src) => (VCVTSI642SSZrr:{ *:[f32] } (IMPLICIT_DEF:{ *:[f32] }), GR64:{ *:[i64] }:$src) 21496 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, 21497 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, 21498 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 21499 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 21500 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VCVTSI642SSZrr, 21501 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 21502 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 21503 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 21504 GIR_EraseFromParent, /*InsnID*/0, 21505 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 21506 // GIR_Coverage, 19623, 21507 GIR_Done, 21508 // Label 1723: @49173 21509 GIM_Reject, 21510 // Label 1705: @49174 21511 GIM_Try, /*On fail goto*//*Label 1724*/ 49197, // Rule ID 1528 // 21512 GIM_CheckFeatures, GIFBS_UseSSE2, 21513 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 21514 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::FR64RegClassID, 21515 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR32RegClassID, 21516 // (sint_to_fp:{ *:[f64] } GR32:{ *:[i32] }:$src) => (CVTSI2SDrr:{ *:[f64] } GR32:{ *:[i32] }:$src) 21517 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::CVTSI2SDrr, 21518 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 21519 // GIR_Coverage, 1528, 21520 GIR_Done, 21521 // Label 1724: @49197 21522 GIM_Try, /*On fail goto*//*Label 1725*/ 49223, // Rule ID 1532 // 21523 GIM_CheckFeatures, GIFBS_UseSSE2, 21524 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 21525 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::FR64RegClassID, 21526 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR64RegClassID, 21527 // (sint_to_fp:{ *:[f64] } GR64:{ *:[i64] }:$src) => (CVTSI642SDrr:{ *:[f64] } GR64:{ *:[i64] }:$src) 21528 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::CVTSI642SDrr, 21529 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 21530 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 21531 // GIR_Coverage, 1532, 21532 GIR_Done, 21533 // Label 1725: @49223 21534 GIM_Try, /*On fail goto*//*Label 1726*/ 49271, // Rule ID 16441 // 21535 GIM_CheckFeatures, GIFBS_UseAVX, 21536 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 21537 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::FR64RegClassID, 21538 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR32RegClassID, 21539 // (sint_to_fp:{ *:[f64] } GR32:{ *:[i32] }:$src) => (VCVTSI2SDrr:{ *:[f64] } (IMPLICIT_DEF:{ *:[f64] }), GR32:{ *:[i32] }:$src) 21540 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, 21541 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, 21542 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 21543 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 21544 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VCVTSI2SDrr, 21545 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 21546 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 21547 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 21548 GIR_EraseFromParent, /*InsnID*/0, 21549 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 21550 // GIR_Coverage, 16441, 21551 GIR_Done, 21552 // Label 1726: @49271 21553 GIM_Try, /*On fail goto*//*Label 1727*/ 49319, // Rule ID 16443 // 21554 GIM_CheckFeatures, GIFBS_UseAVX, 21555 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 21556 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::FR64RegClassID, 21557 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR64RegClassID, 21558 // (sint_to_fp:{ *:[f64] } GR64:{ *:[i64] }:$src) => (VCVTSI642SDrr:{ *:[f64] } (IMPLICIT_DEF:{ *:[f64] }), GR64:{ *:[i64] }:$src) 21559 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, 21560 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, 21561 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 21562 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 21563 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VCVTSI642SDrr, 21564 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 21565 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 21566 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 21567 GIR_EraseFromParent, /*InsnID*/0, 21568 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 21569 // GIR_Coverage, 16443, 21570 GIR_Done, 21571 // Label 1727: @49319 21572 GIM_Try, /*On fail goto*//*Label 1728*/ 49367, // Rule ID 19625 // 21573 GIM_CheckFeatures, GIFBS_HasAVX512, 21574 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 21575 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::FR64XRegClassID, 21576 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR32RegClassID, 21577 // (sint_to_fp:{ *:[f64] } GR32:{ *:[i32] }:$src) => (VCVTSI2SDZrr:{ *:[f64] } (IMPLICIT_DEF:{ *:[f64] }), GR32:{ *:[i32] }:$src) 21578 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, 21579 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, 21580 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 21581 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 21582 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VCVTSI2SDZrr, 21583 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 21584 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 21585 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 21586 GIR_EraseFromParent, /*InsnID*/0, 21587 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 21588 // GIR_Coverage, 19625, 21589 GIR_Done, 21590 // Label 1728: @49367 21591 GIM_Try, /*On fail goto*//*Label 1729*/ 49415, // Rule ID 19627 // 21592 GIM_CheckFeatures, GIFBS_HasAVX512, 21593 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 21594 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::FR64XRegClassID, 21595 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR64RegClassID, 21596 // (sint_to_fp:{ *:[f64] } GR64:{ *:[i64] }:$src) => (VCVTSI642SDZrr:{ *:[f64] } (IMPLICIT_DEF:{ *:[f64] }), GR64:{ *:[i64] }:$src) 21597 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, 21598 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, 21599 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 21600 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 21601 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VCVTSI642SDZrr, 21602 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 21603 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 21604 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 21605 GIR_EraseFromParent, /*InsnID*/0, 21606 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 21607 // GIR_Coverage, 19627, 21608 GIR_Done, 21609 // Label 1729: @49415 21610 GIM_Reject, 21611 // Label 1706: @49416 21612 GIM_Try, /*On fail goto*//*Label 1730*/ 49442, // Rule ID 10948 // 21613 GIM_CheckFeatures, GIFBS_HasDQI_HasVLX, 21614 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, 21615 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID, 21616 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID, 21617 // (sint_to_fp:{ *:[v2f64] } VR128X:{ *:[v2i64] }:$src) => (VCVTQQ2PDZ128rr:{ *:[v2f64] } VR128X:{ *:[v2i64] }:$src) 21618 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VCVTQQ2PDZ128rr, 21619 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 21620 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 21621 // GIR_Coverage, 10948, 21622 GIR_Done, 21623 // Label 1730: @49442 21624 GIM_Reject, 21625 // Label 1707: @49443 21626 GIM_Try, /*On fail goto*//*Label 1731*/ 49469, // Rule ID 1600 // 21627 GIM_CheckFeatures, GIFBS_HasAVX_NoVLX, 21628 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, 21629 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 21630 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 21631 // (sint_to_fp:{ *:[v4f32] } VR128:{ *:[v4i32] }:$src) => (VCVTDQ2PSrr:{ *:[v4f32] } VR128:{ *:[v4i32] }:$src) 21632 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VCVTDQ2PSrr, 21633 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 21634 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 21635 // GIR_Coverage, 1600, 21636 GIR_Done, 21637 // Label 1731: @49469 21638 GIM_Try, /*On fail goto*//*Label 1732*/ 49495, // Rule ID 1608 // 21639 GIM_CheckFeatures, GIFBS_UseSSE2, 21640 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, 21641 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 21642 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 21643 // (sint_to_fp:{ *:[v4f32] } VR128:{ *:[v4i32] }:$src) => (CVTDQ2PSrr:{ *:[v4f32] } VR128:{ *:[v4i32] }:$src) 21644 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::CVTDQ2PSrr, 21645 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 21646 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 21647 // GIR_Coverage, 1608, 21648 GIR_Done, 21649 // Label 1732: @49495 21650 GIM_Try, /*On fail goto*//*Label 1733*/ 49521, // Rule ID 10324 // 21651 GIM_CheckFeatures, GIFBS_HasVLX, 21652 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, 21653 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID, 21654 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID, 21655 // (sint_to_fp:{ *:[v4f32] } VR128X:{ *:[v4i32] }:$src) => (VCVTDQ2PSZ128rr:{ *:[v4f32] } VR128X:{ *:[v4i32] }:$src) 21656 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VCVTDQ2PSZ128rr, 21657 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 21658 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 21659 // GIR_Coverage, 10324, 21660 GIR_Done, 21661 // Label 1733: @49521 21662 GIM_Try, /*On fail goto*//*Label 1734*/ 49547, // Rule ID 11080 // 21663 GIM_CheckFeatures, GIFBS_HasDQI_HasVLX, 21664 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s64, 21665 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID, 21666 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID, 21667 // (sint_to_fp:{ *:[v4f32] } VR256X:{ *:[v4i64] }:$src) => (VCVTQQ2PSZ256rr:{ *:[v4f32] } VR256X:{ *:[v4i64] }:$src) 21668 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VCVTQQ2PSZ256rr, 21669 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 21670 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 21671 // GIR_Coverage, 11080, 21672 GIR_Done, 21673 // Label 1734: @49547 21674 GIM_Reject, 21675 // Label 1708: @49548 21676 GIM_Try, /*On fail goto*//*Label 1735*/ 49571, // Rule ID 1679 // 21677 GIM_CheckFeatures, GIFBS_HasAVX_NoVLX, 21678 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, 21679 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID, 21680 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 21681 // (sint_to_fp:{ *:[v4f64] } VR128:{ *:[v4i32] }:$src) => (VCVTDQ2PDYrr:{ *:[v4f64] } VR128:{ *:[v4i32] }:$src) 21682 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VCVTDQ2PDYrr, 21683 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 21684 // GIR_Coverage, 1679, 21685 GIR_Done, 21686 // Label 1735: @49571 21687 GIM_Try, /*On fail goto*//*Label 1736*/ 49594, // Rule ID 10297 // 21688 GIM_CheckFeatures, GIFBS_HasVLX, 21689 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, 21690 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID, 21691 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID, 21692 // (sint_to_fp:{ *:[v4f64] } VR128X:{ *:[v4i32] }:$src) => (VCVTDQ2PDZ256rr:{ *:[v4f64] } VR128X:{ *:[v4i32] }:$src) 21693 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VCVTDQ2PDZ256rr, 21694 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 21695 // GIR_Coverage, 10297, 21696 GIR_Done, 21697 // Label 1736: @49594 21698 GIM_Try, /*On fail goto*//*Label 1737*/ 49620, // Rule ID 10960 // 21699 GIM_CheckFeatures, GIFBS_HasDQI_HasVLX, 21700 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s64, 21701 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID, 21702 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID, 21703 // (sint_to_fp:{ *:[v4f64] } VR256X:{ *:[v4i64] }:$src) => (VCVTQQ2PDZ256rr:{ *:[v4f64] } VR256X:{ *:[v4i64] }:$src) 21704 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VCVTQQ2PDZ256rr, 21705 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 21706 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 21707 // GIR_Coverage, 10960, 21708 GIR_Done, 21709 // Label 1737: @49620 21710 GIM_Reject, 21711 // Label 1709: @49621 21712 GIM_Try, /*On fail goto*//*Label 1738*/ 49647, // Rule ID 11026 // 21713 GIM_CheckFeatures, GIFBS_HasFP16_HasVLX, 21714 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s32, 21715 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID, 21716 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID, 21717 // (sint_to_fp:{ *:[v8f16] } VR256X:{ *:[v8i32] }:$src) => (VCVTDQ2PHZ256rr:{ *:[v8f16] } VR256X:{ *:[v8i32] }:$src) 21718 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VCVTDQ2PHZ256rr, 21719 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 21720 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 21721 // GIR_Coverage, 11026, 21722 GIR_Done, 21723 // Label 1738: @49647 21724 GIM_Try, /*On fail goto*//*Label 1739*/ 49673, // Rule ID 14596 // 21725 GIM_CheckFeatures, GIFBS_HasFP16_HasVLX, 21726 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, 21727 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID, 21728 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID, 21729 // (sint_to_fp:{ *:[v8f16] } VR128X:{ *:[v8i16] }:$src) => (VCVTW2PHZ128rr:{ *:[v8f16] } VR128X:{ *:[v8i16] }:$src) 21730 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VCVTW2PHZ128rr, 21731 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 21732 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 21733 // GIR_Coverage, 14596, 21734 GIR_Done, 21735 // Label 1739: @49673 21736 GIM_Try, /*On fail goto*//*Label 1740*/ 49699, // Rule ID 14896 // 21737 GIM_CheckFeatures, GIFBS_HasFP16, 21738 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s64, 21739 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID, 21740 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR512RegClassID, 21741 // (sint_to_fp:{ *:[v8f16] } VR512:{ *:[v8i64] }:$src) => (VCVTQQ2PHZrr:{ *:[v8f16] } VR512:{ *:[v8i64] }:$src) 21742 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VCVTQQ2PHZrr, 21743 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 21744 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 21745 // GIR_Coverage, 14896, 21746 GIR_Done, 21747 // Label 1740: @49699 21748 GIM_Reject, 21749 // Label 1710: @49700 21750 GIM_Try, /*On fail goto*//*Label 1741*/ 49726, // Rule ID 1604 // 21751 GIM_CheckFeatures, GIFBS_HasAVX_NoVLX, 21752 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s32, 21753 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID, 21754 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256RegClassID, 21755 // (sint_to_fp:{ *:[v8f32] } VR256:{ *:[v8i32] }:$src) => (VCVTDQ2PSYrr:{ *:[v8f32] } VR256:{ *:[v8i32] }:$src) 21756 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VCVTDQ2PSYrr, 21757 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 21758 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 21759 // GIR_Coverage, 1604, 21760 GIR_Done, 21761 // Label 1741: @49726 21762 GIM_Try, /*On fail goto*//*Label 1742*/ 49752, // Rule ID 10336 // 21763 GIM_CheckFeatures, GIFBS_HasVLX, 21764 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s32, 21765 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID, 21766 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID, 21767 // (sint_to_fp:{ *:[v8f32] } VR256X:{ *:[v8i32] }:$src) => (VCVTDQ2PSZ256rr:{ *:[v8f32] } VR256X:{ *:[v8i32] }:$src) 21768 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VCVTDQ2PSZ256rr, 21769 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 21770 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 21771 // GIR_Coverage, 10336, 21772 GIR_Done, 21773 // Label 1742: @49752 21774 GIM_Try, /*On fail goto*//*Label 1743*/ 49778, // Rule ID 11065 // 21775 GIM_CheckFeatures, GIFBS_HasDQI, 21776 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s64, 21777 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID, 21778 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR512RegClassID, 21779 // (sint_to_fp:{ *:[v8f32] } VR512:{ *:[v8i64] }:$src) => (VCVTQQ2PSZrr:{ *:[v8f32] } VR512:{ *:[v8i64] }:$src) 21780 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VCVTQQ2PSZrr, 21781 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 21782 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 21783 // GIR_Coverage, 11065, 21784 GIR_Done, 21785 // Label 1743: @49778 21786 GIM_Reject, 21787 // Label 1711: @49779 21788 GIM_Try, /*On fail goto*//*Label 1744*/ 49802, // Rule ID 10273 // 21789 GIM_CheckFeatures, GIFBS_HasAVX512, 21790 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s32, 21791 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 21792 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID, 21793 // (sint_to_fp:{ *:[v8f64] } VR256X:{ *:[v8i32] }:$src) => (VCVTDQ2PDZrr:{ *:[v8f64] } VR256X:{ *:[v8i32] }:$src) 21794 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VCVTDQ2PDZrr, 21795 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 21796 // GIR_Coverage, 10273, 21797 GIR_Done, 21798 // Label 1744: @49802 21799 GIM_Try, /*On fail goto*//*Label 1745*/ 49828, // Rule ID 10933 // 21800 GIM_CheckFeatures, GIFBS_HasDQI, 21801 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s64, 21802 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 21803 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR512RegClassID, 21804 // (sint_to_fp:{ *:[v8f64] } VR512:{ *:[v8i64] }:$src) => (VCVTQQ2PDZrr:{ *:[v8f64] } VR512:{ *:[v8i64] }:$src) 21805 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VCVTQQ2PDZrr, 21806 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 21807 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 21808 // GIR_Coverage, 10933, 21809 GIR_Done, 21810 // Label 1745: @49828 21811 GIM_Reject, 21812 // Label 1712: @49829 21813 GIM_Try, /*On fail goto*//*Label 1746*/ 49855, // Rule ID 11011 // 21814 GIM_CheckFeatures, GIFBS_HasFP16, 21815 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s32, 21816 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID, 21817 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR512RegClassID, 21818 // (sint_to_fp:{ *:[v16f16] } VR512:{ *:[v16i32] }:$src) => (VCVTDQ2PHZrr:{ *:[v16f16] } VR512:{ *:[v16i32] }:$src) 21819 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VCVTDQ2PHZrr, 21820 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 21821 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 21822 // GIR_Coverage, 11011, 21823 GIR_Done, 21824 // Label 1746: @49855 21825 GIM_Try, /*On fail goto*//*Label 1747*/ 49881, // Rule ID 14608 // 21826 GIM_CheckFeatures, GIFBS_HasFP16_HasVLX, 21827 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s16, 21828 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID, 21829 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID, 21830 // (sint_to_fp:{ *:[v16f16] } VR256X:{ *:[v16i16] }:$src) => (VCVTW2PHZ256rr:{ *:[v16f16] } VR256X:{ *:[v16i16] }:$src) 21831 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VCVTW2PHZ256rr, 21832 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 21833 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 21834 // GIR_Coverage, 14608, 21835 GIR_Done, 21836 // Label 1747: @49881 21837 GIM_Reject, 21838 // Label 1713: @49882 21839 GIM_Try, /*On fail goto*//*Label 1748*/ 49908, // Rule ID 10309 // 21840 GIM_CheckFeatures, GIFBS_HasAVX512, 21841 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s32, 21842 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 21843 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR512RegClassID, 21844 // (sint_to_fp:{ *:[v16f32] } VR512:{ *:[v16i32] }:$src) => (VCVTDQ2PSZrr:{ *:[v16f32] } VR512:{ *:[v16i32] }:$src) 21845 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VCVTDQ2PSZrr, 21846 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 21847 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 21848 // GIR_Coverage, 10309, 21849 GIR_Done, 21850 // Label 1748: @49908 21851 GIM_Reject, 21852 // Label 1714: @49909 21853 GIM_Try, /*On fail goto*//*Label 1749*/ 49935, // Rule ID 14581 // 21854 GIM_CheckFeatures, GIFBS_HasFP16, 21855 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v32s16, 21856 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 21857 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR512RegClassID, 21858 // (sint_to_fp:{ *:[v32f16] } VR512:{ *:[v32i16] }:$src) => (VCVTW2PHZrr:{ *:[v32f16] } VR512:{ *:[v32i16] }:$src) 21859 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VCVTW2PHZrr, 21860 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 21861 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 21862 // GIR_Coverage, 14581, 21863 GIR_Done, 21864 // Label 1749: @49935 21865 GIM_Reject, 21866 // Label 1715: @49936 21867 GIM_Reject, 21868 // Label 42: @49937 21869 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/2, 23, /*)*//*default:*//*Label 1762*/ 50674, 21870 /*GILLT_s16*//*Label 1750*/ 49964, 21871 /*GILLT_s32*//*Label 1751*/ 50061, 21872 /*GILLT_s64*//*Label 1752*/ 50158, 0, 0, 0, 21873 /*GILLT_v2s64*//*Label 1753*/ 50255, 0, 21874 /*GILLT_v4s32*//*Label 1754*/ 50282, 21875 /*GILLT_v4s64*//*Label 1755*/ 50335, 0, 21876 /*GILLT_v8s16*//*Label 1756*/ 50385, 21877 /*GILLT_v8s32*//*Label 1757*/ 50464, 21878 /*GILLT_v8s64*//*Label 1758*/ 50517, 0, 0, 21879 /*GILLT_v16s16*//*Label 1759*/ 50567, 21880 /*GILLT_v16s32*//*Label 1760*/ 50620, 0, 0, 21881 /*GILLT_v32s16*//*Label 1761*/ 50647, 21882 // Label 1750: @49964 21883 GIM_Try, /*On fail goto*//*Label 1763*/ 50012, // Rule ID 20582 // 21884 GIM_CheckFeatures, GIFBS_HasFP16, 21885 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 21886 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::FR16XRegClassID, 21887 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR32RegClassID, 21888 // (uint_to_fp:{ *:[f16] } GR32:{ *:[i32] }:$src) => (VCVTUSI2SHZrr:{ *:[f16] } (IMPLICIT_DEF:{ *:[f16] }), GR32:{ *:[i32] }:$src) 21889 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16, 21890 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, 21891 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 21892 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 21893 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VCVTUSI2SHZrr, 21894 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 21895 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 21896 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 21897 GIR_EraseFromParent, /*InsnID*/0, 21898 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 21899 // GIR_Coverage, 20582, 21900 GIR_Done, 21901 // Label 1763: @50012 21902 GIM_Try, /*On fail goto*//*Label 1764*/ 50060, // Rule ID 20584 // 21903 GIM_CheckFeatures, GIFBS_HasFP16, 21904 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 21905 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::FR16XRegClassID, 21906 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR64RegClassID, 21907 // (uint_to_fp:{ *:[f16] } GR64:{ *:[i64] }:$src) => (VCVTUSI642SHZrr:{ *:[f16] } (IMPLICIT_DEF:{ *:[f16] }), GR64:{ *:[i64] }:$src) 21908 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16, 21909 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, 21910 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 21911 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 21912 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VCVTUSI642SHZrr, 21913 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 21914 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 21915 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 21916 GIR_EraseFromParent, /*InsnID*/0, 21917 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 21918 // GIR_Coverage, 20584, 21919 GIR_Done, 21920 // Label 1764: @50060 21921 GIM_Reject, 21922 // Label 1751: @50061 21923 GIM_Try, /*On fail goto*//*Label 1765*/ 50109, // Rule ID 19637 // 21924 GIM_CheckFeatures, GIFBS_HasAVX512, 21925 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 21926 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::FR32XRegClassID, 21927 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR32RegClassID, 21928 // (uint_to_fp:{ *:[f32] } GR32:{ *:[i32] }:$src) => (VCVTUSI2SSZrr:{ *:[f32] } (IMPLICIT_DEF:{ *:[f32] }), GR32:{ *:[i32] }:$src) 21929 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, 21930 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, 21931 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 21932 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 21933 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VCVTUSI2SSZrr, 21934 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 21935 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 21936 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 21937 GIR_EraseFromParent, /*InsnID*/0, 21938 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 21939 // GIR_Coverage, 19637, 21940 GIR_Done, 21941 // Label 1765: @50109 21942 GIM_Try, /*On fail goto*//*Label 1766*/ 50157, // Rule ID 19639 // 21943 GIM_CheckFeatures, GIFBS_HasAVX512, 21944 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 21945 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::FR32XRegClassID, 21946 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR64RegClassID, 21947 // (uint_to_fp:{ *:[f32] } GR64:{ *:[i64] }:$src) => (VCVTUSI642SSZrr:{ *:[f32] } (IMPLICIT_DEF:{ *:[f32] }), GR64:{ *:[i64] }:$src) 21948 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, 21949 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, 21950 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 21951 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 21952 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VCVTUSI642SSZrr, 21953 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 21954 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 21955 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 21956 GIR_EraseFromParent, /*InsnID*/0, 21957 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 21958 // GIR_Coverage, 19639, 21959 GIR_Done, 21960 // Label 1766: @50157 21961 GIM_Reject, 21962 // Label 1752: @50158 21963 GIM_Try, /*On fail goto*//*Label 1767*/ 50206, // Rule ID 19641 // 21964 GIM_CheckFeatures, GIFBS_HasAVX512, 21965 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 21966 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::FR64XRegClassID, 21967 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR32RegClassID, 21968 // (uint_to_fp:{ *:[f64] } GR32:{ *:[i32] }:$src) => (VCVTUSI2SDZrr:{ *:[f64] } (IMPLICIT_DEF:{ *:[f64] }), GR32:{ *:[i32] }:$src) 21969 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, 21970 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, 21971 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 21972 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 21973 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VCVTUSI2SDZrr, 21974 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 21975 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 21976 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 21977 GIR_EraseFromParent, /*InsnID*/0, 21978 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 21979 // GIR_Coverage, 19641, 21980 GIR_Done, 21981 // Label 1767: @50206 21982 GIM_Try, /*On fail goto*//*Label 1768*/ 50254, // Rule ID 19643 // 21983 GIM_CheckFeatures, GIFBS_HasAVX512, 21984 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 21985 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::FR64XRegClassID, 21986 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR64RegClassID, 21987 // (uint_to_fp:{ *:[f64] } GR64:{ *:[i64] }:$src) => (VCVTUSI642SDZrr:{ *:[f64] } (IMPLICIT_DEF:{ *:[f64] }), GR64:{ *:[i64] }:$src) 21988 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, 21989 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, 21990 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 21991 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 21992 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VCVTUSI642SDZrr, 21993 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 21994 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 21995 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 21996 GIR_EraseFromParent, /*InsnID*/0, 21997 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 21998 // GIR_Coverage, 19643, 21999 GIR_Done, 22000 // Label 1768: @50254 22001 GIM_Reject, 22002 // Label 1753: @50255 22003 GIM_Try, /*On fail goto*//*Label 1769*/ 50281, // Rule ID 10987 // 22004 GIM_CheckFeatures, GIFBS_HasDQI_HasVLX, 22005 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, 22006 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID, 22007 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID, 22008 // (uint_to_fp:{ *:[v2f64] } VR128X:{ *:[v2i64] }:$src) => (VCVTUQQ2PDZ128rr:{ *:[v2f64] } VR128X:{ *:[v2i64] }:$src) 22009 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VCVTUQQ2PDZ128rr, 22010 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 22011 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 22012 // GIR_Coverage, 10987, 22013 GIR_Done, 22014 // Label 1769: @50281 22015 GIM_Reject, 22016 // Label 1754: @50282 22017 GIM_Try, /*On fail goto*//*Label 1770*/ 50308, // Rule ID 10531 // 22018 GIM_CheckFeatures, GIFBS_HasVLX, 22019 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, 22020 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID, 22021 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID, 22022 // (uint_to_fp:{ *:[v4f32] } VR128X:{ *:[v4i32] }:$src) => (VCVTUDQ2PSZ128rr:{ *:[v4f32] } VR128X:{ *:[v4i32] }:$src) 22023 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VCVTUDQ2PSZ128rr, 22024 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 22025 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 22026 // GIR_Coverage, 10531, 22027 GIR_Done, 22028 // Label 1770: @50308 22029 GIM_Try, /*On fail goto*//*Label 1771*/ 50334, // Rule ID 11107 // 22030 GIM_CheckFeatures, GIFBS_HasDQI_HasVLX, 22031 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s64, 22032 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID, 22033 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID, 22034 // (uint_to_fp:{ *:[v4f32] } VR256X:{ *:[v4i64] }:$src) => (VCVTUQQ2PSZ256rr:{ *:[v4f32] } VR256X:{ *:[v4i64] }:$src) 22035 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VCVTUQQ2PSZ256rr, 22036 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 22037 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 22038 // GIR_Coverage, 11107, 22039 GIR_Done, 22040 // Label 1771: @50334 22041 GIM_Reject, 22042 // Label 1755: @50335 22043 GIM_Try, /*On fail goto*//*Label 1772*/ 50358, // Rule ID 10504 // 22044 GIM_CheckFeatures, GIFBS_HasVLX, 22045 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, 22046 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID, 22047 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID, 22048 // (uint_to_fp:{ *:[v4f64] } VR128X:{ *:[v4i32] }:$src) => (VCVTUDQ2PDZ256rr:{ *:[v4f64] } VR128X:{ *:[v4i32] }:$src) 22049 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VCVTUDQ2PDZ256rr, 22050 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 22051 // GIR_Coverage, 10504, 22052 GIR_Done, 22053 // Label 1772: @50358 22054 GIM_Try, /*On fail goto*//*Label 1773*/ 50384, // Rule ID 10999 // 22055 GIM_CheckFeatures, GIFBS_HasDQI_HasVLX, 22056 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s64, 22057 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID, 22058 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID, 22059 // (uint_to_fp:{ *:[v4f64] } VR256X:{ *:[v4i64] }:$src) => (VCVTUQQ2PDZ256rr:{ *:[v4f64] } VR256X:{ *:[v4i64] }:$src) 22060 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VCVTUQQ2PDZ256rr, 22061 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 22062 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 22063 // GIR_Coverage, 10999, 22064 GIR_Done, 22065 // Label 1773: @50384 22066 GIM_Reject, 22067 // Label 1756: @50385 22068 GIM_Try, /*On fail goto*//*Label 1774*/ 50411, // Rule ID 11053 // 22069 GIM_CheckFeatures, GIFBS_HasFP16_HasVLX, 22070 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s32, 22071 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID, 22072 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID, 22073 // (uint_to_fp:{ *:[v8f16] } VR256X:{ *:[v8i32] }:$src) => (VCVTUDQ2PHZ256rr:{ *:[v8f16] } VR256X:{ *:[v8i32] }:$src) 22074 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VCVTUDQ2PHZ256rr, 22075 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 22076 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 22077 // GIR_Coverage, 11053, 22078 GIR_Done, 22079 // Label 1774: @50411 22080 GIM_Try, /*On fail goto*//*Label 1775*/ 50437, // Rule ID 14449 // 22081 GIM_CheckFeatures, GIFBS_HasFP16_HasVLX, 22082 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, 22083 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID, 22084 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID, 22085 // (uint_to_fp:{ *:[v8f16] } VR128X:{ *:[v8i16] }:$src) => (VCVTUW2PHZ128rr:{ *:[v8f16] } VR128X:{ *:[v8i16] }:$src) 22086 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VCVTUW2PHZ128rr, 22087 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 22088 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 22089 // GIR_Coverage, 14449, 22090 GIR_Done, 22091 // Label 1775: @50437 22092 GIM_Try, /*On fail goto*//*Label 1776*/ 50463, // Rule ID 14911 // 22093 GIM_CheckFeatures, GIFBS_HasFP16, 22094 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s64, 22095 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID, 22096 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR512RegClassID, 22097 // (uint_to_fp:{ *:[v8f16] } VR512:{ *:[v8i64] }:$src) => (VCVTUQQ2PHZrr:{ *:[v8f16] } VR512:{ *:[v8i64] }:$src) 22098 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VCVTUQQ2PHZrr, 22099 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 22100 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 22101 // GIR_Coverage, 14911, 22102 GIR_Done, 22103 // Label 1776: @50463 22104 GIM_Reject, 22105 // Label 1757: @50464 22106 GIM_Try, /*On fail goto*//*Label 1777*/ 50490, // Rule ID 10543 // 22107 GIM_CheckFeatures, GIFBS_HasVLX, 22108 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s32, 22109 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID, 22110 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID, 22111 // (uint_to_fp:{ *:[v8f32] } VR256X:{ *:[v8i32] }:$src) => (VCVTUDQ2PSZ256rr:{ *:[v8f32] } VR256X:{ *:[v8i32] }:$src) 22112 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VCVTUDQ2PSZ256rr, 22113 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 22114 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 22115 // GIR_Coverage, 10543, 22116 GIR_Done, 22117 // Label 1777: @50490 22118 GIM_Try, /*On fail goto*//*Label 1778*/ 50516, // Rule ID 11092 // 22119 GIM_CheckFeatures, GIFBS_HasDQI, 22120 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s64, 22121 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID, 22122 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR512RegClassID, 22123 // (uint_to_fp:{ *:[v8f32] } VR512:{ *:[v8i64] }:$src) => (VCVTUQQ2PSZrr:{ *:[v8f32] } VR512:{ *:[v8i64] }:$src) 22124 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VCVTUQQ2PSZrr, 22125 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 22126 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 22127 // GIR_Coverage, 11092, 22128 GIR_Done, 22129 // Label 1778: @50516 22130 GIM_Reject, 22131 // Label 1758: @50517 22132 GIM_Try, /*On fail goto*//*Label 1779*/ 50540, // Rule ID 10480 // 22133 GIM_CheckFeatures, GIFBS_HasAVX512, 22134 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s32, 22135 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 22136 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID, 22137 // (uint_to_fp:{ *:[v8f64] } VR256X:{ *:[v8i32] }:$src) => (VCVTUDQ2PDZrr:{ *:[v8f64] } VR256X:{ *:[v8i32] }:$src) 22138 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VCVTUDQ2PDZrr, 22139 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 22140 // GIR_Coverage, 10480, 22141 GIR_Done, 22142 // Label 1779: @50540 22143 GIM_Try, /*On fail goto*//*Label 1780*/ 50566, // Rule ID 10972 // 22144 GIM_CheckFeatures, GIFBS_HasDQI, 22145 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s64, 22146 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 22147 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR512RegClassID, 22148 // (uint_to_fp:{ *:[v8f64] } VR512:{ *:[v8i64] }:$src) => (VCVTUQQ2PDZrr:{ *:[v8f64] } VR512:{ *:[v8i64] }:$src) 22149 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VCVTUQQ2PDZrr, 22150 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 22151 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 22152 // GIR_Coverage, 10972, 22153 GIR_Done, 22154 // Label 1780: @50566 22155 GIM_Reject, 22156 // Label 1759: @50567 22157 GIM_Try, /*On fail goto*//*Label 1781*/ 50593, // Rule ID 11038 // 22158 GIM_CheckFeatures, GIFBS_HasFP16, 22159 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s32, 22160 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID, 22161 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR512RegClassID, 22162 // (uint_to_fp:{ *:[v16f16] } VR512:{ *:[v16i32] }:$src) => (VCVTUDQ2PHZrr:{ *:[v16f16] } VR512:{ *:[v16i32] }:$src) 22163 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VCVTUDQ2PHZrr, 22164 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 22165 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 22166 // GIR_Coverage, 11038, 22167 GIR_Done, 22168 // Label 1781: @50593 22169 GIM_Try, /*On fail goto*//*Label 1782*/ 50619, // Rule ID 14461 // 22170 GIM_CheckFeatures, GIFBS_HasFP16_HasVLX, 22171 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s16, 22172 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID, 22173 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID, 22174 // (uint_to_fp:{ *:[v16f16] } VR256X:{ *:[v16i16] }:$src) => (VCVTUW2PHZ256rr:{ *:[v16f16] } VR256X:{ *:[v16i16] }:$src) 22175 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VCVTUW2PHZ256rr, 22176 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 22177 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 22178 // GIR_Coverage, 14461, 22179 GIR_Done, 22180 // Label 1782: @50619 22181 GIM_Reject, 22182 // Label 1760: @50620 22183 GIM_Try, /*On fail goto*//*Label 1783*/ 50646, // Rule ID 10516 // 22184 GIM_CheckFeatures, GIFBS_HasAVX512, 22185 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s32, 22186 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 22187 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR512RegClassID, 22188 // (uint_to_fp:{ *:[v16f32] } VR512:{ *:[v16i32] }:$src) => (VCVTUDQ2PSZrr:{ *:[v16f32] } VR512:{ *:[v16i32] }:$src) 22189 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VCVTUDQ2PSZrr, 22190 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 22191 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 22192 // GIR_Coverage, 10516, 22193 GIR_Done, 22194 // Label 1783: @50646 22195 GIM_Reject, 22196 // Label 1761: @50647 22197 GIM_Try, /*On fail goto*//*Label 1784*/ 50673, // Rule ID 14434 // 22198 GIM_CheckFeatures, GIFBS_HasFP16, 22199 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v32s16, 22200 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 22201 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR512RegClassID, 22202 // (uint_to_fp:{ *:[v32f16] } VR512:{ *:[v32i16] }:$src) => (VCVTUW2PHZrr:{ *:[v32f16] } VR512:{ *:[v32i16] }:$src) 22203 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VCVTUW2PHZrr, 22204 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 22205 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 22206 // GIR_Coverage, 14434, 22207 GIR_Done, 22208 // Label 1784: @50673 22209 GIM_Reject, 22210 // Label 1762: @50674 22211 GIM_Reject, 22212 // Label 43: @50675 22213 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/3, 6, /*)*//*default:*//*Label 1788*/ 50765, 22214 /*GILLT_s32*//*Label 1785*/ 50684, 22215 /*GILLT_s64*//*Label 1786*/ 50711, 22216 /*GILLT_s80*//*Label 1787*/ 50738, 22217 // Label 1785: @50684 22218 GIM_Try, /*On fail goto*//*Label 1789*/ 50710, // Rule ID 779 // 22219 GIM_CheckFeatures, GIFBS_FPStackf32, 22220 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 22221 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::RFP32RegClassID, 22222 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::RFP32RegClassID, 22223 // (fabs:{ *:[f32] } RFP32:{ *:[f32] }:$src) => (ABS_Fp32:{ *:[f32] }:{ *:[i16] } RFP32:{ *:[f32] }:$src) 22224 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::ABS_Fp32, 22225 GIR_AddImplicitDef, /*InsnID*/0, X86::FPSW, 22226 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 22227 // GIR_Coverage, 779, 22228 GIR_Done, 22229 // Label 1789: @50710 22230 GIM_Reject, 22231 // Label 1786: @50711 22232 GIM_Try, /*On fail goto*//*Label 1790*/ 50737, // Rule ID 780 // 22233 GIM_CheckFeatures, GIFBS_FPStackf64, 22234 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 22235 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::RFP64RegClassID, 22236 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::RFP64RegClassID, 22237 // (fabs:{ *:[f64] } RFP64:{ *:[f64] }:$src) => (ABS_Fp64:{ *:[f64] }:{ *:[i16] } RFP64:{ *:[f64] }:$src) 22238 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::ABS_Fp64, 22239 GIR_AddImplicitDef, /*InsnID*/0, X86::FPSW, 22240 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 22241 // GIR_Coverage, 780, 22242 GIR_Done, 22243 // Label 1790: @50737 22244 GIM_Reject, 22245 // Label 1787: @50738 22246 GIM_Try, /*On fail goto*//*Label 1791*/ 50764, // Rule ID 781 // 22247 GIM_CheckFeatures, GIFBS_HasX87, 22248 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s80, 22249 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::RFP80RegClassID, 22250 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::RFP80RegClassID, 22251 // (fabs:{ *:[f80] } RFP80:{ *:[f80] }:$src) => (ABS_Fp80:{ *:[f80] }:{ *:[i16] } RFP80:{ *:[f80] }:$src) 22252 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::ABS_Fp80, 22253 GIR_AddImplicitDef, /*InsnID*/0, X86::FPSW, 22254 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 22255 // GIR_Coverage, 781, 22256 GIR_Done, 22257 // Label 1791: @50764 22258 GIM_Reject, 22259 // Label 1788: @50765 22260 GIM_Reject, 22261 // Label 44: @50766 22262 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/8, 25, /*)*//*default:*//*Label 1804*/ 51702, 22263 /*GILLT_v2s64*//*Label 1792*/ 50789, 0, 22264 /*GILLT_v4s32*//*Label 1793*/ 50973, 22265 /*GILLT_v4s64*//*Label 1794*/ 51054, 0, 22266 /*GILLT_v8s16*//*Label 1795*/ 51238, 22267 /*GILLT_v8s32*//*Label 1796*/ 51319, 22268 /*GILLT_v8s64*//*Label 1797*/ 51377, 0, 22269 /*GILLT_v16s8*//*Label 1798*/ 51409, 22270 /*GILLT_v16s16*//*Label 1799*/ 51490, 22271 /*GILLT_v16s32*//*Label 1800*/ 51548, 0, 22272 /*GILLT_v32s8*//*Label 1801*/ 51580, 22273 /*GILLT_v32s16*//*Label 1802*/ 51638, 0, 22274 /*GILLT_v64s8*//*Label 1803*/ 51670, 22275 // Label 1792: @50789 22276 GIM_Try, /*On fail goto*//*Label 1805*/ 50972, 22277 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, 22278 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 22279 GIM_Try, /*On fail goto*//*Label 1806*/ 50822, // Rule ID 5226 // 22280 GIM_CheckFeatures, GIFBS_HasAVX512_HasVLX, 22281 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID, 22282 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID, 22283 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128XRegClassID, 22284 // (smin:{ *:[v2i64] } VR128X:{ *:[v2i64] }:$src1, VR128X:{ *:[v2i64] }:$src2) => (VPMINSQZ128rr:{ *:[v2i64] } VR128X:{ *:[v2i64] }:$src1, VR128X:{ *:[v2i64] }:$src2) 22285 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMINSQZ128rr, 22286 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 22287 // GIR_Coverage, 5226, 22288 GIR_Done, 22289 // Label 1806: @50822 22290 GIM_Try, /*On fail goto*//*Label 1807*/ 50971, // Rule ID 18499 // 22291 GIM_CheckFeatures, GIFBS_HasAVX512_NoVLX, 22292 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 22293 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID, 22294 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128XRegClassID, 22295 // (smin:{ *:[v2i64] } VR128X:{ *:[v2i64] }:$src1, VR128X:{ *:[v2i64] }:$src2) => (EXTRACT_SUBREG:{ *:[v2i64] } (VPMINSQZrr:{ *:[v64i8] } (INSERT_SUBREG:{ *:[v8i64] } (IMPLICIT_DEF:{ *:[v8i64] }), VR128X:{ *:[v2i64] }:$src1, sub_xmm:{ *:[i32] }), (INSERT_SUBREG:{ *:[v8i64] } (IMPLICIT_DEF:{ *:[v8i64] }), VR128X:{ *:[v2i64] }:$src2, sub_xmm:{ *:[i32] })), sub_xmm:{ *:[i32] }) 22296 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v64s8, 22297 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s64, 22298 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v8s64, 22299 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v8s64, 22300 GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v8s64, 22301 GIR_BuildMI, /*InsnID*/5, /*Opcode*/TargetOpcode::IMPLICIT_DEF, 22302 GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/RegState::Define, 22303 GIR_ConstrainSelectedInstOperands, /*InsnID*/5, 22304 GIR_BuildMI, /*InsnID*/4, /*Opcode*/TargetOpcode::INSERT_SUBREG, 22305 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define, 22306 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/4, /*TempRegFlags*/0, 22307 GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/2, // src2 22308 GIR_AddImm, /*InsnID*/4, /*Imm*/9, 22309 GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, X86::VR512RegClassID, 22310 GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/1, X86::VR512RegClassID, 22311 GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/2, X86::VR128XRegClassID, 22312 GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::IMPLICIT_DEF, 22313 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, 22314 GIR_ConstrainSelectedInstOperands, /*InsnID*/3, 22315 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::INSERT_SUBREG, 22316 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 22317 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/2, /*TempRegFlags*/0, 22318 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src1 22319 GIR_AddImm, /*InsnID*/2, /*Imm*/9, 22320 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, X86::VR512RegClassID, 22321 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, X86::VR512RegClassID, 22322 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, X86::VR128XRegClassID, 22323 GIR_BuildMI, /*InsnID*/1, /*Opcode*/X86::VPMINSQZrr, 22324 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 22325 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, 22326 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/3, /*TempRegFlags*/0, 22327 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 22328 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 22329 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 22330 GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, X86::sub_xmm, 22331 GIR_EraseFromParent, /*InsnID*/0, 22332 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, X86::FR16XRegClassID, 22333 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, X86::VR512RegClassID, 22334 // GIR_Coverage, 18499, 22335 GIR_Done, 22336 // Label 1807: @50971 22337 GIM_Reject, 22338 // Label 1805: @50972 22339 GIM_Reject, 22340 // Label 1793: @50973 22341 GIM_Try, /*On fail goto*//*Label 1808*/ 51053, 22342 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, 22343 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 22344 GIM_Try, /*On fail goto*//*Label 1809*/ 51006, // Rule ID 2877 // 22345 GIM_CheckFeatures, GIFBS_HasAVX_NoVLX, 22346 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 22347 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 22348 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 22349 // (smin:{ *:[v4i32] } VR128:{ *:[v4i32] }:$src1, VR128:{ *:[v4i32] }:$src2) => (VPMINSDrr:{ *:[v4i32] } VR128:{ *:[v4i32] }:$src1, VR128:{ *:[v4i32] }:$src2) 22350 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMINSDrr, 22351 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 22352 // GIR_Coverage, 2877, 22353 GIR_Done, 22354 // Label 1809: @51006 22355 GIM_Try, /*On fail goto*//*Label 1810*/ 51029, // Rule ID 2915 // 22356 GIM_CheckFeatures, GIFBS_UseSSE41, 22357 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 22358 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 22359 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 22360 // (smin:{ *:[v4i32] } VR128:{ *:[v4i32] }:$src1, VR128:{ *:[v4i32] }:$src2) => (PMINSDrr:{ *:[v4i32] } VR128:{ *:[v4i32] }:$src1, VR128:{ *:[v4i32] }:$src2) 22361 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::PMINSDrr, 22362 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 22363 // GIR_Coverage, 2915, 22364 GIR_Done, 22365 // Label 1810: @51029 22366 GIM_Try, /*On fail goto*//*Label 1811*/ 51052, // Rule ID 5199 // 22367 GIM_CheckFeatures, GIFBS_HasAVX512_HasVLX, 22368 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID, 22369 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID, 22370 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128XRegClassID, 22371 // (smin:{ *:[v4i32] } VR128X:{ *:[v4i32] }:$src1, VR128X:{ *:[v4i32] }:$src2) => (VPMINSDZ128rr:{ *:[v4i32] } VR128X:{ *:[v4i32] }:$src1, VR128X:{ *:[v4i32] }:$src2) 22372 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMINSDZ128rr, 22373 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 22374 // GIR_Coverage, 5199, 22375 GIR_Done, 22376 // Label 1811: @51052 22377 GIM_Reject, 22378 // Label 1808: @51053 22379 GIM_Reject, 22380 // Label 1794: @51054 22381 GIM_Try, /*On fail goto*//*Label 1812*/ 51237, 22382 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s64, 22383 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s64, 22384 GIM_Try, /*On fail goto*//*Label 1813*/ 51087, // Rule ID 5217 // 22385 GIM_CheckFeatures, GIFBS_HasAVX512_HasVLX, 22386 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID, 22387 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID, 22388 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256XRegClassID, 22389 // (smin:{ *:[v4i64] } VR256X:{ *:[v4i64] }:$src1, VR256X:{ *:[v4i64] }:$src2) => (VPMINSQZ256rr:{ *:[v4i64] } VR256X:{ *:[v4i64] }:$src1, VR256X:{ *:[v4i64] }:$src2) 22390 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMINSQZ256rr, 22391 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 22392 // GIR_Coverage, 5217, 22393 GIR_Done, 22394 // Label 1813: @51087 22395 GIM_Try, /*On fail goto*//*Label 1814*/ 51236, // Rule ID 18497 // 22396 GIM_CheckFeatures, GIFBS_HasAVX512_NoVLX, 22397 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 22398 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID, 22399 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256XRegClassID, 22400 // (smin:{ *:[v4i64] } VR256X:{ *:[v4i64] }:$src1, VR256X:{ *:[v4i64] }:$src2) => (EXTRACT_SUBREG:{ *:[v4i64] } (VPMINSQZrr:{ *:[v64i8] } (INSERT_SUBREG:{ *:[v8i64] } (IMPLICIT_DEF:{ *:[v8i64] }), VR256X:{ *:[v4i64] }:$src1, sub_ymm:{ *:[i32] }), (INSERT_SUBREG:{ *:[v8i64] } (IMPLICIT_DEF:{ *:[v8i64] }), VR256X:{ *:[v4i64] }:$src2, sub_ymm:{ *:[i32] })), sub_ymm:{ *:[i32] }) 22401 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v64s8, 22402 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s64, 22403 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v8s64, 22404 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v8s64, 22405 GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v8s64, 22406 GIR_BuildMI, /*InsnID*/5, /*Opcode*/TargetOpcode::IMPLICIT_DEF, 22407 GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/RegState::Define, 22408 GIR_ConstrainSelectedInstOperands, /*InsnID*/5, 22409 GIR_BuildMI, /*InsnID*/4, /*Opcode*/TargetOpcode::INSERT_SUBREG, 22410 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define, 22411 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/4, /*TempRegFlags*/0, 22412 GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/2, // src2 22413 GIR_AddImm, /*InsnID*/4, /*Imm*/10, 22414 GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, X86::VR512RegClassID, 22415 GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/1, X86::VR512RegClassID, 22416 GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/2, X86::VR256XRegClassID, 22417 GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::IMPLICIT_DEF, 22418 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, 22419 GIR_ConstrainSelectedInstOperands, /*InsnID*/3, 22420 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::INSERT_SUBREG, 22421 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 22422 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/2, /*TempRegFlags*/0, 22423 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src1 22424 GIR_AddImm, /*InsnID*/2, /*Imm*/10, 22425 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, X86::VR512RegClassID, 22426 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, X86::VR512RegClassID, 22427 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, X86::VR256XRegClassID, 22428 GIR_BuildMI, /*InsnID*/1, /*Opcode*/X86::VPMINSQZrr, 22429 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 22430 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, 22431 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/3, /*TempRegFlags*/0, 22432 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 22433 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 22434 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 22435 GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, X86::sub_ymm, 22436 GIR_EraseFromParent, /*InsnID*/0, 22437 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, X86::VR256XRegClassID, 22438 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, X86::VR512RegClassID, 22439 // GIR_Coverage, 18497, 22440 GIR_Done, 22441 // Label 1814: @51236 22442 GIM_Reject, 22443 // Label 1812: @51237 22444 GIM_Reject, 22445 // Label 1795: @51238 22446 GIM_Try, /*On fail goto*//*Label 1815*/ 51318, 22447 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, 22448 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 22449 GIM_Try, /*On fail goto*//*Label 1816*/ 51271, // Rule ID 2334 // 22450 GIM_CheckFeatures, GIFBS_HasAVX_NoVLX_Or_NoBWI, 22451 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 22452 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 22453 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 22454 // (smin:{ *:[v8i16] } VR128:{ *:[v8i16] }:$src1, VR128:{ *:[v8i16] }:$src2) => (VPMINSWrr:{ *:[v8i16] } VR128:{ *:[v8i16] }:$src1, VR128:{ *:[v8i16] }:$src2) 22455 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMINSWrr, 22456 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 22457 // GIR_Coverage, 2334, 22458 GIR_Done, 22459 // Label 1816: @51271 22460 GIM_Try, /*On fail goto*//*Label 1817*/ 51294, // Rule ID 2336 // 22461 GIM_CheckFeatures, GIFBS_UseSSE2, 22462 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 22463 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 22464 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 22465 // (smin:{ *:[v8i16] } VR128:{ *:[v8i16] }:$src1, VR128:{ *:[v8i16] }:$src2) => (PMINSWrr:{ *:[v8i16] } VR128:{ *:[v8i16] }:$src1, VR128:{ *:[v8i16] }:$src2) 22466 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::PMINSWrr, 22467 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 22468 // GIR_Coverage, 2336, 22469 GIR_Done, 22470 // Label 1817: @51294 22471 GIM_Try, /*On fail goto*//*Label 1818*/ 51317, // Rule ID 5175 // 22472 GIM_CheckFeatures, GIFBS_HasBWI_HasVLX, 22473 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID, 22474 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID, 22475 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128XRegClassID, 22476 // (smin:{ *:[v8i16] } VR128X:{ *:[v8i16] }:$src1, VR128X:{ *:[v8i16] }:$src2) => (VPMINSWZ128rr:{ *:[v8i16] } VR128X:{ *:[v8i16] }:$src1, VR128X:{ *:[v8i16] }:$src2) 22477 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMINSWZ128rr, 22478 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 22479 // GIR_Coverage, 5175, 22480 GIR_Done, 22481 // Label 1818: @51317 22482 GIM_Reject, 22483 // Label 1815: @51318 22484 GIM_Reject, 22485 // Label 1796: @51319 22486 GIM_Try, /*On fail goto*//*Label 1819*/ 51376, 22487 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s32, 22488 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s32, 22489 GIM_Try, /*On fail goto*//*Label 1820*/ 51352, // Rule ID 2895 // 22490 GIM_CheckFeatures, GIFBS_HasAVX2_NoVLX, 22491 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID, 22492 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256RegClassID, 22493 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256RegClassID, 22494 // (smin:{ *:[v8i32] } VR256:{ *:[v8i32] }:$src1, VR256:{ *:[v8i32] }:$src2) => (VPMINSDYrr:{ *:[v8i32] } VR256:{ *:[v8i32] }:$src1, VR256:{ *:[v8i32] }:$src2) 22495 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMINSDYrr, 22496 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 22497 // GIR_Coverage, 2895, 22498 GIR_Done, 22499 // Label 1820: @51352 22500 GIM_Try, /*On fail goto*//*Label 1821*/ 51375, // Rule ID 5190 // 22501 GIM_CheckFeatures, GIFBS_HasAVX512_HasVLX, 22502 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID, 22503 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID, 22504 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256XRegClassID, 22505 // (smin:{ *:[v8i32] } VR256X:{ *:[v8i32] }:$src1, VR256X:{ *:[v8i32] }:$src2) => (VPMINSDZ256rr:{ *:[v8i32] } VR256X:{ *:[v8i32] }:$src1, VR256X:{ *:[v8i32] }:$src2) 22506 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMINSDZ256rr, 22507 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 22508 // GIR_Coverage, 5190, 22509 GIR_Done, 22510 // Label 1821: @51375 22511 GIM_Reject, 22512 // Label 1819: @51376 22513 GIM_Reject, 22514 // Label 1797: @51377 22515 GIM_Try, /*On fail goto*//*Label 1822*/ 51408, // Rule ID 5208 // 22516 GIM_CheckFeatures, GIFBS_HasAVX512, 22517 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s64, 22518 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s64, 22519 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 22520 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR512RegClassID, 22521 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR512RegClassID, 22522 // (smin:{ *:[v8i64] } VR512:{ *:[v8i64] }:$src1, VR512:{ *:[v8i64] }:$src2) => (VPMINSQZrr:{ *:[v8i64] } VR512:{ *:[v8i64] }:$src1, VR512:{ *:[v8i64] }:$src2) 22523 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMINSQZrr, 22524 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 22525 // GIR_Coverage, 5208, 22526 GIR_Done, 22527 // Label 1822: @51408 22528 GIM_Reject, 22529 // Label 1798: @51409 22530 GIM_Try, /*On fail goto*//*Label 1823*/ 51489, 22531 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, 22532 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, 22533 GIM_Try, /*On fail goto*//*Label 1824*/ 51442, // Rule ID 2887 // 22534 GIM_CheckFeatures, GIFBS_HasAVX_NoVLX_Or_NoBWI, 22535 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 22536 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 22537 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 22538 // (smin:{ *:[v16i8] } VR128:{ *:[v16i8] }:$src1, VR128:{ *:[v16i8] }:$src2) => (VPMINSBrr:{ *:[v16i8] } VR128:{ *:[v16i8] }:$src1, VR128:{ *:[v16i8] }:$src2) 22539 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMINSBrr, 22540 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 22541 // GIR_Coverage, 2887, 22542 GIR_Done, 22543 // Label 1824: @51442 22544 GIM_Try, /*On fail goto*//*Label 1825*/ 51465, // Rule ID 2913 // 22545 GIM_CheckFeatures, GIFBS_UseSSE41, 22546 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 22547 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 22548 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 22549 // (smin:{ *:[v16i8] } VR128:{ *:[v16i8] }:$src1, VR128:{ *:[v16i8] }:$src2) => (PMINSBrr:{ *:[v16i8] } VR128:{ *:[v16i8] }:$src1, VR128:{ *:[v16i8] }:$src2) 22550 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::PMINSBrr, 22551 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 22552 // GIR_Coverage, 2913, 22553 GIR_Done, 22554 // Label 1825: @51465 22555 GIM_Try, /*On fail goto*//*Label 1826*/ 51488, // Rule ID 5157 // 22556 GIM_CheckFeatures, GIFBS_HasBWI_HasVLX, 22557 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID, 22558 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID, 22559 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128XRegClassID, 22560 // (smin:{ *:[v16i8] } VR128X:{ *:[v16i8] }:$src1, VR128X:{ *:[v16i8] }:$src2) => (VPMINSBZ128rr:{ *:[v16i8] } VR128X:{ *:[v16i8] }:$src1, VR128X:{ *:[v16i8] }:$src2) 22561 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMINSBZ128rr, 22562 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 22563 // GIR_Coverage, 5157, 22564 GIR_Done, 22565 // Label 1826: @51488 22566 GIM_Reject, 22567 // Label 1823: @51489 22568 GIM_Reject, 22569 // Label 1799: @51490 22570 GIM_Try, /*On fail goto*//*Label 1827*/ 51547, 22571 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s16, 22572 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s16, 22573 GIM_Try, /*On fail goto*//*Label 1828*/ 51523, // Rule ID 2338 // 22574 GIM_CheckFeatures, GIFBS_HasAVX2_NoVLX_Or_NoBWI, 22575 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID, 22576 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256RegClassID, 22577 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256RegClassID, 22578 // (smin:{ *:[v16i16] } VR256:{ *:[v16i16] }:$src1, VR256:{ *:[v16i16] }:$src2) => (VPMINSWYrr:{ *:[v16i16] } VR256:{ *:[v16i16] }:$src1, VR256:{ *:[v16i16] }:$src2) 22579 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMINSWYrr, 22580 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 22581 // GIR_Coverage, 2338, 22582 GIR_Done, 22583 // Label 1828: @51523 22584 GIM_Try, /*On fail goto*//*Label 1829*/ 51546, // Rule ID 5169 // 22585 GIM_CheckFeatures, GIFBS_HasBWI_HasVLX, 22586 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID, 22587 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID, 22588 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256XRegClassID, 22589 // (smin:{ *:[v16i16] } VR256X:{ *:[v16i16] }:$src1, VR256X:{ *:[v16i16] }:$src2) => (VPMINSWZ256rr:{ *:[v16i16] } VR256X:{ *:[v16i16] }:$src1, VR256X:{ *:[v16i16] }:$src2) 22590 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMINSWZ256rr, 22591 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 22592 // GIR_Coverage, 5169, 22593 GIR_Done, 22594 // Label 1829: @51546 22595 GIM_Reject, 22596 // Label 1827: @51547 22597 GIM_Reject, 22598 // Label 1800: @51548 22599 GIM_Try, /*On fail goto*//*Label 1830*/ 51579, // Rule ID 5181 // 22600 GIM_CheckFeatures, GIFBS_HasAVX512, 22601 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s32, 22602 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s32, 22603 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 22604 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR512RegClassID, 22605 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR512RegClassID, 22606 // (smin:{ *:[v16i32] } VR512:{ *:[v16i32] }:$src1, VR512:{ *:[v16i32] }:$src2) => (VPMINSDZrr:{ *:[v16i32] } VR512:{ *:[v16i32] }:$src1, VR512:{ *:[v16i32] }:$src2) 22607 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMINSDZrr, 22608 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 22609 // GIR_Coverage, 5181, 22610 GIR_Done, 22611 // Label 1830: @51579 22612 GIM_Reject, 22613 // Label 1801: @51580 22614 GIM_Try, /*On fail goto*//*Label 1831*/ 51637, 22615 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v32s8, 22616 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v32s8, 22617 GIM_Try, /*On fail goto*//*Label 1832*/ 51613, // Rule ID 2905 // 22618 GIM_CheckFeatures, GIFBS_HasAVX2_NoVLX_Or_NoBWI, 22619 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID, 22620 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256RegClassID, 22621 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256RegClassID, 22622 // (smin:{ *:[v32i8] } VR256:{ *:[v32i8] }:$src1, VR256:{ *:[v32i8] }:$src2) => (VPMINSBYrr:{ *:[v32i8] } VR256:{ *:[v32i8] }:$src1, VR256:{ *:[v32i8] }:$src2) 22623 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMINSBYrr, 22624 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 22625 // GIR_Coverage, 2905, 22626 GIR_Done, 22627 // Label 1832: @51613 22628 GIM_Try, /*On fail goto*//*Label 1833*/ 51636, // Rule ID 5151 // 22629 GIM_CheckFeatures, GIFBS_HasBWI_HasVLX, 22630 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID, 22631 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID, 22632 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256XRegClassID, 22633 // (smin:{ *:[v32i8] } VR256X:{ *:[v32i8] }:$src1, VR256X:{ *:[v32i8] }:$src2) => (VPMINSBZ256rr:{ *:[v32i8] } VR256X:{ *:[v32i8] }:$src1, VR256X:{ *:[v32i8] }:$src2) 22634 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMINSBZ256rr, 22635 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 22636 // GIR_Coverage, 5151, 22637 GIR_Done, 22638 // Label 1833: @51636 22639 GIM_Reject, 22640 // Label 1831: @51637 22641 GIM_Reject, 22642 // Label 1802: @51638 22643 GIM_Try, /*On fail goto*//*Label 1834*/ 51669, // Rule ID 5163 // 22644 GIM_CheckFeatures, GIFBS_HasBWI, 22645 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v32s16, 22646 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v32s16, 22647 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 22648 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR512RegClassID, 22649 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR512RegClassID, 22650 // (smin:{ *:[v32i16] } VR512:{ *:[v32i16] }:$src1, VR512:{ *:[v32i16] }:$src2) => (VPMINSWZrr:{ *:[v32i16] } VR512:{ *:[v32i16] }:$src1, VR512:{ *:[v32i16] }:$src2) 22651 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMINSWZrr, 22652 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 22653 // GIR_Coverage, 5163, 22654 GIR_Done, 22655 // Label 1834: @51669 22656 GIM_Reject, 22657 // Label 1803: @51670 22658 GIM_Try, /*On fail goto*//*Label 1835*/ 51701, // Rule ID 5145 // 22659 GIM_CheckFeatures, GIFBS_HasBWI, 22660 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v64s8, 22661 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v64s8, 22662 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 22663 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR512RegClassID, 22664 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR512RegClassID, 22665 // (smin:{ *:[v64i8] } VR512:{ *:[v64i8] }:$src1, VR512:{ *:[v64i8] }:$src2) => (VPMINSBZrr:{ *:[v64i8] } VR512:{ *:[v64i8] }:$src1, VR512:{ *:[v64i8] }:$src2) 22666 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMINSBZrr, 22667 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 22668 // GIR_Coverage, 5145, 22669 GIR_Done, 22670 // Label 1835: @51701 22671 GIM_Reject, 22672 // Label 1804: @51702 22673 GIM_Reject, 22674 // Label 45: @51703 22675 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/8, 25, /*)*//*default:*//*Label 1848*/ 52639, 22676 /*GILLT_v2s64*//*Label 1836*/ 51726, 0, 22677 /*GILLT_v4s32*//*Label 1837*/ 51910, 22678 /*GILLT_v4s64*//*Label 1838*/ 51991, 0, 22679 /*GILLT_v8s16*//*Label 1839*/ 52175, 22680 /*GILLT_v8s32*//*Label 1840*/ 52256, 22681 /*GILLT_v8s64*//*Label 1841*/ 52314, 0, 22682 /*GILLT_v16s8*//*Label 1842*/ 52346, 22683 /*GILLT_v16s16*//*Label 1843*/ 52427, 22684 /*GILLT_v16s32*//*Label 1844*/ 52485, 0, 22685 /*GILLT_v32s8*//*Label 1845*/ 52517, 22686 /*GILLT_v32s16*//*Label 1846*/ 52575, 0, 22687 /*GILLT_v64s8*//*Label 1847*/ 52607, 22688 // Label 1836: @51726 22689 GIM_Try, /*On fail goto*//*Label 1849*/ 51909, 22690 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, 22691 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 22692 GIM_Try, /*On fail goto*//*Label 1850*/ 51759, // Rule ID 5046 // 22693 GIM_CheckFeatures, GIFBS_HasAVX512_HasVLX, 22694 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID, 22695 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID, 22696 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128XRegClassID, 22697 // (smax:{ *:[v2i64] } VR128X:{ *:[v2i64] }:$src1, VR128X:{ *:[v2i64] }:$src2) => (VPMAXSQZ128rr:{ *:[v2i64] } VR128X:{ *:[v2i64] }:$src1, VR128X:{ *:[v2i64] }:$src2) 22698 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMAXSQZ128rr, 22699 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 22700 // GIR_Coverage, 5046, 22701 GIR_Done, 22702 // Label 1850: @51759 22703 GIM_Try, /*On fail goto*//*Label 1851*/ 51908, // Rule ID 18495 // 22704 GIM_CheckFeatures, GIFBS_HasAVX512_NoVLX, 22705 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 22706 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID, 22707 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128XRegClassID, 22708 // (smax:{ *:[v2i64] } VR128X:{ *:[v2i64] }:$src1, VR128X:{ *:[v2i64] }:$src2) => (EXTRACT_SUBREG:{ *:[v2i64] } (VPMAXSQZrr:{ *:[v64i8] } (INSERT_SUBREG:{ *:[v8i64] } (IMPLICIT_DEF:{ *:[v8i64] }), VR128X:{ *:[v2i64] }:$src1, sub_xmm:{ *:[i32] }), (INSERT_SUBREG:{ *:[v8i64] } (IMPLICIT_DEF:{ *:[v8i64] }), VR128X:{ *:[v2i64] }:$src2, sub_xmm:{ *:[i32] })), sub_xmm:{ *:[i32] }) 22709 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v64s8, 22710 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s64, 22711 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v8s64, 22712 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v8s64, 22713 GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v8s64, 22714 GIR_BuildMI, /*InsnID*/5, /*Opcode*/TargetOpcode::IMPLICIT_DEF, 22715 GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/RegState::Define, 22716 GIR_ConstrainSelectedInstOperands, /*InsnID*/5, 22717 GIR_BuildMI, /*InsnID*/4, /*Opcode*/TargetOpcode::INSERT_SUBREG, 22718 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define, 22719 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/4, /*TempRegFlags*/0, 22720 GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/2, // src2 22721 GIR_AddImm, /*InsnID*/4, /*Imm*/9, 22722 GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, X86::VR512RegClassID, 22723 GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/1, X86::VR512RegClassID, 22724 GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/2, X86::VR128XRegClassID, 22725 GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::IMPLICIT_DEF, 22726 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, 22727 GIR_ConstrainSelectedInstOperands, /*InsnID*/3, 22728 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::INSERT_SUBREG, 22729 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 22730 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/2, /*TempRegFlags*/0, 22731 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src1 22732 GIR_AddImm, /*InsnID*/2, /*Imm*/9, 22733 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, X86::VR512RegClassID, 22734 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, X86::VR512RegClassID, 22735 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, X86::VR128XRegClassID, 22736 GIR_BuildMI, /*InsnID*/1, /*Opcode*/X86::VPMAXSQZrr, 22737 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 22738 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, 22739 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/3, /*TempRegFlags*/0, 22740 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 22741 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 22742 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 22743 GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, X86::sub_xmm, 22744 GIR_EraseFromParent, /*InsnID*/0, 22745 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, X86::FR16XRegClassID, 22746 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, X86::VR512RegClassID, 22747 // GIR_Coverage, 18495, 22748 GIR_Done, 22749 // Label 1851: @51908 22750 GIM_Reject, 22751 // Label 1849: @51909 22752 GIM_Reject, 22753 // Label 1837: @51910 22754 GIM_Try, /*On fail goto*//*Label 1852*/ 51990, 22755 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, 22756 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 22757 GIM_Try, /*On fail goto*//*Label 1853*/ 51943, // Rule ID 2881 // 22758 GIM_CheckFeatures, GIFBS_HasAVX_NoVLX, 22759 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 22760 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 22761 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 22762 // (smax:{ *:[v4i32] } VR128:{ *:[v4i32] }:$src1, VR128:{ *:[v4i32] }:$src2) => (VPMAXSDrr:{ *:[v4i32] } VR128:{ *:[v4i32] }:$src1, VR128:{ *:[v4i32] }:$src2) 22763 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMAXSDrr, 22764 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 22765 // GIR_Coverage, 2881, 22766 GIR_Done, 22767 // Label 1853: @51943 22768 GIM_Try, /*On fail goto*//*Label 1854*/ 51966, // Rule ID 2923 // 22769 GIM_CheckFeatures, GIFBS_UseSSE41, 22770 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 22771 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 22772 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 22773 // (smax:{ *:[v4i32] } VR128:{ *:[v4i32] }:$src1, VR128:{ *:[v4i32] }:$src2) => (PMAXSDrr:{ *:[v4i32] } VR128:{ *:[v4i32] }:$src1, VR128:{ *:[v4i32] }:$src2) 22774 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::PMAXSDrr, 22775 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 22776 // GIR_Coverage, 2923, 22777 GIR_Done, 22778 // Label 1854: @51966 22779 GIM_Try, /*On fail goto*//*Label 1855*/ 51989, // Rule ID 5019 // 22780 GIM_CheckFeatures, GIFBS_HasAVX512_HasVLX, 22781 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID, 22782 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID, 22783 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128XRegClassID, 22784 // (smax:{ *:[v4i32] } VR128X:{ *:[v4i32] }:$src1, VR128X:{ *:[v4i32] }:$src2) => (VPMAXSDZ128rr:{ *:[v4i32] } VR128X:{ *:[v4i32] }:$src1, VR128X:{ *:[v4i32] }:$src2) 22785 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMAXSDZ128rr, 22786 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 22787 // GIR_Coverage, 5019, 22788 GIR_Done, 22789 // Label 1855: @51989 22790 GIM_Reject, 22791 // Label 1852: @51990 22792 GIM_Reject, 22793 // Label 1838: @51991 22794 GIM_Try, /*On fail goto*//*Label 1856*/ 52174, 22795 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s64, 22796 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s64, 22797 GIM_Try, /*On fail goto*//*Label 1857*/ 52024, // Rule ID 5037 // 22798 GIM_CheckFeatures, GIFBS_HasAVX512_HasVLX, 22799 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID, 22800 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID, 22801 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256XRegClassID, 22802 // (smax:{ *:[v4i64] } VR256X:{ *:[v4i64] }:$src1, VR256X:{ *:[v4i64] }:$src2) => (VPMAXSQZ256rr:{ *:[v4i64] } VR256X:{ *:[v4i64] }:$src1, VR256X:{ *:[v4i64] }:$src2) 22803 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMAXSQZ256rr, 22804 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 22805 // GIR_Coverage, 5037, 22806 GIR_Done, 22807 // Label 1857: @52024 22808 GIM_Try, /*On fail goto*//*Label 1858*/ 52173, // Rule ID 18493 // 22809 GIM_CheckFeatures, GIFBS_HasAVX512_NoVLX, 22810 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 22811 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID, 22812 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256XRegClassID, 22813 // (smax:{ *:[v4i64] } VR256X:{ *:[v4i64] }:$src1, VR256X:{ *:[v4i64] }:$src2) => (EXTRACT_SUBREG:{ *:[v4i64] } (VPMAXSQZrr:{ *:[v64i8] } (INSERT_SUBREG:{ *:[v8i64] } (IMPLICIT_DEF:{ *:[v8i64] }), VR256X:{ *:[v4i64] }:$src1, sub_ymm:{ *:[i32] }), (INSERT_SUBREG:{ *:[v8i64] } (IMPLICIT_DEF:{ *:[v8i64] }), VR256X:{ *:[v4i64] }:$src2, sub_ymm:{ *:[i32] })), sub_ymm:{ *:[i32] }) 22814 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v64s8, 22815 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s64, 22816 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v8s64, 22817 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v8s64, 22818 GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v8s64, 22819 GIR_BuildMI, /*InsnID*/5, /*Opcode*/TargetOpcode::IMPLICIT_DEF, 22820 GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/RegState::Define, 22821 GIR_ConstrainSelectedInstOperands, /*InsnID*/5, 22822 GIR_BuildMI, /*InsnID*/4, /*Opcode*/TargetOpcode::INSERT_SUBREG, 22823 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define, 22824 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/4, /*TempRegFlags*/0, 22825 GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/2, // src2 22826 GIR_AddImm, /*InsnID*/4, /*Imm*/10, 22827 GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, X86::VR512RegClassID, 22828 GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/1, X86::VR512RegClassID, 22829 GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/2, X86::VR256XRegClassID, 22830 GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::IMPLICIT_DEF, 22831 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, 22832 GIR_ConstrainSelectedInstOperands, /*InsnID*/3, 22833 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::INSERT_SUBREG, 22834 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 22835 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/2, /*TempRegFlags*/0, 22836 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src1 22837 GIR_AddImm, /*InsnID*/2, /*Imm*/10, 22838 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, X86::VR512RegClassID, 22839 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, X86::VR512RegClassID, 22840 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, X86::VR256XRegClassID, 22841 GIR_BuildMI, /*InsnID*/1, /*Opcode*/X86::VPMAXSQZrr, 22842 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 22843 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, 22844 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/3, /*TempRegFlags*/0, 22845 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 22846 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 22847 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 22848 GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, X86::sub_ymm, 22849 GIR_EraseFromParent, /*InsnID*/0, 22850 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, X86::VR256XRegClassID, 22851 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, X86::VR512RegClassID, 22852 // GIR_Coverage, 18493, 22853 GIR_Done, 22854 // Label 1858: @52173 22855 GIM_Reject, 22856 // Label 1856: @52174 22857 GIM_Reject, 22858 // Label 1839: @52175 22859 GIM_Try, /*On fail goto*//*Label 1859*/ 52255, 22860 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, 22861 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 22862 GIM_Try, /*On fail goto*//*Label 1860*/ 52208, // Rule ID 2346 // 22863 GIM_CheckFeatures, GIFBS_HasAVX_NoVLX_Or_NoBWI, 22864 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 22865 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 22866 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 22867 // (smax:{ *:[v8i16] } VR128:{ *:[v8i16] }:$src1, VR128:{ *:[v8i16] }:$src2) => (VPMAXSWrr:{ *:[v8i16] } VR128:{ *:[v8i16] }:$src1, VR128:{ *:[v8i16] }:$src2) 22868 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMAXSWrr, 22869 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 22870 // GIR_Coverage, 2346, 22871 GIR_Done, 22872 // Label 1860: @52208 22873 GIM_Try, /*On fail goto*//*Label 1861*/ 52231, // Rule ID 2348 // 22874 GIM_CheckFeatures, GIFBS_UseSSE2, 22875 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 22876 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 22877 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 22878 // (smax:{ *:[v8i16] } VR128:{ *:[v8i16] }:$src1, VR128:{ *:[v8i16] }:$src2) => (PMAXSWrr:{ *:[v8i16] } VR128:{ *:[v8i16] }:$src1, VR128:{ *:[v8i16] }:$src2) 22879 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::PMAXSWrr, 22880 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 22881 // GIR_Coverage, 2348, 22882 GIR_Done, 22883 // Label 1861: @52231 22884 GIM_Try, /*On fail goto*//*Label 1862*/ 52254, // Rule ID 4995 // 22885 GIM_CheckFeatures, GIFBS_HasBWI_HasVLX, 22886 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID, 22887 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID, 22888 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128XRegClassID, 22889 // (smax:{ *:[v8i16] } VR128X:{ *:[v8i16] }:$src1, VR128X:{ *:[v8i16] }:$src2) => (VPMAXSWZ128rr:{ *:[v8i16] } VR128X:{ *:[v8i16] }:$src1, VR128X:{ *:[v8i16] }:$src2) 22890 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMAXSWZ128rr, 22891 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 22892 // GIR_Coverage, 4995, 22893 GIR_Done, 22894 // Label 1862: @52254 22895 GIM_Reject, 22896 // Label 1859: @52255 22897 GIM_Reject, 22898 // Label 1840: @52256 22899 GIM_Try, /*On fail goto*//*Label 1863*/ 52313, 22900 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s32, 22901 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s32, 22902 GIM_Try, /*On fail goto*//*Label 1864*/ 52289, // Rule ID 2899 // 22903 GIM_CheckFeatures, GIFBS_HasAVX2_NoVLX, 22904 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID, 22905 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256RegClassID, 22906 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256RegClassID, 22907 // (smax:{ *:[v8i32] } VR256:{ *:[v8i32] }:$src1, VR256:{ *:[v8i32] }:$src2) => (VPMAXSDYrr:{ *:[v8i32] } VR256:{ *:[v8i32] }:$src1, VR256:{ *:[v8i32] }:$src2) 22908 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMAXSDYrr, 22909 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 22910 // GIR_Coverage, 2899, 22911 GIR_Done, 22912 // Label 1864: @52289 22913 GIM_Try, /*On fail goto*//*Label 1865*/ 52312, // Rule ID 5010 // 22914 GIM_CheckFeatures, GIFBS_HasAVX512_HasVLX, 22915 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID, 22916 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID, 22917 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256XRegClassID, 22918 // (smax:{ *:[v8i32] } VR256X:{ *:[v8i32] }:$src1, VR256X:{ *:[v8i32] }:$src2) => (VPMAXSDZ256rr:{ *:[v8i32] } VR256X:{ *:[v8i32] }:$src1, VR256X:{ *:[v8i32] }:$src2) 22919 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMAXSDZ256rr, 22920 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 22921 // GIR_Coverage, 5010, 22922 GIR_Done, 22923 // Label 1865: @52312 22924 GIM_Reject, 22925 // Label 1863: @52313 22926 GIM_Reject, 22927 // Label 1841: @52314 22928 GIM_Try, /*On fail goto*//*Label 1866*/ 52345, // Rule ID 5028 // 22929 GIM_CheckFeatures, GIFBS_HasAVX512, 22930 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s64, 22931 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s64, 22932 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 22933 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR512RegClassID, 22934 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR512RegClassID, 22935 // (smax:{ *:[v8i64] } VR512:{ *:[v8i64] }:$src1, VR512:{ *:[v8i64] }:$src2) => (VPMAXSQZrr:{ *:[v8i64] } VR512:{ *:[v8i64] }:$src1, VR512:{ *:[v8i64] }:$src2) 22936 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMAXSQZrr, 22937 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 22938 // GIR_Coverage, 5028, 22939 GIR_Done, 22940 // Label 1866: @52345 22941 GIM_Reject, 22942 // Label 1842: @52346 22943 GIM_Try, /*On fail goto*//*Label 1867*/ 52426, 22944 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, 22945 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, 22946 GIM_Try, /*On fail goto*//*Label 1868*/ 52379, // Rule ID 2891 // 22947 GIM_CheckFeatures, GIFBS_HasAVX_NoVLX_Or_NoBWI, 22948 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 22949 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 22950 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 22951 // (smax:{ *:[v16i8] } VR128:{ *:[v16i8] }:$src1, VR128:{ *:[v16i8] }:$src2) => (VPMAXSBrr:{ *:[v16i8] } VR128:{ *:[v16i8] }:$src1, VR128:{ *:[v16i8] }:$src2) 22952 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMAXSBrr, 22953 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 22954 // GIR_Coverage, 2891, 22955 GIR_Done, 22956 // Label 1868: @52379 22957 GIM_Try, /*On fail goto*//*Label 1869*/ 52402, // Rule ID 2921 // 22958 GIM_CheckFeatures, GIFBS_UseSSE41, 22959 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 22960 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 22961 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 22962 // (smax:{ *:[v16i8] } VR128:{ *:[v16i8] }:$src1, VR128:{ *:[v16i8] }:$src2) => (PMAXSBrr:{ *:[v16i8] } VR128:{ *:[v16i8] }:$src1, VR128:{ *:[v16i8] }:$src2) 22963 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::PMAXSBrr, 22964 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 22965 // GIR_Coverage, 2921, 22966 GIR_Done, 22967 // Label 1869: @52402 22968 GIM_Try, /*On fail goto*//*Label 1870*/ 52425, // Rule ID 4977 // 22969 GIM_CheckFeatures, GIFBS_HasBWI_HasVLX, 22970 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID, 22971 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID, 22972 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128XRegClassID, 22973 // (smax:{ *:[v16i8] } VR128X:{ *:[v16i8] }:$src1, VR128X:{ *:[v16i8] }:$src2) => (VPMAXSBZ128rr:{ *:[v16i8] } VR128X:{ *:[v16i8] }:$src1, VR128X:{ *:[v16i8] }:$src2) 22974 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMAXSBZ128rr, 22975 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 22976 // GIR_Coverage, 4977, 22977 GIR_Done, 22978 // Label 1870: @52425 22979 GIM_Reject, 22980 // Label 1867: @52426 22981 GIM_Reject, 22982 // Label 1843: @52427 22983 GIM_Try, /*On fail goto*//*Label 1871*/ 52484, 22984 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s16, 22985 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s16, 22986 GIM_Try, /*On fail goto*//*Label 1872*/ 52460, // Rule ID 2350 // 22987 GIM_CheckFeatures, GIFBS_HasAVX2_NoVLX_Or_NoBWI, 22988 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID, 22989 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256RegClassID, 22990 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256RegClassID, 22991 // (smax:{ *:[v16i16] } VR256:{ *:[v16i16] }:$src1, VR256:{ *:[v16i16] }:$src2) => (VPMAXSWYrr:{ *:[v16i16] } VR256:{ *:[v16i16] }:$src1, VR256:{ *:[v16i16] }:$src2) 22992 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMAXSWYrr, 22993 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 22994 // GIR_Coverage, 2350, 22995 GIR_Done, 22996 // Label 1872: @52460 22997 GIM_Try, /*On fail goto*//*Label 1873*/ 52483, // Rule ID 4989 // 22998 GIM_CheckFeatures, GIFBS_HasBWI_HasVLX, 22999 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID, 23000 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID, 23001 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256XRegClassID, 23002 // (smax:{ *:[v16i16] } VR256X:{ *:[v16i16] }:$src1, VR256X:{ *:[v16i16] }:$src2) => (VPMAXSWZ256rr:{ *:[v16i16] } VR256X:{ *:[v16i16] }:$src1, VR256X:{ *:[v16i16] }:$src2) 23003 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMAXSWZ256rr, 23004 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 23005 // GIR_Coverage, 4989, 23006 GIR_Done, 23007 // Label 1873: @52483 23008 GIM_Reject, 23009 // Label 1871: @52484 23010 GIM_Reject, 23011 // Label 1844: @52485 23012 GIM_Try, /*On fail goto*//*Label 1874*/ 52516, // Rule ID 5001 // 23013 GIM_CheckFeatures, GIFBS_HasAVX512, 23014 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s32, 23015 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s32, 23016 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 23017 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR512RegClassID, 23018 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR512RegClassID, 23019 // (smax:{ *:[v16i32] } VR512:{ *:[v16i32] }:$src1, VR512:{ *:[v16i32] }:$src2) => (VPMAXSDZrr:{ *:[v16i32] } VR512:{ *:[v16i32] }:$src1, VR512:{ *:[v16i32] }:$src2) 23020 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMAXSDZrr, 23021 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 23022 // GIR_Coverage, 5001, 23023 GIR_Done, 23024 // Label 1874: @52516 23025 GIM_Reject, 23026 // Label 1845: @52517 23027 GIM_Try, /*On fail goto*//*Label 1875*/ 52574, 23028 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v32s8, 23029 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v32s8, 23030 GIM_Try, /*On fail goto*//*Label 1876*/ 52550, // Rule ID 2909 // 23031 GIM_CheckFeatures, GIFBS_HasAVX2_NoVLX_Or_NoBWI, 23032 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID, 23033 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256RegClassID, 23034 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256RegClassID, 23035 // (smax:{ *:[v32i8] } VR256:{ *:[v32i8] }:$src1, VR256:{ *:[v32i8] }:$src2) => (VPMAXSBYrr:{ *:[v32i8] } VR256:{ *:[v32i8] }:$src1, VR256:{ *:[v32i8] }:$src2) 23036 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMAXSBYrr, 23037 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 23038 // GIR_Coverage, 2909, 23039 GIR_Done, 23040 // Label 1876: @52550 23041 GIM_Try, /*On fail goto*//*Label 1877*/ 52573, // Rule ID 4971 // 23042 GIM_CheckFeatures, GIFBS_HasBWI_HasVLX, 23043 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID, 23044 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID, 23045 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256XRegClassID, 23046 // (smax:{ *:[v32i8] } VR256X:{ *:[v32i8] }:$src1, VR256X:{ *:[v32i8] }:$src2) => (VPMAXSBZ256rr:{ *:[v32i8] } VR256X:{ *:[v32i8] }:$src1, VR256X:{ *:[v32i8] }:$src2) 23047 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMAXSBZ256rr, 23048 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 23049 // GIR_Coverage, 4971, 23050 GIR_Done, 23051 // Label 1877: @52573 23052 GIM_Reject, 23053 // Label 1875: @52574 23054 GIM_Reject, 23055 // Label 1846: @52575 23056 GIM_Try, /*On fail goto*//*Label 1878*/ 52606, // Rule ID 4983 // 23057 GIM_CheckFeatures, GIFBS_HasBWI, 23058 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v32s16, 23059 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v32s16, 23060 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 23061 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR512RegClassID, 23062 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR512RegClassID, 23063 // (smax:{ *:[v32i16] } VR512:{ *:[v32i16] }:$src1, VR512:{ *:[v32i16] }:$src2) => (VPMAXSWZrr:{ *:[v32i16] } VR512:{ *:[v32i16] }:$src1, VR512:{ *:[v32i16] }:$src2) 23064 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMAXSWZrr, 23065 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 23066 // GIR_Coverage, 4983, 23067 GIR_Done, 23068 // Label 1878: @52606 23069 GIM_Reject, 23070 // Label 1847: @52607 23071 GIM_Try, /*On fail goto*//*Label 1879*/ 52638, // Rule ID 4965 // 23072 GIM_CheckFeatures, GIFBS_HasBWI, 23073 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v64s8, 23074 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v64s8, 23075 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 23076 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR512RegClassID, 23077 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR512RegClassID, 23078 // (smax:{ *:[v64i8] } VR512:{ *:[v64i8] }:$src1, VR512:{ *:[v64i8] }:$src2) => (VPMAXSBZrr:{ *:[v64i8] } VR512:{ *:[v64i8] }:$src1, VR512:{ *:[v64i8] }:$src2) 23079 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMAXSBZrr, 23080 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 23081 // GIR_Coverage, 4965, 23082 GIR_Done, 23083 // Label 1879: @52638 23084 GIM_Reject, 23085 // Label 1848: @52639 23086 GIM_Reject, 23087 // Label 46: @52640 23088 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/8, 25, /*)*//*default:*//*Label 1892*/ 53576, 23089 /*GILLT_v2s64*//*Label 1880*/ 52663, 0, 23090 /*GILLT_v4s32*//*Label 1881*/ 52847, 23091 /*GILLT_v4s64*//*Label 1882*/ 52928, 0, 23092 /*GILLT_v8s16*//*Label 1883*/ 53112, 23093 /*GILLT_v8s32*//*Label 1884*/ 53193, 23094 /*GILLT_v8s64*//*Label 1885*/ 53251, 0, 23095 /*GILLT_v16s8*//*Label 1886*/ 53283, 23096 /*GILLT_v16s16*//*Label 1887*/ 53364, 23097 /*GILLT_v16s32*//*Label 1888*/ 53422, 0, 23098 /*GILLT_v32s8*//*Label 1889*/ 53454, 23099 /*GILLT_v32s16*//*Label 1890*/ 53512, 0, 23100 /*GILLT_v64s8*//*Label 1891*/ 53544, 23101 // Label 1880: @52663 23102 GIM_Try, /*On fail goto*//*Label 1893*/ 52846, 23103 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, 23104 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 23105 GIM_Try, /*On fail goto*//*Label 1894*/ 52696, // Rule ID 5316 // 23106 GIM_CheckFeatures, GIFBS_HasAVX512_HasVLX, 23107 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID, 23108 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID, 23109 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128XRegClassID, 23110 // (umin:{ *:[v2i64] } VR128X:{ *:[v2i64] }:$src1, VR128X:{ *:[v2i64] }:$src2) => (VPMINUQZ128rr:{ *:[v2i64] } VR128X:{ *:[v2i64] }:$src1, VR128X:{ *:[v2i64] }:$src2) 23111 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMINUQZ128rr, 23112 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 23113 // GIR_Coverage, 5316, 23114 GIR_Done, 23115 // Label 1894: @52696 23116 GIM_Try, /*On fail goto*//*Label 1895*/ 52845, // Rule ID 18491 // 23117 GIM_CheckFeatures, GIFBS_HasAVX512_NoVLX, 23118 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 23119 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID, 23120 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128XRegClassID, 23121 // (umin:{ *:[v2i64] } VR128X:{ *:[v2i64] }:$src1, VR128X:{ *:[v2i64] }:$src2) => (EXTRACT_SUBREG:{ *:[v2i64] } (VPMINUQZrr:{ *:[v64i8] } (INSERT_SUBREG:{ *:[v8i64] } (IMPLICIT_DEF:{ *:[v8i64] }), VR128X:{ *:[v2i64] }:$src1, sub_xmm:{ *:[i32] }), (INSERT_SUBREG:{ *:[v8i64] } (IMPLICIT_DEF:{ *:[v8i64] }), VR128X:{ *:[v2i64] }:$src2, sub_xmm:{ *:[i32] })), sub_xmm:{ *:[i32] }) 23122 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v64s8, 23123 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s64, 23124 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v8s64, 23125 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v8s64, 23126 GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v8s64, 23127 GIR_BuildMI, /*InsnID*/5, /*Opcode*/TargetOpcode::IMPLICIT_DEF, 23128 GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/RegState::Define, 23129 GIR_ConstrainSelectedInstOperands, /*InsnID*/5, 23130 GIR_BuildMI, /*InsnID*/4, /*Opcode*/TargetOpcode::INSERT_SUBREG, 23131 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define, 23132 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/4, /*TempRegFlags*/0, 23133 GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/2, // src2 23134 GIR_AddImm, /*InsnID*/4, /*Imm*/9, 23135 GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, X86::VR512RegClassID, 23136 GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/1, X86::VR512RegClassID, 23137 GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/2, X86::VR128XRegClassID, 23138 GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::IMPLICIT_DEF, 23139 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, 23140 GIR_ConstrainSelectedInstOperands, /*InsnID*/3, 23141 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::INSERT_SUBREG, 23142 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 23143 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/2, /*TempRegFlags*/0, 23144 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src1 23145 GIR_AddImm, /*InsnID*/2, /*Imm*/9, 23146 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, X86::VR512RegClassID, 23147 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, X86::VR512RegClassID, 23148 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, X86::VR128XRegClassID, 23149 GIR_BuildMI, /*InsnID*/1, /*Opcode*/X86::VPMINUQZrr, 23150 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 23151 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, 23152 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/3, /*TempRegFlags*/0, 23153 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 23154 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 23155 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 23156 GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, X86::sub_xmm, 23157 GIR_EraseFromParent, /*InsnID*/0, 23158 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, X86::FR16XRegClassID, 23159 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, X86::VR512RegClassID, 23160 // GIR_Coverage, 18491, 23161 GIR_Done, 23162 // Label 1895: @52845 23163 GIM_Reject, 23164 // Label 1893: @52846 23165 GIM_Reject, 23166 // Label 1881: @52847 23167 GIM_Try, /*On fail goto*//*Label 1896*/ 52927, 23168 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, 23169 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 23170 GIM_Try, /*On fail goto*//*Label 1897*/ 52880, // Rule ID 2879 // 23171 GIM_CheckFeatures, GIFBS_HasAVX_NoVLX, 23172 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 23173 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 23174 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 23175 // (umin:{ *:[v4i32] } VR128:{ *:[v4i32] }:$src1, VR128:{ *:[v4i32] }:$src2) => (VPMINUDrr:{ *:[v4i32] } VR128:{ *:[v4i32] }:$src1, VR128:{ *:[v4i32] }:$src2) 23176 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMINUDrr, 23177 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 23178 // GIR_Coverage, 2879, 23179 GIR_Done, 23180 // Label 1897: @52880 23181 GIM_Try, /*On fail goto*//*Label 1898*/ 52903, // Rule ID 2917 // 23182 GIM_CheckFeatures, GIFBS_UseSSE41, 23183 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 23184 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 23185 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 23186 // (umin:{ *:[v4i32] } VR128:{ *:[v4i32] }:$src1, VR128:{ *:[v4i32] }:$src2) => (PMINUDrr:{ *:[v4i32] } VR128:{ *:[v4i32] }:$src1, VR128:{ *:[v4i32] }:$src2) 23187 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::PMINUDrr, 23188 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 23189 // GIR_Coverage, 2917, 23190 GIR_Done, 23191 // Label 1898: @52903 23192 GIM_Try, /*On fail goto*//*Label 1899*/ 52926, // Rule ID 5289 // 23193 GIM_CheckFeatures, GIFBS_HasAVX512_HasVLX, 23194 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID, 23195 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID, 23196 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128XRegClassID, 23197 // (umin:{ *:[v4i32] } VR128X:{ *:[v4i32] }:$src1, VR128X:{ *:[v4i32] }:$src2) => (VPMINUDZ128rr:{ *:[v4i32] } VR128X:{ *:[v4i32] }:$src1, VR128X:{ *:[v4i32] }:$src2) 23198 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMINUDZ128rr, 23199 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 23200 // GIR_Coverage, 5289, 23201 GIR_Done, 23202 // Label 1899: @52926 23203 GIM_Reject, 23204 // Label 1896: @52927 23205 GIM_Reject, 23206 // Label 1882: @52928 23207 GIM_Try, /*On fail goto*//*Label 1900*/ 53111, 23208 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s64, 23209 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s64, 23210 GIM_Try, /*On fail goto*//*Label 1901*/ 52961, // Rule ID 5307 // 23211 GIM_CheckFeatures, GIFBS_HasAVX512_HasVLX, 23212 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID, 23213 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID, 23214 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256XRegClassID, 23215 // (umin:{ *:[v4i64] } VR256X:{ *:[v4i64] }:$src1, VR256X:{ *:[v4i64] }:$src2) => (VPMINUQZ256rr:{ *:[v4i64] } VR256X:{ *:[v4i64] }:$src1, VR256X:{ *:[v4i64] }:$src2) 23216 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMINUQZ256rr, 23217 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 23218 // GIR_Coverage, 5307, 23219 GIR_Done, 23220 // Label 1901: @52961 23221 GIM_Try, /*On fail goto*//*Label 1902*/ 53110, // Rule ID 18489 // 23222 GIM_CheckFeatures, GIFBS_HasAVX512_NoVLX, 23223 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 23224 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID, 23225 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256XRegClassID, 23226 // (umin:{ *:[v4i64] } VR256X:{ *:[v4i64] }:$src1, VR256X:{ *:[v4i64] }:$src2) => (EXTRACT_SUBREG:{ *:[v4i64] } (VPMINUQZrr:{ *:[v64i8] } (INSERT_SUBREG:{ *:[v8i64] } (IMPLICIT_DEF:{ *:[v8i64] }), VR256X:{ *:[v4i64] }:$src1, sub_ymm:{ *:[i32] }), (INSERT_SUBREG:{ *:[v8i64] } (IMPLICIT_DEF:{ *:[v8i64] }), VR256X:{ *:[v4i64] }:$src2, sub_ymm:{ *:[i32] })), sub_ymm:{ *:[i32] }) 23227 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v64s8, 23228 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s64, 23229 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v8s64, 23230 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v8s64, 23231 GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v8s64, 23232 GIR_BuildMI, /*InsnID*/5, /*Opcode*/TargetOpcode::IMPLICIT_DEF, 23233 GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/RegState::Define, 23234 GIR_ConstrainSelectedInstOperands, /*InsnID*/5, 23235 GIR_BuildMI, /*InsnID*/4, /*Opcode*/TargetOpcode::INSERT_SUBREG, 23236 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define, 23237 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/4, /*TempRegFlags*/0, 23238 GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/2, // src2 23239 GIR_AddImm, /*InsnID*/4, /*Imm*/10, 23240 GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, X86::VR512RegClassID, 23241 GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/1, X86::VR512RegClassID, 23242 GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/2, X86::VR256XRegClassID, 23243 GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::IMPLICIT_DEF, 23244 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, 23245 GIR_ConstrainSelectedInstOperands, /*InsnID*/3, 23246 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::INSERT_SUBREG, 23247 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 23248 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/2, /*TempRegFlags*/0, 23249 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src1 23250 GIR_AddImm, /*InsnID*/2, /*Imm*/10, 23251 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, X86::VR512RegClassID, 23252 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, X86::VR512RegClassID, 23253 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, X86::VR256XRegClassID, 23254 GIR_BuildMI, /*InsnID*/1, /*Opcode*/X86::VPMINUQZrr, 23255 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 23256 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, 23257 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/3, /*TempRegFlags*/0, 23258 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 23259 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 23260 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 23261 GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, X86::sub_ymm, 23262 GIR_EraseFromParent, /*InsnID*/0, 23263 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, X86::VR256XRegClassID, 23264 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, X86::VR512RegClassID, 23265 // GIR_Coverage, 18489, 23266 GIR_Done, 23267 // Label 1902: @53110 23268 GIM_Reject, 23269 // Label 1900: @53111 23270 GIM_Reject, 23271 // Label 1883: @53112 23272 GIM_Try, /*On fail goto*//*Label 1903*/ 53192, 23273 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, 23274 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 23275 GIM_Try, /*On fail goto*//*Label 1904*/ 53145, // Rule ID 2889 // 23276 GIM_CheckFeatures, GIFBS_HasAVX_NoVLX_Or_NoBWI, 23277 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 23278 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 23279 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 23280 // (umin:{ *:[v8i16] } VR128:{ *:[v8i16] }:$src1, VR128:{ *:[v8i16] }:$src2) => (VPMINUWrr:{ *:[v8i16] } VR128:{ *:[v8i16] }:$src1, VR128:{ *:[v8i16] }:$src2) 23281 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMINUWrr, 23282 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 23283 // GIR_Coverage, 2889, 23284 GIR_Done, 23285 // Label 1904: @53145 23286 GIM_Try, /*On fail goto*//*Label 1905*/ 53168, // Rule ID 2919 // 23287 GIM_CheckFeatures, GIFBS_UseSSE41, 23288 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 23289 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 23290 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 23291 // (umin:{ *:[v8i16] } VR128:{ *:[v8i16] }:$src1, VR128:{ *:[v8i16] }:$src2) => (PMINUWrr:{ *:[v8i16] } VR128:{ *:[v8i16] }:$src1, VR128:{ *:[v8i16] }:$src2) 23292 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::PMINUWrr, 23293 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 23294 // GIR_Coverage, 2919, 23295 GIR_Done, 23296 // Label 1905: @53168 23297 GIM_Try, /*On fail goto*//*Label 1906*/ 53191, // Rule ID 5265 // 23298 GIM_CheckFeatures, GIFBS_HasBWI_HasVLX, 23299 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID, 23300 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID, 23301 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128XRegClassID, 23302 // (umin:{ *:[v8i16] } VR128X:{ *:[v8i16] }:$src1, VR128X:{ *:[v8i16] }:$src2) => (VPMINUWZ128rr:{ *:[v8i16] } VR128X:{ *:[v8i16] }:$src1, VR128X:{ *:[v8i16] }:$src2) 23303 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMINUWZ128rr, 23304 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 23305 // GIR_Coverage, 5265, 23306 GIR_Done, 23307 // Label 1906: @53191 23308 GIM_Reject, 23309 // Label 1903: @53192 23310 GIM_Reject, 23311 // Label 1884: @53193 23312 GIM_Try, /*On fail goto*//*Label 1907*/ 53250, 23313 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s32, 23314 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s32, 23315 GIM_Try, /*On fail goto*//*Label 1908*/ 53226, // Rule ID 2897 // 23316 GIM_CheckFeatures, GIFBS_HasAVX2_NoVLX, 23317 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID, 23318 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256RegClassID, 23319 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256RegClassID, 23320 // (umin:{ *:[v8i32] } VR256:{ *:[v8i32] }:$src1, VR256:{ *:[v8i32] }:$src2) => (VPMINUDYrr:{ *:[v8i32] } VR256:{ *:[v8i32] }:$src1, VR256:{ *:[v8i32] }:$src2) 23321 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMINUDYrr, 23322 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 23323 // GIR_Coverage, 2897, 23324 GIR_Done, 23325 // Label 1908: @53226 23326 GIM_Try, /*On fail goto*//*Label 1909*/ 53249, // Rule ID 5280 // 23327 GIM_CheckFeatures, GIFBS_HasAVX512_HasVLX, 23328 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID, 23329 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID, 23330 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256XRegClassID, 23331 // (umin:{ *:[v8i32] } VR256X:{ *:[v8i32] }:$src1, VR256X:{ *:[v8i32] }:$src2) => (VPMINUDZ256rr:{ *:[v8i32] } VR256X:{ *:[v8i32] }:$src1, VR256X:{ *:[v8i32] }:$src2) 23332 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMINUDZ256rr, 23333 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 23334 // GIR_Coverage, 5280, 23335 GIR_Done, 23336 // Label 1909: @53249 23337 GIM_Reject, 23338 // Label 1907: @53250 23339 GIM_Reject, 23340 // Label 1885: @53251 23341 GIM_Try, /*On fail goto*//*Label 1910*/ 53282, // Rule ID 5298 // 23342 GIM_CheckFeatures, GIFBS_HasAVX512, 23343 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s64, 23344 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s64, 23345 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 23346 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR512RegClassID, 23347 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR512RegClassID, 23348 // (umin:{ *:[v8i64] } VR512:{ *:[v8i64] }:$src1, VR512:{ *:[v8i64] }:$src2) => (VPMINUQZrr:{ *:[v8i64] } VR512:{ *:[v8i64] }:$src1, VR512:{ *:[v8i64] }:$src2) 23349 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMINUQZrr, 23350 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 23351 // GIR_Coverage, 5298, 23352 GIR_Done, 23353 // Label 1910: @53282 23354 GIM_Reject, 23355 // Label 1886: @53283 23356 GIM_Try, /*On fail goto*//*Label 1911*/ 53363, 23357 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, 23358 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, 23359 GIM_Try, /*On fail goto*//*Label 1912*/ 53316, // Rule ID 2328 // 23360 GIM_CheckFeatures, GIFBS_HasAVX_NoVLX_Or_NoBWI, 23361 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 23362 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 23363 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 23364 // (umin:{ *:[v16i8] } VR128:{ *:[v16i8] }:$src1, VR128:{ *:[v16i8] }:$src2) => (VPMINUBrr:{ *:[v16i8] } VR128:{ *:[v16i8] }:$src1, VR128:{ *:[v16i8] }:$src2) 23365 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMINUBrr, 23366 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 23367 // GIR_Coverage, 2328, 23368 GIR_Done, 23369 // Label 1912: @53316 23370 GIM_Try, /*On fail goto*//*Label 1913*/ 53339, // Rule ID 2330 // 23371 GIM_CheckFeatures, GIFBS_UseSSE2, 23372 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 23373 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 23374 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 23375 // (umin:{ *:[v16i8] } VR128:{ *:[v16i8] }:$src1, VR128:{ *:[v16i8] }:$src2) => (PMINUBrr:{ *:[v16i8] } VR128:{ *:[v16i8] }:$src1, VR128:{ *:[v16i8] }:$src2) 23376 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::PMINUBrr, 23377 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 23378 // GIR_Coverage, 2330, 23379 GIR_Done, 23380 // Label 1913: @53339 23381 GIM_Try, /*On fail goto*//*Label 1914*/ 53362, // Rule ID 5247 // 23382 GIM_CheckFeatures, GIFBS_HasBWI_HasVLX, 23383 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID, 23384 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID, 23385 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128XRegClassID, 23386 // (umin:{ *:[v16i8] } VR128X:{ *:[v16i8] }:$src1, VR128X:{ *:[v16i8] }:$src2) => (VPMINUBZ128rr:{ *:[v16i8] } VR128X:{ *:[v16i8] }:$src1, VR128X:{ *:[v16i8] }:$src2) 23387 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMINUBZ128rr, 23388 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 23389 // GIR_Coverage, 5247, 23390 GIR_Done, 23391 // Label 1914: @53362 23392 GIM_Reject, 23393 // Label 1911: @53363 23394 GIM_Reject, 23395 // Label 1887: @53364 23396 GIM_Try, /*On fail goto*//*Label 1915*/ 53421, 23397 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s16, 23398 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s16, 23399 GIM_Try, /*On fail goto*//*Label 1916*/ 53397, // Rule ID 2907 // 23400 GIM_CheckFeatures, GIFBS_HasAVX2_NoVLX_Or_NoBWI, 23401 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID, 23402 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256RegClassID, 23403 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256RegClassID, 23404 // (umin:{ *:[v16i16] } VR256:{ *:[v16i16] }:$src1, VR256:{ *:[v16i16] }:$src2) => (VPMINUWYrr:{ *:[v16i16] } VR256:{ *:[v16i16] }:$src1, VR256:{ *:[v16i16] }:$src2) 23405 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMINUWYrr, 23406 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 23407 // GIR_Coverage, 2907, 23408 GIR_Done, 23409 // Label 1916: @53397 23410 GIM_Try, /*On fail goto*//*Label 1917*/ 53420, // Rule ID 5259 // 23411 GIM_CheckFeatures, GIFBS_HasBWI_HasVLX, 23412 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID, 23413 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID, 23414 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256XRegClassID, 23415 // (umin:{ *:[v16i16] } VR256X:{ *:[v16i16] }:$src1, VR256X:{ *:[v16i16] }:$src2) => (VPMINUWZ256rr:{ *:[v16i16] } VR256X:{ *:[v16i16] }:$src1, VR256X:{ *:[v16i16] }:$src2) 23416 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMINUWZ256rr, 23417 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 23418 // GIR_Coverage, 5259, 23419 GIR_Done, 23420 // Label 1917: @53420 23421 GIM_Reject, 23422 // Label 1915: @53421 23423 GIM_Reject, 23424 // Label 1888: @53422 23425 GIM_Try, /*On fail goto*//*Label 1918*/ 53453, // Rule ID 5271 // 23426 GIM_CheckFeatures, GIFBS_HasAVX512, 23427 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s32, 23428 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s32, 23429 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 23430 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR512RegClassID, 23431 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR512RegClassID, 23432 // (umin:{ *:[v16i32] } VR512:{ *:[v16i32] }:$src1, VR512:{ *:[v16i32] }:$src2) => (VPMINUDZrr:{ *:[v16i32] } VR512:{ *:[v16i32] }:$src1, VR512:{ *:[v16i32] }:$src2) 23433 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMINUDZrr, 23434 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 23435 // GIR_Coverage, 5271, 23436 GIR_Done, 23437 // Label 1918: @53453 23438 GIM_Reject, 23439 // Label 1889: @53454 23440 GIM_Try, /*On fail goto*//*Label 1919*/ 53511, 23441 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v32s8, 23442 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v32s8, 23443 GIM_Try, /*On fail goto*//*Label 1920*/ 53487, // Rule ID 2332 // 23444 GIM_CheckFeatures, GIFBS_HasAVX2_NoVLX_Or_NoBWI, 23445 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID, 23446 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256RegClassID, 23447 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256RegClassID, 23448 // (umin:{ *:[v32i8] } VR256:{ *:[v32i8] }:$src1, VR256:{ *:[v32i8] }:$src2) => (VPMINUBYrr:{ *:[v32i8] } VR256:{ *:[v32i8] }:$src1, VR256:{ *:[v32i8] }:$src2) 23449 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMINUBYrr, 23450 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 23451 // GIR_Coverage, 2332, 23452 GIR_Done, 23453 // Label 1920: @53487 23454 GIM_Try, /*On fail goto*//*Label 1921*/ 53510, // Rule ID 5241 // 23455 GIM_CheckFeatures, GIFBS_HasBWI_HasVLX, 23456 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID, 23457 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID, 23458 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256XRegClassID, 23459 // (umin:{ *:[v32i8] } VR256X:{ *:[v32i8] }:$src1, VR256X:{ *:[v32i8] }:$src2) => (VPMINUBZ256rr:{ *:[v32i8] } VR256X:{ *:[v32i8] }:$src1, VR256X:{ *:[v32i8] }:$src2) 23460 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMINUBZ256rr, 23461 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 23462 // GIR_Coverage, 5241, 23463 GIR_Done, 23464 // Label 1921: @53510 23465 GIM_Reject, 23466 // Label 1919: @53511 23467 GIM_Reject, 23468 // Label 1890: @53512 23469 GIM_Try, /*On fail goto*//*Label 1922*/ 53543, // Rule ID 5253 // 23470 GIM_CheckFeatures, GIFBS_HasBWI, 23471 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v32s16, 23472 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v32s16, 23473 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 23474 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR512RegClassID, 23475 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR512RegClassID, 23476 // (umin:{ *:[v32i16] } VR512:{ *:[v32i16] }:$src1, VR512:{ *:[v32i16] }:$src2) => (VPMINUWZrr:{ *:[v32i16] } VR512:{ *:[v32i16] }:$src1, VR512:{ *:[v32i16] }:$src2) 23477 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMINUWZrr, 23478 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 23479 // GIR_Coverage, 5253, 23480 GIR_Done, 23481 // Label 1922: @53543 23482 GIM_Reject, 23483 // Label 1891: @53544 23484 GIM_Try, /*On fail goto*//*Label 1923*/ 53575, // Rule ID 5235 // 23485 GIM_CheckFeatures, GIFBS_HasBWI, 23486 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v64s8, 23487 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v64s8, 23488 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 23489 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR512RegClassID, 23490 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR512RegClassID, 23491 // (umin:{ *:[v64i8] } VR512:{ *:[v64i8] }:$src1, VR512:{ *:[v64i8] }:$src2) => (VPMINUBZrr:{ *:[v64i8] } VR512:{ *:[v64i8] }:$src1, VR512:{ *:[v64i8] }:$src2) 23492 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMINUBZrr, 23493 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 23494 // GIR_Coverage, 5235, 23495 GIR_Done, 23496 // Label 1923: @53575 23497 GIM_Reject, 23498 // Label 1892: @53576 23499 GIM_Reject, 23500 // Label 47: @53577 23501 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/8, 25, /*)*//*default:*//*Label 1936*/ 54513, 23502 /*GILLT_v2s64*//*Label 1924*/ 53600, 0, 23503 /*GILLT_v4s32*//*Label 1925*/ 53784, 23504 /*GILLT_v4s64*//*Label 1926*/ 53865, 0, 23505 /*GILLT_v8s16*//*Label 1927*/ 54049, 23506 /*GILLT_v8s32*//*Label 1928*/ 54130, 23507 /*GILLT_v8s64*//*Label 1929*/ 54188, 0, 23508 /*GILLT_v16s8*//*Label 1930*/ 54220, 23509 /*GILLT_v16s16*//*Label 1931*/ 54301, 23510 /*GILLT_v16s32*//*Label 1932*/ 54359, 0, 23511 /*GILLT_v32s8*//*Label 1933*/ 54391, 23512 /*GILLT_v32s16*//*Label 1934*/ 54449, 0, 23513 /*GILLT_v64s8*//*Label 1935*/ 54481, 23514 // Label 1924: @53600 23515 GIM_Try, /*On fail goto*//*Label 1937*/ 53783, 23516 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, 23517 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 23518 GIM_Try, /*On fail goto*//*Label 1938*/ 53633, // Rule ID 5136 // 23519 GIM_CheckFeatures, GIFBS_HasAVX512_HasVLX, 23520 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID, 23521 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID, 23522 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128XRegClassID, 23523 // (umax:{ *:[v2i64] } VR128X:{ *:[v2i64] }:$src1, VR128X:{ *:[v2i64] }:$src2) => (VPMAXUQZ128rr:{ *:[v2i64] } VR128X:{ *:[v2i64] }:$src1, VR128X:{ *:[v2i64] }:$src2) 23524 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMAXUQZ128rr, 23525 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 23526 // GIR_Coverage, 5136, 23527 GIR_Done, 23528 // Label 1938: @53633 23529 GIM_Try, /*On fail goto*//*Label 1939*/ 53782, // Rule ID 18487 // 23530 GIM_CheckFeatures, GIFBS_HasAVX512_NoVLX, 23531 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 23532 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID, 23533 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128XRegClassID, 23534 // (umax:{ *:[v2i64] } VR128X:{ *:[v2i64] }:$src1, VR128X:{ *:[v2i64] }:$src2) => (EXTRACT_SUBREG:{ *:[v2i64] } (VPMAXUQZrr:{ *:[v64i8] } (INSERT_SUBREG:{ *:[v8i64] } (IMPLICIT_DEF:{ *:[v8i64] }), VR128X:{ *:[v2i64] }:$src1, sub_xmm:{ *:[i32] }), (INSERT_SUBREG:{ *:[v8i64] } (IMPLICIT_DEF:{ *:[v8i64] }), VR128X:{ *:[v2i64] }:$src2, sub_xmm:{ *:[i32] })), sub_xmm:{ *:[i32] }) 23535 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v64s8, 23536 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s64, 23537 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v8s64, 23538 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v8s64, 23539 GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v8s64, 23540 GIR_BuildMI, /*InsnID*/5, /*Opcode*/TargetOpcode::IMPLICIT_DEF, 23541 GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/RegState::Define, 23542 GIR_ConstrainSelectedInstOperands, /*InsnID*/5, 23543 GIR_BuildMI, /*InsnID*/4, /*Opcode*/TargetOpcode::INSERT_SUBREG, 23544 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define, 23545 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/4, /*TempRegFlags*/0, 23546 GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/2, // src2 23547 GIR_AddImm, /*InsnID*/4, /*Imm*/9, 23548 GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, X86::VR512RegClassID, 23549 GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/1, X86::VR512RegClassID, 23550 GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/2, X86::VR128XRegClassID, 23551 GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::IMPLICIT_DEF, 23552 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, 23553 GIR_ConstrainSelectedInstOperands, /*InsnID*/3, 23554 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::INSERT_SUBREG, 23555 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 23556 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/2, /*TempRegFlags*/0, 23557 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src1 23558 GIR_AddImm, /*InsnID*/2, /*Imm*/9, 23559 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, X86::VR512RegClassID, 23560 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, X86::VR512RegClassID, 23561 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, X86::VR128XRegClassID, 23562 GIR_BuildMI, /*InsnID*/1, /*Opcode*/X86::VPMAXUQZrr, 23563 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 23564 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, 23565 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/3, /*TempRegFlags*/0, 23566 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 23567 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 23568 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 23569 GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, X86::sub_xmm, 23570 GIR_EraseFromParent, /*InsnID*/0, 23571 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, X86::FR16XRegClassID, 23572 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, X86::VR512RegClassID, 23573 // GIR_Coverage, 18487, 23574 GIR_Done, 23575 // Label 1939: @53782 23576 GIM_Reject, 23577 // Label 1937: @53783 23578 GIM_Reject, 23579 // Label 1925: @53784 23580 GIM_Try, /*On fail goto*//*Label 1940*/ 53864, 23581 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, 23582 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 23583 GIM_Try, /*On fail goto*//*Label 1941*/ 53817, // Rule ID 2883 // 23584 GIM_CheckFeatures, GIFBS_HasAVX_NoVLX, 23585 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 23586 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 23587 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 23588 // (umax:{ *:[v4i32] } VR128:{ *:[v4i32] }:$src1, VR128:{ *:[v4i32] }:$src2) => (VPMAXUDrr:{ *:[v4i32] } VR128:{ *:[v4i32] }:$src1, VR128:{ *:[v4i32] }:$src2) 23589 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMAXUDrr, 23590 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 23591 // GIR_Coverage, 2883, 23592 GIR_Done, 23593 // Label 1941: @53817 23594 GIM_Try, /*On fail goto*//*Label 1942*/ 53840, // Rule ID 2925 // 23595 GIM_CheckFeatures, GIFBS_UseSSE41, 23596 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 23597 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 23598 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 23599 // (umax:{ *:[v4i32] } VR128:{ *:[v4i32] }:$src1, VR128:{ *:[v4i32] }:$src2) => (PMAXUDrr:{ *:[v4i32] } VR128:{ *:[v4i32] }:$src1, VR128:{ *:[v4i32] }:$src2) 23600 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::PMAXUDrr, 23601 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 23602 // GIR_Coverage, 2925, 23603 GIR_Done, 23604 // Label 1942: @53840 23605 GIM_Try, /*On fail goto*//*Label 1943*/ 53863, // Rule ID 5109 // 23606 GIM_CheckFeatures, GIFBS_HasAVX512_HasVLX, 23607 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID, 23608 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID, 23609 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128XRegClassID, 23610 // (umax:{ *:[v4i32] } VR128X:{ *:[v4i32] }:$src1, VR128X:{ *:[v4i32] }:$src2) => (VPMAXUDZ128rr:{ *:[v4i32] } VR128X:{ *:[v4i32] }:$src1, VR128X:{ *:[v4i32] }:$src2) 23611 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMAXUDZ128rr, 23612 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 23613 // GIR_Coverage, 5109, 23614 GIR_Done, 23615 // Label 1943: @53863 23616 GIM_Reject, 23617 // Label 1940: @53864 23618 GIM_Reject, 23619 // Label 1926: @53865 23620 GIM_Try, /*On fail goto*//*Label 1944*/ 54048, 23621 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s64, 23622 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s64, 23623 GIM_Try, /*On fail goto*//*Label 1945*/ 53898, // Rule ID 5127 // 23624 GIM_CheckFeatures, GIFBS_HasAVX512_HasVLX, 23625 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID, 23626 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID, 23627 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256XRegClassID, 23628 // (umax:{ *:[v4i64] } VR256X:{ *:[v4i64] }:$src1, VR256X:{ *:[v4i64] }:$src2) => (VPMAXUQZ256rr:{ *:[v4i64] } VR256X:{ *:[v4i64] }:$src1, VR256X:{ *:[v4i64] }:$src2) 23629 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMAXUQZ256rr, 23630 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 23631 // GIR_Coverage, 5127, 23632 GIR_Done, 23633 // Label 1945: @53898 23634 GIM_Try, /*On fail goto*//*Label 1946*/ 54047, // Rule ID 18485 // 23635 GIM_CheckFeatures, GIFBS_HasAVX512_NoVLX, 23636 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 23637 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID, 23638 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256XRegClassID, 23639 // (umax:{ *:[v4i64] } VR256X:{ *:[v4i64] }:$src1, VR256X:{ *:[v4i64] }:$src2) => (EXTRACT_SUBREG:{ *:[v4i64] } (VPMAXUQZrr:{ *:[v64i8] } (INSERT_SUBREG:{ *:[v8i64] } (IMPLICIT_DEF:{ *:[v8i64] }), VR256X:{ *:[v4i64] }:$src1, sub_ymm:{ *:[i32] }), (INSERT_SUBREG:{ *:[v8i64] } (IMPLICIT_DEF:{ *:[v8i64] }), VR256X:{ *:[v4i64] }:$src2, sub_ymm:{ *:[i32] })), sub_ymm:{ *:[i32] }) 23640 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v64s8, 23641 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s64, 23642 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v8s64, 23643 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v8s64, 23644 GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v8s64, 23645 GIR_BuildMI, /*InsnID*/5, /*Opcode*/TargetOpcode::IMPLICIT_DEF, 23646 GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/RegState::Define, 23647 GIR_ConstrainSelectedInstOperands, /*InsnID*/5, 23648 GIR_BuildMI, /*InsnID*/4, /*Opcode*/TargetOpcode::INSERT_SUBREG, 23649 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define, 23650 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/4, /*TempRegFlags*/0, 23651 GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/2, // src2 23652 GIR_AddImm, /*InsnID*/4, /*Imm*/10, 23653 GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, X86::VR512RegClassID, 23654 GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/1, X86::VR512RegClassID, 23655 GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/2, X86::VR256XRegClassID, 23656 GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::IMPLICIT_DEF, 23657 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, 23658 GIR_ConstrainSelectedInstOperands, /*InsnID*/3, 23659 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::INSERT_SUBREG, 23660 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 23661 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/2, /*TempRegFlags*/0, 23662 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src1 23663 GIR_AddImm, /*InsnID*/2, /*Imm*/10, 23664 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, X86::VR512RegClassID, 23665 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, X86::VR512RegClassID, 23666 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, X86::VR256XRegClassID, 23667 GIR_BuildMI, /*InsnID*/1, /*Opcode*/X86::VPMAXUQZrr, 23668 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 23669 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, 23670 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/3, /*TempRegFlags*/0, 23671 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 23672 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 23673 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 23674 GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, X86::sub_ymm, 23675 GIR_EraseFromParent, /*InsnID*/0, 23676 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, X86::VR256XRegClassID, 23677 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, X86::VR512RegClassID, 23678 // GIR_Coverage, 18485, 23679 GIR_Done, 23680 // Label 1946: @54047 23681 GIM_Reject, 23682 // Label 1944: @54048 23683 GIM_Reject, 23684 // Label 1927: @54049 23685 GIM_Try, /*On fail goto*//*Label 1947*/ 54129, 23686 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, 23687 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 23688 GIM_Try, /*On fail goto*//*Label 1948*/ 54082, // Rule ID 2893 // 23689 GIM_CheckFeatures, GIFBS_HasAVX_NoVLX_Or_NoBWI, 23690 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 23691 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 23692 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 23693 // (umax:{ *:[v8i16] } VR128:{ *:[v8i16] }:$src1, VR128:{ *:[v8i16] }:$src2) => (VPMAXUWrr:{ *:[v8i16] } VR128:{ *:[v8i16] }:$src1, VR128:{ *:[v8i16] }:$src2) 23694 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMAXUWrr, 23695 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 23696 // GIR_Coverage, 2893, 23697 GIR_Done, 23698 // Label 1948: @54082 23699 GIM_Try, /*On fail goto*//*Label 1949*/ 54105, // Rule ID 2927 // 23700 GIM_CheckFeatures, GIFBS_UseSSE41, 23701 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 23702 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 23703 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 23704 // (umax:{ *:[v8i16] } VR128:{ *:[v8i16] }:$src1, VR128:{ *:[v8i16] }:$src2) => (PMAXUWrr:{ *:[v8i16] } VR128:{ *:[v8i16] }:$src1, VR128:{ *:[v8i16] }:$src2) 23705 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::PMAXUWrr, 23706 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 23707 // GIR_Coverage, 2927, 23708 GIR_Done, 23709 // Label 1949: @54105 23710 GIM_Try, /*On fail goto*//*Label 1950*/ 54128, // Rule ID 5085 // 23711 GIM_CheckFeatures, GIFBS_HasBWI_HasVLX, 23712 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID, 23713 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID, 23714 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128XRegClassID, 23715 // (umax:{ *:[v8i16] } VR128X:{ *:[v8i16] }:$src1, VR128X:{ *:[v8i16] }:$src2) => (VPMAXUWZ128rr:{ *:[v8i16] } VR128X:{ *:[v8i16] }:$src1, VR128X:{ *:[v8i16] }:$src2) 23716 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMAXUWZ128rr, 23717 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 23718 // GIR_Coverage, 5085, 23719 GIR_Done, 23720 // Label 1950: @54128 23721 GIM_Reject, 23722 // Label 1947: @54129 23723 GIM_Reject, 23724 // Label 1928: @54130 23725 GIM_Try, /*On fail goto*//*Label 1951*/ 54187, 23726 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s32, 23727 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s32, 23728 GIM_Try, /*On fail goto*//*Label 1952*/ 54163, // Rule ID 2901 // 23729 GIM_CheckFeatures, GIFBS_HasAVX2_NoVLX, 23730 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID, 23731 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256RegClassID, 23732 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256RegClassID, 23733 // (umax:{ *:[v8i32] } VR256:{ *:[v8i32] }:$src1, VR256:{ *:[v8i32] }:$src2) => (VPMAXUDYrr:{ *:[v8i32] } VR256:{ *:[v8i32] }:$src1, VR256:{ *:[v8i32] }:$src2) 23734 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMAXUDYrr, 23735 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 23736 // GIR_Coverage, 2901, 23737 GIR_Done, 23738 // Label 1952: @54163 23739 GIM_Try, /*On fail goto*//*Label 1953*/ 54186, // Rule ID 5100 // 23740 GIM_CheckFeatures, GIFBS_HasAVX512_HasVLX, 23741 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID, 23742 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID, 23743 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256XRegClassID, 23744 // (umax:{ *:[v8i32] } VR256X:{ *:[v8i32] }:$src1, VR256X:{ *:[v8i32] }:$src2) => (VPMAXUDZ256rr:{ *:[v8i32] } VR256X:{ *:[v8i32] }:$src1, VR256X:{ *:[v8i32] }:$src2) 23745 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMAXUDZ256rr, 23746 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 23747 // GIR_Coverage, 5100, 23748 GIR_Done, 23749 // Label 1953: @54186 23750 GIM_Reject, 23751 // Label 1951: @54187 23752 GIM_Reject, 23753 // Label 1929: @54188 23754 GIM_Try, /*On fail goto*//*Label 1954*/ 54219, // Rule ID 5118 // 23755 GIM_CheckFeatures, GIFBS_HasAVX512, 23756 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s64, 23757 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s64, 23758 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 23759 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR512RegClassID, 23760 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR512RegClassID, 23761 // (umax:{ *:[v8i64] } VR512:{ *:[v8i64] }:$src1, VR512:{ *:[v8i64] }:$src2) => (VPMAXUQZrr:{ *:[v8i64] } VR512:{ *:[v8i64] }:$src1, VR512:{ *:[v8i64] }:$src2) 23762 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMAXUQZrr, 23763 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 23764 // GIR_Coverage, 5118, 23765 GIR_Done, 23766 // Label 1954: @54219 23767 GIM_Reject, 23768 // Label 1930: @54220 23769 GIM_Try, /*On fail goto*//*Label 1955*/ 54300, 23770 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, 23771 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, 23772 GIM_Try, /*On fail goto*//*Label 1956*/ 54253, // Rule ID 2340 // 23773 GIM_CheckFeatures, GIFBS_HasAVX_NoVLX_Or_NoBWI, 23774 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 23775 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 23776 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 23777 // (umax:{ *:[v16i8] } VR128:{ *:[v16i8] }:$src1, VR128:{ *:[v16i8] }:$src2) => (VPMAXUBrr:{ *:[v16i8] } VR128:{ *:[v16i8] }:$src1, VR128:{ *:[v16i8] }:$src2) 23778 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMAXUBrr, 23779 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 23780 // GIR_Coverage, 2340, 23781 GIR_Done, 23782 // Label 1956: @54253 23783 GIM_Try, /*On fail goto*//*Label 1957*/ 54276, // Rule ID 2342 // 23784 GIM_CheckFeatures, GIFBS_UseSSE2, 23785 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 23786 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 23787 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 23788 // (umax:{ *:[v16i8] } VR128:{ *:[v16i8] }:$src1, VR128:{ *:[v16i8] }:$src2) => (PMAXUBrr:{ *:[v16i8] } VR128:{ *:[v16i8] }:$src1, VR128:{ *:[v16i8] }:$src2) 23789 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::PMAXUBrr, 23790 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 23791 // GIR_Coverage, 2342, 23792 GIR_Done, 23793 // Label 1957: @54276 23794 GIM_Try, /*On fail goto*//*Label 1958*/ 54299, // Rule ID 5067 // 23795 GIM_CheckFeatures, GIFBS_HasBWI_HasVLX, 23796 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID, 23797 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID, 23798 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128XRegClassID, 23799 // (umax:{ *:[v16i8] } VR128X:{ *:[v16i8] }:$src1, VR128X:{ *:[v16i8] }:$src2) => (VPMAXUBZ128rr:{ *:[v16i8] } VR128X:{ *:[v16i8] }:$src1, VR128X:{ *:[v16i8] }:$src2) 23800 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMAXUBZ128rr, 23801 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 23802 // GIR_Coverage, 5067, 23803 GIR_Done, 23804 // Label 1958: @54299 23805 GIM_Reject, 23806 // Label 1955: @54300 23807 GIM_Reject, 23808 // Label 1931: @54301 23809 GIM_Try, /*On fail goto*//*Label 1959*/ 54358, 23810 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s16, 23811 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s16, 23812 GIM_Try, /*On fail goto*//*Label 1960*/ 54334, // Rule ID 2911 // 23813 GIM_CheckFeatures, GIFBS_HasAVX2_NoVLX_Or_NoBWI, 23814 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID, 23815 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256RegClassID, 23816 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256RegClassID, 23817 // (umax:{ *:[v16i16] } VR256:{ *:[v16i16] }:$src1, VR256:{ *:[v16i16] }:$src2) => (VPMAXUWYrr:{ *:[v16i16] } VR256:{ *:[v16i16] }:$src1, VR256:{ *:[v16i16] }:$src2) 23818 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMAXUWYrr, 23819 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 23820 // GIR_Coverage, 2911, 23821 GIR_Done, 23822 // Label 1960: @54334 23823 GIM_Try, /*On fail goto*//*Label 1961*/ 54357, // Rule ID 5079 // 23824 GIM_CheckFeatures, GIFBS_HasBWI_HasVLX, 23825 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID, 23826 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID, 23827 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256XRegClassID, 23828 // (umax:{ *:[v16i16] } VR256X:{ *:[v16i16] }:$src1, VR256X:{ *:[v16i16] }:$src2) => (VPMAXUWZ256rr:{ *:[v16i16] } VR256X:{ *:[v16i16] }:$src1, VR256X:{ *:[v16i16] }:$src2) 23829 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMAXUWZ256rr, 23830 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 23831 // GIR_Coverage, 5079, 23832 GIR_Done, 23833 // Label 1961: @54357 23834 GIM_Reject, 23835 // Label 1959: @54358 23836 GIM_Reject, 23837 // Label 1932: @54359 23838 GIM_Try, /*On fail goto*//*Label 1962*/ 54390, // Rule ID 5091 // 23839 GIM_CheckFeatures, GIFBS_HasAVX512, 23840 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s32, 23841 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s32, 23842 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 23843 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR512RegClassID, 23844 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR512RegClassID, 23845 // (umax:{ *:[v16i32] } VR512:{ *:[v16i32] }:$src1, VR512:{ *:[v16i32] }:$src2) => (VPMAXUDZrr:{ *:[v16i32] } VR512:{ *:[v16i32] }:$src1, VR512:{ *:[v16i32] }:$src2) 23846 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMAXUDZrr, 23847 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 23848 // GIR_Coverage, 5091, 23849 GIR_Done, 23850 // Label 1962: @54390 23851 GIM_Reject, 23852 // Label 1933: @54391 23853 GIM_Try, /*On fail goto*//*Label 1963*/ 54448, 23854 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v32s8, 23855 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v32s8, 23856 GIM_Try, /*On fail goto*//*Label 1964*/ 54424, // Rule ID 2344 // 23857 GIM_CheckFeatures, GIFBS_HasAVX2_NoVLX_Or_NoBWI, 23858 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID, 23859 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256RegClassID, 23860 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256RegClassID, 23861 // (umax:{ *:[v32i8] } VR256:{ *:[v32i8] }:$src1, VR256:{ *:[v32i8] }:$src2) => (VPMAXUBYrr:{ *:[v32i8] } VR256:{ *:[v32i8] }:$src1, VR256:{ *:[v32i8] }:$src2) 23862 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMAXUBYrr, 23863 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 23864 // GIR_Coverage, 2344, 23865 GIR_Done, 23866 // Label 1964: @54424 23867 GIM_Try, /*On fail goto*//*Label 1965*/ 54447, // Rule ID 5061 // 23868 GIM_CheckFeatures, GIFBS_HasBWI_HasVLX, 23869 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID, 23870 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID, 23871 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256XRegClassID, 23872 // (umax:{ *:[v32i8] } VR256X:{ *:[v32i8] }:$src1, VR256X:{ *:[v32i8] }:$src2) => (VPMAXUBZ256rr:{ *:[v32i8] } VR256X:{ *:[v32i8] }:$src1, VR256X:{ *:[v32i8] }:$src2) 23873 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMAXUBZ256rr, 23874 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 23875 // GIR_Coverage, 5061, 23876 GIR_Done, 23877 // Label 1965: @54447 23878 GIM_Reject, 23879 // Label 1963: @54448 23880 GIM_Reject, 23881 // Label 1934: @54449 23882 GIM_Try, /*On fail goto*//*Label 1966*/ 54480, // Rule ID 5073 // 23883 GIM_CheckFeatures, GIFBS_HasBWI, 23884 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v32s16, 23885 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v32s16, 23886 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 23887 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR512RegClassID, 23888 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR512RegClassID, 23889 // (umax:{ *:[v32i16] } VR512:{ *:[v32i16] }:$src1, VR512:{ *:[v32i16] }:$src2) => (VPMAXUWZrr:{ *:[v32i16] } VR512:{ *:[v32i16] }:$src1, VR512:{ *:[v32i16] }:$src2) 23890 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMAXUWZrr, 23891 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 23892 // GIR_Coverage, 5073, 23893 GIR_Done, 23894 // Label 1966: @54480 23895 GIM_Reject, 23896 // Label 1935: @54481 23897 GIM_Try, /*On fail goto*//*Label 1967*/ 54512, // Rule ID 5055 // 23898 GIM_CheckFeatures, GIFBS_HasBWI, 23899 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v64s8, 23900 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v64s8, 23901 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 23902 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR512RegClassID, 23903 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR512RegClassID, 23904 // (umax:{ *:[v64i8] } VR512:{ *:[v64i8] }:$src1, VR512:{ *:[v64i8] }:$src2) => (VPMAXUBZrr:{ *:[v64i8] } VR512:{ *:[v64i8] }:$src1, VR512:{ *:[v64i8] }:$src2) 23905 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMAXUBZrr, 23906 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 23907 // GIR_Coverage, 5055, 23908 GIR_Done, 23909 // Label 1967: @54512 23910 GIM_Reject, 23911 // Label 1936: @54513 23912 GIM_Reject, 23913 // Label 48: @54514 23914 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/8, 25, /*)*//*default:*//*Label 1980*/ 55212, 23915 /*GILLT_v2s64*//*Label 1968*/ 54537, 0, 23916 /*GILLT_v4s32*//*Label 1969*/ 54660, 23917 /*GILLT_v4s64*//*Label 1970*/ 54725, 0, 23918 /*GILLT_v8s16*//*Label 1971*/ 54848, 23919 /*GILLT_v8s32*//*Label 1972*/ 54913, 23920 /*GILLT_v8s64*//*Label 1973*/ 54959, 0, 23921 /*GILLT_v16s8*//*Label 1974*/ 54983, 23922 /*GILLT_v16s16*//*Label 1975*/ 55048, 23923 /*GILLT_v16s32*//*Label 1976*/ 55094, 0, 23924 /*GILLT_v32s8*//*Label 1977*/ 55118, 23925 /*GILLT_v32s16*//*Label 1978*/ 55164, 0, 23926 /*GILLT_v64s8*//*Label 1979*/ 55188, 23927 // Label 1968: @54537 23928 GIM_Try, /*On fail goto*//*Label 1981*/ 54659, 23929 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, 23930 GIM_Try, /*On fail goto*//*Label 1982*/ 54562, // Rule ID 12969 // 23931 GIM_CheckFeatures, GIFBS_HasAVX512_HasVLX, 23932 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID, 23933 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID, 23934 // (abs:{ *:[v2i64] } VR128X:{ *:[v2i64] }:$src1) => (VPABSQZ128rr:{ *:[v2i64] } VR128X:{ *:[v2i64] }:$src1) 23935 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPABSQZ128rr, 23936 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 23937 // GIR_Coverage, 12969, 23938 GIR_Done, 23939 // Label 1982: @54562 23940 GIM_Try, /*On fail goto*//*Label 1983*/ 54658, // Rule ID 20243 // 23941 GIM_CheckFeatures, GIFBS_HasAVX512_NoVLX, 23942 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 23943 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID, 23944 // (abs:{ *:[v2i64] } VR128X:{ *:[v2i64] }:$src) => (EXTRACT_SUBREG:{ *:[v2i64] } (VPABSQZrr:{ *:[v64i8] } (INSERT_SUBREG:{ *:[v8i64] } (IMPLICIT_DEF:{ *:[v8i64] }), VR128X:{ *:[v2i64] }:$src, sub_xmm:{ *:[i32] })), sub_xmm:{ *:[i32] }) 23945 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v64s8, 23946 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s64, 23947 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v8s64, 23948 GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::IMPLICIT_DEF, 23949 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, 23950 GIR_ConstrainSelectedInstOperands, /*InsnID*/3, 23951 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::INSERT_SUBREG, 23952 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 23953 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/2, /*TempRegFlags*/0, 23954 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src 23955 GIR_AddImm, /*InsnID*/2, /*Imm*/9, 23956 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, X86::VR512RegClassID, 23957 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, X86::VR512RegClassID, 23958 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, X86::VR128XRegClassID, 23959 GIR_BuildMI, /*InsnID*/1, /*Opcode*/X86::VPABSQZrr, 23960 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 23961 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, 23962 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 23963 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 23964 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 23965 GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, X86::sub_xmm, 23966 GIR_EraseFromParent, /*InsnID*/0, 23967 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, X86::FR16XRegClassID, 23968 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, X86::VR512RegClassID, 23969 // GIR_Coverage, 20243, 23970 GIR_Done, 23971 // Label 1983: @54658 23972 GIM_Reject, 23973 // Label 1981: @54659 23974 GIM_Reject, 23975 // Label 1969: @54660 23976 GIM_Try, /*On fail goto*//*Label 1984*/ 54724, 23977 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, 23978 GIM_Try, /*On fail goto*//*Label 1985*/ 54685, // Rule ID 2686 // 23979 GIM_CheckFeatures, GIFBS_HasAVX_NoVLX, 23980 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 23981 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 23982 // (abs:{ *:[v4i32] } VR128:{ *:[v4i32] }:$src) => (VPABSDrr:{ *:[v4i32] } VR128:{ *:[v4i32] }:$src) 23983 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPABSDrr, 23984 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 23985 // GIR_Coverage, 2686, 23986 GIR_Done, 23987 // Label 1985: @54685 23988 GIM_Try, /*On fail goto*//*Label 1986*/ 54704, // Rule ID 2698 // 23989 GIM_CheckFeatures, GIFBS_UseSSSE3, 23990 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 23991 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 23992 // (abs:{ *:[v4i32] } VR128:{ *:[v4i32] }:$src) => (PABSDrr:{ *:[v4i32] } VR128:{ *:[v4i32] }:$src) 23993 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::PABSDrr, 23994 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 23995 // GIR_Coverage, 2698, 23996 GIR_Done, 23997 // Label 1986: @54704 23998 GIM_Try, /*On fail goto*//*Label 1987*/ 54723, // Rule ID 12996 // 23999 GIM_CheckFeatures, GIFBS_HasAVX512_HasVLX, 24000 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID, 24001 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID, 24002 // (abs:{ *:[v4i32] } VR128X:{ *:[v4i32] }:$src1) => (VPABSDZ128rr:{ *:[v4i32] } VR128X:{ *:[v4i32] }:$src1) 24003 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPABSDZ128rr, 24004 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 24005 // GIR_Coverage, 12996, 24006 GIR_Done, 24007 // Label 1987: @54723 24008 GIM_Reject, 24009 // Label 1984: @54724 24010 GIM_Reject, 24011 // Label 1970: @54725 24012 GIM_Try, /*On fail goto*//*Label 1988*/ 54847, 24013 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s64, 24014 GIM_Try, /*On fail goto*//*Label 1989*/ 54750, // Rule ID 12960 // 24015 GIM_CheckFeatures, GIFBS_HasAVX512_HasVLX, 24016 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID, 24017 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID, 24018 // (abs:{ *:[v4i64] } VR256X:{ *:[v4i64] }:$src1) => (VPABSQZ256rr:{ *:[v4i64] } VR256X:{ *:[v4i64] }:$src1) 24019 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPABSQZ256rr, 24020 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 24021 // GIR_Coverage, 12960, 24022 GIR_Done, 24023 // Label 1989: @54750 24024 GIM_Try, /*On fail goto*//*Label 1990*/ 54846, // Rule ID 20242 // 24025 GIM_CheckFeatures, GIFBS_HasAVX512_NoVLX, 24026 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 24027 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID, 24028 // (abs:{ *:[v4i64] } VR256X:{ *:[v4i64] }:$src) => (EXTRACT_SUBREG:{ *:[v4i64] } (VPABSQZrr:{ *:[v64i8] } (INSERT_SUBREG:{ *:[v8i64] } (IMPLICIT_DEF:{ *:[v8i64] }), VR256X:{ *:[v4i64] }:$src, sub_ymm:{ *:[i32] })), sub_ymm:{ *:[i32] }) 24029 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v64s8, 24030 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s64, 24031 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v8s64, 24032 GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::IMPLICIT_DEF, 24033 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, 24034 GIR_ConstrainSelectedInstOperands, /*InsnID*/3, 24035 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::INSERT_SUBREG, 24036 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 24037 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/2, /*TempRegFlags*/0, 24038 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src 24039 GIR_AddImm, /*InsnID*/2, /*Imm*/10, 24040 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, X86::VR512RegClassID, 24041 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, X86::VR512RegClassID, 24042 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, X86::VR256XRegClassID, 24043 GIR_BuildMI, /*InsnID*/1, /*Opcode*/X86::VPABSQZrr, 24044 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 24045 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, 24046 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 24047 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 24048 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 24049 GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, X86::sub_ymm, 24050 GIR_EraseFromParent, /*InsnID*/0, 24051 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, X86::VR256XRegClassID, 24052 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, X86::VR512RegClassID, 24053 // GIR_Coverage, 20242, 24054 GIR_Done, 24055 // Label 1990: @54846 24056 GIM_Reject, 24057 // Label 1988: @54847 24058 GIM_Reject, 24059 // Label 1971: @54848 24060 GIM_Try, /*On fail goto*//*Label 1991*/ 54912, 24061 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, 24062 GIM_Try, /*On fail goto*//*Label 1992*/ 54873, // Rule ID 2684 // 24063 GIM_CheckFeatures, GIFBS_HasAVX_NoVLX_Or_NoBWI, 24064 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 24065 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 24066 // (abs:{ *:[v8i16] } VR128:{ *:[v8i16] }:$src) => (VPABSWrr:{ *:[v8i16] } VR128:{ *:[v8i16] }:$src) 24067 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPABSWrr, 24068 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 24069 // GIR_Coverage, 2684, 24070 GIR_Done, 24071 // Label 1992: @54873 24072 GIM_Try, /*On fail goto*//*Label 1993*/ 54892, // Rule ID 2696 // 24073 GIM_CheckFeatures, GIFBS_UseSSSE3, 24074 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 24075 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 24076 // (abs:{ *:[v8i16] } VR128:{ *:[v8i16] }:$src) => (PABSWrr:{ *:[v8i16] } VR128:{ *:[v8i16] }:$src) 24077 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::PABSWrr, 24078 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 24079 // GIR_Coverage, 2696, 24080 GIR_Done, 24081 // Label 1993: @54892 24082 GIM_Try, /*On fail goto*//*Label 1994*/ 54911, // Rule ID 13017 // 24083 GIM_CheckFeatures, GIFBS_HasBWI_HasVLX, 24084 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID, 24085 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID, 24086 // (abs:{ *:[v8i16] } VR128X:{ *:[v8i16] }:$src1) => (VPABSWZ128rr:{ *:[v8i16] } VR128X:{ *:[v8i16] }:$src1) 24087 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPABSWZ128rr, 24088 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 24089 // GIR_Coverage, 13017, 24090 GIR_Done, 24091 // Label 1994: @54911 24092 GIM_Reject, 24093 // Label 1991: @54912 24094 GIM_Reject, 24095 // Label 1972: @54913 24096 GIM_Try, /*On fail goto*//*Label 1995*/ 54958, 24097 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s32, 24098 GIM_Try, /*On fail goto*//*Label 1996*/ 54938, // Rule ID 2692 // 24099 GIM_CheckFeatures, GIFBS_HasAVX2_NoVLX, 24100 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID, 24101 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256RegClassID, 24102 // (abs:{ *:[v8i32] } VR256:{ *:[v8i32] }:$src) => (VPABSDYrr:{ *:[v8i32] } VR256:{ *:[v8i32] }:$src) 24103 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPABSDYrr, 24104 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 24105 // GIR_Coverage, 2692, 24106 GIR_Done, 24107 // Label 1996: @54938 24108 GIM_Try, /*On fail goto*//*Label 1997*/ 54957, // Rule ID 12987 // 24109 GIM_CheckFeatures, GIFBS_HasAVX512_HasVLX, 24110 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID, 24111 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID, 24112 // (abs:{ *:[v8i32] } VR256X:{ *:[v8i32] }:$src1) => (VPABSDZ256rr:{ *:[v8i32] } VR256X:{ *:[v8i32] }:$src1) 24113 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPABSDZ256rr, 24114 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 24115 // GIR_Coverage, 12987, 24116 GIR_Done, 24117 // Label 1997: @54957 24118 GIM_Reject, 24119 // Label 1995: @54958 24120 GIM_Reject, 24121 // Label 1973: @54959 24122 GIM_Try, /*On fail goto*//*Label 1998*/ 54982, // Rule ID 12951 // 24123 GIM_CheckFeatures, GIFBS_HasAVX512, 24124 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s64, 24125 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 24126 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR512RegClassID, 24127 // (abs:{ *:[v8i64] } VR512:{ *:[v8i64] }:$src1) => (VPABSQZrr:{ *:[v8i64] } VR512:{ *:[v8i64] }:$src1) 24128 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPABSQZrr, 24129 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 24130 // GIR_Coverage, 12951, 24131 GIR_Done, 24132 // Label 1998: @54982 24133 GIM_Reject, 24134 // Label 1974: @54983 24135 GIM_Try, /*On fail goto*//*Label 1999*/ 55047, 24136 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, 24137 GIM_Try, /*On fail goto*//*Label 2000*/ 55008, // Rule ID 2682 // 24138 GIM_CheckFeatures, GIFBS_HasAVX_NoVLX_Or_NoBWI, 24139 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 24140 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 24141 // (abs:{ *:[v16i8] } VR128:{ *:[v16i8] }:$src) => (VPABSBrr:{ *:[v16i8] } VR128:{ *:[v16i8] }:$src) 24142 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPABSBrr, 24143 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 24144 // GIR_Coverage, 2682, 24145 GIR_Done, 24146 // Label 2000: @55008 24147 GIM_Try, /*On fail goto*//*Label 2001*/ 55027, // Rule ID 2694 // 24148 GIM_CheckFeatures, GIFBS_UseSSSE3, 24149 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 24150 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 24151 // (abs:{ *:[v16i8] } VR128:{ *:[v16i8] }:$src) => (PABSBrr:{ *:[v16i8] } VR128:{ *:[v16i8] }:$src) 24152 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::PABSBrr, 24153 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 24154 // GIR_Coverage, 2694, 24155 GIR_Done, 24156 // Label 2001: @55027 24157 GIM_Try, /*On fail goto*//*Label 2002*/ 55046, // Rule ID 13035 // 24158 GIM_CheckFeatures, GIFBS_HasBWI_HasVLX, 24159 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID, 24160 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID, 24161 // (abs:{ *:[v16i8] } VR128X:{ *:[v16i8] }:$src1) => (VPABSBZ128rr:{ *:[v16i8] } VR128X:{ *:[v16i8] }:$src1) 24162 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPABSBZ128rr, 24163 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 24164 // GIR_Coverage, 13035, 24165 GIR_Done, 24166 // Label 2002: @55046 24167 GIM_Reject, 24168 // Label 1999: @55047 24169 GIM_Reject, 24170 // Label 1975: @55048 24171 GIM_Try, /*On fail goto*//*Label 2003*/ 55093, 24172 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s16, 24173 GIM_Try, /*On fail goto*//*Label 2004*/ 55073, // Rule ID 2690 // 24174 GIM_CheckFeatures, GIFBS_HasAVX2_NoVLX_Or_NoBWI, 24175 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID, 24176 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256RegClassID, 24177 // (abs:{ *:[v16i16] } VR256:{ *:[v16i16] }:$src) => (VPABSWYrr:{ *:[v16i16] } VR256:{ *:[v16i16] }:$src) 24178 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPABSWYrr, 24179 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 24180 // GIR_Coverage, 2690, 24181 GIR_Done, 24182 // Label 2004: @55073 24183 GIM_Try, /*On fail goto*//*Label 2005*/ 55092, // Rule ID 13011 // 24184 GIM_CheckFeatures, GIFBS_HasBWI_HasVLX, 24185 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID, 24186 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID, 24187 // (abs:{ *:[v16i16] } VR256X:{ *:[v16i16] }:$src1) => (VPABSWZ256rr:{ *:[v16i16] } VR256X:{ *:[v16i16] }:$src1) 24188 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPABSWZ256rr, 24189 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 24190 // GIR_Coverage, 13011, 24191 GIR_Done, 24192 // Label 2005: @55092 24193 GIM_Reject, 24194 // Label 2003: @55093 24195 GIM_Reject, 24196 // Label 1976: @55094 24197 GIM_Try, /*On fail goto*//*Label 2006*/ 55117, // Rule ID 12978 // 24198 GIM_CheckFeatures, GIFBS_HasAVX512, 24199 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s32, 24200 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 24201 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR512RegClassID, 24202 // (abs:{ *:[v16i32] } VR512:{ *:[v16i32] }:$src1) => (VPABSDZrr:{ *:[v16i32] } VR512:{ *:[v16i32] }:$src1) 24203 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPABSDZrr, 24204 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 24205 // GIR_Coverage, 12978, 24206 GIR_Done, 24207 // Label 2006: @55117 24208 GIM_Reject, 24209 // Label 1977: @55118 24210 GIM_Try, /*On fail goto*//*Label 2007*/ 55163, 24211 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v32s8, 24212 GIM_Try, /*On fail goto*//*Label 2008*/ 55143, // Rule ID 2688 // 24213 GIM_CheckFeatures, GIFBS_HasAVX2_NoVLX_Or_NoBWI, 24214 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID, 24215 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256RegClassID, 24216 // (abs:{ *:[v32i8] } VR256:{ *:[v32i8] }:$src) => (VPABSBYrr:{ *:[v32i8] } VR256:{ *:[v32i8] }:$src) 24217 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPABSBYrr, 24218 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 24219 // GIR_Coverage, 2688, 24220 GIR_Done, 24221 // Label 2008: @55143 24222 GIM_Try, /*On fail goto*//*Label 2009*/ 55162, // Rule ID 13029 // 24223 GIM_CheckFeatures, GIFBS_HasBWI_HasVLX, 24224 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID, 24225 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID, 24226 // (abs:{ *:[v32i8] } VR256X:{ *:[v32i8] }:$src1) => (VPABSBZ256rr:{ *:[v32i8] } VR256X:{ *:[v32i8] }:$src1) 24227 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPABSBZ256rr, 24228 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 24229 // GIR_Coverage, 13029, 24230 GIR_Done, 24231 // Label 2009: @55162 24232 GIM_Reject, 24233 // Label 2007: @55163 24234 GIM_Reject, 24235 // Label 1978: @55164 24236 GIM_Try, /*On fail goto*//*Label 2010*/ 55187, // Rule ID 13005 // 24237 GIM_CheckFeatures, GIFBS_HasBWI, 24238 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v32s16, 24239 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 24240 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR512RegClassID, 24241 // (abs:{ *:[v32i16] } VR512:{ *:[v32i16] }:$src1) => (VPABSWZrr:{ *:[v32i16] } VR512:{ *:[v32i16] }:$src1) 24242 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPABSWZrr, 24243 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 24244 // GIR_Coverage, 13005, 24245 GIR_Done, 24246 // Label 2010: @55187 24247 GIM_Reject, 24248 // Label 1979: @55188 24249 GIM_Try, /*On fail goto*//*Label 2011*/ 55211, // Rule ID 13023 // 24250 GIM_CheckFeatures, GIFBS_HasBWI, 24251 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v64s8, 24252 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 24253 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR512RegClassID, 24254 // (abs:{ *:[v64i8] } VR512:{ *:[v64i8] }:$src1) => (VPABSBZrr:{ *:[v64i8] } VR512:{ *:[v64i8] }:$src1) 24255 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPABSBZrr, 24256 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 24257 // GIR_Coverage, 13023, 24258 GIR_Done, 24259 // Label 2011: @55211 24260 GIM_Reject, 24261 // Label 1980: @55212 24262 GIM_Reject, 24263 // Label 49: @55213 24264 GIM_Try, /*On fail goto*//*Label 2012*/ 55225, // Rule ID 433 // 24265 // MIs[0] dst 24266 GIM_CheckIsMBB, /*MI*/0, /*Op*/0, 24267 // (br (bb:{ *:[Other] }):$dst) => (JMP_1 (bb:{ *:[Other] }):$dst) 24268 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::JMP_1, 24269 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 24270 // GIR_Coverage, 433, 24271 GIR_Done, 24272 // Label 2012: @55225 24273 GIM_Reject, 24274 // Label 50: @55226 24275 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/2, 5, /*)*//*default:*//*Label 2016*/ 55310, 24276 /*GILLT_s16*//*Label 2013*/ 55235, 24277 /*GILLT_s32*//*Label 2014*/ 55260, 24278 /*GILLT_s64*//*Label 2015*/ 55285, 24279 // Label 2013: @55235 24280 GIM_Try, /*On fail goto*//*Label 2017*/ 55259, // Rule ID 15710 // 24281 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16, 24282 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR16RegClassID, 24283 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR16RegClassID, 24284 // (cttz_zero_undef:{ *:[i16] } GR16:{ *:[i16] }:$src) => (BSF16rr:{ *:[i16] }:{ *:[i32] } GR16:{ *:[i16] }:$src) 24285 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::BSF16rr, 24286 GIR_AddImplicitDef, /*InsnID*/0, X86::EFLAGS, 24287 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 24288 // GIR_Coverage, 15710, 24289 GIR_Done, 24290 // Label 2017: @55259 24291 GIM_Reject, 24292 // Label 2014: @55260 24293 GIM_Try, /*On fail goto*//*Label 2018*/ 55284, // Rule ID 15711 // 24294 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 24295 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID, 24296 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR32RegClassID, 24297 // (cttz_zero_undef:{ *:[i32] } GR32:{ *:[i32] }:$src) => (BSF32rr:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src) 24298 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::BSF32rr, 24299 GIR_AddImplicitDef, /*InsnID*/0, X86::EFLAGS, 24300 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 24301 // GIR_Coverage, 15711, 24302 GIR_Done, 24303 // Label 2018: @55284 24304 GIM_Reject, 24305 // Label 2015: @55285 24306 GIM_Try, /*On fail goto*//*Label 2019*/ 55309, // Rule ID 15712 // 24307 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 24308 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID, 24309 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR64RegClassID, 24310 // (cttz_zero_undef:{ *:[i64] } GR64:{ *:[i64] }:$src) => (BSF64rr:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src) 24311 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::BSF64rr, 24312 GIR_AddImplicitDef, /*InsnID*/0, X86::EFLAGS, 24313 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 24314 // GIR_Coverage, 15712, 24315 GIR_Done, 24316 // Label 2019: @55309 24317 GIM_Reject, 24318 // Label 2016: @55310 24319 GIM_Reject, 24320 // Label 51: @55311 24321 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/8, 20, /*)*//*default:*//*Label 2026*/ 55869, 24322 /*GILLT_v2s64*//*Label 2020*/ 55329, 0, 24323 /*GILLT_v4s32*//*Label 2021*/ 55452, 24324 /*GILLT_v4s64*//*Label 2022*/ 55575, 0, 0, 24325 /*GILLT_v8s32*//*Label 2023*/ 55698, 24326 /*GILLT_v8s64*//*Label 2024*/ 55821, 0, 0, 0, 24327 /*GILLT_v16s32*//*Label 2025*/ 55845, 24328 // Label 2020: @55329 24329 GIM_Try, /*On fail goto*//*Label 2027*/ 55451, 24330 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, 24331 GIM_Try, /*On fail goto*//*Label 2028*/ 55354, // Rule ID 13059 // 24332 GIM_CheckFeatures, GIFBS_HasCDI_HasVLX, 24333 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID, 24334 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID, 24335 // (ctlz:{ *:[v2i64] } VR128X:{ *:[v2i64] }:$src1) => (VPLZCNTQZ128rr:{ *:[v2i64] } VR128X:{ *:[v2i64] }:$src1) 24336 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPLZCNTQZ128rr, 24337 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 24338 // GIR_Coverage, 13059, 24339 GIR_Done, 24340 // Label 2028: @55354 24341 GIM_Try, /*On fail goto*//*Label 2029*/ 55450, // Rule ID 20245 // 24342 GIM_CheckFeatures, GIFBS_HasCDI_NoVLX, 24343 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 24344 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID, 24345 // (ctlz:{ *:[v2i64] } VR128X:{ *:[v2i64] }:$src1) => (EXTRACT_SUBREG:{ *:[v2i64] } (VPLZCNTQZrr:{ *:[v64i8] } (INSERT_SUBREG:{ *:[v8i64] } (IMPLICIT_DEF:{ *:[v8i64] }), VR128X:{ *:[v2i64] }:$src1, sub_xmm:{ *:[i32] })), sub_xmm:{ *:[i32] }) 24346 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v64s8, 24347 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s64, 24348 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v8s64, 24349 GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::IMPLICIT_DEF, 24350 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, 24351 GIR_ConstrainSelectedInstOperands, /*InsnID*/3, 24352 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::INSERT_SUBREG, 24353 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 24354 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/2, /*TempRegFlags*/0, 24355 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src1 24356 GIR_AddImm, /*InsnID*/2, /*Imm*/9, 24357 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, X86::VR512RegClassID, 24358 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, X86::VR512RegClassID, 24359 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, X86::VR128XRegClassID, 24360 GIR_BuildMI, /*InsnID*/1, /*Opcode*/X86::VPLZCNTQZrr, 24361 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 24362 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, 24363 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 24364 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 24365 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 24366 GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, X86::sub_xmm, 24367 GIR_EraseFromParent, /*InsnID*/0, 24368 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, X86::FR16XRegClassID, 24369 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, X86::VR512RegClassID, 24370 // GIR_Coverage, 20245, 24371 GIR_Done, 24372 // Label 2029: @55450 24373 GIM_Reject, 24374 // Label 2027: @55451 24375 GIM_Reject, 24376 // Label 2021: @55452 24377 GIM_Try, /*On fail goto*//*Label 2030*/ 55574, 24378 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, 24379 GIM_Try, /*On fail goto*//*Label 2031*/ 55477, // Rule ID 13086 // 24380 GIM_CheckFeatures, GIFBS_HasCDI_HasVLX, 24381 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID, 24382 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID, 24383 // (ctlz:{ *:[v4i32] } VR128X:{ *:[v4i32] }:$src1) => (VPLZCNTDZ128rr:{ *:[v4i32] } VR128X:{ *:[v4i32] }:$src1) 24384 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPLZCNTDZ128rr, 24385 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 24386 // GIR_Coverage, 13086, 24387 GIR_Done, 24388 // Label 2031: @55477 24389 GIM_Try, /*On fail goto*//*Label 2032*/ 55573, // Rule ID 20247 // 24390 GIM_CheckFeatures, GIFBS_HasCDI_NoVLX, 24391 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 24392 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID, 24393 // (ctlz:{ *:[v4i32] } VR128X:{ *:[v4i32] }:$src1) => (EXTRACT_SUBREG:{ *:[v4i32] } (VPLZCNTDZrr:{ *:[v64i8] } (INSERT_SUBREG:{ *:[v16i32] } (IMPLICIT_DEF:{ *:[v16i32] }), VR128X:{ *:[v4i32] }:$src1, sub_xmm:{ *:[i32] })), sub_xmm:{ *:[i32] }) 24394 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v64s8, 24395 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s32, 24396 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s32, 24397 GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::IMPLICIT_DEF, 24398 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, 24399 GIR_ConstrainSelectedInstOperands, /*InsnID*/3, 24400 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::INSERT_SUBREG, 24401 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 24402 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/2, /*TempRegFlags*/0, 24403 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src1 24404 GIR_AddImm, /*InsnID*/2, /*Imm*/9, 24405 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, X86::VR512RegClassID, 24406 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, X86::VR512RegClassID, 24407 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, X86::VR128XRegClassID, 24408 GIR_BuildMI, /*InsnID*/1, /*Opcode*/X86::VPLZCNTDZrr, 24409 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 24410 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, 24411 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 24412 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 24413 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 24414 GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, X86::sub_xmm, 24415 GIR_EraseFromParent, /*InsnID*/0, 24416 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, X86::FR16XRegClassID, 24417 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, X86::VR512RegClassID, 24418 // GIR_Coverage, 20247, 24419 GIR_Done, 24420 // Label 2032: @55573 24421 GIM_Reject, 24422 // Label 2030: @55574 24423 GIM_Reject, 24424 // Label 2022: @55575 24425 GIM_Try, /*On fail goto*//*Label 2033*/ 55697, 24426 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s64, 24427 GIM_Try, /*On fail goto*//*Label 2034*/ 55600, // Rule ID 13050 // 24428 GIM_CheckFeatures, GIFBS_HasCDI_HasVLX, 24429 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID, 24430 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID, 24431 // (ctlz:{ *:[v4i64] } VR256X:{ *:[v4i64] }:$src1) => (VPLZCNTQZ256rr:{ *:[v4i64] } VR256X:{ *:[v4i64] }:$src1) 24432 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPLZCNTQZ256rr, 24433 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 24434 // GIR_Coverage, 13050, 24435 GIR_Done, 24436 // Label 2034: @55600 24437 GIM_Try, /*On fail goto*//*Label 2035*/ 55696, // Rule ID 20244 // 24438 GIM_CheckFeatures, GIFBS_HasCDI_NoVLX, 24439 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 24440 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID, 24441 // (ctlz:{ *:[v4i64] } VR256X:{ *:[v4i64] }:$src1) => (EXTRACT_SUBREG:{ *:[v4i64] } (VPLZCNTQZrr:{ *:[v64i8] } (INSERT_SUBREG:{ *:[v8i64] } (IMPLICIT_DEF:{ *:[v8i64] }), VR256X:{ *:[v4i64] }:$src1, sub_ymm:{ *:[i32] })), sub_ymm:{ *:[i32] }) 24442 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v64s8, 24443 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s64, 24444 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v8s64, 24445 GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::IMPLICIT_DEF, 24446 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, 24447 GIR_ConstrainSelectedInstOperands, /*InsnID*/3, 24448 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::INSERT_SUBREG, 24449 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 24450 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/2, /*TempRegFlags*/0, 24451 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src1 24452 GIR_AddImm, /*InsnID*/2, /*Imm*/10, 24453 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, X86::VR512RegClassID, 24454 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, X86::VR512RegClassID, 24455 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, X86::VR256XRegClassID, 24456 GIR_BuildMI, /*InsnID*/1, /*Opcode*/X86::VPLZCNTQZrr, 24457 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 24458 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, 24459 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 24460 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 24461 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 24462 GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, X86::sub_ymm, 24463 GIR_EraseFromParent, /*InsnID*/0, 24464 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, X86::VR256XRegClassID, 24465 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, X86::VR512RegClassID, 24466 // GIR_Coverage, 20244, 24467 GIR_Done, 24468 // Label 2035: @55696 24469 GIM_Reject, 24470 // Label 2033: @55697 24471 GIM_Reject, 24472 // Label 2023: @55698 24473 GIM_Try, /*On fail goto*//*Label 2036*/ 55820, 24474 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s32, 24475 GIM_Try, /*On fail goto*//*Label 2037*/ 55723, // Rule ID 13077 // 24476 GIM_CheckFeatures, GIFBS_HasCDI_HasVLX, 24477 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID, 24478 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID, 24479 // (ctlz:{ *:[v8i32] } VR256X:{ *:[v8i32] }:$src1) => (VPLZCNTDZ256rr:{ *:[v8i32] } VR256X:{ *:[v8i32] }:$src1) 24480 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPLZCNTDZ256rr, 24481 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 24482 // GIR_Coverage, 13077, 24483 GIR_Done, 24484 // Label 2037: @55723 24485 GIM_Try, /*On fail goto*//*Label 2038*/ 55819, // Rule ID 20246 // 24486 GIM_CheckFeatures, GIFBS_HasCDI_NoVLX, 24487 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 24488 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID, 24489 // (ctlz:{ *:[v8i32] } VR256X:{ *:[v8i32] }:$src1) => (EXTRACT_SUBREG:{ *:[v8i32] } (VPLZCNTDZrr:{ *:[v64i8] } (INSERT_SUBREG:{ *:[v16i32] } (IMPLICIT_DEF:{ *:[v16i32] }), VR256X:{ *:[v8i32] }:$src1, sub_ymm:{ *:[i32] })), sub_ymm:{ *:[i32] }) 24490 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v64s8, 24491 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s32, 24492 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s32, 24493 GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::IMPLICIT_DEF, 24494 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, 24495 GIR_ConstrainSelectedInstOperands, /*InsnID*/3, 24496 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::INSERT_SUBREG, 24497 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 24498 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/2, /*TempRegFlags*/0, 24499 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src1 24500 GIR_AddImm, /*InsnID*/2, /*Imm*/10, 24501 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, X86::VR512RegClassID, 24502 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, X86::VR512RegClassID, 24503 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, X86::VR256XRegClassID, 24504 GIR_BuildMI, /*InsnID*/1, /*Opcode*/X86::VPLZCNTDZrr, 24505 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 24506 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, 24507 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 24508 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 24509 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 24510 GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, X86::sub_ymm, 24511 GIR_EraseFromParent, /*InsnID*/0, 24512 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, X86::VR256XRegClassID, 24513 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, X86::VR512RegClassID, 24514 // GIR_Coverage, 20246, 24515 GIR_Done, 24516 // Label 2038: @55819 24517 GIM_Reject, 24518 // Label 2036: @55820 24519 GIM_Reject, 24520 // Label 2024: @55821 24521 GIM_Try, /*On fail goto*//*Label 2039*/ 55844, // Rule ID 13041 // 24522 GIM_CheckFeatures, GIFBS_HasCDI, 24523 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s64, 24524 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 24525 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR512RegClassID, 24526 // (ctlz:{ *:[v8i64] } VR512:{ *:[v8i64] }:$src1) => (VPLZCNTQZrr:{ *:[v8i64] } VR512:{ *:[v8i64] }:$src1) 24527 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPLZCNTQZrr, 24528 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 24529 // GIR_Coverage, 13041, 24530 GIR_Done, 24531 // Label 2039: @55844 24532 GIM_Reject, 24533 // Label 2025: @55845 24534 GIM_Try, /*On fail goto*//*Label 2040*/ 55868, // Rule ID 13068 // 24535 GIM_CheckFeatures, GIFBS_HasCDI, 24536 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s32, 24537 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 24538 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR512RegClassID, 24539 // (ctlz:{ *:[v16i32] } VR512:{ *:[v16i32] }:$src1) => (VPLZCNTDZrr:{ *:[v16i32] } VR512:{ *:[v16i32] }:$src1) 24540 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPLZCNTDZrr, 24541 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 24542 // GIR_Coverage, 13068, 24543 GIR_Done, 24544 // Label 2040: @55868 24545 GIM_Reject, 24546 // Label 2026: @55869 24547 GIM_Reject, 24548 // Label 52: @55870 24549 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/8, 25, /*)*//*default:*//*Label 2053*/ 56973, 24550 /*GILLT_v2s64*//*Label 2041*/ 55893, 0, 24551 /*GILLT_v4s32*//*Label 2042*/ 56016, 24552 /*GILLT_v4s64*//*Label 2043*/ 56139, 0, 24553 /*GILLT_v8s16*//*Label 2044*/ 56262, 24554 /*GILLT_v8s32*//*Label 2045*/ 56385, 24555 /*GILLT_v8s64*//*Label 2046*/ 56508, 0, 24556 /*GILLT_v16s8*//*Label 2047*/ 56532, 24557 /*GILLT_v16s16*//*Label 2048*/ 56655, 24558 /*GILLT_v16s32*//*Label 2049*/ 56778, 0, 24559 /*GILLT_v32s8*//*Label 2050*/ 56802, 24560 /*GILLT_v32s16*//*Label 2051*/ 56925, 0, 24561 /*GILLT_v64s8*//*Label 2052*/ 56949, 24562 // Label 2041: @55893 24563 GIM_Try, /*On fail goto*//*Label 2054*/ 56015, 24564 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, 24565 GIM_Try, /*On fail goto*//*Label 2055*/ 55918, // Rule ID 13167 // 24566 GIM_CheckFeatures, GIFBS_HasVLX_HasVPOPCNTDQ, 24567 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID, 24568 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID, 24569 // (ctpop:{ *:[v2i64] } VR128X:{ *:[v2i64] }:$src1) => (VPOPCNTQZ128rr:{ *:[v2i64] } VR128X:{ *:[v2i64] }:$src1) 24570 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPOPCNTQZ128rr, 24571 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 24572 // GIR_Coverage, 13167, 24573 GIR_Done, 24574 // Label 2055: @55918 24575 GIM_Try, /*On fail goto*//*Label 2056*/ 56014, // Rule ID 20249 // 24576 GIM_CheckFeatures, GIFBS_HasVPOPCNTDQ_NoVLX, 24577 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 24578 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID, 24579 // (ctpop:{ *:[v2i64] } VR128X:{ *:[v2i64] }:$src1) => (EXTRACT_SUBREG:{ *:[v2i64] } (VPOPCNTQZrr:{ *:[v64i8] } (INSERT_SUBREG:{ *:[v8i64] } (IMPLICIT_DEF:{ *:[v8i64] }), VR128X:{ *:[v2i64] }:$src1, sub_xmm:{ *:[i32] })), sub_xmm:{ *:[i32] }) 24580 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v64s8, 24581 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s64, 24582 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v8s64, 24583 GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::IMPLICIT_DEF, 24584 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, 24585 GIR_ConstrainSelectedInstOperands, /*InsnID*/3, 24586 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::INSERT_SUBREG, 24587 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 24588 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/2, /*TempRegFlags*/0, 24589 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src1 24590 GIR_AddImm, /*InsnID*/2, /*Imm*/9, 24591 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, X86::VR512RegClassID, 24592 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, X86::VR512RegClassID, 24593 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, X86::VR128XRegClassID, 24594 GIR_BuildMI, /*InsnID*/1, /*Opcode*/X86::VPOPCNTQZrr, 24595 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 24596 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, 24597 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 24598 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 24599 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 24600 GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, X86::sub_xmm, 24601 GIR_EraseFromParent, /*InsnID*/0, 24602 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, X86::FR16XRegClassID, 24603 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, X86::VR512RegClassID, 24604 // GIR_Coverage, 20249, 24605 GIR_Done, 24606 // Label 2056: @56014 24607 GIM_Reject, 24608 // Label 2054: @56015 24609 GIM_Reject, 24610 // Label 2042: @56016 24611 GIM_Try, /*On fail goto*//*Label 2057*/ 56138, 24612 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, 24613 GIM_Try, /*On fail goto*//*Label 2058*/ 56041, // Rule ID 13194 // 24614 GIM_CheckFeatures, GIFBS_HasVLX_HasVPOPCNTDQ, 24615 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID, 24616 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID, 24617 // (ctpop:{ *:[v4i32] } VR128X:{ *:[v4i32] }:$src1) => (VPOPCNTDZ128rr:{ *:[v4i32] } VR128X:{ *:[v4i32] }:$src1) 24618 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPOPCNTDZ128rr, 24619 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 24620 // GIR_Coverage, 13194, 24621 GIR_Done, 24622 // Label 2058: @56041 24623 GIM_Try, /*On fail goto*//*Label 2059*/ 56137, // Rule ID 20251 // 24624 GIM_CheckFeatures, GIFBS_HasVPOPCNTDQ_NoVLX, 24625 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 24626 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID, 24627 // (ctpop:{ *:[v4i32] } VR128X:{ *:[v4i32] }:$src1) => (EXTRACT_SUBREG:{ *:[v4i32] } (VPOPCNTDZrr:{ *:[v64i8] } (INSERT_SUBREG:{ *:[v16i32] } (IMPLICIT_DEF:{ *:[v16i32] }), VR128X:{ *:[v4i32] }:$src1, sub_xmm:{ *:[i32] })), sub_xmm:{ *:[i32] }) 24628 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v64s8, 24629 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s32, 24630 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s32, 24631 GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::IMPLICIT_DEF, 24632 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, 24633 GIR_ConstrainSelectedInstOperands, /*InsnID*/3, 24634 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::INSERT_SUBREG, 24635 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 24636 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/2, /*TempRegFlags*/0, 24637 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src1 24638 GIR_AddImm, /*InsnID*/2, /*Imm*/9, 24639 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, X86::VR512RegClassID, 24640 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, X86::VR512RegClassID, 24641 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, X86::VR128XRegClassID, 24642 GIR_BuildMI, /*InsnID*/1, /*Opcode*/X86::VPOPCNTDZrr, 24643 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 24644 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, 24645 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 24646 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 24647 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 24648 GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, X86::sub_xmm, 24649 GIR_EraseFromParent, /*InsnID*/0, 24650 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, X86::FR16XRegClassID, 24651 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, X86::VR512RegClassID, 24652 // GIR_Coverage, 20251, 24653 GIR_Done, 24654 // Label 2059: @56137 24655 GIM_Reject, 24656 // Label 2057: @56138 24657 GIM_Reject, 24658 // Label 2043: @56139 24659 GIM_Try, /*On fail goto*//*Label 2060*/ 56261, 24660 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s64, 24661 GIM_Try, /*On fail goto*//*Label 2061*/ 56164, // Rule ID 13158 // 24662 GIM_CheckFeatures, GIFBS_HasVLX_HasVPOPCNTDQ, 24663 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID, 24664 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID, 24665 // (ctpop:{ *:[v4i64] } VR256X:{ *:[v4i64] }:$src1) => (VPOPCNTQZ256rr:{ *:[v4i64] } VR256X:{ *:[v4i64] }:$src1) 24666 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPOPCNTQZ256rr, 24667 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 24668 // GIR_Coverage, 13158, 24669 GIR_Done, 24670 // Label 2061: @56164 24671 GIM_Try, /*On fail goto*//*Label 2062*/ 56260, // Rule ID 20248 // 24672 GIM_CheckFeatures, GIFBS_HasVPOPCNTDQ_NoVLX, 24673 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 24674 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID, 24675 // (ctpop:{ *:[v4i64] } VR256X:{ *:[v4i64] }:$src1) => (EXTRACT_SUBREG:{ *:[v4i64] } (VPOPCNTQZrr:{ *:[v64i8] } (INSERT_SUBREG:{ *:[v8i64] } (IMPLICIT_DEF:{ *:[v8i64] }), VR256X:{ *:[v4i64] }:$src1, sub_ymm:{ *:[i32] })), sub_ymm:{ *:[i32] }) 24676 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v64s8, 24677 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s64, 24678 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v8s64, 24679 GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::IMPLICIT_DEF, 24680 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, 24681 GIR_ConstrainSelectedInstOperands, /*InsnID*/3, 24682 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::INSERT_SUBREG, 24683 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 24684 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/2, /*TempRegFlags*/0, 24685 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src1 24686 GIR_AddImm, /*InsnID*/2, /*Imm*/10, 24687 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, X86::VR512RegClassID, 24688 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, X86::VR512RegClassID, 24689 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, X86::VR256XRegClassID, 24690 GIR_BuildMI, /*InsnID*/1, /*Opcode*/X86::VPOPCNTQZrr, 24691 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 24692 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, 24693 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 24694 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 24695 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 24696 GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, X86::sub_ymm, 24697 GIR_EraseFromParent, /*InsnID*/0, 24698 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, X86::VR256XRegClassID, 24699 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, X86::VR512RegClassID, 24700 // GIR_Coverage, 20248, 24701 GIR_Done, 24702 // Label 2062: @56260 24703 GIM_Reject, 24704 // Label 2060: @56261 24705 GIM_Reject, 24706 // Label 2044: @56262 24707 GIM_Try, /*On fail goto*//*Label 2063*/ 56384, 24708 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, 24709 GIM_Try, /*On fail goto*//*Label 2064*/ 56287, // Rule ID 14221 // 24710 GIM_CheckFeatures, GIFBS_HasBITALG_HasVLX, 24711 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID, 24712 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID, 24713 // (ctpop:{ *:[v8i16] } VR128X:{ *:[v8i16] }:$src1) => (VPOPCNTWZ128rr:{ *:[v8i16] } VR128X:{ *:[v8i16] }:$src1) 24714 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPOPCNTWZ128rr, 24715 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 24716 // GIR_Coverage, 14221, 24717 GIR_Done, 24718 // Label 2064: @56287 24719 GIM_Try, /*On fail goto*//*Label 2065*/ 56383, // Rule ID 20540 // 24720 GIM_CheckFeatures, GIFBS_HasBITALG_NoVLX, 24721 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 24722 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID, 24723 // (ctpop:{ *:[v8i16] } VR128X:{ *:[v8i16] }:$src1) => (EXTRACT_SUBREG:{ *:[v8i16] } (VPOPCNTWZrr:{ *:[v64i8] } (INSERT_SUBREG:{ *:[v32i16] } (IMPLICIT_DEF:{ *:[v32i16] }), VR128X:{ *:[v8i16] }:$src1, sub_xmm:{ *:[i32] })), sub_xmm:{ *:[i32] }) 24724 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v64s8, 24725 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v32s16, 24726 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v32s16, 24727 GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::IMPLICIT_DEF, 24728 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, 24729 GIR_ConstrainSelectedInstOperands, /*InsnID*/3, 24730 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::INSERT_SUBREG, 24731 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 24732 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/2, /*TempRegFlags*/0, 24733 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src1 24734 GIR_AddImm, /*InsnID*/2, /*Imm*/9, 24735 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, X86::VR512RegClassID, 24736 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, X86::VR512RegClassID, 24737 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, X86::VR128XRegClassID, 24738 GIR_BuildMI, /*InsnID*/1, /*Opcode*/X86::VPOPCNTWZrr, 24739 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 24740 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, 24741 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 24742 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 24743 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 24744 GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, X86::sub_xmm, 24745 GIR_EraseFromParent, /*InsnID*/0, 24746 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, X86::FR16XRegClassID, 24747 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, X86::VR512RegClassID, 24748 // GIR_Coverage, 20540, 24749 GIR_Done, 24750 // Label 2065: @56383 24751 GIM_Reject, 24752 // Label 2063: @56384 24753 GIM_Reject, 24754 // Label 2045: @56385 24755 GIM_Try, /*On fail goto*//*Label 2066*/ 56507, 24756 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s32, 24757 GIM_Try, /*On fail goto*//*Label 2067*/ 56410, // Rule ID 13185 // 24758 GIM_CheckFeatures, GIFBS_HasVLX_HasVPOPCNTDQ, 24759 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID, 24760 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID, 24761 // (ctpop:{ *:[v8i32] } VR256X:{ *:[v8i32] }:$src1) => (VPOPCNTDZ256rr:{ *:[v8i32] } VR256X:{ *:[v8i32] }:$src1) 24762 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPOPCNTDZ256rr, 24763 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 24764 // GIR_Coverage, 13185, 24765 GIR_Done, 24766 // Label 2067: @56410 24767 GIM_Try, /*On fail goto*//*Label 2068*/ 56506, // Rule ID 20250 // 24768 GIM_CheckFeatures, GIFBS_HasVPOPCNTDQ_NoVLX, 24769 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 24770 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID, 24771 // (ctpop:{ *:[v8i32] } VR256X:{ *:[v8i32] }:$src1) => (EXTRACT_SUBREG:{ *:[v8i32] } (VPOPCNTDZrr:{ *:[v64i8] } (INSERT_SUBREG:{ *:[v16i32] } (IMPLICIT_DEF:{ *:[v16i32] }), VR256X:{ *:[v8i32] }:$src1, sub_ymm:{ *:[i32] })), sub_ymm:{ *:[i32] }) 24772 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v64s8, 24773 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s32, 24774 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s32, 24775 GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::IMPLICIT_DEF, 24776 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, 24777 GIR_ConstrainSelectedInstOperands, /*InsnID*/3, 24778 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::INSERT_SUBREG, 24779 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 24780 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/2, /*TempRegFlags*/0, 24781 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src1 24782 GIR_AddImm, /*InsnID*/2, /*Imm*/10, 24783 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, X86::VR512RegClassID, 24784 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, X86::VR512RegClassID, 24785 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, X86::VR256XRegClassID, 24786 GIR_BuildMI, /*InsnID*/1, /*Opcode*/X86::VPOPCNTDZrr, 24787 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 24788 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, 24789 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 24790 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 24791 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 24792 GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, X86::sub_ymm, 24793 GIR_EraseFromParent, /*InsnID*/0, 24794 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, X86::VR256XRegClassID, 24795 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, X86::VR512RegClassID, 24796 // GIR_Coverage, 20250, 24797 GIR_Done, 24798 // Label 2068: @56506 24799 GIM_Reject, 24800 // Label 2066: @56507 24801 GIM_Reject, 24802 // Label 2046: @56508 24803 GIM_Try, /*On fail goto*//*Label 2069*/ 56531, // Rule ID 13149 // 24804 GIM_CheckFeatures, GIFBS_HasVPOPCNTDQ, 24805 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s64, 24806 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 24807 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR512RegClassID, 24808 // (ctpop:{ *:[v8i64] } VR512:{ *:[v8i64] }:$src1) => (VPOPCNTQZrr:{ *:[v8i64] } VR512:{ *:[v8i64] }:$src1) 24809 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPOPCNTQZrr, 24810 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 24811 // GIR_Coverage, 13149, 24812 GIR_Done, 24813 // Label 2069: @56531 24814 GIM_Reject, 24815 // Label 2047: @56532 24816 GIM_Try, /*On fail goto*//*Label 2070*/ 56654, 24817 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, 24818 GIM_Try, /*On fail goto*//*Label 2071*/ 56557, // Rule ID 14203 // 24819 GIM_CheckFeatures, GIFBS_HasBITALG_HasVLX, 24820 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID, 24821 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID, 24822 // (ctpop:{ *:[v16i8] } VR128X:{ *:[v16i8] }:$src1) => (VPOPCNTBZ128rr:{ *:[v16i8] } VR128X:{ *:[v16i8] }:$src1) 24823 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPOPCNTBZ128rr, 24824 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 24825 // GIR_Coverage, 14203, 24826 GIR_Done, 24827 // Label 2071: @56557 24828 GIM_Try, /*On fail goto*//*Label 2072*/ 56653, // Rule ID 20538 // 24829 GIM_CheckFeatures, GIFBS_HasBITALG_NoVLX, 24830 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 24831 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID, 24832 // (ctpop:{ *:[v16i8] } VR128X:{ *:[v16i8] }:$src1) => (EXTRACT_SUBREG:{ *:[v16i8] } (VPOPCNTBZrr:{ *:[v64i8] } (INSERT_SUBREG:{ *:[v64i8] } (IMPLICIT_DEF:{ *:[v64i8] }), VR128X:{ *:[v16i8] }:$src1, sub_xmm:{ *:[i32] })), sub_xmm:{ *:[i32] }) 24833 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v64s8, 24834 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v64s8, 24835 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v64s8, 24836 GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::IMPLICIT_DEF, 24837 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, 24838 GIR_ConstrainSelectedInstOperands, /*InsnID*/3, 24839 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::INSERT_SUBREG, 24840 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 24841 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/2, /*TempRegFlags*/0, 24842 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src1 24843 GIR_AddImm, /*InsnID*/2, /*Imm*/9, 24844 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, X86::VR512RegClassID, 24845 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, X86::VR512RegClassID, 24846 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, X86::VR128XRegClassID, 24847 GIR_BuildMI, /*InsnID*/1, /*Opcode*/X86::VPOPCNTBZrr, 24848 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 24849 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, 24850 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 24851 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 24852 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 24853 GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, X86::sub_xmm, 24854 GIR_EraseFromParent, /*InsnID*/0, 24855 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, X86::FR16XRegClassID, 24856 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, X86::VR512RegClassID, 24857 // GIR_Coverage, 20538, 24858 GIR_Done, 24859 // Label 2072: @56653 24860 GIM_Reject, 24861 // Label 2070: @56654 24862 GIM_Reject, 24863 // Label 2048: @56655 24864 GIM_Try, /*On fail goto*//*Label 2073*/ 56777, 24865 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s16, 24866 GIM_Try, /*On fail goto*//*Label 2074*/ 56680, // Rule ID 14215 // 24867 GIM_CheckFeatures, GIFBS_HasBITALG_HasVLX, 24868 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID, 24869 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID, 24870 // (ctpop:{ *:[v16i16] } VR256X:{ *:[v16i16] }:$src1) => (VPOPCNTWZ256rr:{ *:[v16i16] } VR256X:{ *:[v16i16] }:$src1) 24871 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPOPCNTWZ256rr, 24872 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 24873 // GIR_Coverage, 14215, 24874 GIR_Done, 24875 // Label 2074: @56680 24876 GIM_Try, /*On fail goto*//*Label 2075*/ 56776, // Rule ID 20539 // 24877 GIM_CheckFeatures, GIFBS_HasBITALG_NoVLX, 24878 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 24879 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID, 24880 // (ctpop:{ *:[v16i16] } VR256X:{ *:[v16i16] }:$src1) => (EXTRACT_SUBREG:{ *:[v16i16] } (VPOPCNTWZrr:{ *:[v64i8] } (INSERT_SUBREG:{ *:[v32i16] } (IMPLICIT_DEF:{ *:[v32i16] }), VR256X:{ *:[v16i16] }:$src1, sub_ymm:{ *:[i32] })), sub_ymm:{ *:[i32] }) 24881 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v64s8, 24882 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v32s16, 24883 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v32s16, 24884 GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::IMPLICIT_DEF, 24885 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, 24886 GIR_ConstrainSelectedInstOperands, /*InsnID*/3, 24887 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::INSERT_SUBREG, 24888 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 24889 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/2, /*TempRegFlags*/0, 24890 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src1 24891 GIR_AddImm, /*InsnID*/2, /*Imm*/10, 24892 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, X86::VR512RegClassID, 24893 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, X86::VR512RegClassID, 24894 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, X86::VR256XRegClassID, 24895 GIR_BuildMI, /*InsnID*/1, /*Opcode*/X86::VPOPCNTWZrr, 24896 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 24897 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, 24898 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 24899 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 24900 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 24901 GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, X86::sub_ymm, 24902 GIR_EraseFromParent, /*InsnID*/0, 24903 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, X86::VR256XRegClassID, 24904 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, X86::VR512RegClassID, 24905 // GIR_Coverage, 20539, 24906 GIR_Done, 24907 // Label 2075: @56776 24908 GIM_Reject, 24909 // Label 2073: @56777 24910 GIM_Reject, 24911 // Label 2049: @56778 24912 GIM_Try, /*On fail goto*//*Label 2076*/ 56801, // Rule ID 13176 // 24913 GIM_CheckFeatures, GIFBS_HasVPOPCNTDQ, 24914 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s32, 24915 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 24916 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR512RegClassID, 24917 // (ctpop:{ *:[v16i32] } VR512:{ *:[v16i32] }:$src1) => (VPOPCNTDZrr:{ *:[v16i32] } VR512:{ *:[v16i32] }:$src1) 24918 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPOPCNTDZrr, 24919 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 24920 // GIR_Coverage, 13176, 24921 GIR_Done, 24922 // Label 2076: @56801 24923 GIM_Reject, 24924 // Label 2050: @56802 24925 GIM_Try, /*On fail goto*//*Label 2077*/ 56924, 24926 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v32s8, 24927 GIM_Try, /*On fail goto*//*Label 2078*/ 56827, // Rule ID 14197 // 24928 GIM_CheckFeatures, GIFBS_HasBITALG_HasVLX, 24929 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID, 24930 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID, 24931 // (ctpop:{ *:[v32i8] } VR256X:{ *:[v32i8] }:$src1) => (VPOPCNTBZ256rr:{ *:[v32i8] } VR256X:{ *:[v32i8] }:$src1) 24932 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPOPCNTBZ256rr, 24933 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 24934 // GIR_Coverage, 14197, 24935 GIR_Done, 24936 // Label 2078: @56827 24937 GIM_Try, /*On fail goto*//*Label 2079*/ 56923, // Rule ID 20537 // 24938 GIM_CheckFeatures, GIFBS_HasBITALG_NoVLX, 24939 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 24940 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID, 24941 // (ctpop:{ *:[v32i8] } VR256X:{ *:[v32i8] }:$src1) => (EXTRACT_SUBREG:{ *:[v32i8] } (VPOPCNTBZrr:{ *:[v64i8] } (INSERT_SUBREG:{ *:[v64i8] } (IMPLICIT_DEF:{ *:[v64i8] }), VR256X:{ *:[v32i8] }:$src1, sub_ymm:{ *:[i32] })), sub_ymm:{ *:[i32] }) 24942 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v64s8, 24943 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v64s8, 24944 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v64s8, 24945 GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::IMPLICIT_DEF, 24946 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, 24947 GIR_ConstrainSelectedInstOperands, /*InsnID*/3, 24948 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::INSERT_SUBREG, 24949 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 24950 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/2, /*TempRegFlags*/0, 24951 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src1 24952 GIR_AddImm, /*InsnID*/2, /*Imm*/10, 24953 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, X86::VR512RegClassID, 24954 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, X86::VR512RegClassID, 24955 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, X86::VR256XRegClassID, 24956 GIR_BuildMI, /*InsnID*/1, /*Opcode*/X86::VPOPCNTBZrr, 24957 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 24958 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, 24959 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 24960 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 24961 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 24962 GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, X86::sub_ymm, 24963 GIR_EraseFromParent, /*InsnID*/0, 24964 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, X86::VR256XRegClassID, 24965 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, X86::VR512RegClassID, 24966 // GIR_Coverage, 20537, 24967 GIR_Done, 24968 // Label 2079: @56923 24969 GIM_Reject, 24970 // Label 2077: @56924 24971 GIM_Reject, 24972 // Label 2051: @56925 24973 GIM_Try, /*On fail goto*//*Label 2080*/ 56948, // Rule ID 14209 // 24974 GIM_CheckFeatures, GIFBS_HasBITALG, 24975 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v32s16, 24976 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 24977 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR512RegClassID, 24978 // (ctpop:{ *:[v32i16] } VR512:{ *:[v32i16] }:$src1) => (VPOPCNTWZrr:{ *:[v32i16] } VR512:{ *:[v32i16] }:$src1) 24979 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPOPCNTWZrr, 24980 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 24981 // GIR_Coverage, 14209, 24982 GIR_Done, 24983 // Label 2080: @56948 24984 GIM_Reject, 24985 // Label 2052: @56949 24986 GIM_Try, /*On fail goto*//*Label 2081*/ 56972, // Rule ID 14191 // 24987 GIM_CheckFeatures, GIFBS_HasBITALG, 24988 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v64s8, 24989 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 24990 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR512RegClassID, 24991 // (ctpop:{ *:[v64i8] } VR512:{ *:[v64i8] }:$src1) => (VPOPCNTBZrr:{ *:[v64i8] } VR512:{ *:[v64i8] }:$src1) 24992 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPOPCNTBZrr, 24993 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 24994 // GIR_Coverage, 14191, 24995 GIR_Done, 24996 // Label 2081: @56972 24997 GIM_Reject, 24998 // Label 2053: @56973 24999 GIM_Reject, 25000 // Label 53: @56974 25001 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/2, 5, /*)*//*default:*//*Label 2085*/ 57063, 25002 /*GILLT_s16*//*Label 2082*/ 56983, 25003 /*GILLT_s32*//*Label 2083*/ 57019, 25004 /*GILLT_s64*//*Label 2084*/ 57041, 25005 // Label 2082: @56983 25006 GIM_Try, /*On fail goto*//*Label 2086*/ 57018, // Rule ID 15716 // 25007 GIM_CheckFeatures, GIFBS_HasMOVBE, 25008 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16, 25009 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR16RegClassID, 25010 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR16RegClassID, 25011 // (bswap:{ *:[i16] } GR16:{ *:[i16] }:$src) => (ROL16ri:{ *:[i16] }:{ *:[i32] } GR16:{ *:[i16] }:$src, 8:{ *:[i8] }) 25012 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::ROL16ri, 25013 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 25014 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 25015 GIR_AddImm, /*InsnID*/0, /*Imm*/8, 25016 GIR_EraseFromParent, /*InsnID*/0, 25017 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 25018 // GIR_Coverage, 15716, 25019 GIR_Done, 25020 // Label 2086: @57018 25021 GIM_Reject, 25022 // Label 2083: @57019 25023 GIM_Try, /*On fail goto*//*Label 2087*/ 57040, // Rule ID 5 // 25024 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 25025 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID, 25026 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR32RegClassID, 25027 // (bswap:{ *:[i32] } GR32:{ *:[i32] }:$src) => (BSWAP32r:{ *:[i32] } GR32:{ *:[i32] }:$src) 25028 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::BSWAP32r, 25029 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 25030 // GIR_Coverage, 5, 25031 GIR_Done, 25032 // Label 2087: @57040 25033 GIM_Reject, 25034 // Label 2084: @57041 25035 GIM_Try, /*On fail goto*//*Label 2088*/ 57062, // Rule ID 6 // 25036 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 25037 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID, 25038 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR64RegClassID, 25039 // (bswap:{ *:[i64] } GR64:{ *:[i64] }:$src) => (BSWAP64r:{ *:[i64] } GR64:{ *:[i64] }:$src) 25040 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::BSWAP64r, 25041 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 25042 // GIR_Coverage, 6, 25043 GIR_Done, 25044 // Label 2088: @57062 25045 GIM_Reject, 25046 // Label 2085: @57063 25047 GIM_Reject, 25048 // Label 54: @57064 25049 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/2, 23, /*)*//*default:*//*Label 2102*/ 57843, 25050 /*GILLT_s16*//*Label 2089*/ 57091, 25051 /*GILLT_s32*//*Label 2090*/ 57140, 25052 /*GILLT_s64*//*Label 2091*/ 57283, 25053 /*GILLT_s80*//*Label 2092*/ 57426, 0, 0, 25054 /*GILLT_v2s64*//*Label 2093*/ 57456, 0, 25055 /*GILLT_v4s32*//*Label 2094*/ 57530, 25056 /*GILLT_v4s64*//*Label 2095*/ 57604, 0, 25057 /*GILLT_v8s16*//*Label 2096*/ 57656, 25058 /*GILLT_v8s32*//*Label 2097*/ 57683, 25059 /*GILLT_v8s64*//*Label 2098*/ 57735, 0, 0, 25060 /*GILLT_v16s16*//*Label 2099*/ 57762, 25061 /*GILLT_v16s32*//*Label 2100*/ 57789, 0, 0, 25062 /*GILLT_v32s16*//*Label 2101*/ 57816, 25063 // Label 2089: @57091 25064 GIM_Try, /*On fail goto*//*Label 2103*/ 57139, // Rule ID 19874 // 25065 GIM_CheckFeatures, GIFBS_HasFP16, 25066 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16, 25067 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::FR16XRegClassID, 25068 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::FR16XRegClassID, 25069 // (fsqrt:{ *:[f16] } FR16X:{ *:[f16] }:$src) => (VSQRTSHZr:{ *:[f16] } (IMPLICIT_DEF:{ *:[f16] }), FR16X:{ *:[f16] }:$src) 25070 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16, 25071 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, 25072 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 25073 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 25074 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VSQRTSHZr, 25075 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 25076 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 25077 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 25078 GIR_EraseFromParent, /*InsnID*/0, 25079 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 25080 // GIR_Coverage, 19874, 25081 GIR_Done, 25082 // Label 2103: @57139 25083 GIM_Reject, 25084 // Label 2090: @57140 25085 GIM_Try, /*On fail goto*//*Label 2104*/ 57282, 25086 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 25087 GIM_Try, /*On fail goto*//*Label 2105*/ 57171, // Rule ID 783 // 25088 GIM_CheckFeatures, GIFBS_FPStackf32, 25089 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::RFP32RegClassID, 25090 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::RFP32RegClassID, 25091 // (fsqrt:{ *:[f32] } RFP32:{ *:[f32] }:$src) => (SQRT_Fp32:{ *:[f32] }:{ *:[i16] } RFP32:{ *:[f32] }:$src) 25092 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::SQRT_Fp32, 25093 GIR_AddImplicitDef, /*InsnID*/0, X86::FPSW, 25094 GIR_AddImplicitUse, /*InsnID*/0, X86::FPCW, 25095 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 25096 // GIR_Coverage, 783, 25097 GIR_Done, 25098 // Label 2105: @57171 25099 GIM_Try, /*On fail goto*//*Label 2106*/ 57193, // Rule ID 2139 // 25100 GIM_CheckFeatures, GIFBS_UseSSE1, 25101 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::FR32RegClassID, 25102 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::FR32RegClassID, 25103 // (fsqrt:{ *:[f32] } FR32:{ *:[f32] }:$src1) => (SQRTSSr:{ *:[f32] } FR32:{ *:[f32] }:$src1) 25104 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::SQRTSSr, 25105 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 25106 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 25107 // GIR_Coverage, 2139, 25108 GIR_Done, 25109 // Label 2106: @57193 25110 GIM_Try, /*On fail goto*//*Label 2107*/ 57237, // Rule ID 16722 // 25111 GIM_CheckFeatures, GIFBS_UseAVX, 25112 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::FR32RegClassID, 25113 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::FR32RegClassID, 25114 // (fsqrt:{ *:[f32] } FR32:{ *:[f32] }:$src) => (VSQRTSSr:{ *:[f32] } (IMPLICIT_DEF:{ *:[f32] }), FR32:{ *:[f32] }:$src) 25115 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, 25116 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, 25117 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 25118 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 25119 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VSQRTSSr, 25120 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 25121 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 25122 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 25123 GIR_EraseFromParent, /*InsnID*/0, 25124 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 25125 // GIR_Coverage, 16722, 25126 GIR_Done, 25127 // Label 2107: @57237 25128 GIM_Try, /*On fail goto*//*Label 2108*/ 57281, // Rule ID 19878 // 25129 GIM_CheckFeatures, GIFBS_HasAVX512, 25130 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::FR32XRegClassID, 25131 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::FR32XRegClassID, 25132 // (fsqrt:{ *:[f32] } FR32X:{ *:[f32] }:$src) => (VSQRTSSZr:{ *:[f32] } (IMPLICIT_DEF:{ *:[f32] }), FR32X:{ *:[f32] }:$src) 25133 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, 25134 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, 25135 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 25136 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 25137 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VSQRTSSZr, 25138 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 25139 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 25140 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 25141 GIR_EraseFromParent, /*InsnID*/0, 25142 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 25143 // GIR_Coverage, 19878, 25144 GIR_Done, 25145 // Label 2108: @57281 25146 GIM_Reject, 25147 // Label 2104: @57282 25148 GIM_Reject, 25149 // Label 2091: @57283 25150 GIM_Try, /*On fail goto*//*Label 2109*/ 57425, 25151 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 25152 GIM_Try, /*On fail goto*//*Label 2110*/ 57314, // Rule ID 785 // 25153 GIM_CheckFeatures, GIFBS_FPStackf64, 25154 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::RFP64RegClassID, 25155 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::RFP64RegClassID, 25156 // (fsqrt:{ *:[f64] } RFP64:{ *:[f64] }:$src) => (SQRT_Fp64:{ *:[f64] }:{ *:[i16] } RFP64:{ *:[f64] }:$src) 25157 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::SQRT_Fp64, 25158 GIR_AddImplicitDef, /*InsnID*/0, X86::FPSW, 25159 GIR_AddImplicitUse, /*InsnID*/0, X86::FPCW, 25160 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 25161 // GIR_Coverage, 785, 25162 GIR_Done, 25163 // Label 2110: @57314 25164 GIM_Try, /*On fail goto*//*Label 2111*/ 57336, // Rule ID 2155 // 25165 GIM_CheckFeatures, GIFBS_UseSSE2, 25166 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::FR64RegClassID, 25167 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::FR64RegClassID, 25168 // (fsqrt:{ *:[f64] } FR64:{ *:[f64] }:$src1) => (SQRTSDr:{ *:[f64] } FR64:{ *:[f64] }:$src1) 25169 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::SQRTSDr, 25170 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 25171 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 25172 // GIR_Coverage, 2155, 25173 GIR_Done, 25174 // Label 2111: @57336 25175 GIM_Try, /*On fail goto*//*Label 2112*/ 57380, // Rule ID 16726 // 25176 GIM_CheckFeatures, GIFBS_UseAVX, 25177 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::FR64RegClassID, 25178 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::FR64RegClassID, 25179 // (fsqrt:{ *:[f64] } FR64:{ *:[f64] }:$src) => (VSQRTSDr:{ *:[f64] } (IMPLICIT_DEF:{ *:[f64] }), FR64:{ *:[f64] }:$src) 25180 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, 25181 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, 25182 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 25183 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 25184 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VSQRTSDr, 25185 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 25186 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 25187 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 25188 GIR_EraseFromParent, /*InsnID*/0, 25189 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 25190 // GIR_Coverage, 16726, 25191 GIR_Done, 25192 // Label 2112: @57380 25193 GIM_Try, /*On fail goto*//*Label 2113*/ 57424, // Rule ID 19882 // 25194 GIM_CheckFeatures, GIFBS_HasAVX512, 25195 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::FR64XRegClassID, 25196 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::FR64XRegClassID, 25197 // (fsqrt:{ *:[f64] } FR64X:{ *:[f64] }:$src) => (VSQRTSDZr:{ *:[f64] } (IMPLICIT_DEF:{ *:[f64] }), FR64X:{ *:[f64] }:$src) 25198 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, 25199 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, 25200 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 25201 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 25202 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VSQRTSDZr, 25203 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 25204 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 25205 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 25206 GIR_EraseFromParent, /*InsnID*/0, 25207 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 25208 // GIR_Coverage, 19882, 25209 GIR_Done, 25210 // Label 2113: @57424 25211 GIM_Reject, 25212 // Label 2109: @57425 25213 GIM_Reject, 25214 // Label 2092: @57426 25215 GIM_Try, /*On fail goto*//*Label 2114*/ 57455, // Rule ID 787 // 25216 GIM_CheckFeatures, GIFBS_HasX87, 25217 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s80, 25218 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::RFP80RegClassID, 25219 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::RFP80RegClassID, 25220 // (fsqrt:{ *:[f80] } RFP80:{ *:[f80] }:$src) => (SQRT_Fp80:{ *:[f80] }:{ *:[i16] } RFP80:{ *:[f80] }:$src) 25221 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::SQRT_Fp80, 25222 GIR_AddImplicitDef, /*InsnID*/0, X86::FPSW, 25223 GIR_AddImplicitUse, /*InsnID*/0, X86::FPCW, 25224 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 25225 // GIR_Coverage, 787, 25226 GIR_Done, 25227 // Label 2114: @57455 25228 GIM_Reject, 25229 // Label 2093: @57456 25230 GIM_Try, /*On fail goto*//*Label 2115*/ 57529, 25231 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, 25232 GIM_Try, /*On fail goto*//*Label 2116*/ 57484, // Rule ID 2159 // 25233 GIM_CheckFeatures, GIFBS_HasAVX_NoVLX, 25234 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 25235 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 25236 // (fsqrt:{ *:[v2f64] } VR128:{ *:[v2f64] }:$src) => (VSQRTPDr:{ *:[v2f64] } VR128:{ *:[v2f64] }:$src) 25237 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VSQRTPDr, 25238 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 25239 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 25240 // GIR_Coverage, 2159, 25241 GIR_Done, 25242 // Label 2116: @57484 25243 GIM_Try, /*On fail goto*//*Label 2117*/ 57506, // Rule ID 2167 // 25244 GIM_CheckFeatures, GIFBS_UseSSE2, 25245 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 25246 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 25247 // (fsqrt:{ *:[v2f64] } VR128:{ *:[v2f64] }:$src) => (SQRTPDr:{ *:[v2f64] } VR128:{ *:[v2f64] }:$src) 25248 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::SQRTPDr, 25249 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 25250 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 25251 // GIR_Coverage, 2167, 25252 GIR_Done, 25253 // Label 2117: @57506 25254 GIM_Try, /*On fail goto*//*Label 2118*/ 57528, // Rule ID 11788 // 25255 GIM_CheckFeatures, GIFBS_HasVLX, 25256 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID, 25257 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID, 25258 // (fsqrt:{ *:[v2f64] } VR128X:{ *:[v2f64] }:$src) => (VSQRTPDZ128r:{ *:[v2f64] } VR128X:{ *:[v2f64] }:$src) 25259 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VSQRTPDZ128r, 25260 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 25261 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 25262 // GIR_Coverage, 11788, 25263 GIR_Done, 25264 // Label 2118: @57528 25265 GIM_Reject, 25266 // Label 2115: @57529 25267 GIM_Reject, 25268 // Label 2094: @57530 25269 GIM_Try, /*On fail goto*//*Label 2119*/ 57603, 25270 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, 25271 GIM_Try, /*On fail goto*//*Label 2120*/ 57558, // Rule ID 2143 // 25272 GIM_CheckFeatures, GIFBS_HasAVX_NoVLX, 25273 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 25274 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 25275 // (fsqrt:{ *:[v4f32] } VR128:{ *:[v4f32] }:$src) => (VSQRTPSr:{ *:[v4f32] } VR128:{ *:[v4f32] }:$src) 25276 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VSQRTPSr, 25277 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 25278 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 25279 // GIR_Coverage, 2143, 25280 GIR_Done, 25281 // Label 2120: @57558 25282 GIM_Try, /*On fail goto*//*Label 2121*/ 57580, // Rule ID 2151 // 25283 GIM_CheckFeatures, GIFBS_UseSSE1, 25284 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 25285 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 25286 // (fsqrt:{ *:[v4f32] } VR128:{ *:[v4f32] }:$src) => (SQRTPSr:{ *:[v4f32] } VR128:{ *:[v4f32] }:$src) 25287 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::SQRTPSr, 25288 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 25289 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 25290 // GIR_Coverage, 2151, 25291 GIR_Done, 25292 // Label 2121: @57580 25293 GIM_Try, /*On fail goto*//*Label 2122*/ 57602, // Rule ID 11764 // 25294 GIM_CheckFeatures, GIFBS_HasVLX, 25295 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID, 25296 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID, 25297 // (fsqrt:{ *:[v4f32] } VR128X:{ *:[v4f32] }:$src) => (VSQRTPSZ128r:{ *:[v4f32] } VR128X:{ *:[v4f32] }:$src) 25298 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VSQRTPSZ128r, 25299 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 25300 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 25301 // GIR_Coverage, 11764, 25302 GIR_Done, 25303 // Label 2122: @57602 25304 GIM_Reject, 25305 // Label 2119: @57603 25306 GIM_Reject, 25307 // Label 2095: @57604 25308 GIM_Try, /*On fail goto*//*Label 2123*/ 57655, 25309 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s64, 25310 GIM_Try, /*On fail goto*//*Label 2124*/ 57632, // Rule ID 2163 // 25311 GIM_CheckFeatures, GIFBS_HasAVX_NoVLX, 25312 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID, 25313 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256RegClassID, 25314 // (fsqrt:{ *:[v4f64] } VR256:{ *:[v4f64] }:$src) => (VSQRTPDYr:{ *:[v4f64] } VR256:{ *:[v4f64] }:$src) 25315 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VSQRTPDYr, 25316 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 25317 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 25318 // GIR_Coverage, 2163, 25319 GIR_Done, 25320 // Label 2124: @57632 25321 GIM_Try, /*On fail goto*//*Label 2125*/ 57654, // Rule ID 11800 // 25322 GIM_CheckFeatures, GIFBS_HasVLX, 25323 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID, 25324 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID, 25325 // (fsqrt:{ *:[v4f64] } VR256X:{ *:[v4f64] }:$src) => (VSQRTPDZ256r:{ *:[v4f64] } VR256X:{ *:[v4f64] }:$src) 25326 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VSQRTPDZ256r, 25327 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 25328 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 25329 // GIR_Coverage, 11800, 25330 GIR_Done, 25331 // Label 2125: @57654 25332 GIM_Reject, 25333 // Label 2123: @57655 25334 GIM_Reject, 25335 // Label 2096: @57656 25336 GIM_Try, /*On fail goto*//*Label 2126*/ 57682, // Rule ID 11716 // 25337 GIM_CheckFeatures, GIFBS_HasFP16_HasVLX, 25338 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, 25339 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID, 25340 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID, 25341 // (fsqrt:{ *:[v8f16] } VR128X:{ *:[v8f16] }:$src) => (VSQRTPHZ128r:{ *:[v8f16] } VR128X:{ *:[v8f16] }:$src) 25342 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VSQRTPHZ128r, 25343 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 25344 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 25345 // GIR_Coverage, 11716, 25346 GIR_Done, 25347 // Label 2126: @57682 25348 GIM_Reject, 25349 // Label 2097: @57683 25350 GIM_Try, /*On fail goto*//*Label 2127*/ 57734, 25351 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s32, 25352 GIM_Try, /*On fail goto*//*Label 2128*/ 57711, // Rule ID 2147 // 25353 GIM_CheckFeatures, GIFBS_HasAVX_NoVLX, 25354 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID, 25355 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256RegClassID, 25356 // (fsqrt:{ *:[v8f32] } VR256:{ *:[v8f32] }:$src) => (VSQRTPSYr:{ *:[v8f32] } VR256:{ *:[v8f32] }:$src) 25357 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VSQRTPSYr, 25358 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 25359 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 25360 // GIR_Coverage, 2147, 25361 GIR_Done, 25362 // Label 2128: @57711 25363 GIM_Try, /*On fail goto*//*Label 2129*/ 57733, // Rule ID 11776 // 25364 GIM_CheckFeatures, GIFBS_HasVLX, 25365 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID, 25366 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID, 25367 // (fsqrt:{ *:[v8f32] } VR256X:{ *:[v8f32] }:$src) => (VSQRTPSZ256r:{ *:[v8f32] } VR256X:{ *:[v8f32] }:$src) 25368 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VSQRTPSZ256r, 25369 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 25370 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 25371 // GIR_Coverage, 11776, 25372 GIR_Done, 25373 // Label 2129: @57733 25374 GIM_Reject, 25375 // Label 2127: @57734 25376 GIM_Reject, 25377 // Label 2098: @57735 25378 GIM_Try, /*On fail goto*//*Label 2130*/ 57761, // Rule ID 11752 // 25379 GIM_CheckFeatures, GIFBS_HasAVX512, 25380 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s64, 25381 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 25382 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR512RegClassID, 25383 // (fsqrt:{ *:[v8f64] } VR512:{ *:[v8f64] }:$src) => (VSQRTPDZr:{ *:[v8f64] } VR512:{ *:[v8f64] }:$src) 25384 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VSQRTPDZr, 25385 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 25386 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 25387 // GIR_Coverage, 11752, 25388 GIR_Done, 25389 // Label 2130: @57761 25390 GIM_Reject, 25391 // Label 2099: @57762 25392 GIM_Try, /*On fail goto*//*Label 2131*/ 57788, // Rule ID 11728 // 25393 GIM_CheckFeatures, GIFBS_HasFP16_HasVLX, 25394 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s16, 25395 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID, 25396 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID, 25397 // (fsqrt:{ *:[v16f16] } VR256X:{ *:[v16f16] }:$src) => (VSQRTPHZ256r:{ *:[v16f16] } VR256X:{ *:[v16f16] }:$src) 25398 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VSQRTPHZ256r, 25399 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 25400 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 25401 // GIR_Coverage, 11728, 25402 GIR_Done, 25403 // Label 2131: @57788 25404 GIM_Reject, 25405 // Label 2100: @57789 25406 GIM_Try, /*On fail goto*//*Label 2132*/ 57815, // Rule ID 11740 // 25407 GIM_CheckFeatures, GIFBS_HasAVX512, 25408 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s32, 25409 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 25410 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR512RegClassID, 25411 // (fsqrt:{ *:[v16f32] } VR512:{ *:[v16f32] }:$src) => (VSQRTPSZr:{ *:[v16f32] } VR512:{ *:[v16f32] }:$src) 25412 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VSQRTPSZr, 25413 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 25414 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 25415 // GIR_Coverage, 11740, 25416 GIR_Done, 25417 // Label 2132: @57815 25418 GIM_Reject, 25419 // Label 2101: @57816 25420 GIM_Try, /*On fail goto*//*Label 2133*/ 57842, // Rule ID 11704 // 25421 GIM_CheckFeatures, GIFBS_HasFP16, 25422 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v32s16, 25423 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 25424 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR512RegClassID, 25425 // (fsqrt:{ *:[v32f16] } VR512:{ *:[v32f16] }:$src) => (VSQRTPHZr:{ *:[v32f16] } VR512:{ *:[v32f16] }:$src) 25426 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VSQRTPHZr, 25427 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 25428 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 25429 // GIR_Coverage, 11704, 25430 GIR_Done, 25431 // Label 2133: @57842 25432 GIM_Reject, 25433 // Label 2102: @57843 25434 GIM_Reject, 25435 // Label 55: @57844 25436 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/2, 23, /*)*//*default:*//*Label 2147*/ 58665, 25437 /*GILLT_s16*//*Label 2134*/ 57871, 25438 /*GILLT_s32*//*Label 2135*/ 57906, 25439 /*GILLT_s64*//*Label 2136*/ 58025, 25440 /*GILLT_s80*//*Label 2137*/ 58144, 0, 0, 25441 /*GILLT_v2s64*//*Label 2138*/ 58182, 0, 25442 /*GILLT_v4s32*//*Label 2139*/ 58272, 25443 /*GILLT_v4s64*//*Label 2140*/ 58362, 0, 25444 /*GILLT_v8s16*//*Label 2141*/ 58426, 25445 /*GILLT_v8s32*//*Label 2142*/ 58461, 25446 /*GILLT_v8s64*//*Label 2143*/ 58525, 0, 0, 25447 /*GILLT_v16s16*//*Label 2144*/ 58560, 25448 /*GILLT_v16s32*//*Label 2145*/ 58595, 0, 0, 25449 /*GILLT_v32s16*//*Label 2146*/ 58630, 25450 // Label 2134: @57871 25451 GIM_Try, /*On fail goto*//*Label 2148*/ 57905, // Rule ID 5591 // 25452 GIM_CheckFeatures, GIFBS_HasFP16, 25453 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16, 25454 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16, 25455 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::FR16XRegClassID, 25456 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::FR16XRegClassID, 25457 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::FR16XRegClassID, 25458 // (strict_fadd:{ *:[f16] } FR16X:{ *:[f16] }:$src1, FR16X:{ *:[f16] }:$src2) => (VADDSHZrr:{ *:[f16] } FR16X:{ *:[f16] }:$src1, FR16X:{ *:[f16] }:$src2) 25459 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VADDSHZrr, 25460 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 25461 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 25462 // GIR_Coverage, 5591, 25463 GIR_Done, 25464 // Label 2148: @57905 25465 GIM_Reject, 25466 // Label 2135: @57906 25467 GIM_Try, /*On fail goto*//*Label 2149*/ 58024, 25468 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 25469 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 25470 GIM_Try, /*On fail goto*//*Label 2150*/ 57945, // Rule ID 620 // 25471 GIM_CheckFeatures, GIFBS_FPStackf32, 25472 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::RFP32RegClassID, 25473 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::RFP32RegClassID, 25474 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::RFP32RegClassID, 25475 // (strict_fadd:{ *:[f32] } RFP32:{ *:[f32] }:$src1, RFP32:{ *:[f32] }:$src2) => (ADD_Fp32:{ *:[f32] }:{ *:[i16] } RFP32:{ *:[f32] }:$src1, RFP32:{ *:[f32] }:$src2) 25476 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::ADD_Fp32, 25477 GIR_AddImplicitDef, /*InsnID*/0, X86::FPSW, 25478 GIR_AddImplicitUse, /*InsnID*/0, X86::FPCW, 25479 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 25480 // GIR_Coverage, 620, 25481 GIR_Done, 25482 // Label 2150: @57945 25483 GIM_Try, /*On fail goto*//*Label 2151*/ 57971, // Rule ID 1890 // 25484 GIM_CheckFeatures, GIFBS_UseAVX, 25485 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::FR32RegClassID, 25486 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::FR32RegClassID, 25487 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::FR32RegClassID, 25488 // (strict_fadd:{ *:[f32] } FR32:{ *:[f32] }:$src1, FR32:{ *:[f32] }:$src2) => (VADDSSrr:{ *:[f32] } FR32:{ *:[f32] }:$src1, FR32:{ *:[f32] }:$src2) 25489 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VADDSSrr, 25490 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 25491 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 25492 // GIR_Coverage, 1890, 25493 GIR_Done, 25494 // Label 2151: @57971 25495 GIM_Try, /*On fail goto*//*Label 2152*/ 57997, // Rule ID 1898 // 25496 GIM_CheckFeatures, GIFBS_UseSSE1, 25497 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::FR32RegClassID, 25498 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::FR32RegClassID, 25499 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::FR32RegClassID, 25500 // (strict_fadd:{ *:[f32] } FR32:{ *:[f32] }:$src1, FR32:{ *:[f32] }:$src2) => (ADDSSrr:{ *:[f32] } FR32:{ *:[f32] }:$src1, FR32:{ *:[f32] }:$src2) 25501 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::ADDSSrr, 25502 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 25503 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 25504 // GIR_Coverage, 1898, 25505 GIR_Done, 25506 // Label 2152: @57997 25507 GIM_Try, /*On fail goto*//*Label 2153*/ 58023, // Rule ID 5553 // 25508 GIM_CheckFeatures, GIFBS_HasAVX512, 25509 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::FR32XRegClassID, 25510 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::FR32XRegClassID, 25511 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::FR32XRegClassID, 25512 // (strict_fadd:{ *:[f32] } FR32X:{ *:[f32] }:$src1, FR32X:{ *:[f32] }:$src2) => (VADDSSZrr:{ *:[f32] } FR32X:{ *:[f32] }:$src1, FR32X:{ *:[f32] }:$src2) 25513 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VADDSSZrr, 25514 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 25515 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 25516 // GIR_Coverage, 5553, 25517 GIR_Done, 25518 // Label 2153: @58023 25519 GIM_Reject, 25520 // Label 2149: @58024 25521 GIM_Reject, 25522 // Label 2136: @58025 25523 GIM_Try, /*On fail goto*//*Label 2154*/ 58143, 25524 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 25525 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 25526 GIM_Try, /*On fail goto*//*Label 2155*/ 58064, // Rule ID 622 // 25527 GIM_CheckFeatures, GIFBS_FPStackf64, 25528 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::RFP64RegClassID, 25529 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::RFP64RegClassID, 25530 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::RFP64RegClassID, 25531 // (strict_fadd:{ *:[f64] } RFP64:{ *:[f64] }:$src1, RFP64:{ *:[f64] }:$src2) => (ADD_Fp64:{ *:[f64] }:{ *:[i16] } RFP64:{ *:[f64] }:$src1, RFP64:{ *:[f64] }:$src2) 25532 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::ADD_Fp64, 25533 GIR_AddImplicitDef, /*InsnID*/0, X86::FPSW, 25534 GIR_AddImplicitUse, /*InsnID*/0, X86::FPCW, 25535 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 25536 // GIR_Coverage, 622, 25537 GIR_Done, 25538 // Label 2155: @58064 25539 GIM_Try, /*On fail goto*//*Label 2156*/ 58090, // Rule ID 1894 // 25540 GIM_CheckFeatures, GIFBS_UseAVX, 25541 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::FR64RegClassID, 25542 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::FR64RegClassID, 25543 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::FR64RegClassID, 25544 // (strict_fadd:{ *:[f64] } FR64:{ *:[f64] }:$src1, FR64:{ *:[f64] }:$src2) => (VADDSDrr:{ *:[f64] } FR64:{ *:[f64] }:$src1, FR64:{ *:[f64] }:$src2) 25545 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VADDSDrr, 25546 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 25547 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 25548 // GIR_Coverage, 1894, 25549 GIR_Done, 25550 // Label 2156: @58090 25551 GIM_Try, /*On fail goto*//*Label 2157*/ 58116, // Rule ID 1902 // 25552 GIM_CheckFeatures, GIFBS_UseSSE2, 25553 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::FR64RegClassID, 25554 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::FR64RegClassID, 25555 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::FR64RegClassID, 25556 // (strict_fadd:{ *:[f64] } FR64:{ *:[f64] }:$src1, FR64:{ *:[f64] }:$src2) => (ADDSDrr:{ *:[f64] } FR64:{ *:[f64] }:$src1, FR64:{ *:[f64] }:$src2) 25557 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::ADDSDrr, 25558 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 25559 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 25560 // GIR_Coverage, 1902, 25561 GIR_Done, 25562 // Label 2157: @58116 25563 GIM_Try, /*On fail goto*//*Label 2158*/ 58142, // Rule ID 5572 // 25564 GIM_CheckFeatures, GIFBS_HasAVX512, 25565 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::FR64XRegClassID, 25566 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::FR64XRegClassID, 25567 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::FR64XRegClassID, 25568 // (strict_fadd:{ *:[f64] } FR64X:{ *:[f64] }:$src1, FR64X:{ *:[f64] }:$src2) => (VADDSDZrr:{ *:[f64] } FR64X:{ *:[f64] }:$src1, FR64X:{ *:[f64] }:$src2) 25569 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VADDSDZrr, 25570 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 25571 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 25572 // GIR_Coverage, 5572, 25573 GIR_Done, 25574 // Label 2158: @58142 25575 GIM_Reject, 25576 // Label 2154: @58143 25577 GIM_Reject, 25578 // Label 2137: @58144 25579 GIM_Try, /*On fail goto*//*Label 2159*/ 58181, // Rule ID 624 // 25580 GIM_CheckFeatures, GIFBS_HasX87, 25581 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s80, 25582 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s80, 25583 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::RFP80RegClassID, 25584 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::RFP80RegClassID, 25585 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::RFP80RegClassID, 25586 // (strict_fadd:{ *:[f80] } RFP80:{ *:[f80] }:$src1, RFP80:{ *:[f80] }:$src2) => (ADD_Fp80:{ *:[f80] }:{ *:[i16] } RFP80:{ *:[f80] }:$src1, RFP80:{ *:[f80] }:$src2) 25587 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::ADD_Fp80, 25588 GIR_AddImplicitDef, /*InsnID*/0, X86::FPSW, 25589 GIR_AddImplicitUse, /*InsnID*/0, X86::FPCW, 25590 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 25591 // GIR_Coverage, 624, 25592 GIR_Done, 25593 // Label 2159: @58181 25594 GIM_Reject, 25595 // Label 2138: @58182 25596 GIM_Try, /*On fail goto*//*Label 2160*/ 58271, 25597 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, 25598 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 25599 GIM_Try, /*On fail goto*//*Label 2161*/ 58218, // Rule ID 1870 // 25600 GIM_CheckFeatures, GIFBS_HasAVX_NoVLX, 25601 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 25602 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 25603 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 25604 // (strict_fadd:{ *:[v2f64] } VR128:{ *:[v2f64] }:$src1, VR128:{ *:[v2f64] }:$src2) => (VADDPDrr:{ *:[v2f64] } VR128:{ *:[v2f64] }:$src1, VR128:{ *:[v2f64] }:$src2) 25605 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VADDPDrr, 25606 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 25607 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 25608 // GIR_Coverage, 1870, 25609 GIR_Done, 25610 // Label 2161: @58218 25611 GIM_Try, /*On fail goto*//*Label 2162*/ 58244, // Rule ID 1886 // 25612 GIM_CheckFeatures, GIFBS_UseSSE2, 25613 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 25614 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 25615 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 25616 // (strict_fadd:{ *:[v2f64] } VR128:{ *:[v2f64] }:$src1, VR128:{ *:[v2f64] }:$src2) => (ADDPDrr:{ *:[v2f64] } VR128:{ *:[v2f64] }:$src1, VR128:{ *:[v2f64] }:$src2) 25617 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::ADDPDrr, 25618 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 25619 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 25620 // GIR_Coverage, 1886, 25621 GIR_Done, 25622 // Label 2162: @58244 25623 GIM_Try, /*On fail goto*//*Label 2163*/ 58270, // Rule ID 5931 // 25624 GIM_CheckFeatures, GIFBS_HasAVX512_HasVLX, 25625 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID, 25626 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID, 25627 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128XRegClassID, 25628 // (strict_fadd:{ *:[v2f64] } VR128X:{ *:[v2f64] }:$src1, VR128X:{ *:[v2f64] }:$src2) => (VADDPDZ128rr:{ *:[v2f64] } VR128X:{ *:[v2f64] }:$src1, VR128X:{ *:[v2f64] }:$src2) 25629 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VADDPDZ128rr, 25630 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 25631 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 25632 // GIR_Coverage, 5931, 25633 GIR_Done, 25634 // Label 2163: @58270 25635 GIM_Reject, 25636 // Label 2160: @58271 25637 GIM_Reject, 25638 // Label 2139: @58272 25639 GIM_Try, /*On fail goto*//*Label 2164*/ 58361, 25640 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, 25641 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 25642 GIM_Try, /*On fail goto*//*Label 2165*/ 58308, // Rule ID 1866 // 25643 GIM_CheckFeatures, GIFBS_HasAVX_NoVLX, 25644 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 25645 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 25646 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 25647 // (strict_fadd:{ *:[v4f32] } VR128:{ *:[v4f32] }:$src1, VR128:{ *:[v4f32] }:$src2) => (VADDPSrr:{ *:[v4f32] } VR128:{ *:[v4f32] }:$src1, VR128:{ *:[v4f32] }:$src2) 25648 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VADDPSrr, 25649 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 25650 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 25651 // GIR_Coverage, 1866, 25652 GIR_Done, 25653 // Label 2165: @58308 25654 GIM_Try, /*On fail goto*//*Label 2166*/ 58334, // Rule ID 1882 // 25655 GIM_CheckFeatures, GIFBS_UseSSE1, 25656 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 25657 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 25658 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 25659 // (strict_fadd:{ *:[v4f32] } VR128:{ *:[v4f32] }:$src1, VR128:{ *:[v4f32] }:$src2) => (ADDPSrr:{ *:[v4f32] } VR128:{ *:[v4f32] }:$src1, VR128:{ *:[v4f32] }:$src2) 25660 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::ADDPSrr, 25661 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 25662 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 25663 // GIR_Coverage, 1882, 25664 GIR_Done, 25665 // Label 2166: @58334 25666 GIM_Try, /*On fail goto*//*Label 2167*/ 58360, // Rule ID 5907 // 25667 GIM_CheckFeatures, GIFBS_HasAVX512_HasVLX, 25668 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID, 25669 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID, 25670 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128XRegClassID, 25671 // (strict_fadd:{ *:[v4f32] } VR128X:{ *:[v4f32] }:$src1, VR128X:{ *:[v4f32] }:$src2) => (VADDPSZ128rr:{ *:[v4f32] } VR128X:{ *:[v4f32] }:$src1, VR128X:{ *:[v4f32] }:$src2) 25672 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VADDPSZ128rr, 25673 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 25674 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 25675 // GIR_Coverage, 5907, 25676 GIR_Done, 25677 // Label 2167: @58360 25678 GIM_Reject, 25679 // Label 2164: @58361 25680 GIM_Reject, 25681 // Label 2140: @58362 25682 GIM_Try, /*On fail goto*//*Label 2168*/ 58425, 25683 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s64, 25684 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s64, 25685 GIM_Try, /*On fail goto*//*Label 2169*/ 58398, // Rule ID 1878 // 25686 GIM_CheckFeatures, GIFBS_HasAVX_NoVLX, 25687 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID, 25688 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256RegClassID, 25689 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256RegClassID, 25690 // (strict_fadd:{ *:[v4f64] } VR256:{ *:[v4f64] }:$src1, VR256:{ *:[v4f64] }:$src2) => (VADDPDYrr:{ *:[v4f64] } VR256:{ *:[v4f64] }:$src1, VR256:{ *:[v4f64] }:$src2) 25691 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VADDPDYrr, 25692 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 25693 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 25694 // GIR_Coverage, 1878, 25695 GIR_Done, 25696 // Label 2169: @58398 25697 GIM_Try, /*On fail goto*//*Label 2170*/ 58424, // Rule ID 5943 // 25698 GIM_CheckFeatures, GIFBS_HasAVX512_HasVLX, 25699 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID, 25700 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID, 25701 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256XRegClassID, 25702 // (strict_fadd:{ *:[v4f64] } VR256X:{ *:[v4f64] }:$src1, VR256X:{ *:[v4f64] }:$src2) => (VADDPDZ256rr:{ *:[v4f64] } VR256X:{ *:[v4f64] }:$src1, VR256X:{ *:[v4f64] }:$src2) 25703 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VADDPDZ256rr, 25704 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 25705 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 25706 // GIR_Coverage, 5943, 25707 GIR_Done, 25708 // Label 2170: @58424 25709 GIM_Reject, 25710 // Label 2168: @58425 25711 GIM_Reject, 25712 // Label 2141: @58426 25713 GIM_Try, /*On fail goto*//*Label 2171*/ 58460, // Rule ID 5967 // 25714 GIM_CheckFeatures, GIFBS_HasFP16_HasVLX, 25715 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, 25716 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 25717 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID, 25718 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID, 25719 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128XRegClassID, 25720 // (strict_fadd:{ *:[v8f16] } VR128X:{ *:[v8f16] }:$src1, VR128X:{ *:[v8f16] }:$src2) => (VADDPHZ128rr:{ *:[v8f16] } VR128X:{ *:[v8f16] }:$src1, VR128X:{ *:[v8f16] }:$src2) 25721 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VADDPHZ128rr, 25722 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 25723 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 25724 // GIR_Coverage, 5967, 25725 GIR_Done, 25726 // Label 2171: @58460 25727 GIM_Reject, 25728 // Label 2142: @58461 25729 GIM_Try, /*On fail goto*//*Label 2172*/ 58524, 25730 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s32, 25731 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s32, 25732 GIM_Try, /*On fail goto*//*Label 2173*/ 58497, // Rule ID 1874 // 25733 GIM_CheckFeatures, GIFBS_HasAVX_NoVLX, 25734 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID, 25735 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256RegClassID, 25736 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256RegClassID, 25737 // (strict_fadd:{ *:[v8f32] } VR256:{ *:[v8f32] }:$src1, VR256:{ *:[v8f32] }:$src2) => (VADDPSYrr:{ *:[v8f32] } VR256:{ *:[v8f32] }:$src1, VR256:{ *:[v8f32] }:$src2) 25738 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VADDPSYrr, 25739 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 25740 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 25741 // GIR_Coverage, 1874, 25742 GIR_Done, 25743 // Label 2173: @58497 25744 GIM_Try, /*On fail goto*//*Label 2174*/ 58523, // Rule ID 5919 // 25745 GIM_CheckFeatures, GIFBS_HasAVX512_HasVLX, 25746 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID, 25747 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID, 25748 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256XRegClassID, 25749 // (strict_fadd:{ *:[v8f32] } VR256X:{ *:[v8f32] }:$src1, VR256X:{ *:[v8f32] }:$src2) => (VADDPSZ256rr:{ *:[v8f32] } VR256X:{ *:[v8f32] }:$src1, VR256X:{ *:[v8f32] }:$src2) 25750 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VADDPSZ256rr, 25751 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 25752 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 25753 // GIR_Coverage, 5919, 25754 GIR_Done, 25755 // Label 2174: @58523 25756 GIM_Reject, 25757 // Label 2172: @58524 25758 GIM_Reject, 25759 // Label 2143: @58525 25760 GIM_Try, /*On fail goto*//*Label 2175*/ 58559, // Rule ID 5895 // 25761 GIM_CheckFeatures, GIFBS_HasAVX512, 25762 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s64, 25763 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s64, 25764 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 25765 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR512RegClassID, 25766 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR512RegClassID, 25767 // (strict_fadd:{ *:[v8f64] } VR512:{ *:[v8f64] }:$src1, VR512:{ *:[v8f64] }:$src2) => (VADDPDZrr:{ *:[v8f64] } VR512:{ *:[v8f64] }:$src1, VR512:{ *:[v8f64] }:$src2) 25768 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VADDPDZrr, 25769 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 25770 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 25771 // GIR_Coverage, 5895, 25772 GIR_Done, 25773 // Label 2175: @58559 25774 GIM_Reject, 25775 // Label 2144: @58560 25776 GIM_Try, /*On fail goto*//*Label 2176*/ 58594, // Rule ID 5979 // 25777 GIM_CheckFeatures, GIFBS_HasFP16_HasVLX, 25778 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s16, 25779 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s16, 25780 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID, 25781 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID, 25782 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256XRegClassID, 25783 // (strict_fadd:{ *:[v16f16] } VR256X:{ *:[v16f16] }:$src1, VR256X:{ *:[v16f16] }:$src2) => (VADDPHZ256rr:{ *:[v16f16] } VR256X:{ *:[v16f16] }:$src1, VR256X:{ *:[v16f16] }:$src2) 25784 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VADDPHZ256rr, 25785 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 25786 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 25787 // GIR_Coverage, 5979, 25788 GIR_Done, 25789 // Label 2176: @58594 25790 GIM_Reject, 25791 // Label 2145: @58595 25792 GIM_Try, /*On fail goto*//*Label 2177*/ 58629, // Rule ID 5883 // 25793 GIM_CheckFeatures, GIFBS_HasAVX512, 25794 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s32, 25795 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s32, 25796 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 25797 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR512RegClassID, 25798 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR512RegClassID, 25799 // (strict_fadd:{ *:[v16f32] } VR512:{ *:[v16f32] }:$src1, VR512:{ *:[v16f32] }:$src2) => (VADDPSZrr:{ *:[v16f32] } VR512:{ *:[v16f32] }:$src1, VR512:{ *:[v16f32] }:$src2) 25800 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VADDPSZrr, 25801 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 25802 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 25803 // GIR_Coverage, 5883, 25804 GIR_Done, 25805 // Label 2177: @58629 25806 GIM_Reject, 25807 // Label 2146: @58630 25808 GIM_Try, /*On fail goto*//*Label 2178*/ 58664, // Rule ID 5955 // 25809 GIM_CheckFeatures, GIFBS_HasFP16, 25810 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v32s16, 25811 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v32s16, 25812 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 25813 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR512RegClassID, 25814 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR512RegClassID, 25815 // (strict_fadd:{ *:[v32f16] } VR512:{ *:[v32f16] }:$src1, VR512:{ *:[v32f16] }:$src2) => (VADDPHZrr:{ *:[v32f16] } VR512:{ *:[v32f16] }:$src1, VR512:{ *:[v32f16] }:$src2) 25816 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VADDPHZrr, 25817 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 25818 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 25819 // GIR_Coverage, 5955, 25820 GIR_Done, 25821 // Label 2178: @58664 25822 GIM_Reject, 25823 // Label 2147: @58665 25824 GIM_Reject, 25825 // Label 56: @58666 25826 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/2, 23, /*)*//*default:*//*Label 2192*/ 59487, 25827 /*GILLT_s16*//*Label 2179*/ 58693, 25828 /*GILLT_s32*//*Label 2180*/ 58728, 25829 /*GILLT_s64*//*Label 2181*/ 58847, 25830 /*GILLT_s80*//*Label 2182*/ 58966, 0, 0, 25831 /*GILLT_v2s64*//*Label 2183*/ 59004, 0, 25832 /*GILLT_v4s32*//*Label 2184*/ 59094, 25833 /*GILLT_v4s64*//*Label 2185*/ 59184, 0, 25834 /*GILLT_v8s16*//*Label 2186*/ 59248, 25835 /*GILLT_v8s32*//*Label 2187*/ 59283, 25836 /*GILLT_v8s64*//*Label 2188*/ 59347, 0, 0, 25837 /*GILLT_v16s16*//*Label 2189*/ 59382, 25838 /*GILLT_v16s32*//*Label 2190*/ 59417, 0, 0, 25839 /*GILLT_v32s16*//*Label 2191*/ 59452, 25840 // Label 2179: @58693 25841 GIM_Try, /*On fail goto*//*Label 2193*/ 58727, // Rule ID 5705 // 25842 GIM_CheckFeatures, GIFBS_HasFP16, 25843 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16, 25844 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16, 25845 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::FR16XRegClassID, 25846 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::FR16XRegClassID, 25847 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::FR16XRegClassID, 25848 // (strict_fsub:{ *:[f16] } FR16X:{ *:[f16] }:$src1, FR16X:{ *:[f16] }:$src2) => (VSUBSHZrr:{ *:[f16] } FR16X:{ *:[f16] }:$src1, FR16X:{ *:[f16] }:$src2) 25849 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VSUBSHZrr, 25850 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 25851 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 25852 // GIR_Coverage, 5705, 25853 GIR_Done, 25854 // Label 2193: @58727 25855 GIM_Reject, 25856 // Label 2180: @58728 25857 GIM_Try, /*On fail goto*//*Label 2194*/ 58846, 25858 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 25859 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 25860 GIM_Try, /*On fail goto*//*Label 2195*/ 58767, // Rule ID 626 // 25861 GIM_CheckFeatures, GIFBS_FPStackf32, 25862 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::RFP32RegClassID, 25863 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::RFP32RegClassID, 25864 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::RFP32RegClassID, 25865 // (strict_fsub:{ *:[f32] } RFP32:{ *:[f32] }:$src1, RFP32:{ *:[f32] }:$src2) => (SUB_Fp32:{ *:[f32] }:{ *:[i16] } RFP32:{ *:[f32] }:$src1, RFP32:{ *:[f32] }:$src2) 25866 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::SUB_Fp32, 25867 GIR_AddImplicitDef, /*InsnID*/0, X86::FPSW, 25868 GIR_AddImplicitUse, /*InsnID*/0, X86::FPCW, 25869 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 25870 // GIR_Coverage, 626, 25871 GIR_Done, 25872 // Label 2195: @58767 25873 GIM_Try, /*On fail goto*//*Label 2196*/ 58793, // Rule ID 1970 // 25874 GIM_CheckFeatures, GIFBS_UseAVX, 25875 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::FR32RegClassID, 25876 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::FR32RegClassID, 25877 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::FR32RegClassID, 25878 // (strict_fsub:{ *:[f32] } FR32:{ *:[f32] }:$src1, FR32:{ *:[f32] }:$src2) => (VSUBSSrr:{ *:[f32] } FR32:{ *:[f32] }:$src1, FR32:{ *:[f32] }:$src2) 25879 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VSUBSSrr, 25880 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 25881 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 25882 // GIR_Coverage, 1970, 25883 GIR_Done, 25884 // Label 2196: @58793 25885 GIM_Try, /*On fail goto*//*Label 2197*/ 58819, // Rule ID 1978 // 25886 GIM_CheckFeatures, GIFBS_UseSSE1, 25887 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::FR32RegClassID, 25888 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::FR32RegClassID, 25889 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::FR32RegClassID, 25890 // (strict_fsub:{ *:[f32] } FR32:{ *:[f32] }:$src1, FR32:{ *:[f32] }:$src2) => (SUBSSrr:{ *:[f32] } FR32:{ *:[f32] }:$src1, FR32:{ *:[f32] }:$src2) 25891 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::SUBSSrr, 25892 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 25893 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 25894 // GIR_Coverage, 1978, 25895 GIR_Done, 25896 // Label 2197: @58819 25897 GIM_Try, /*On fail goto*//*Label 2198*/ 58845, // Rule ID 5667 // 25898 GIM_CheckFeatures, GIFBS_HasAVX512, 25899 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::FR32XRegClassID, 25900 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::FR32XRegClassID, 25901 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::FR32XRegClassID, 25902 // (strict_fsub:{ *:[f32] } FR32X:{ *:[f32] }:$src1, FR32X:{ *:[f32] }:$src2) => (VSUBSSZrr:{ *:[f32] } FR32X:{ *:[f32] }:$src1, FR32X:{ *:[f32] }:$src2) 25903 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VSUBSSZrr, 25904 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 25905 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 25906 // GIR_Coverage, 5667, 25907 GIR_Done, 25908 // Label 2198: @58845 25909 GIM_Reject, 25910 // Label 2194: @58846 25911 GIM_Reject, 25912 // Label 2181: @58847 25913 GIM_Try, /*On fail goto*//*Label 2199*/ 58965, 25914 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 25915 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 25916 GIM_Try, /*On fail goto*//*Label 2200*/ 58886, // Rule ID 628 // 25917 GIM_CheckFeatures, GIFBS_FPStackf64, 25918 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::RFP64RegClassID, 25919 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::RFP64RegClassID, 25920 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::RFP64RegClassID, 25921 // (strict_fsub:{ *:[f64] } RFP64:{ *:[f64] }:$src1, RFP64:{ *:[f64] }:$src2) => (SUB_Fp64:{ *:[f64] }:{ *:[i16] } RFP64:{ *:[f64] }:$src1, RFP64:{ *:[f64] }:$src2) 25922 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::SUB_Fp64, 25923 GIR_AddImplicitDef, /*InsnID*/0, X86::FPSW, 25924 GIR_AddImplicitUse, /*InsnID*/0, X86::FPCW, 25925 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 25926 // GIR_Coverage, 628, 25927 GIR_Done, 25928 // Label 2200: @58886 25929 GIM_Try, /*On fail goto*//*Label 2201*/ 58912, // Rule ID 1974 // 25930 GIM_CheckFeatures, GIFBS_UseAVX, 25931 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::FR64RegClassID, 25932 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::FR64RegClassID, 25933 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::FR64RegClassID, 25934 // (strict_fsub:{ *:[f64] } FR64:{ *:[f64] }:$src1, FR64:{ *:[f64] }:$src2) => (VSUBSDrr:{ *:[f64] } FR64:{ *:[f64] }:$src1, FR64:{ *:[f64] }:$src2) 25935 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VSUBSDrr, 25936 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 25937 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 25938 // GIR_Coverage, 1974, 25939 GIR_Done, 25940 // Label 2201: @58912 25941 GIM_Try, /*On fail goto*//*Label 2202*/ 58938, // Rule ID 1982 // 25942 GIM_CheckFeatures, GIFBS_UseSSE2, 25943 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::FR64RegClassID, 25944 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::FR64RegClassID, 25945 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::FR64RegClassID, 25946 // (strict_fsub:{ *:[f64] } FR64:{ *:[f64] }:$src1, FR64:{ *:[f64] }:$src2) => (SUBSDrr:{ *:[f64] } FR64:{ *:[f64] }:$src1, FR64:{ *:[f64] }:$src2) 25947 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::SUBSDrr, 25948 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 25949 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 25950 // GIR_Coverage, 1982, 25951 GIR_Done, 25952 // Label 2202: @58938 25953 GIM_Try, /*On fail goto*//*Label 2203*/ 58964, // Rule ID 5686 // 25954 GIM_CheckFeatures, GIFBS_HasAVX512, 25955 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::FR64XRegClassID, 25956 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::FR64XRegClassID, 25957 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::FR64XRegClassID, 25958 // (strict_fsub:{ *:[f64] } FR64X:{ *:[f64] }:$src1, FR64X:{ *:[f64] }:$src2) => (VSUBSDZrr:{ *:[f64] } FR64X:{ *:[f64] }:$src1, FR64X:{ *:[f64] }:$src2) 25959 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VSUBSDZrr, 25960 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 25961 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 25962 // GIR_Coverage, 5686, 25963 GIR_Done, 25964 // Label 2203: @58964 25965 GIM_Reject, 25966 // Label 2199: @58965 25967 GIM_Reject, 25968 // Label 2182: @58966 25969 GIM_Try, /*On fail goto*//*Label 2204*/ 59003, // Rule ID 630 // 25970 GIM_CheckFeatures, GIFBS_HasX87, 25971 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s80, 25972 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s80, 25973 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::RFP80RegClassID, 25974 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::RFP80RegClassID, 25975 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::RFP80RegClassID, 25976 // (strict_fsub:{ *:[f80] } RFP80:{ *:[f80] }:$src1, RFP80:{ *:[f80] }:$src2) => (SUB_Fp80:{ *:[f80] }:{ *:[i16] } RFP80:{ *:[f80] }:$src1, RFP80:{ *:[f80] }:$src2) 25977 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::SUB_Fp80, 25978 GIR_AddImplicitDef, /*InsnID*/0, X86::FPSW, 25979 GIR_AddImplicitUse, /*InsnID*/0, X86::FPCW, 25980 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 25981 // GIR_Coverage, 630, 25982 GIR_Done, 25983 // Label 2204: @59003 25984 GIM_Reject, 25985 // Label 2183: @59004 25986 GIM_Try, /*On fail goto*//*Label 2205*/ 59093, 25987 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, 25988 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 25989 GIM_Try, /*On fail goto*//*Label 2206*/ 59040, // Rule ID 1950 // 25990 GIM_CheckFeatures, GIFBS_HasAVX_NoVLX, 25991 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 25992 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 25993 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 25994 // (strict_fsub:{ *:[v2f64] } VR128:{ *:[v2f64] }:$src1, VR128:{ *:[v2f64] }:$src2) => (VSUBPDrr:{ *:[v2f64] } VR128:{ *:[v2f64] }:$src1, VR128:{ *:[v2f64] }:$src2) 25995 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VSUBPDrr, 25996 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 25997 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 25998 // GIR_Coverage, 1950, 25999 GIR_Done, 26000 // Label 2206: @59040 26001 GIM_Try, /*On fail goto*//*Label 2207*/ 59066, // Rule ID 1966 // 26002 GIM_CheckFeatures, GIFBS_UseSSE2, 26003 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 26004 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 26005 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 26006 // (strict_fsub:{ *:[v2f64] } VR128:{ *:[v2f64] }:$src1, VR128:{ *:[v2f64] }:$src2) => (SUBPDrr:{ *:[v2f64] } VR128:{ *:[v2f64] }:$src1, VR128:{ *:[v2f64] }:$src2) 26007 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::SUBPDrr, 26008 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 26009 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 26010 // GIR_Coverage, 1966, 26011 GIR_Done, 26012 // Label 2207: @59066 26013 GIM_Try, /*On fail goto*//*Label 2208*/ 59092, // Rule ID 6165 // 26014 GIM_CheckFeatures, GIFBS_HasAVX512_HasVLX, 26015 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID, 26016 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID, 26017 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128XRegClassID, 26018 // (strict_fsub:{ *:[v2f64] } VR128X:{ *:[v2f64] }:$src1, VR128X:{ *:[v2f64] }:$src2) => (VSUBPDZ128rr:{ *:[v2f64] } VR128X:{ *:[v2f64] }:$src1, VR128X:{ *:[v2f64] }:$src2) 26019 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VSUBPDZ128rr, 26020 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 26021 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 26022 // GIR_Coverage, 6165, 26023 GIR_Done, 26024 // Label 2208: @59092 26025 GIM_Reject, 26026 // Label 2205: @59093 26027 GIM_Reject, 26028 // Label 2184: @59094 26029 GIM_Try, /*On fail goto*//*Label 2209*/ 59183, 26030 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, 26031 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 26032 GIM_Try, /*On fail goto*//*Label 2210*/ 59130, // Rule ID 1946 // 26033 GIM_CheckFeatures, GIFBS_HasAVX_NoVLX, 26034 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 26035 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 26036 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 26037 // (strict_fsub:{ *:[v4f32] } VR128:{ *:[v4f32] }:$src1, VR128:{ *:[v4f32] }:$src2) => (VSUBPSrr:{ *:[v4f32] } VR128:{ *:[v4f32] }:$src1, VR128:{ *:[v4f32] }:$src2) 26038 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VSUBPSrr, 26039 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 26040 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 26041 // GIR_Coverage, 1946, 26042 GIR_Done, 26043 // Label 2210: @59130 26044 GIM_Try, /*On fail goto*//*Label 2211*/ 59156, // Rule ID 1962 // 26045 GIM_CheckFeatures, GIFBS_UseSSE1, 26046 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 26047 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 26048 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 26049 // (strict_fsub:{ *:[v4f32] } VR128:{ *:[v4f32] }:$src1, VR128:{ *:[v4f32] }:$src2) => (SUBPSrr:{ *:[v4f32] } VR128:{ *:[v4f32] }:$src1, VR128:{ *:[v4f32] }:$src2) 26050 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::SUBPSrr, 26051 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 26052 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 26053 // GIR_Coverage, 1962, 26054 GIR_Done, 26055 // Label 2211: @59156 26056 GIM_Try, /*On fail goto*//*Label 2212*/ 59182, // Rule ID 6141 // 26057 GIM_CheckFeatures, GIFBS_HasAVX512_HasVLX, 26058 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID, 26059 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID, 26060 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128XRegClassID, 26061 // (strict_fsub:{ *:[v4f32] } VR128X:{ *:[v4f32] }:$src1, VR128X:{ *:[v4f32] }:$src2) => (VSUBPSZ128rr:{ *:[v4f32] } VR128X:{ *:[v4f32] }:$src1, VR128X:{ *:[v4f32] }:$src2) 26062 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VSUBPSZ128rr, 26063 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 26064 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 26065 // GIR_Coverage, 6141, 26066 GIR_Done, 26067 // Label 2212: @59182 26068 GIM_Reject, 26069 // Label 2209: @59183 26070 GIM_Reject, 26071 // Label 2185: @59184 26072 GIM_Try, /*On fail goto*//*Label 2213*/ 59247, 26073 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s64, 26074 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s64, 26075 GIM_Try, /*On fail goto*//*Label 2214*/ 59220, // Rule ID 1958 // 26076 GIM_CheckFeatures, GIFBS_HasAVX_NoVLX, 26077 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID, 26078 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256RegClassID, 26079 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256RegClassID, 26080 // (strict_fsub:{ *:[v4f64] } VR256:{ *:[v4f64] }:$src1, VR256:{ *:[v4f64] }:$src2) => (VSUBPDYrr:{ *:[v4f64] } VR256:{ *:[v4f64] }:$src1, VR256:{ *:[v4f64] }:$src2) 26081 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VSUBPDYrr, 26082 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 26083 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 26084 // GIR_Coverage, 1958, 26085 GIR_Done, 26086 // Label 2214: @59220 26087 GIM_Try, /*On fail goto*//*Label 2215*/ 59246, // Rule ID 6177 // 26088 GIM_CheckFeatures, GIFBS_HasAVX512_HasVLX, 26089 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID, 26090 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID, 26091 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256XRegClassID, 26092 // (strict_fsub:{ *:[v4f64] } VR256X:{ *:[v4f64] }:$src1, VR256X:{ *:[v4f64] }:$src2) => (VSUBPDZ256rr:{ *:[v4f64] } VR256X:{ *:[v4f64] }:$src1, VR256X:{ *:[v4f64] }:$src2) 26093 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VSUBPDZ256rr, 26094 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 26095 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 26096 // GIR_Coverage, 6177, 26097 GIR_Done, 26098 // Label 2215: @59246 26099 GIM_Reject, 26100 // Label 2213: @59247 26101 GIM_Reject, 26102 // Label 2186: @59248 26103 GIM_Try, /*On fail goto*//*Label 2216*/ 59282, // Rule ID 6201 // 26104 GIM_CheckFeatures, GIFBS_HasFP16_HasVLX, 26105 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, 26106 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 26107 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID, 26108 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID, 26109 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128XRegClassID, 26110 // (strict_fsub:{ *:[v8f16] } VR128X:{ *:[v8f16] }:$src1, VR128X:{ *:[v8f16] }:$src2) => (VSUBPHZ128rr:{ *:[v8f16] } VR128X:{ *:[v8f16] }:$src1, VR128X:{ *:[v8f16] }:$src2) 26111 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VSUBPHZ128rr, 26112 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 26113 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 26114 // GIR_Coverage, 6201, 26115 GIR_Done, 26116 // Label 2216: @59282 26117 GIM_Reject, 26118 // Label 2187: @59283 26119 GIM_Try, /*On fail goto*//*Label 2217*/ 59346, 26120 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s32, 26121 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s32, 26122 GIM_Try, /*On fail goto*//*Label 2218*/ 59319, // Rule ID 1954 // 26123 GIM_CheckFeatures, GIFBS_HasAVX_NoVLX, 26124 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID, 26125 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256RegClassID, 26126 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256RegClassID, 26127 // (strict_fsub:{ *:[v8f32] } VR256:{ *:[v8f32] }:$src1, VR256:{ *:[v8f32] }:$src2) => (VSUBPSYrr:{ *:[v8f32] } VR256:{ *:[v8f32] }:$src1, VR256:{ *:[v8f32] }:$src2) 26128 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VSUBPSYrr, 26129 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 26130 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 26131 // GIR_Coverage, 1954, 26132 GIR_Done, 26133 // Label 2218: @59319 26134 GIM_Try, /*On fail goto*//*Label 2219*/ 59345, // Rule ID 6153 // 26135 GIM_CheckFeatures, GIFBS_HasAVX512_HasVLX, 26136 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID, 26137 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID, 26138 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256XRegClassID, 26139 // (strict_fsub:{ *:[v8f32] } VR256X:{ *:[v8f32] }:$src1, VR256X:{ *:[v8f32] }:$src2) => (VSUBPSZ256rr:{ *:[v8f32] } VR256X:{ *:[v8f32] }:$src1, VR256X:{ *:[v8f32] }:$src2) 26140 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VSUBPSZ256rr, 26141 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 26142 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 26143 // GIR_Coverage, 6153, 26144 GIR_Done, 26145 // Label 2219: @59345 26146 GIM_Reject, 26147 // Label 2217: @59346 26148 GIM_Reject, 26149 // Label 2188: @59347 26150 GIM_Try, /*On fail goto*//*Label 2220*/ 59381, // Rule ID 6129 // 26151 GIM_CheckFeatures, GIFBS_HasAVX512, 26152 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s64, 26153 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s64, 26154 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 26155 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR512RegClassID, 26156 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR512RegClassID, 26157 // (strict_fsub:{ *:[v8f64] } VR512:{ *:[v8f64] }:$src1, VR512:{ *:[v8f64] }:$src2) => (VSUBPDZrr:{ *:[v8f64] } VR512:{ *:[v8f64] }:$src1, VR512:{ *:[v8f64] }:$src2) 26158 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VSUBPDZrr, 26159 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 26160 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 26161 // GIR_Coverage, 6129, 26162 GIR_Done, 26163 // Label 2220: @59381 26164 GIM_Reject, 26165 // Label 2189: @59382 26166 GIM_Try, /*On fail goto*//*Label 2221*/ 59416, // Rule ID 6213 // 26167 GIM_CheckFeatures, GIFBS_HasFP16_HasVLX, 26168 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s16, 26169 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s16, 26170 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID, 26171 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID, 26172 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256XRegClassID, 26173 // (strict_fsub:{ *:[v16f16] } VR256X:{ *:[v16f16] }:$src1, VR256X:{ *:[v16f16] }:$src2) => (VSUBPHZ256rr:{ *:[v16f16] } VR256X:{ *:[v16f16] }:$src1, VR256X:{ *:[v16f16] }:$src2) 26174 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VSUBPHZ256rr, 26175 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 26176 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 26177 // GIR_Coverage, 6213, 26178 GIR_Done, 26179 // Label 2221: @59416 26180 GIM_Reject, 26181 // Label 2190: @59417 26182 GIM_Try, /*On fail goto*//*Label 2222*/ 59451, // Rule ID 6117 // 26183 GIM_CheckFeatures, GIFBS_HasAVX512, 26184 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s32, 26185 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s32, 26186 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 26187 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR512RegClassID, 26188 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR512RegClassID, 26189 // (strict_fsub:{ *:[v16f32] } VR512:{ *:[v16f32] }:$src1, VR512:{ *:[v16f32] }:$src2) => (VSUBPSZrr:{ *:[v16f32] } VR512:{ *:[v16f32] }:$src1, VR512:{ *:[v16f32] }:$src2) 26190 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VSUBPSZrr, 26191 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 26192 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 26193 // GIR_Coverage, 6117, 26194 GIR_Done, 26195 // Label 2222: @59451 26196 GIM_Reject, 26197 // Label 2191: @59452 26198 GIM_Try, /*On fail goto*//*Label 2223*/ 59486, // Rule ID 6189 // 26199 GIM_CheckFeatures, GIFBS_HasFP16, 26200 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v32s16, 26201 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v32s16, 26202 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 26203 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR512RegClassID, 26204 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR512RegClassID, 26205 // (strict_fsub:{ *:[v32f16] } VR512:{ *:[v32f16] }:$src1, VR512:{ *:[v32f16] }:$src2) => (VSUBPHZrr:{ *:[v32f16] } VR512:{ *:[v32f16] }:$src1, VR512:{ *:[v32f16] }:$src2) 26206 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VSUBPHZrr, 26207 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 26208 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 26209 // GIR_Coverage, 6189, 26210 GIR_Done, 26211 // Label 2223: @59486 26212 GIM_Reject, 26213 // Label 2192: @59487 26214 GIM_Reject, 26215 // Label 57: @59488 26216 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/2, 23, /*)*//*default:*//*Label 2237*/ 60309, 26217 /*GILLT_s16*//*Label 2224*/ 59515, 26218 /*GILLT_s32*//*Label 2225*/ 59550, 26219 /*GILLT_s64*//*Label 2226*/ 59669, 26220 /*GILLT_s80*//*Label 2227*/ 59788, 0, 0, 26221 /*GILLT_v2s64*//*Label 2228*/ 59826, 0, 26222 /*GILLT_v4s32*//*Label 2229*/ 59916, 26223 /*GILLT_v4s64*//*Label 2230*/ 60006, 0, 26224 /*GILLT_v8s16*//*Label 2231*/ 60070, 26225 /*GILLT_v8s32*//*Label 2232*/ 60105, 26226 /*GILLT_v8s64*//*Label 2233*/ 60169, 0, 0, 26227 /*GILLT_v16s16*//*Label 2234*/ 60204, 26228 /*GILLT_v16s32*//*Label 2235*/ 60239, 0, 0, 26229 /*GILLT_v32s16*//*Label 2236*/ 60274, 26230 // Label 2224: @59515 26231 GIM_Try, /*On fail goto*//*Label 2238*/ 59549, // Rule ID 5648 // 26232 GIM_CheckFeatures, GIFBS_HasFP16, 26233 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16, 26234 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16, 26235 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::FR16XRegClassID, 26236 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::FR16XRegClassID, 26237 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::FR16XRegClassID, 26238 // (strict_fmul:{ *:[f16] } FR16X:{ *:[f16] }:$src1, FR16X:{ *:[f16] }:$src2) => (VMULSHZrr:{ *:[f16] } FR16X:{ *:[f16] }:$src1, FR16X:{ *:[f16] }:$src2) 26239 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VMULSHZrr, 26240 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 26241 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 26242 // GIR_Coverage, 5648, 26243 GIR_Done, 26244 // Label 2238: @59549 26245 GIM_Reject, 26246 // Label 2225: @59550 26247 GIM_Try, /*On fail goto*//*Label 2239*/ 59668, 26248 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 26249 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 26250 GIM_Try, /*On fail goto*//*Label 2240*/ 59589, // Rule ID 632 // 26251 GIM_CheckFeatures, GIFBS_FPStackf32, 26252 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::RFP32RegClassID, 26253 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::RFP32RegClassID, 26254 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::RFP32RegClassID, 26255 // (strict_fmul:{ *:[f32] } RFP32:{ *:[f32] }:$src1, RFP32:{ *:[f32] }:$src2) => (MUL_Fp32:{ *:[f32] }:{ *:[i16] } RFP32:{ *:[f32] }:$src1, RFP32:{ *:[f32] }:$src2) 26256 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::MUL_Fp32, 26257 GIR_AddImplicitDef, /*InsnID*/0, X86::FPSW, 26258 GIR_AddImplicitUse, /*InsnID*/0, X86::FPCW, 26259 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 26260 // GIR_Coverage, 632, 26261 GIR_Done, 26262 // Label 2240: @59589 26263 GIM_Try, /*On fail goto*//*Label 2241*/ 59615, // Rule ID 1930 // 26264 GIM_CheckFeatures, GIFBS_UseAVX, 26265 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::FR32RegClassID, 26266 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::FR32RegClassID, 26267 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::FR32RegClassID, 26268 // (strict_fmul:{ *:[f32] } FR32:{ *:[f32] }:$src1, FR32:{ *:[f32] }:$src2) => (VMULSSrr:{ *:[f32] } FR32:{ *:[f32] }:$src1, FR32:{ *:[f32] }:$src2) 26269 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VMULSSrr, 26270 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 26271 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 26272 // GIR_Coverage, 1930, 26273 GIR_Done, 26274 // Label 2241: @59615 26275 GIM_Try, /*On fail goto*//*Label 2242*/ 59641, // Rule ID 1938 // 26276 GIM_CheckFeatures, GIFBS_UseSSE1, 26277 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::FR32RegClassID, 26278 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::FR32RegClassID, 26279 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::FR32RegClassID, 26280 // (strict_fmul:{ *:[f32] } FR32:{ *:[f32] }:$src1, FR32:{ *:[f32] }:$src2) => (MULSSrr:{ *:[f32] } FR32:{ *:[f32] }:$src1, FR32:{ *:[f32] }:$src2) 26281 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::MULSSrr, 26282 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 26283 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 26284 // GIR_Coverage, 1938, 26285 GIR_Done, 26286 // Label 2242: @59641 26287 GIM_Try, /*On fail goto*//*Label 2243*/ 59667, // Rule ID 5610 // 26288 GIM_CheckFeatures, GIFBS_HasAVX512, 26289 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::FR32XRegClassID, 26290 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::FR32XRegClassID, 26291 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::FR32XRegClassID, 26292 // (strict_fmul:{ *:[f32] } FR32X:{ *:[f32] }:$src1, FR32X:{ *:[f32] }:$src2) => (VMULSSZrr:{ *:[f32] } FR32X:{ *:[f32] }:$src1, FR32X:{ *:[f32] }:$src2) 26293 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VMULSSZrr, 26294 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 26295 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 26296 // GIR_Coverage, 5610, 26297 GIR_Done, 26298 // Label 2243: @59667 26299 GIM_Reject, 26300 // Label 2239: @59668 26301 GIM_Reject, 26302 // Label 2226: @59669 26303 GIM_Try, /*On fail goto*//*Label 2244*/ 59787, 26304 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 26305 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 26306 GIM_Try, /*On fail goto*//*Label 2245*/ 59708, // Rule ID 634 // 26307 GIM_CheckFeatures, GIFBS_FPStackf64, 26308 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::RFP64RegClassID, 26309 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::RFP64RegClassID, 26310 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::RFP64RegClassID, 26311 // (strict_fmul:{ *:[f64] } RFP64:{ *:[f64] }:$src1, RFP64:{ *:[f64] }:$src2) => (MUL_Fp64:{ *:[f64] }:{ *:[i16] } RFP64:{ *:[f64] }:$src1, RFP64:{ *:[f64] }:$src2) 26312 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::MUL_Fp64, 26313 GIR_AddImplicitDef, /*InsnID*/0, X86::FPSW, 26314 GIR_AddImplicitUse, /*InsnID*/0, X86::FPCW, 26315 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 26316 // GIR_Coverage, 634, 26317 GIR_Done, 26318 // Label 2245: @59708 26319 GIM_Try, /*On fail goto*//*Label 2246*/ 59734, // Rule ID 1934 // 26320 GIM_CheckFeatures, GIFBS_UseAVX, 26321 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::FR64RegClassID, 26322 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::FR64RegClassID, 26323 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::FR64RegClassID, 26324 // (strict_fmul:{ *:[f64] } FR64:{ *:[f64] }:$src1, FR64:{ *:[f64] }:$src2) => (VMULSDrr:{ *:[f64] } FR64:{ *:[f64] }:$src1, FR64:{ *:[f64] }:$src2) 26325 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VMULSDrr, 26326 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 26327 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 26328 // GIR_Coverage, 1934, 26329 GIR_Done, 26330 // Label 2246: @59734 26331 GIM_Try, /*On fail goto*//*Label 2247*/ 59760, // Rule ID 1942 // 26332 GIM_CheckFeatures, GIFBS_UseSSE2, 26333 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::FR64RegClassID, 26334 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::FR64RegClassID, 26335 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::FR64RegClassID, 26336 // (strict_fmul:{ *:[f64] } FR64:{ *:[f64] }:$src1, FR64:{ *:[f64] }:$src2) => (MULSDrr:{ *:[f64] } FR64:{ *:[f64] }:$src1, FR64:{ *:[f64] }:$src2) 26337 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::MULSDrr, 26338 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 26339 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 26340 // GIR_Coverage, 1942, 26341 GIR_Done, 26342 // Label 2247: @59760 26343 GIM_Try, /*On fail goto*//*Label 2248*/ 59786, // Rule ID 5629 // 26344 GIM_CheckFeatures, GIFBS_HasAVX512, 26345 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::FR64XRegClassID, 26346 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::FR64XRegClassID, 26347 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::FR64XRegClassID, 26348 // (strict_fmul:{ *:[f64] } FR64X:{ *:[f64] }:$src1, FR64X:{ *:[f64] }:$src2) => (VMULSDZrr:{ *:[f64] } FR64X:{ *:[f64] }:$src1, FR64X:{ *:[f64] }:$src2) 26349 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VMULSDZrr, 26350 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 26351 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 26352 // GIR_Coverage, 5629, 26353 GIR_Done, 26354 // Label 2248: @59786 26355 GIM_Reject, 26356 // Label 2244: @59787 26357 GIM_Reject, 26358 // Label 2227: @59788 26359 GIM_Try, /*On fail goto*//*Label 2249*/ 59825, // Rule ID 636 // 26360 GIM_CheckFeatures, GIFBS_HasX87, 26361 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s80, 26362 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s80, 26363 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::RFP80RegClassID, 26364 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::RFP80RegClassID, 26365 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::RFP80RegClassID, 26366 // (strict_fmul:{ *:[f80] } RFP80:{ *:[f80] }:$src1, RFP80:{ *:[f80] }:$src2) => (MUL_Fp80:{ *:[f80] }:{ *:[i16] } RFP80:{ *:[f80] }:$src1, RFP80:{ *:[f80] }:$src2) 26367 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::MUL_Fp80, 26368 GIR_AddImplicitDef, /*InsnID*/0, X86::FPSW, 26369 GIR_AddImplicitUse, /*InsnID*/0, X86::FPCW, 26370 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 26371 // GIR_Coverage, 636, 26372 GIR_Done, 26373 // Label 2249: @59825 26374 GIM_Reject, 26375 // Label 2228: @59826 26376 GIM_Try, /*On fail goto*//*Label 2250*/ 59915, 26377 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, 26378 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 26379 GIM_Try, /*On fail goto*//*Label 2251*/ 59862, // Rule ID 1910 // 26380 GIM_CheckFeatures, GIFBS_HasAVX_NoVLX, 26381 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 26382 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 26383 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 26384 // (strict_fmul:{ *:[v2f64] } VR128:{ *:[v2f64] }:$src1, VR128:{ *:[v2f64] }:$src2) => (VMULPDrr:{ *:[v2f64] } VR128:{ *:[v2f64] }:$src1, VR128:{ *:[v2f64] }:$src2) 26385 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VMULPDrr, 26386 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 26387 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 26388 // GIR_Coverage, 1910, 26389 GIR_Done, 26390 // Label 2251: @59862 26391 GIM_Try, /*On fail goto*//*Label 2252*/ 59888, // Rule ID 1926 // 26392 GIM_CheckFeatures, GIFBS_UseSSE2, 26393 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 26394 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 26395 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 26396 // (strict_fmul:{ *:[v2f64] } VR128:{ *:[v2f64] }:$src1, VR128:{ *:[v2f64] }:$src2) => (MULPDrr:{ *:[v2f64] } VR128:{ *:[v2f64] }:$src1, VR128:{ *:[v2f64] }:$src2) 26397 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::MULPDrr, 26398 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 26399 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 26400 // GIR_Coverage, 1926, 26401 GIR_Done, 26402 // Label 2252: @59888 26403 GIM_Try, /*On fail goto*//*Label 2253*/ 59914, // Rule ID 6048 // 26404 GIM_CheckFeatures, GIFBS_HasAVX512_HasVLX, 26405 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID, 26406 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID, 26407 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128XRegClassID, 26408 // (strict_fmul:{ *:[v2f64] } VR128X:{ *:[v2f64] }:$src1, VR128X:{ *:[v2f64] }:$src2) => (VMULPDZ128rr:{ *:[v2f64] } VR128X:{ *:[v2f64] }:$src1, VR128X:{ *:[v2f64] }:$src2) 26409 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VMULPDZ128rr, 26410 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 26411 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 26412 // GIR_Coverage, 6048, 26413 GIR_Done, 26414 // Label 2253: @59914 26415 GIM_Reject, 26416 // Label 2250: @59915 26417 GIM_Reject, 26418 // Label 2229: @59916 26419 GIM_Try, /*On fail goto*//*Label 2254*/ 60005, 26420 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, 26421 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 26422 GIM_Try, /*On fail goto*//*Label 2255*/ 59952, // Rule ID 1906 // 26423 GIM_CheckFeatures, GIFBS_HasAVX_NoVLX, 26424 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 26425 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 26426 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 26427 // (strict_fmul:{ *:[v4f32] } VR128:{ *:[v4f32] }:$src1, VR128:{ *:[v4f32] }:$src2) => (VMULPSrr:{ *:[v4f32] } VR128:{ *:[v4f32] }:$src1, VR128:{ *:[v4f32] }:$src2) 26428 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VMULPSrr, 26429 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 26430 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 26431 // GIR_Coverage, 1906, 26432 GIR_Done, 26433 // Label 2255: @59952 26434 GIM_Try, /*On fail goto*//*Label 2256*/ 59978, // Rule ID 1922 // 26435 GIM_CheckFeatures, GIFBS_UseSSE1, 26436 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 26437 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 26438 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 26439 // (strict_fmul:{ *:[v4f32] } VR128:{ *:[v4f32] }:$src1, VR128:{ *:[v4f32] }:$src2) => (MULPSrr:{ *:[v4f32] } VR128:{ *:[v4f32] }:$src1, VR128:{ *:[v4f32] }:$src2) 26440 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::MULPSrr, 26441 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 26442 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 26443 // GIR_Coverage, 1922, 26444 GIR_Done, 26445 // Label 2256: @59978 26446 GIM_Try, /*On fail goto*//*Label 2257*/ 60004, // Rule ID 6024 // 26447 GIM_CheckFeatures, GIFBS_HasAVX512_HasVLX, 26448 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID, 26449 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID, 26450 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128XRegClassID, 26451 // (strict_fmul:{ *:[v4f32] } VR128X:{ *:[v4f32] }:$src1, VR128X:{ *:[v4f32] }:$src2) => (VMULPSZ128rr:{ *:[v4f32] } VR128X:{ *:[v4f32] }:$src1, VR128X:{ *:[v4f32] }:$src2) 26452 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VMULPSZ128rr, 26453 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 26454 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 26455 // GIR_Coverage, 6024, 26456 GIR_Done, 26457 // Label 2257: @60004 26458 GIM_Reject, 26459 // Label 2254: @60005 26460 GIM_Reject, 26461 // Label 2230: @60006 26462 GIM_Try, /*On fail goto*//*Label 2258*/ 60069, 26463 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s64, 26464 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s64, 26465 GIM_Try, /*On fail goto*//*Label 2259*/ 60042, // Rule ID 1918 // 26466 GIM_CheckFeatures, GIFBS_HasAVX_NoVLX, 26467 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID, 26468 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256RegClassID, 26469 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256RegClassID, 26470 // (strict_fmul:{ *:[v4f64] } VR256:{ *:[v4f64] }:$src1, VR256:{ *:[v4f64] }:$src2) => (VMULPDYrr:{ *:[v4f64] } VR256:{ *:[v4f64] }:$src1, VR256:{ *:[v4f64] }:$src2) 26471 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VMULPDYrr, 26472 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 26473 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 26474 // GIR_Coverage, 1918, 26475 GIR_Done, 26476 // Label 2259: @60042 26477 GIM_Try, /*On fail goto*//*Label 2260*/ 60068, // Rule ID 6060 // 26478 GIM_CheckFeatures, GIFBS_HasAVX512_HasVLX, 26479 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID, 26480 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID, 26481 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256XRegClassID, 26482 // (strict_fmul:{ *:[v4f64] } VR256X:{ *:[v4f64] }:$src1, VR256X:{ *:[v4f64] }:$src2) => (VMULPDZ256rr:{ *:[v4f64] } VR256X:{ *:[v4f64] }:$src1, VR256X:{ *:[v4f64] }:$src2) 26483 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VMULPDZ256rr, 26484 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 26485 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 26486 // GIR_Coverage, 6060, 26487 GIR_Done, 26488 // Label 2260: @60068 26489 GIM_Reject, 26490 // Label 2258: @60069 26491 GIM_Reject, 26492 // Label 2231: @60070 26493 GIM_Try, /*On fail goto*//*Label 2261*/ 60104, // Rule ID 6084 // 26494 GIM_CheckFeatures, GIFBS_HasFP16_HasVLX, 26495 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, 26496 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 26497 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID, 26498 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID, 26499 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128XRegClassID, 26500 // (strict_fmul:{ *:[v8f16] } VR128X:{ *:[v8f16] }:$src1, VR128X:{ *:[v8f16] }:$src2) => (VMULPHZ128rr:{ *:[v8f16] } VR128X:{ *:[v8f16] }:$src1, VR128X:{ *:[v8f16] }:$src2) 26501 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VMULPHZ128rr, 26502 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 26503 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 26504 // GIR_Coverage, 6084, 26505 GIR_Done, 26506 // Label 2261: @60104 26507 GIM_Reject, 26508 // Label 2232: @60105 26509 GIM_Try, /*On fail goto*//*Label 2262*/ 60168, 26510 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s32, 26511 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s32, 26512 GIM_Try, /*On fail goto*//*Label 2263*/ 60141, // Rule ID 1914 // 26513 GIM_CheckFeatures, GIFBS_HasAVX_NoVLX, 26514 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID, 26515 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256RegClassID, 26516 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256RegClassID, 26517 // (strict_fmul:{ *:[v8f32] } VR256:{ *:[v8f32] }:$src1, VR256:{ *:[v8f32] }:$src2) => (VMULPSYrr:{ *:[v8f32] } VR256:{ *:[v8f32] }:$src1, VR256:{ *:[v8f32] }:$src2) 26518 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VMULPSYrr, 26519 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 26520 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 26521 // GIR_Coverage, 1914, 26522 GIR_Done, 26523 // Label 2263: @60141 26524 GIM_Try, /*On fail goto*//*Label 2264*/ 60167, // Rule ID 6036 // 26525 GIM_CheckFeatures, GIFBS_HasAVX512_HasVLX, 26526 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID, 26527 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID, 26528 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256XRegClassID, 26529 // (strict_fmul:{ *:[v8f32] } VR256X:{ *:[v8f32] }:$src1, VR256X:{ *:[v8f32] }:$src2) => (VMULPSZ256rr:{ *:[v8f32] } VR256X:{ *:[v8f32] }:$src1, VR256X:{ *:[v8f32] }:$src2) 26530 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VMULPSZ256rr, 26531 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 26532 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 26533 // GIR_Coverage, 6036, 26534 GIR_Done, 26535 // Label 2264: @60167 26536 GIM_Reject, 26537 // Label 2262: @60168 26538 GIM_Reject, 26539 // Label 2233: @60169 26540 GIM_Try, /*On fail goto*//*Label 2265*/ 60203, // Rule ID 6012 // 26541 GIM_CheckFeatures, GIFBS_HasAVX512, 26542 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s64, 26543 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s64, 26544 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 26545 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR512RegClassID, 26546 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR512RegClassID, 26547 // (strict_fmul:{ *:[v8f64] } VR512:{ *:[v8f64] }:$src1, VR512:{ *:[v8f64] }:$src2) => (VMULPDZrr:{ *:[v8f64] } VR512:{ *:[v8f64] }:$src1, VR512:{ *:[v8f64] }:$src2) 26548 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VMULPDZrr, 26549 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 26550 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 26551 // GIR_Coverage, 6012, 26552 GIR_Done, 26553 // Label 2265: @60203 26554 GIM_Reject, 26555 // Label 2234: @60204 26556 GIM_Try, /*On fail goto*//*Label 2266*/ 60238, // Rule ID 6096 // 26557 GIM_CheckFeatures, GIFBS_HasFP16_HasVLX, 26558 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s16, 26559 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s16, 26560 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID, 26561 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID, 26562 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256XRegClassID, 26563 // (strict_fmul:{ *:[v16f16] } VR256X:{ *:[v16f16] }:$src1, VR256X:{ *:[v16f16] }:$src2) => (VMULPHZ256rr:{ *:[v16f16] } VR256X:{ *:[v16f16] }:$src1, VR256X:{ *:[v16f16] }:$src2) 26564 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VMULPHZ256rr, 26565 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 26566 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 26567 // GIR_Coverage, 6096, 26568 GIR_Done, 26569 // Label 2266: @60238 26570 GIM_Reject, 26571 // Label 2235: @60239 26572 GIM_Try, /*On fail goto*//*Label 2267*/ 60273, // Rule ID 6000 // 26573 GIM_CheckFeatures, GIFBS_HasAVX512, 26574 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s32, 26575 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s32, 26576 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 26577 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR512RegClassID, 26578 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR512RegClassID, 26579 // (strict_fmul:{ *:[v16f32] } VR512:{ *:[v16f32] }:$src1, VR512:{ *:[v16f32] }:$src2) => (VMULPSZrr:{ *:[v16f32] } VR512:{ *:[v16f32] }:$src1, VR512:{ *:[v16f32] }:$src2) 26580 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VMULPSZrr, 26581 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 26582 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 26583 // GIR_Coverage, 6000, 26584 GIR_Done, 26585 // Label 2267: @60273 26586 GIM_Reject, 26587 // Label 2236: @60274 26588 GIM_Try, /*On fail goto*//*Label 2268*/ 60308, // Rule ID 6072 // 26589 GIM_CheckFeatures, GIFBS_HasFP16, 26590 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v32s16, 26591 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v32s16, 26592 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 26593 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR512RegClassID, 26594 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR512RegClassID, 26595 // (strict_fmul:{ *:[v32f16] } VR512:{ *:[v32f16] }:$src1, VR512:{ *:[v32f16] }:$src2) => (VMULPHZrr:{ *:[v32f16] } VR512:{ *:[v32f16] }:$src1, VR512:{ *:[v32f16] }:$src2) 26596 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VMULPHZrr, 26597 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 26598 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 26599 // GIR_Coverage, 6072, 26600 GIR_Done, 26601 // Label 2268: @60308 26602 GIM_Reject, 26603 // Label 2237: @60309 26604 GIM_Reject, 26605 // Label 58: @60310 26606 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/2, 23, /*)*//*default:*//*Label 2282*/ 61131, 26607 /*GILLT_s16*//*Label 2269*/ 60337, 26608 /*GILLT_s32*//*Label 2270*/ 60372, 26609 /*GILLT_s64*//*Label 2271*/ 60491, 26610 /*GILLT_s80*//*Label 2272*/ 60610, 0, 0, 26611 /*GILLT_v2s64*//*Label 2273*/ 60648, 0, 26612 /*GILLT_v4s32*//*Label 2274*/ 60738, 26613 /*GILLT_v4s64*//*Label 2275*/ 60828, 0, 26614 /*GILLT_v8s16*//*Label 2276*/ 60892, 26615 /*GILLT_v8s32*//*Label 2277*/ 60927, 26616 /*GILLT_v8s64*//*Label 2278*/ 60991, 0, 0, 26617 /*GILLT_v16s16*//*Label 2279*/ 61026, 26618 /*GILLT_v16s32*//*Label 2280*/ 61061, 0, 0, 26619 /*GILLT_v32s16*//*Label 2281*/ 61096, 26620 // Label 2269: @60337 26621 GIM_Try, /*On fail goto*//*Label 2283*/ 60371, // Rule ID 5762 // 26622 GIM_CheckFeatures, GIFBS_HasFP16, 26623 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16, 26624 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16, 26625 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::FR16XRegClassID, 26626 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::FR16XRegClassID, 26627 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::FR16XRegClassID, 26628 // (strict_fdiv:{ *:[f16] } FR16X:{ *:[f16] }:$src1, FR16X:{ *:[f16] }:$src2) => (VDIVSHZrr:{ *:[f16] } FR16X:{ *:[f16] }:$src1, FR16X:{ *:[f16] }:$src2) 26629 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VDIVSHZrr, 26630 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 26631 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 26632 // GIR_Coverage, 5762, 26633 GIR_Done, 26634 // Label 2283: @60371 26635 GIM_Reject, 26636 // Label 2270: @60372 26637 GIM_Try, /*On fail goto*//*Label 2284*/ 60490, 26638 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 26639 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 26640 GIM_Try, /*On fail goto*//*Label 2285*/ 60411, // Rule ID 638 // 26641 GIM_CheckFeatures, GIFBS_FPStackf32, 26642 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::RFP32RegClassID, 26643 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::RFP32RegClassID, 26644 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::RFP32RegClassID, 26645 // (strict_fdiv:{ *:[f32] } RFP32:{ *:[f32] }:$src1, RFP32:{ *:[f32] }:$src2) => (DIV_Fp32:{ *:[f32] }:{ *:[i16] } RFP32:{ *:[f32] }:$src1, RFP32:{ *:[f32] }:$src2) 26646 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::DIV_Fp32, 26647 GIR_AddImplicitDef, /*InsnID*/0, X86::FPSW, 26648 GIR_AddImplicitUse, /*InsnID*/0, X86::FPCW, 26649 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 26650 // GIR_Coverage, 638, 26651 GIR_Done, 26652 // Label 2285: @60411 26653 GIM_Try, /*On fail goto*//*Label 2286*/ 60437, // Rule ID 2010 // 26654 GIM_CheckFeatures, GIFBS_UseAVX, 26655 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::FR32RegClassID, 26656 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::FR32RegClassID, 26657 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::FR32RegClassID, 26658 // (strict_fdiv:{ *:[f32] } FR32:{ *:[f32] }:$src1, FR32:{ *:[f32] }:$src2) => (VDIVSSrr:{ *:[f32] } FR32:{ *:[f32] }:$src1, FR32:{ *:[f32] }:$src2) 26659 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VDIVSSrr, 26660 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 26661 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 26662 // GIR_Coverage, 2010, 26663 GIR_Done, 26664 // Label 2286: @60437 26665 GIM_Try, /*On fail goto*//*Label 2287*/ 60463, // Rule ID 2018 // 26666 GIM_CheckFeatures, GIFBS_UseSSE1, 26667 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::FR32RegClassID, 26668 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::FR32RegClassID, 26669 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::FR32RegClassID, 26670 // (strict_fdiv:{ *:[f32] } FR32:{ *:[f32] }:$src1, FR32:{ *:[f32] }:$src2) => (DIVSSrr:{ *:[f32] } FR32:{ *:[f32] }:$src1, FR32:{ *:[f32] }:$src2) 26671 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::DIVSSrr, 26672 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 26673 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 26674 // GIR_Coverage, 2018, 26675 GIR_Done, 26676 // Label 2287: @60463 26677 GIM_Try, /*On fail goto*//*Label 2288*/ 60489, // Rule ID 5724 // 26678 GIM_CheckFeatures, GIFBS_HasAVX512, 26679 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::FR32XRegClassID, 26680 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::FR32XRegClassID, 26681 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::FR32XRegClassID, 26682 // (strict_fdiv:{ *:[f32] } FR32X:{ *:[f32] }:$src1, FR32X:{ *:[f32] }:$src2) => (VDIVSSZrr:{ *:[f32] } FR32X:{ *:[f32] }:$src1, FR32X:{ *:[f32] }:$src2) 26683 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VDIVSSZrr, 26684 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 26685 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 26686 // GIR_Coverage, 5724, 26687 GIR_Done, 26688 // Label 2288: @60489 26689 GIM_Reject, 26690 // Label 2284: @60490 26691 GIM_Reject, 26692 // Label 2271: @60491 26693 GIM_Try, /*On fail goto*//*Label 2289*/ 60609, 26694 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 26695 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 26696 GIM_Try, /*On fail goto*//*Label 2290*/ 60530, // Rule ID 640 // 26697 GIM_CheckFeatures, GIFBS_FPStackf64, 26698 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::RFP64RegClassID, 26699 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::RFP64RegClassID, 26700 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::RFP64RegClassID, 26701 // (strict_fdiv:{ *:[f64] } RFP64:{ *:[f64] }:$src1, RFP64:{ *:[f64] }:$src2) => (DIV_Fp64:{ *:[f64] }:{ *:[i16] } RFP64:{ *:[f64] }:$src1, RFP64:{ *:[f64] }:$src2) 26702 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::DIV_Fp64, 26703 GIR_AddImplicitDef, /*InsnID*/0, X86::FPSW, 26704 GIR_AddImplicitUse, /*InsnID*/0, X86::FPCW, 26705 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 26706 // GIR_Coverage, 640, 26707 GIR_Done, 26708 // Label 2290: @60530 26709 GIM_Try, /*On fail goto*//*Label 2291*/ 60556, // Rule ID 2014 // 26710 GIM_CheckFeatures, GIFBS_UseAVX, 26711 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::FR64RegClassID, 26712 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::FR64RegClassID, 26713 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::FR64RegClassID, 26714 // (strict_fdiv:{ *:[f64] } FR64:{ *:[f64] }:$src1, FR64:{ *:[f64] }:$src2) => (VDIVSDrr:{ *:[f64] } FR64:{ *:[f64] }:$src1, FR64:{ *:[f64] }:$src2) 26715 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VDIVSDrr, 26716 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 26717 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 26718 // GIR_Coverage, 2014, 26719 GIR_Done, 26720 // Label 2291: @60556 26721 GIM_Try, /*On fail goto*//*Label 2292*/ 60582, // Rule ID 2022 // 26722 GIM_CheckFeatures, GIFBS_UseSSE2, 26723 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::FR64RegClassID, 26724 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::FR64RegClassID, 26725 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::FR64RegClassID, 26726 // (strict_fdiv:{ *:[f64] } FR64:{ *:[f64] }:$src1, FR64:{ *:[f64] }:$src2) => (DIVSDrr:{ *:[f64] } FR64:{ *:[f64] }:$src1, FR64:{ *:[f64] }:$src2) 26727 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::DIVSDrr, 26728 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 26729 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 26730 // GIR_Coverage, 2022, 26731 GIR_Done, 26732 // Label 2292: @60582 26733 GIM_Try, /*On fail goto*//*Label 2293*/ 60608, // Rule ID 5743 // 26734 GIM_CheckFeatures, GIFBS_HasAVX512, 26735 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::FR64XRegClassID, 26736 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::FR64XRegClassID, 26737 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::FR64XRegClassID, 26738 // (strict_fdiv:{ *:[f64] } FR64X:{ *:[f64] }:$src1, FR64X:{ *:[f64] }:$src2) => (VDIVSDZrr:{ *:[f64] } FR64X:{ *:[f64] }:$src1, FR64X:{ *:[f64] }:$src2) 26739 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VDIVSDZrr, 26740 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 26741 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 26742 // GIR_Coverage, 5743, 26743 GIR_Done, 26744 // Label 2293: @60608 26745 GIM_Reject, 26746 // Label 2289: @60609 26747 GIM_Reject, 26748 // Label 2272: @60610 26749 GIM_Try, /*On fail goto*//*Label 2294*/ 60647, // Rule ID 642 // 26750 GIM_CheckFeatures, GIFBS_HasX87, 26751 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s80, 26752 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s80, 26753 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::RFP80RegClassID, 26754 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::RFP80RegClassID, 26755 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::RFP80RegClassID, 26756 // (strict_fdiv:{ *:[f80] } RFP80:{ *:[f80] }:$src1, RFP80:{ *:[f80] }:$src2) => (DIV_Fp80:{ *:[f80] }:{ *:[i16] } RFP80:{ *:[f80] }:$src1, RFP80:{ *:[f80] }:$src2) 26757 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::DIV_Fp80, 26758 GIR_AddImplicitDef, /*InsnID*/0, X86::FPSW, 26759 GIR_AddImplicitUse, /*InsnID*/0, X86::FPCW, 26760 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 26761 // GIR_Coverage, 642, 26762 GIR_Done, 26763 // Label 2294: @60647 26764 GIM_Reject, 26765 // Label 2273: @60648 26766 GIM_Try, /*On fail goto*//*Label 2295*/ 60737, 26767 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, 26768 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 26769 GIM_Try, /*On fail goto*//*Label 2296*/ 60684, // Rule ID 1990 // 26770 GIM_CheckFeatures, GIFBS_HasAVX_NoVLX, 26771 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 26772 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 26773 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 26774 // (strict_fdiv:{ *:[v2f64] } VR128:{ *:[v2f64] }:$src1, VR128:{ *:[v2f64] }:$src2) => (VDIVPDrr:{ *:[v2f64] } VR128:{ *:[v2f64] }:$src1, VR128:{ *:[v2f64] }:$src2) 26775 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VDIVPDrr, 26776 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 26777 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 26778 // GIR_Coverage, 1990, 26779 GIR_Done, 26780 // Label 2296: @60684 26781 GIM_Try, /*On fail goto*//*Label 2297*/ 60710, // Rule ID 2006 // 26782 GIM_CheckFeatures, GIFBS_UseSSE2, 26783 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 26784 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 26785 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 26786 // (strict_fdiv:{ *:[v2f64] } VR128:{ *:[v2f64] }:$src1, VR128:{ *:[v2f64] }:$src2) => (DIVPDrr:{ *:[v2f64] } VR128:{ *:[v2f64] }:$src1, VR128:{ *:[v2f64] }:$src2) 26787 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::DIVPDrr, 26788 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 26789 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 26790 // GIR_Coverage, 2006, 26791 GIR_Done, 26792 // Label 2297: @60710 26793 GIM_Try, /*On fail goto*//*Label 2298*/ 60736, // Rule ID 6282 // 26794 GIM_CheckFeatures, GIFBS_HasAVX512_HasVLX, 26795 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID, 26796 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID, 26797 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128XRegClassID, 26798 // (strict_fdiv:{ *:[v2f64] } VR128X:{ *:[v2f64] }:$src1, VR128X:{ *:[v2f64] }:$src2) => (VDIVPDZ128rr:{ *:[v2f64] } VR128X:{ *:[v2f64] }:$src1, VR128X:{ *:[v2f64] }:$src2) 26799 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VDIVPDZ128rr, 26800 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 26801 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 26802 // GIR_Coverage, 6282, 26803 GIR_Done, 26804 // Label 2298: @60736 26805 GIM_Reject, 26806 // Label 2295: @60737 26807 GIM_Reject, 26808 // Label 2274: @60738 26809 GIM_Try, /*On fail goto*//*Label 2299*/ 60827, 26810 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, 26811 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 26812 GIM_Try, /*On fail goto*//*Label 2300*/ 60774, // Rule ID 1986 // 26813 GIM_CheckFeatures, GIFBS_HasAVX_NoVLX, 26814 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 26815 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 26816 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 26817 // (strict_fdiv:{ *:[v4f32] } VR128:{ *:[v4f32] }:$src1, VR128:{ *:[v4f32] }:$src2) => (VDIVPSrr:{ *:[v4f32] } VR128:{ *:[v4f32] }:$src1, VR128:{ *:[v4f32] }:$src2) 26818 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VDIVPSrr, 26819 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 26820 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 26821 // GIR_Coverage, 1986, 26822 GIR_Done, 26823 // Label 2300: @60774 26824 GIM_Try, /*On fail goto*//*Label 2301*/ 60800, // Rule ID 2002 // 26825 GIM_CheckFeatures, GIFBS_UseSSE1, 26826 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 26827 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 26828 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 26829 // (strict_fdiv:{ *:[v4f32] } VR128:{ *:[v4f32] }:$src1, VR128:{ *:[v4f32] }:$src2) => (DIVPSrr:{ *:[v4f32] } VR128:{ *:[v4f32] }:$src1, VR128:{ *:[v4f32] }:$src2) 26830 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::DIVPSrr, 26831 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 26832 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 26833 // GIR_Coverage, 2002, 26834 GIR_Done, 26835 // Label 2301: @60800 26836 GIM_Try, /*On fail goto*//*Label 2302*/ 60826, // Rule ID 6258 // 26837 GIM_CheckFeatures, GIFBS_HasAVX512_HasVLX, 26838 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID, 26839 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID, 26840 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128XRegClassID, 26841 // (strict_fdiv:{ *:[v4f32] } VR128X:{ *:[v4f32] }:$src1, VR128X:{ *:[v4f32] }:$src2) => (VDIVPSZ128rr:{ *:[v4f32] } VR128X:{ *:[v4f32] }:$src1, VR128X:{ *:[v4f32] }:$src2) 26842 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VDIVPSZ128rr, 26843 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 26844 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 26845 // GIR_Coverage, 6258, 26846 GIR_Done, 26847 // Label 2302: @60826 26848 GIM_Reject, 26849 // Label 2299: @60827 26850 GIM_Reject, 26851 // Label 2275: @60828 26852 GIM_Try, /*On fail goto*//*Label 2303*/ 60891, 26853 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s64, 26854 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s64, 26855 GIM_Try, /*On fail goto*//*Label 2304*/ 60864, // Rule ID 1998 // 26856 GIM_CheckFeatures, GIFBS_HasAVX_NoVLX, 26857 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID, 26858 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256RegClassID, 26859 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256RegClassID, 26860 // (strict_fdiv:{ *:[v4f64] } VR256:{ *:[v4f64] }:$src1, VR256:{ *:[v4f64] }:$src2) => (VDIVPDYrr:{ *:[v4f64] } VR256:{ *:[v4f64] }:$src1, VR256:{ *:[v4f64] }:$src2) 26861 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VDIVPDYrr, 26862 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 26863 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 26864 // GIR_Coverage, 1998, 26865 GIR_Done, 26866 // Label 2304: @60864 26867 GIM_Try, /*On fail goto*//*Label 2305*/ 60890, // Rule ID 6294 // 26868 GIM_CheckFeatures, GIFBS_HasAVX512_HasVLX, 26869 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID, 26870 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID, 26871 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256XRegClassID, 26872 // (strict_fdiv:{ *:[v4f64] } VR256X:{ *:[v4f64] }:$src1, VR256X:{ *:[v4f64] }:$src2) => (VDIVPDZ256rr:{ *:[v4f64] } VR256X:{ *:[v4f64] }:$src1, VR256X:{ *:[v4f64] }:$src2) 26873 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VDIVPDZ256rr, 26874 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 26875 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 26876 // GIR_Coverage, 6294, 26877 GIR_Done, 26878 // Label 2305: @60890 26879 GIM_Reject, 26880 // Label 2303: @60891 26881 GIM_Reject, 26882 // Label 2276: @60892 26883 GIM_Try, /*On fail goto*//*Label 2306*/ 60926, // Rule ID 6318 // 26884 GIM_CheckFeatures, GIFBS_HasFP16_HasVLX, 26885 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, 26886 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 26887 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID, 26888 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID, 26889 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128XRegClassID, 26890 // (strict_fdiv:{ *:[v8f16] } VR128X:{ *:[v8f16] }:$src1, VR128X:{ *:[v8f16] }:$src2) => (VDIVPHZ128rr:{ *:[v8f16] } VR128X:{ *:[v8f16] }:$src1, VR128X:{ *:[v8f16] }:$src2) 26891 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VDIVPHZ128rr, 26892 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 26893 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 26894 // GIR_Coverage, 6318, 26895 GIR_Done, 26896 // Label 2306: @60926 26897 GIM_Reject, 26898 // Label 2277: @60927 26899 GIM_Try, /*On fail goto*//*Label 2307*/ 60990, 26900 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s32, 26901 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s32, 26902 GIM_Try, /*On fail goto*//*Label 2308*/ 60963, // Rule ID 1994 // 26903 GIM_CheckFeatures, GIFBS_HasAVX_NoVLX, 26904 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID, 26905 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256RegClassID, 26906 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256RegClassID, 26907 // (strict_fdiv:{ *:[v8f32] } VR256:{ *:[v8f32] }:$src1, VR256:{ *:[v8f32] }:$src2) => (VDIVPSYrr:{ *:[v8f32] } VR256:{ *:[v8f32] }:$src1, VR256:{ *:[v8f32] }:$src2) 26908 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VDIVPSYrr, 26909 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 26910 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 26911 // GIR_Coverage, 1994, 26912 GIR_Done, 26913 // Label 2308: @60963 26914 GIM_Try, /*On fail goto*//*Label 2309*/ 60989, // Rule ID 6270 // 26915 GIM_CheckFeatures, GIFBS_HasAVX512_HasVLX, 26916 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID, 26917 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID, 26918 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256XRegClassID, 26919 // (strict_fdiv:{ *:[v8f32] } VR256X:{ *:[v8f32] }:$src1, VR256X:{ *:[v8f32] }:$src2) => (VDIVPSZ256rr:{ *:[v8f32] } VR256X:{ *:[v8f32] }:$src1, VR256X:{ *:[v8f32] }:$src2) 26920 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VDIVPSZ256rr, 26921 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 26922 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 26923 // GIR_Coverage, 6270, 26924 GIR_Done, 26925 // Label 2309: @60989 26926 GIM_Reject, 26927 // Label 2307: @60990 26928 GIM_Reject, 26929 // Label 2278: @60991 26930 GIM_Try, /*On fail goto*//*Label 2310*/ 61025, // Rule ID 6246 // 26931 GIM_CheckFeatures, GIFBS_HasAVX512, 26932 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s64, 26933 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s64, 26934 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 26935 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR512RegClassID, 26936 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR512RegClassID, 26937 // (strict_fdiv:{ *:[v8f64] } VR512:{ *:[v8f64] }:$src1, VR512:{ *:[v8f64] }:$src2) => (VDIVPDZrr:{ *:[v8f64] } VR512:{ *:[v8f64] }:$src1, VR512:{ *:[v8f64] }:$src2) 26938 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VDIVPDZrr, 26939 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 26940 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 26941 // GIR_Coverage, 6246, 26942 GIR_Done, 26943 // Label 2310: @61025 26944 GIM_Reject, 26945 // Label 2279: @61026 26946 GIM_Try, /*On fail goto*//*Label 2311*/ 61060, // Rule ID 6330 // 26947 GIM_CheckFeatures, GIFBS_HasFP16_HasVLX, 26948 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s16, 26949 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s16, 26950 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID, 26951 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID, 26952 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256XRegClassID, 26953 // (strict_fdiv:{ *:[v16f16] } VR256X:{ *:[v16f16] }:$src1, VR256X:{ *:[v16f16] }:$src2) => (VDIVPHZ256rr:{ *:[v16f16] } VR256X:{ *:[v16f16] }:$src1, VR256X:{ *:[v16f16] }:$src2) 26954 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VDIVPHZ256rr, 26955 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 26956 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 26957 // GIR_Coverage, 6330, 26958 GIR_Done, 26959 // Label 2311: @61060 26960 GIM_Reject, 26961 // Label 2280: @61061 26962 GIM_Try, /*On fail goto*//*Label 2312*/ 61095, // Rule ID 6234 // 26963 GIM_CheckFeatures, GIFBS_HasAVX512, 26964 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s32, 26965 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s32, 26966 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 26967 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR512RegClassID, 26968 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR512RegClassID, 26969 // (strict_fdiv:{ *:[v16f32] } VR512:{ *:[v16f32] }:$src1, VR512:{ *:[v16f32] }:$src2) => (VDIVPSZrr:{ *:[v16f32] } VR512:{ *:[v16f32] }:$src1, VR512:{ *:[v16f32] }:$src2) 26970 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VDIVPSZrr, 26971 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 26972 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 26973 // GIR_Coverage, 6234, 26974 GIR_Done, 26975 // Label 2312: @61095 26976 GIM_Reject, 26977 // Label 2281: @61096 26978 GIM_Try, /*On fail goto*//*Label 2313*/ 61130, // Rule ID 6306 // 26979 GIM_CheckFeatures, GIFBS_HasFP16, 26980 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v32s16, 26981 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v32s16, 26982 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 26983 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR512RegClassID, 26984 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR512RegClassID, 26985 // (strict_fdiv:{ *:[v32f16] } VR512:{ *:[v32f16] }:$src1, VR512:{ *:[v32f16] }:$src2) => (VDIVPHZrr:{ *:[v32f16] } VR512:{ *:[v32f16] }:$src1, VR512:{ *:[v32f16] }:$src2) 26986 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VDIVPHZrr, 26987 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 26988 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 26989 // GIR_Coverage, 6306, 26990 GIR_Done, 26991 // Label 2313: @61130 26992 GIM_Reject, 26993 // Label 2282: @61131 26994 GIM_Reject, 26995 // Label 59: @61132 26996 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/2, 23, /*)*//*default:*//*Label 2326*/ 62305, 26997 /*GILLT_s16*//*Label 2314*/ 61159, 26998 /*GILLT_s32*//*Label 2315*/ 61216, 26999 /*GILLT_s64*//*Label 2316*/ 61350, 0, 0, 0, 27000 /*GILLT_v2s64*//*Label 2317*/ 61484, 0, 27001 /*GILLT_v4s32*//*Label 2318*/ 61618, 27002 /*GILLT_v4s64*//*Label 2319*/ 61752, 0, 27003 /*GILLT_v8s16*//*Label 2320*/ 61886, 27004 /*GILLT_v8s32*//*Label 2321*/ 61943, 27005 /*GILLT_v8s64*//*Label 2322*/ 62077, 0, 0, 27006 /*GILLT_v16s16*//*Label 2323*/ 62134, 27007 /*GILLT_v16s32*//*Label 2324*/ 62191, 0, 0, 27008 /*GILLT_v32s16*//*Label 2325*/ 62248, 27009 // Label 2314: @61159 27010 GIM_Try, /*On fail goto*//*Label 2327*/ 61215, // Rule ID 9723 // 27011 GIM_CheckFeatures, GIFBS_HasFP16, 27012 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16, 27013 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16, 27014 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s16, 27015 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::FR16XRegClassID, 27016 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::FR16XRegClassID, 27017 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::FR16XRegClassID, 27018 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::FR16XRegClassID, 27019 // (strict_fma:{ *:[f16] } FR16X:{ *:[f16] }:$src2, FR16X:{ *:[f16] }:$src1, FR16X:{ *:[f16] }:$src3) => (VFMADD213SHZr:{ *:[f16] } FR16X:{ *:[f16] }:$src1, FR16X:{ *:[f16] }:$src2, FR16X:{ *:[f16] }:$src3) 27020 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VFMADD213SHZr, 27021 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 27022 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 27023 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src2 27024 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src3 27025 GIR_EraseFromParent, /*InsnID*/0, 27026 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 27027 // GIR_Coverage, 9723, 27028 GIR_Done, 27029 // Label 2327: @61215 27030 GIM_Reject, 27031 // Label 2315: @61216 27032 GIM_Try, /*On fail goto*//*Label 2328*/ 61349, 27033 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 27034 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 27035 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 27036 GIM_Try, /*On fail goto*//*Label 2329*/ 61274, // Rule ID 1029 // 27037 GIM_CheckFeatures, GIFBS_HasFMA_NoAVX512_NoFMA4, 27038 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::FR32RegClassID, 27039 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::FR32RegClassID, 27040 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::FR32RegClassID, 27041 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::FR32RegClassID, 27042 // (strict_fma:{ *:[f32] } FR32:{ *:[f32] }:$src2, FR32:{ *:[f32] }:$src1, FR32:{ *:[f32] }:$src3) => (VFMADD213SSr:{ *:[f32] } FR32:{ *:[f32] }:$src1, FR32:{ *:[f32] }:$src2, FR32:{ *:[f32] }:$src3) 27043 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VFMADD213SSr, 27044 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 27045 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 27046 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src2 27047 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src3 27048 GIR_EraseFromParent, /*InsnID*/0, 27049 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 27050 // GIR_Coverage, 1029, 27051 GIR_Done, 27052 // Label 2329: @61274 27053 GIM_Try, /*On fail goto*//*Label 2330*/ 61304, // Rule ID 1093 // 27054 GIM_CheckFeatures, GIFBS_HasFMA4_NoAVX512, 27055 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::FR32RegClassID, 27056 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::FR32RegClassID, 27057 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::FR32RegClassID, 27058 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::FR32RegClassID, 27059 // (strict_fma:{ *:[f32] } FR32:{ *:[f32] }:$src1, FR32:{ *:[f32] }:$src2, FR32:{ *:[f32] }:$src3) => (VFMADDSS4rr:{ *:[f32] } FR32:{ *:[f32] }:$src1, FR32:{ *:[f32] }:$src2, FR32:{ *:[f32] }:$src3) 27060 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VFMADDSS4rr, 27061 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 27062 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 27063 // GIR_Coverage, 1093, 27064 GIR_Done, 27065 // Label 2330: @61304 27066 GIM_Try, /*On fail goto*//*Label 2331*/ 61348, // Rule ID 9705 // 27067 GIM_CheckFeatures, GIFBS_HasAVX512, 27068 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::FR32XRegClassID, 27069 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::FR32XRegClassID, 27070 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::FR32XRegClassID, 27071 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::FR32XRegClassID, 27072 // (strict_fma:{ *:[f32] } FR32X:{ *:[f32] }:$src2, FR32X:{ *:[f32] }:$src1, FR32X:{ *:[f32] }:$src3) => (VFMADD213SSZr:{ *:[f32] } FR32X:{ *:[f32] }:$src1, FR32X:{ *:[f32] }:$src2, FR32X:{ *:[f32] }:$src3) 27073 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VFMADD213SSZr, 27074 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 27075 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 27076 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src2 27077 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src3 27078 GIR_EraseFromParent, /*InsnID*/0, 27079 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 27080 // GIR_Coverage, 9705, 27081 GIR_Done, 27082 // Label 2331: @61348 27083 GIM_Reject, 27084 // Label 2328: @61349 27085 GIM_Reject, 27086 // Label 2316: @61350 27087 GIM_Try, /*On fail goto*//*Label 2332*/ 61483, 27088 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 27089 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 27090 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, 27091 GIM_Try, /*On fail goto*//*Label 2333*/ 61408, // Rule ID 1037 // 27092 GIM_CheckFeatures, GIFBS_HasFMA_NoAVX512_NoFMA4, 27093 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::FR64RegClassID, 27094 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::FR64RegClassID, 27095 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::FR64RegClassID, 27096 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::FR64RegClassID, 27097 // (strict_fma:{ *:[f64] } FR64:{ *:[f64] }:$src2, FR64:{ *:[f64] }:$src1, FR64:{ *:[f64] }:$src3) => (VFMADD213SDr:{ *:[f64] } FR64:{ *:[f64] }:$src1, FR64:{ *:[f64] }:$src2, FR64:{ *:[f64] }:$src3) 27098 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VFMADD213SDr, 27099 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 27100 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 27101 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src2 27102 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src3 27103 GIR_EraseFromParent, /*InsnID*/0, 27104 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 27105 // GIR_Coverage, 1037, 27106 GIR_Done, 27107 // Label 2333: @61408 27108 GIM_Try, /*On fail goto*//*Label 2334*/ 61438, // Rule ID 1177 // 27109 GIM_CheckFeatures, GIFBS_HasFMA4_NoAVX512, 27110 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::FR64RegClassID, 27111 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::FR64RegClassID, 27112 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::FR64RegClassID, 27113 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::FR64RegClassID, 27114 // (strict_fma:{ *:[f64] } FR64:{ *:[f64] }:$src1, FR64:{ *:[f64] }:$src2, FR64:{ *:[f64] }:$src3) => (VFMADDSD4rr:{ *:[f64] } FR64:{ *:[f64] }:$src1, FR64:{ *:[f64] }:$src2, FR64:{ *:[f64] }:$src3) 27115 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VFMADDSD4rr, 27116 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 27117 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 27118 // GIR_Coverage, 1177, 27119 GIR_Done, 27120 // Label 2334: @61438 27121 GIM_Try, /*On fail goto*//*Label 2335*/ 61482, // Rule ID 9714 // 27122 GIM_CheckFeatures, GIFBS_HasAVX512, 27123 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::FR64XRegClassID, 27124 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::FR64XRegClassID, 27125 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::FR64XRegClassID, 27126 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::FR64XRegClassID, 27127 // (strict_fma:{ *:[f64] } FR64X:{ *:[f64] }:$src2, FR64X:{ *:[f64] }:$src1, FR64X:{ *:[f64] }:$src3) => (VFMADD213SDZr:{ *:[f64] } FR64X:{ *:[f64] }:$src1, FR64X:{ *:[f64] }:$src2, FR64X:{ *:[f64] }:$src3) 27128 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VFMADD213SDZr, 27129 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 27130 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 27131 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src2 27132 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src3 27133 GIR_EraseFromParent, /*InsnID*/0, 27134 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 27135 // GIR_Coverage, 9714, 27136 GIR_Done, 27137 // Label 2335: @61482 27138 GIM_Reject, 27139 // Label 2332: @61483 27140 GIM_Reject, 27141 // Label 2317: @61484 27142 GIM_Try, /*On fail goto*//*Label 2336*/ 61617, 27143 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, 27144 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 27145 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, 27146 GIM_Try, /*On fail goto*//*Label 2337*/ 61542, // Rule ID 917 // 27147 GIM_CheckFeatures, GIFBS_HasFMA_NoFMA4_NoVLX, 27148 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 27149 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 27150 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 27151 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::VR128RegClassID, 27152 // (strict_fma:{ *:[v2f64] } VR128:{ *:[v2f64] }:$src2, VR128:{ *:[v2f64] }:$src1, VR128:{ *:[v2f64] }:$src3) => (VFMADD213PDr:{ *:[v2f64] } VR128:{ *:[v2f64] }:$src1, VR128:{ *:[v2f64] }:$src2, VR128:{ *:[v2f64] }:$src3) 27153 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VFMADD213PDr, 27154 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 27155 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 27156 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src2 27157 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src3 27158 GIR_EraseFromParent, /*InsnID*/0, 27159 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 27160 // GIR_Coverage, 917, 27161 GIR_Done, 27162 // Label 2337: @61542 27163 GIM_Try, /*On fail goto*//*Label 2338*/ 61572, // Rule ID 1201 // 27164 GIM_CheckFeatures, GIFBS_HasFMA4_NoVLX, 27165 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 27166 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 27167 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 27168 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::VR128RegClassID, 27169 // (strict_fma:{ *:[v2f64] } VR128:{ *:[v2f64] }:$src1, VR128:{ *:[v2f64] }:$src2, VR128:{ *:[v2f64] }:$src3) => (VFMADDPD4rr:{ *:[v2f64] } VR128:{ *:[v2f64] }:$src1, VR128:{ *:[v2f64] }:$src2, VR128:{ *:[v2f64] }:$src3) 27170 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VFMADDPD4rr, 27171 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 27172 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 27173 // GIR_Coverage, 1201, 27174 GIR_Done, 27175 // Label 2338: @61572 27176 GIM_Try, /*On fail goto*//*Label 2339*/ 61616, // Rule ID 8082 // 27177 GIM_CheckFeatures, GIFBS_HasAVX512_HasVLX, 27178 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID, 27179 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID, 27180 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128XRegClassID, 27181 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::VR128XRegClassID, 27182 // (strict_fma:{ *:[v2f64] } VR128X:{ *:[v2f64] }:$src2, VR128X:{ *:[v2f64] }:$src1, VR128X:{ *:[v2f64] }:$src3) => (VFMADD213PDZ128r:{ *:[v2f64] } VR128X:{ *:[v2f64] }:$src1, VR128X:{ *:[v2f64] }:$src2, VR128X:{ *:[v2f64] }:$src3) 27183 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VFMADD213PDZ128r, 27184 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 27185 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 27186 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src2 27187 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src3 27188 GIR_EraseFromParent, /*InsnID*/0, 27189 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 27190 // GIR_Coverage, 8082, 27191 GIR_Done, 27192 // Label 2339: @61616 27193 GIM_Reject, 27194 // Label 2336: @61617 27195 GIM_Reject, 27196 // Label 2318: @61618 27197 GIM_Try, /*On fail goto*//*Label 2340*/ 61751, 27198 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, 27199 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 27200 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, 27201 GIM_Try, /*On fail goto*//*Label 2341*/ 61676, // Rule ID 869 // 27202 GIM_CheckFeatures, GIFBS_HasFMA_NoFMA4_NoVLX, 27203 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 27204 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 27205 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 27206 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::VR128RegClassID, 27207 // (strict_fma:{ *:[v4f32] } VR128:{ *:[v4f32] }:$src2, VR128:{ *:[v4f32] }:$src1, VR128:{ *:[v4f32] }:$src3) => (VFMADD213PSr:{ *:[v4f32] } VR128:{ *:[v4f32] }:$src1, VR128:{ *:[v4f32] }:$src2, VR128:{ *:[v4f32] }:$src3) 27208 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VFMADD213PSr, 27209 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 27210 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 27211 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src2 27212 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src3 27213 GIR_EraseFromParent, /*InsnID*/0, 27214 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 27215 // GIR_Coverage, 869, 27216 GIR_Done, 27217 // Label 2341: @61676 27218 GIM_Try, /*On fail goto*//*Label 2342*/ 61706, // Rule ID 1117 // 27219 GIM_CheckFeatures, GIFBS_HasFMA4_NoVLX, 27220 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 27221 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 27222 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 27223 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::VR128RegClassID, 27224 // (strict_fma:{ *:[v4f32] } VR128:{ *:[v4f32] }:$src1, VR128:{ *:[v4f32] }:$src2, VR128:{ *:[v4f32] }:$src3) => (VFMADDPS4rr:{ *:[v4f32] } VR128:{ *:[v4f32] }:$src1, VR128:{ *:[v4f32] }:$src2, VR128:{ *:[v4f32] }:$src3) 27225 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VFMADDPS4rr, 27226 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 27227 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 27228 // GIR_Coverage, 1117, 27229 GIR_Done, 27230 // Label 2342: @61706 27231 GIM_Try, /*On fail goto*//*Label 2343*/ 61750, // Rule ID 8043 // 27232 GIM_CheckFeatures, GIFBS_HasAVX512_HasVLX, 27233 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID, 27234 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID, 27235 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128XRegClassID, 27236 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::VR128XRegClassID, 27237 // (strict_fma:{ *:[v4f32] } VR128X:{ *:[v4f32] }:$src2, VR128X:{ *:[v4f32] }:$src1, VR128X:{ *:[v4f32] }:$src3) => (VFMADD213PSZ128r:{ *:[v4f32] } VR128X:{ *:[v4f32] }:$src1, VR128X:{ *:[v4f32] }:$src2, VR128X:{ *:[v4f32] }:$src3) 27238 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VFMADD213PSZ128r, 27239 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 27240 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 27241 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src2 27242 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src3 27243 GIR_EraseFromParent, /*InsnID*/0, 27244 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 27245 // GIR_Coverage, 8043, 27246 GIR_Done, 27247 // Label 2343: @61750 27248 GIM_Reject, 27249 // Label 2340: @61751 27250 GIM_Reject, 27251 // Label 2319: @61752 27252 GIM_Try, /*On fail goto*//*Label 2344*/ 61885, 27253 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s64, 27254 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s64, 27255 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s64, 27256 GIM_Try, /*On fail goto*//*Label 2345*/ 61810, // Rule ID 925 // 27257 GIM_CheckFeatures, GIFBS_HasFMA_NoFMA4_NoVLX, 27258 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID, 27259 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256RegClassID, 27260 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256RegClassID, 27261 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::VR256RegClassID, 27262 // (strict_fma:{ *:[v4f64] } VR256:{ *:[v4f64] }:$src2, VR256:{ *:[v4f64] }:$src1, VR256:{ *:[v4f64] }:$src3) => (VFMADD213PDYr:{ *:[v4f64] } VR256:{ *:[v4f64] }:$src1, VR256:{ *:[v4f64] }:$src2, VR256:{ *:[v4f64] }:$src3) 27263 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VFMADD213PDYr, 27264 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 27265 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 27266 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src2 27267 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src3 27268 GIR_EraseFromParent, /*InsnID*/0, 27269 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 27270 // GIR_Coverage, 925, 27271 GIR_Done, 27272 // Label 2345: @61810 27273 GIM_Try, /*On fail goto*//*Label 2346*/ 61840, // Rule ID 1207 // 27274 GIM_CheckFeatures, GIFBS_HasFMA4_NoVLX, 27275 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID, 27276 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256RegClassID, 27277 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256RegClassID, 27278 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::VR256RegClassID, 27279 // (strict_fma:{ *:[v4f64] } VR256:{ *:[v4f64] }:$src1, VR256:{ *:[v4f64] }:$src2, VR256:{ *:[v4f64] }:$src3) => (VFMADDPD4Yrr:{ *:[v4f64] } VR256:{ *:[v4f64] }:$src1, VR256:{ *:[v4f64] }:$src2, VR256:{ *:[v4f64] }:$src3) 27280 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VFMADDPD4Yrr, 27281 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 27282 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 27283 // GIR_Coverage, 1207, 27284 GIR_Done, 27285 // Label 2346: @61840 27286 GIM_Try, /*On fail goto*//*Label 2347*/ 61884, // Rule ID 8070 // 27287 GIM_CheckFeatures, GIFBS_HasAVX512_HasVLX, 27288 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID, 27289 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID, 27290 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256XRegClassID, 27291 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::VR256XRegClassID, 27292 // (strict_fma:{ *:[v4f64] } VR256X:{ *:[v4f64] }:$src2, VR256X:{ *:[v4f64] }:$src1, VR256X:{ *:[v4f64] }:$src3) => (VFMADD213PDZ256r:{ *:[v4f64] } VR256X:{ *:[v4f64] }:$src1, VR256X:{ *:[v4f64] }:$src2, VR256X:{ *:[v4f64] }:$src3) 27293 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VFMADD213PDZ256r, 27294 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 27295 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 27296 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src2 27297 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src3 27298 GIR_EraseFromParent, /*InsnID*/0, 27299 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 27300 // GIR_Coverage, 8070, 27301 GIR_Done, 27302 // Label 2347: @61884 27303 GIM_Reject, 27304 // Label 2344: @61885 27305 GIM_Reject, 27306 // Label 2320: @61886 27307 GIM_Try, /*On fail goto*//*Label 2348*/ 61942, // Rule ID 8004 // 27308 GIM_CheckFeatures, GIFBS_HasFP16_HasVLX, 27309 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, 27310 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 27311 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, 27312 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID, 27313 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID, 27314 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128XRegClassID, 27315 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::VR128XRegClassID, 27316 // (strict_fma:{ *:[v8f16] } VR128X:{ *:[v8f16] }:$src2, VR128X:{ *:[v8f16] }:$src1, VR128X:{ *:[v8f16] }:$src3) => (VFMADD213PHZ128r:{ *:[v8f16] } VR128X:{ *:[v8f16] }:$src1, VR128X:{ *:[v8f16] }:$src2, VR128X:{ *:[v8f16] }:$src3) 27317 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VFMADD213PHZ128r, 27318 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 27319 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 27320 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src2 27321 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src3 27322 GIR_EraseFromParent, /*InsnID*/0, 27323 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 27324 // GIR_Coverage, 8004, 27325 GIR_Done, 27326 // Label 2348: @61942 27327 GIM_Reject, 27328 // Label 2321: @61943 27329 GIM_Try, /*On fail goto*//*Label 2349*/ 62076, 27330 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s32, 27331 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s32, 27332 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s32, 27333 GIM_Try, /*On fail goto*//*Label 2350*/ 62001, // Rule ID 877 // 27334 GIM_CheckFeatures, GIFBS_HasFMA_NoFMA4_NoVLX, 27335 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID, 27336 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256RegClassID, 27337 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256RegClassID, 27338 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::VR256RegClassID, 27339 // (strict_fma:{ *:[v8f32] } VR256:{ *:[v8f32] }:$src2, VR256:{ *:[v8f32] }:$src1, VR256:{ *:[v8f32] }:$src3) => (VFMADD213PSYr:{ *:[v8f32] } VR256:{ *:[v8f32] }:$src1, VR256:{ *:[v8f32] }:$src2, VR256:{ *:[v8f32] }:$src3) 27340 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VFMADD213PSYr, 27341 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 27342 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 27343 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src2 27344 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src3 27345 GIR_EraseFromParent, /*InsnID*/0, 27346 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 27347 // GIR_Coverage, 877, 27348 GIR_Done, 27349 // Label 2350: @62001 27350 GIM_Try, /*On fail goto*//*Label 2351*/ 62031, // Rule ID 1123 // 27351 GIM_CheckFeatures, GIFBS_HasFMA4_NoVLX, 27352 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID, 27353 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256RegClassID, 27354 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256RegClassID, 27355 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::VR256RegClassID, 27356 // (strict_fma:{ *:[v8f32] } VR256:{ *:[v8f32] }:$src1, VR256:{ *:[v8f32] }:$src2, VR256:{ *:[v8f32] }:$src3) => (VFMADDPS4Yrr:{ *:[v8f32] } VR256:{ *:[v8f32] }:$src1, VR256:{ *:[v8f32] }:$src2, VR256:{ *:[v8f32] }:$src3) 27357 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VFMADDPS4Yrr, 27358 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 27359 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 27360 // GIR_Coverage, 1123, 27361 GIR_Done, 27362 // Label 2351: @62031 27363 GIM_Try, /*On fail goto*//*Label 2352*/ 62075, // Rule ID 8031 // 27364 GIM_CheckFeatures, GIFBS_HasAVX512_HasVLX, 27365 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID, 27366 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID, 27367 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256XRegClassID, 27368 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::VR256XRegClassID, 27369 // (strict_fma:{ *:[v8f32] } VR256X:{ *:[v8f32] }:$src2, VR256X:{ *:[v8f32] }:$src1, VR256X:{ *:[v8f32] }:$src3) => (VFMADD213PSZ256r:{ *:[v8f32] } VR256X:{ *:[v8f32] }:$src1, VR256X:{ *:[v8f32] }:$src2, VR256X:{ *:[v8f32] }:$src3) 27370 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VFMADD213PSZ256r, 27371 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 27372 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 27373 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src2 27374 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src3 27375 GIR_EraseFromParent, /*InsnID*/0, 27376 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 27377 // GIR_Coverage, 8031, 27378 GIR_Done, 27379 // Label 2352: @62075 27380 GIM_Reject, 27381 // Label 2349: @62076 27382 GIM_Reject, 27383 // Label 2322: @62077 27384 GIM_Try, /*On fail goto*//*Label 2353*/ 62133, // Rule ID 8055 // 27385 GIM_CheckFeatures, GIFBS_HasAVX512, 27386 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s64, 27387 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s64, 27388 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s64, 27389 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 27390 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR512RegClassID, 27391 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR512RegClassID, 27392 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::VR512RegClassID, 27393 // (strict_fma:{ *:[v8f64] } VR512:{ *:[v8f64] }:$src2, VR512:{ *:[v8f64] }:$src1, VR512:{ *:[v8f64] }:$src3) => (VFMADD213PDZr:{ *:[v8f64] } VR512:{ *:[v8f64] }:$src1, VR512:{ *:[v8f64] }:$src2, VR512:{ *:[v8f64] }:$src3) 27394 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VFMADD213PDZr, 27395 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 27396 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 27397 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src2 27398 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src3 27399 GIR_EraseFromParent, /*InsnID*/0, 27400 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 27401 // GIR_Coverage, 8055, 27402 GIR_Done, 27403 // Label 2353: @62133 27404 GIM_Reject, 27405 // Label 2323: @62134 27406 GIM_Try, /*On fail goto*//*Label 2354*/ 62190, // Rule ID 7992 // 27407 GIM_CheckFeatures, GIFBS_HasFP16_HasVLX, 27408 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s16, 27409 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s16, 27410 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s16, 27411 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID, 27412 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID, 27413 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256XRegClassID, 27414 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::VR256XRegClassID, 27415 // (strict_fma:{ *:[v16f16] } VR256X:{ *:[v16f16] }:$src2, VR256X:{ *:[v16f16] }:$src1, VR256X:{ *:[v16f16] }:$src3) => (VFMADD213PHZ256r:{ *:[v16f16] } VR256X:{ *:[v16f16] }:$src1, VR256X:{ *:[v16f16] }:$src2, VR256X:{ *:[v16f16] }:$src3) 27416 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VFMADD213PHZ256r, 27417 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 27418 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 27419 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src2 27420 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src3 27421 GIR_EraseFromParent, /*InsnID*/0, 27422 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 27423 // GIR_Coverage, 7992, 27424 GIR_Done, 27425 // Label 2354: @62190 27426 GIM_Reject, 27427 // Label 2324: @62191 27428 GIM_Try, /*On fail goto*//*Label 2355*/ 62247, // Rule ID 8016 // 27429 GIM_CheckFeatures, GIFBS_HasAVX512, 27430 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s32, 27431 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s32, 27432 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s32, 27433 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 27434 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR512RegClassID, 27435 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR512RegClassID, 27436 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::VR512RegClassID, 27437 // (strict_fma:{ *:[v16f32] } VR512:{ *:[v16f32] }:$src2, VR512:{ *:[v16f32] }:$src1, VR512:{ *:[v16f32] }:$src3) => (VFMADD213PSZr:{ *:[v16f32] } VR512:{ *:[v16f32] }:$src1, VR512:{ *:[v16f32] }:$src2, VR512:{ *:[v16f32] }:$src3) 27438 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VFMADD213PSZr, 27439 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 27440 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 27441 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src2 27442 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src3 27443 GIR_EraseFromParent, /*InsnID*/0, 27444 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 27445 // GIR_Coverage, 8016, 27446 GIR_Done, 27447 // Label 2355: @62247 27448 GIM_Reject, 27449 // Label 2325: @62248 27450 GIM_Try, /*On fail goto*//*Label 2356*/ 62304, // Rule ID 7977 // 27451 GIM_CheckFeatures, GIFBS_HasFP16, 27452 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v32s16, 27453 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v32s16, 27454 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v32s16, 27455 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 27456 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR512RegClassID, 27457 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR512RegClassID, 27458 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::VR512RegClassID, 27459 // (strict_fma:{ *:[v32f16] } VR512:{ *:[v32f16] }:$src2, VR512:{ *:[v32f16] }:$src1, VR512:{ *:[v32f16] }:$src3) => (VFMADD213PHZr:{ *:[v32f16] } VR512:{ *:[v32f16] }:$src1, VR512:{ *:[v32f16] }:$src2, VR512:{ *:[v32f16] }:$src3) 27460 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VFMADD213PHZr, 27461 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 27462 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 27463 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src2 27464 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src3 27465 GIR_EraseFromParent, /*InsnID*/0, 27466 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 27467 // GIR_Coverage, 7977, 27468 GIR_Done, 27469 // Label 2356: @62304 27470 GIM_Reject, 27471 // Label 2326: @62305 27472 GIM_Reject, 27473 // Label 60: @62306 27474 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/2, 23, /*)*//*default:*//*Label 2370*/ 63085, 27475 /*GILLT_s16*//*Label 2357*/ 62333, 27476 /*GILLT_s32*//*Label 2358*/ 62382, 27477 /*GILLT_s64*//*Label 2359*/ 62525, 27478 /*GILLT_s80*//*Label 2360*/ 62668, 0, 0, 27479 /*GILLT_v2s64*//*Label 2361*/ 62698, 0, 27480 /*GILLT_v4s32*//*Label 2362*/ 62772, 27481 /*GILLT_v4s64*//*Label 2363*/ 62846, 0, 27482 /*GILLT_v8s16*//*Label 2364*/ 62898, 27483 /*GILLT_v8s32*//*Label 2365*/ 62925, 27484 /*GILLT_v8s64*//*Label 2366*/ 62977, 0, 0, 27485 /*GILLT_v16s16*//*Label 2367*/ 63004, 27486 /*GILLT_v16s32*//*Label 2368*/ 63031, 0, 0, 27487 /*GILLT_v32s16*//*Label 2369*/ 63058, 27488 // Label 2357: @62333 27489 GIM_Try, /*On fail goto*//*Label 2371*/ 62381, // Rule ID 19873 // 27490 GIM_CheckFeatures, GIFBS_HasFP16, 27491 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16, 27492 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::FR16XRegClassID, 27493 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::FR16XRegClassID, 27494 // (strict_fsqrt:{ *:[f16] } FR16X:{ *:[f16] }:$src) => (VSQRTSHZr:{ *:[f16] } (IMPLICIT_DEF:{ *:[f16] }), FR16X:{ *:[f16] }:$src) 27495 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16, 27496 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, 27497 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 27498 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 27499 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VSQRTSHZr, 27500 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 27501 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 27502 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 27503 GIR_EraseFromParent, /*InsnID*/0, 27504 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 27505 // GIR_Coverage, 19873, 27506 GIR_Done, 27507 // Label 2371: @62381 27508 GIM_Reject, 27509 // Label 2358: @62382 27510 GIM_Try, /*On fail goto*//*Label 2372*/ 62524, 27511 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 27512 GIM_Try, /*On fail goto*//*Label 2373*/ 62413, // Rule ID 782 // 27513 GIM_CheckFeatures, GIFBS_FPStackf32, 27514 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::RFP32RegClassID, 27515 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::RFP32RegClassID, 27516 // (strict_fsqrt:{ *:[f32] } RFP32:{ *:[f32] }:$src) => (SQRT_Fp32:{ *:[f32] }:{ *:[i16] } RFP32:{ *:[f32] }:$src) 27517 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::SQRT_Fp32, 27518 GIR_AddImplicitDef, /*InsnID*/0, X86::FPSW, 27519 GIR_AddImplicitUse, /*InsnID*/0, X86::FPCW, 27520 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 27521 // GIR_Coverage, 782, 27522 GIR_Done, 27523 // Label 2373: @62413 27524 GIM_Try, /*On fail goto*//*Label 2374*/ 62435, // Rule ID 2138 // 27525 GIM_CheckFeatures, GIFBS_UseSSE1, 27526 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::FR32RegClassID, 27527 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::FR32RegClassID, 27528 // (strict_fsqrt:{ *:[f32] } FR32:{ *:[f32] }:$src1) => (SQRTSSr:{ *:[f32] } FR32:{ *:[f32] }:$src1) 27529 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::SQRTSSr, 27530 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 27531 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 27532 // GIR_Coverage, 2138, 27533 GIR_Done, 27534 // Label 2374: @62435 27535 GIM_Try, /*On fail goto*//*Label 2375*/ 62479, // Rule ID 16721 // 27536 GIM_CheckFeatures, GIFBS_UseAVX, 27537 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::FR32RegClassID, 27538 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::FR32RegClassID, 27539 // (strict_fsqrt:{ *:[f32] } FR32:{ *:[f32] }:$src) => (VSQRTSSr:{ *:[f32] } (IMPLICIT_DEF:{ *:[f32] }), FR32:{ *:[f32] }:$src) 27540 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, 27541 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, 27542 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 27543 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 27544 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VSQRTSSr, 27545 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 27546 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 27547 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 27548 GIR_EraseFromParent, /*InsnID*/0, 27549 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 27550 // GIR_Coverage, 16721, 27551 GIR_Done, 27552 // Label 2375: @62479 27553 GIM_Try, /*On fail goto*//*Label 2376*/ 62523, // Rule ID 19877 // 27554 GIM_CheckFeatures, GIFBS_HasAVX512, 27555 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::FR32XRegClassID, 27556 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::FR32XRegClassID, 27557 // (strict_fsqrt:{ *:[f32] } FR32X:{ *:[f32] }:$src) => (VSQRTSSZr:{ *:[f32] } (IMPLICIT_DEF:{ *:[f32] }), FR32X:{ *:[f32] }:$src) 27558 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, 27559 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, 27560 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 27561 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 27562 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VSQRTSSZr, 27563 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 27564 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 27565 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 27566 GIR_EraseFromParent, /*InsnID*/0, 27567 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 27568 // GIR_Coverage, 19877, 27569 GIR_Done, 27570 // Label 2376: @62523 27571 GIM_Reject, 27572 // Label 2372: @62524 27573 GIM_Reject, 27574 // Label 2359: @62525 27575 GIM_Try, /*On fail goto*//*Label 2377*/ 62667, 27576 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 27577 GIM_Try, /*On fail goto*//*Label 2378*/ 62556, // Rule ID 784 // 27578 GIM_CheckFeatures, GIFBS_FPStackf64, 27579 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::RFP64RegClassID, 27580 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::RFP64RegClassID, 27581 // (strict_fsqrt:{ *:[f64] } RFP64:{ *:[f64] }:$src) => (SQRT_Fp64:{ *:[f64] }:{ *:[i16] } RFP64:{ *:[f64] }:$src) 27582 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::SQRT_Fp64, 27583 GIR_AddImplicitDef, /*InsnID*/0, X86::FPSW, 27584 GIR_AddImplicitUse, /*InsnID*/0, X86::FPCW, 27585 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 27586 // GIR_Coverage, 784, 27587 GIR_Done, 27588 // Label 2378: @62556 27589 GIM_Try, /*On fail goto*//*Label 2379*/ 62578, // Rule ID 2154 // 27590 GIM_CheckFeatures, GIFBS_UseSSE2, 27591 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::FR64RegClassID, 27592 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::FR64RegClassID, 27593 // (strict_fsqrt:{ *:[f64] } FR64:{ *:[f64] }:$src1) => (SQRTSDr:{ *:[f64] } FR64:{ *:[f64] }:$src1) 27594 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::SQRTSDr, 27595 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 27596 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 27597 // GIR_Coverage, 2154, 27598 GIR_Done, 27599 // Label 2379: @62578 27600 GIM_Try, /*On fail goto*//*Label 2380*/ 62622, // Rule ID 16725 // 27601 GIM_CheckFeatures, GIFBS_UseAVX, 27602 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::FR64RegClassID, 27603 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::FR64RegClassID, 27604 // (strict_fsqrt:{ *:[f64] } FR64:{ *:[f64] }:$src) => (VSQRTSDr:{ *:[f64] } (IMPLICIT_DEF:{ *:[f64] }), FR64:{ *:[f64] }:$src) 27605 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, 27606 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, 27607 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 27608 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 27609 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VSQRTSDr, 27610 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 27611 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 27612 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 27613 GIR_EraseFromParent, /*InsnID*/0, 27614 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 27615 // GIR_Coverage, 16725, 27616 GIR_Done, 27617 // Label 2380: @62622 27618 GIM_Try, /*On fail goto*//*Label 2381*/ 62666, // Rule ID 19881 // 27619 GIM_CheckFeatures, GIFBS_HasAVX512, 27620 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::FR64XRegClassID, 27621 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::FR64XRegClassID, 27622 // (strict_fsqrt:{ *:[f64] } FR64X:{ *:[f64] }:$src) => (VSQRTSDZr:{ *:[f64] } (IMPLICIT_DEF:{ *:[f64] }), FR64X:{ *:[f64] }:$src) 27623 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, 27624 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, 27625 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 27626 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 27627 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VSQRTSDZr, 27628 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 27629 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 27630 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 27631 GIR_EraseFromParent, /*InsnID*/0, 27632 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 27633 // GIR_Coverage, 19881, 27634 GIR_Done, 27635 // Label 2381: @62666 27636 GIM_Reject, 27637 // Label 2377: @62667 27638 GIM_Reject, 27639 // Label 2360: @62668 27640 GIM_Try, /*On fail goto*//*Label 2382*/ 62697, // Rule ID 786 // 27641 GIM_CheckFeatures, GIFBS_HasX87, 27642 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s80, 27643 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::RFP80RegClassID, 27644 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::RFP80RegClassID, 27645 // (strict_fsqrt:{ *:[f80] } RFP80:{ *:[f80] }:$src) => (SQRT_Fp80:{ *:[f80] }:{ *:[i16] } RFP80:{ *:[f80] }:$src) 27646 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::SQRT_Fp80, 27647 GIR_AddImplicitDef, /*InsnID*/0, X86::FPSW, 27648 GIR_AddImplicitUse, /*InsnID*/0, X86::FPCW, 27649 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 27650 // GIR_Coverage, 786, 27651 GIR_Done, 27652 // Label 2382: @62697 27653 GIM_Reject, 27654 // Label 2361: @62698 27655 GIM_Try, /*On fail goto*//*Label 2383*/ 62771, 27656 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, 27657 GIM_Try, /*On fail goto*//*Label 2384*/ 62726, // Rule ID 2158 // 27658 GIM_CheckFeatures, GIFBS_HasAVX_NoVLX, 27659 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 27660 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 27661 // (strict_fsqrt:{ *:[v2f64] } VR128:{ *:[v2f64] }:$src) => (VSQRTPDr:{ *:[v2f64] } VR128:{ *:[v2f64] }:$src) 27662 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VSQRTPDr, 27663 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 27664 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 27665 // GIR_Coverage, 2158, 27666 GIR_Done, 27667 // Label 2384: @62726 27668 GIM_Try, /*On fail goto*//*Label 2385*/ 62748, // Rule ID 2166 // 27669 GIM_CheckFeatures, GIFBS_UseSSE2, 27670 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 27671 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 27672 // (strict_fsqrt:{ *:[v2f64] } VR128:{ *:[v2f64] }:$src) => (SQRTPDr:{ *:[v2f64] } VR128:{ *:[v2f64] }:$src) 27673 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::SQRTPDr, 27674 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 27675 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 27676 // GIR_Coverage, 2166, 27677 GIR_Done, 27678 // Label 2385: @62748 27679 GIM_Try, /*On fail goto*//*Label 2386*/ 62770, // Rule ID 11787 // 27680 GIM_CheckFeatures, GIFBS_HasVLX, 27681 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID, 27682 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID, 27683 // (strict_fsqrt:{ *:[v2f64] } VR128X:{ *:[v2f64] }:$src) => (VSQRTPDZ128r:{ *:[v2f64] } VR128X:{ *:[v2f64] }:$src) 27684 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VSQRTPDZ128r, 27685 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 27686 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 27687 // GIR_Coverage, 11787, 27688 GIR_Done, 27689 // Label 2386: @62770 27690 GIM_Reject, 27691 // Label 2383: @62771 27692 GIM_Reject, 27693 // Label 2362: @62772 27694 GIM_Try, /*On fail goto*//*Label 2387*/ 62845, 27695 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, 27696 GIM_Try, /*On fail goto*//*Label 2388*/ 62800, // Rule ID 2142 // 27697 GIM_CheckFeatures, GIFBS_HasAVX_NoVLX, 27698 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 27699 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 27700 // (strict_fsqrt:{ *:[v4f32] } VR128:{ *:[v4f32] }:$src) => (VSQRTPSr:{ *:[v4f32] } VR128:{ *:[v4f32] }:$src) 27701 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VSQRTPSr, 27702 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 27703 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 27704 // GIR_Coverage, 2142, 27705 GIR_Done, 27706 // Label 2388: @62800 27707 GIM_Try, /*On fail goto*//*Label 2389*/ 62822, // Rule ID 2150 // 27708 GIM_CheckFeatures, GIFBS_UseSSE1, 27709 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 27710 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 27711 // (strict_fsqrt:{ *:[v4f32] } VR128:{ *:[v4f32] }:$src) => (SQRTPSr:{ *:[v4f32] } VR128:{ *:[v4f32] }:$src) 27712 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::SQRTPSr, 27713 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 27714 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 27715 // GIR_Coverage, 2150, 27716 GIR_Done, 27717 // Label 2389: @62822 27718 GIM_Try, /*On fail goto*//*Label 2390*/ 62844, // Rule ID 11763 // 27719 GIM_CheckFeatures, GIFBS_HasVLX, 27720 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID, 27721 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID, 27722 // (strict_fsqrt:{ *:[v4f32] } VR128X:{ *:[v4f32] }:$src) => (VSQRTPSZ128r:{ *:[v4f32] } VR128X:{ *:[v4f32] }:$src) 27723 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VSQRTPSZ128r, 27724 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 27725 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 27726 // GIR_Coverage, 11763, 27727 GIR_Done, 27728 // Label 2390: @62844 27729 GIM_Reject, 27730 // Label 2387: @62845 27731 GIM_Reject, 27732 // Label 2363: @62846 27733 GIM_Try, /*On fail goto*//*Label 2391*/ 62897, 27734 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s64, 27735 GIM_Try, /*On fail goto*//*Label 2392*/ 62874, // Rule ID 2162 // 27736 GIM_CheckFeatures, GIFBS_HasAVX_NoVLX, 27737 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID, 27738 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256RegClassID, 27739 // (strict_fsqrt:{ *:[v4f64] } VR256:{ *:[v4f64] }:$src) => (VSQRTPDYr:{ *:[v4f64] } VR256:{ *:[v4f64] }:$src) 27740 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VSQRTPDYr, 27741 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 27742 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 27743 // GIR_Coverage, 2162, 27744 GIR_Done, 27745 // Label 2392: @62874 27746 GIM_Try, /*On fail goto*//*Label 2393*/ 62896, // Rule ID 11799 // 27747 GIM_CheckFeatures, GIFBS_HasVLX, 27748 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID, 27749 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID, 27750 // (strict_fsqrt:{ *:[v4f64] } VR256X:{ *:[v4f64] }:$src) => (VSQRTPDZ256r:{ *:[v4f64] } VR256X:{ *:[v4f64] }:$src) 27751 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VSQRTPDZ256r, 27752 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 27753 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 27754 // GIR_Coverage, 11799, 27755 GIR_Done, 27756 // Label 2393: @62896 27757 GIM_Reject, 27758 // Label 2391: @62897 27759 GIM_Reject, 27760 // Label 2364: @62898 27761 GIM_Try, /*On fail goto*//*Label 2394*/ 62924, // Rule ID 11715 // 27762 GIM_CheckFeatures, GIFBS_HasFP16_HasVLX, 27763 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, 27764 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID, 27765 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID, 27766 // (strict_fsqrt:{ *:[v8f16] } VR128X:{ *:[v8f16] }:$src) => (VSQRTPHZ128r:{ *:[v8f16] } VR128X:{ *:[v8f16] }:$src) 27767 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VSQRTPHZ128r, 27768 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 27769 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 27770 // GIR_Coverage, 11715, 27771 GIR_Done, 27772 // Label 2394: @62924 27773 GIM_Reject, 27774 // Label 2365: @62925 27775 GIM_Try, /*On fail goto*//*Label 2395*/ 62976, 27776 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s32, 27777 GIM_Try, /*On fail goto*//*Label 2396*/ 62953, // Rule ID 2146 // 27778 GIM_CheckFeatures, GIFBS_HasAVX_NoVLX, 27779 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID, 27780 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256RegClassID, 27781 // (strict_fsqrt:{ *:[v8f32] } VR256:{ *:[v8f32] }:$src) => (VSQRTPSYr:{ *:[v8f32] } VR256:{ *:[v8f32] }:$src) 27782 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VSQRTPSYr, 27783 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 27784 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 27785 // GIR_Coverage, 2146, 27786 GIR_Done, 27787 // Label 2396: @62953 27788 GIM_Try, /*On fail goto*//*Label 2397*/ 62975, // Rule ID 11775 // 27789 GIM_CheckFeatures, GIFBS_HasVLX, 27790 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID, 27791 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID, 27792 // (strict_fsqrt:{ *:[v8f32] } VR256X:{ *:[v8f32] }:$src) => (VSQRTPSZ256r:{ *:[v8f32] } VR256X:{ *:[v8f32] }:$src) 27793 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VSQRTPSZ256r, 27794 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 27795 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 27796 // GIR_Coverage, 11775, 27797 GIR_Done, 27798 // Label 2397: @62975 27799 GIM_Reject, 27800 // Label 2395: @62976 27801 GIM_Reject, 27802 // Label 2366: @62977 27803 GIM_Try, /*On fail goto*//*Label 2398*/ 63003, // Rule ID 11751 // 27804 GIM_CheckFeatures, GIFBS_HasAVX512, 27805 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s64, 27806 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 27807 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR512RegClassID, 27808 // (strict_fsqrt:{ *:[v8f64] } VR512:{ *:[v8f64] }:$src) => (VSQRTPDZr:{ *:[v8f64] } VR512:{ *:[v8f64] }:$src) 27809 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VSQRTPDZr, 27810 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 27811 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 27812 // GIR_Coverage, 11751, 27813 GIR_Done, 27814 // Label 2398: @63003 27815 GIM_Reject, 27816 // Label 2367: @63004 27817 GIM_Try, /*On fail goto*//*Label 2399*/ 63030, // Rule ID 11727 // 27818 GIM_CheckFeatures, GIFBS_HasFP16_HasVLX, 27819 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s16, 27820 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID, 27821 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID, 27822 // (strict_fsqrt:{ *:[v16f16] } VR256X:{ *:[v16f16] }:$src) => (VSQRTPHZ256r:{ *:[v16f16] } VR256X:{ *:[v16f16] }:$src) 27823 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VSQRTPHZ256r, 27824 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 27825 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 27826 // GIR_Coverage, 11727, 27827 GIR_Done, 27828 // Label 2399: @63030 27829 GIM_Reject, 27830 // Label 2368: @63031 27831 GIM_Try, /*On fail goto*//*Label 2400*/ 63057, // Rule ID 11739 // 27832 GIM_CheckFeatures, GIFBS_HasAVX512, 27833 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s32, 27834 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 27835 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR512RegClassID, 27836 // (strict_fsqrt:{ *:[v16f32] } VR512:{ *:[v16f32] }:$src) => (VSQRTPSZr:{ *:[v16f32] } VR512:{ *:[v16f32] }:$src) 27837 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VSQRTPSZr, 27838 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 27839 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 27840 // GIR_Coverage, 11739, 27841 GIR_Done, 27842 // Label 2400: @63057 27843 GIM_Reject, 27844 // Label 2369: @63058 27845 GIM_Try, /*On fail goto*//*Label 2401*/ 63084, // Rule ID 11703 // 27846 GIM_CheckFeatures, GIFBS_HasFP16, 27847 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v32s16, 27848 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 27849 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR512RegClassID, 27850 // (strict_fsqrt:{ *:[v32f16] } VR512:{ *:[v32f16] }:$src) => (VSQRTPHZr:{ *:[v32f16] } VR512:{ *:[v32f16] }:$src) 27851 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VSQRTPHZr, 27852 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 27853 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 27854 // GIR_Coverage, 11703, 27855 GIR_Done, 27856 // Label 2401: @63084 27857 GIM_Reject, 27858 // Label 2370: @63085 27859 GIM_Reject, 27860 // Label 61: @63086 27861 GIM_Reject, 27862 }; 27863 return MatchTable0; 27864} 27865#endif // ifdef GET_GLOBALISEL_IMPL 27866#ifdef GET_GLOBALISEL_PREDICATES_DECL 27867PredicateBitset AvailableModuleFeatures; 27868mutable PredicateBitset AvailableFunctionFeatures; 27869PredicateBitset getAvailableFeatures() const { 27870 return AvailableModuleFeatures | AvailableFunctionFeatures; 27871} 27872PredicateBitset 27873computeAvailableModuleFeatures(const X86Subtarget *Subtarget) const; 27874PredicateBitset 27875computeAvailableFunctionFeatures(const X86Subtarget *Subtarget, 27876 const MachineFunction *MF) const; 27877void setupGeneratedPerFunctionState(MachineFunction &MF) override; 27878#endif // ifdef GET_GLOBALISEL_PREDICATES_DECL 27879#ifdef GET_GLOBALISEL_PREDICATES_INIT 27880AvailableModuleFeatures(computeAvailableModuleFeatures(&STI)), 27881AvailableFunctionFeatures() 27882#endif // ifdef GET_GLOBALISEL_PREDICATES_INIT 27883