1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ 2|* *| 3|* Register Bank Source Fragments *| 4|* *| 5|* Automatically generated file, do not edit! *| 6|* *| 7\*===----------------------------------------------------------------------===*/ 8 9#ifdef GET_REGBANK_DECLARATIONS 10#undef GET_REGBANK_DECLARATIONS 11namespace llvm { 12namespace X86 { 13enum : unsigned { 14 InvalidRegBankID = ~0u, 15 GPRRegBankID = 0, 16 VECRRegBankID = 1, 17 NumRegisterBanks, 18}; 19} // end namespace X86 20} // end namespace llvm 21#endif // GET_REGBANK_DECLARATIONS 22 23#ifdef GET_TARGET_REGBANK_CLASS 24#undef GET_TARGET_REGBANK_CLASS 25private: 26 static RegisterBank *RegBanks[]; 27 28protected: 29 X86GenRegisterBankInfo(); 30 31#endif // GET_TARGET_REGBANK_CLASS 32 33#ifdef GET_TARGET_REGBANK_IMPL 34#undef GET_TARGET_REGBANK_IMPL 35namespace llvm { 36namespace X86 { 37const uint32_t GPRRegBankCoverageData[] = { 38 // 0-31 39 (1u << (X86::GR8RegClassID - 0)) | 40 (1u << (X86::GR16RegClassID - 0)) | 41 (1u << (X86::LOW32_ADDR_ACCESS_RBPRegClassID - 0)) | 42 (1u << (X86::LOW32_ADDR_ACCESSRegClassID - 0)) | 43 (1u << (X86::GR8_NOREXRegClassID - 0)) | 44 (1u << (X86::GR8_ABCD_HRegClassID - 0)) | 45 (1u << (X86::GR8_ABCD_LRegClassID - 0)) | 46 (1u << (X86::GR16_NOREXRegClassID - 0)) | 47 (1u << (X86::GR16_ABCDRegClassID - 0)) | 48 0, 49 // 32-63 50 (1u << (X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID - 32)) | 51 (1u << (X86::GR32RegClassID - 32)) | 52 (1u << (X86::GR32_NOSPRegClassID - 32)) | 53 (1u << (X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClassID - 32)) | 54 (1u << (X86::GR32_NOREXRegClassID - 32)) | 55 (1u << (X86::GR32_NOREX_NOSPRegClassID - 32)) | 56 (1u << (X86::GR32_ABCDRegClassID - 32)) | 57 (1u << (X86::GR32_TCRegClassID - 32)) | 58 (1u << (X86::GR32_ABCD_and_GR32_TCRegClassID - 32)) | 59 (1u << (X86::GR32_ADRegClassID - 32)) | 60 (1u << (X86::GR32_DCRegClassID - 32)) | 61 (1u << (X86::GR32_AD_and_GR32_DCRegClassID - 32)) | 62 (1u << (X86::GR32_CBRegClassID - 32)) | 63 (1u << (X86::GR32_CB_and_GR32_DCRegClassID - 32)) | 64 (1u << (X86::GR32_SIDIRegClassID - 32)) | 65 (1u << (X86::GR32_BSIRegClassID - 32)) | 66 (1u << (X86::GR32_BSI_and_GR32_SIDIRegClassID - 32)) | 67 (1u << (X86::GR32_DIBPRegClassID - 32)) | 68 (1u << (X86::GR32_DIBP_and_GR32_SIDIRegClassID - 32)) | 69 (1u << (X86::GR32_ABCD_and_GR32_BSIRegClassID - 32)) | 70 (1u << (X86::GR32_BPSPRegClassID - 32)) | 71 (1u << (X86::GR32_BPSP_and_GR32_DIBPRegClassID - 32)) | 72 (1u << (X86::GR32_BPSP_and_GR32_TCRegClassID - 32)) | 73 0, 74 // 64-95 75 (1u << (X86::GR64RegClassID - 64)) | 76 (1u << (X86::GR64_with_sub_8bitRegClassID - 64)) | 77 (1u << (X86::GR64_NOSPRegClassID - 64)) | 78 (1u << (X86::GR64PLTSafeRegClassID - 64)) | 79 (1u << (X86::GR64PLTSafe_and_GR64_TCRegClassID - 64)) | 80 (1u << (X86::GR64PLTSafe_and_GR64_TCW64RegClassID - 64)) | 81 (1u << (X86::GR64_NOREX_and_GR64PLTSafe_and_GR64_TCRegClassID - 64)) | 82 (1u << (X86::GR64_NOREX_NOSPRegClassID - 64)) | 83 (1u << (X86::GR64_ABCDRegClassID - 64)) | 84 (1u << (X86::GR64_NOSP_and_GR64_TCRegClassID - 64)) | 85 (1u << (X86::GR64_TC_and_GR64_NOSP_and_GR64_TCW64RegClassID - 64)) | 86 (1u << (X86::GR64_NOSP_and_GR64_TCW64RegClassID - 64)) | 87 (1u << (X86::GR64_TC_with_sub_8bitRegClassID - 64)) | 88 (1u << (X86::GR64_TCW64_and_GR64_TC_with_sub_8bitRegClassID - 64)) | 89 (1u << (X86::GR64_with_sub_32bit_in_GR32_TCRegClassID - 64)) | 90 (1u << (X86::GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXRegClassID - 64)) | 91 (1u << (X86::GR64_TCW64_with_sub_8bitRegClassID - 64)) | 92 (1u << (X86::GR64_with_sub_16bit_in_GR16_NOREXRegClassID - 64)) | 93 (1u << (X86::GR64_TCRegClassID - 64)) | 94 (1u << (X86::GR64_TC_and_GR64_TCW64RegClassID - 64)) | 95 (1u << (X86::GR64_NOREX_and_GR64_TCW64RegClassID - 64)) | 96 (1u << (X86::GR64_NOREX_and_GR64_TCRegClassID - 64)) | 97 (1u << (X86::GR64_NOREXRegClassID - 64)) | 98 (1u << (X86::GR64_TCW64RegClassID - 64)) | 99 0, 100 // 96-127 101 (1u << (X86::GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TCRegClassID - 96)) | 102 (1u << (X86::GR64_ADRegClassID - 96)) | 103 (1u << (X86::GR64_with_sub_32bit_in_GR32_AD_and_GR32_DCRegClassID - 96)) | 104 (1u << (X86::GR64_with_sub_32bit_in_GR32_DCRegClassID - 96)) | 105 (1u << (X86::GR64_with_sub_32bit_in_GR32_CB_and_GR32_DCRegClassID - 96)) | 106 (1u << (X86::GR64_with_sub_32bit_in_GR32_SIDIRegClassID - 96)) | 107 (1u << (X86::GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDIRegClassID - 96)) | 108 (1u << (X86::GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDIRegClassID - 96)) | 109 (1u << (X86::GR64_with_sub_32bit_in_GR32_CBRegClassID - 96)) | 110 (1u << (X86::GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSIRegClassID - 96)) | 111 (1u << (X86::GR64_with_sub_32bit_in_GR32_BSIRegClassID - 96)) | 112 (1u << (X86::GR64_with_sub_32bit_in_GR32_DIBPRegClassID - 96)) | 113 (1u << (X86::GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBPRegClassID - 96)) | 114 (1u << (X86::GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TCRegClassID - 96)) | 115 (1u << (X86::GR64_with_sub_32bit_in_GR32_BPSPRegClassID - 96)) | 116 (1u << (X86::GR64_and_LOW32_ADDR_ACCESSRegClassID - 96)) | 117 (1u << (X86::GR64_and_LOW32_ADDR_ACCESS_RBPRegClassID - 96)) | 118 0, 119}; 120const uint32_t VECRRegBankCoverageData[] = { 121 // 0-31 122 (1u << (X86::FR16XRegClassID - 0)) | 123 (1u << (X86::FR32XRegClassID - 0)) | 124 (1u << (X86::FR16RegClassID - 0)) | 125 0, 126 // 32-63 127 (1u << (X86::FR32RegClassID - 32)) | 128 0, 129 // 64-95 130 (1u << (X86::FR64XRegClassID - 64)) | 131 (1u << (X86::FR64RegClassID - 64)) | 132 0, 133 // 96-127 134 (1u << (X86::VR512RegClassID - 96)) | 135 (1u << (X86::VR128XRegClassID - 96)) | 136 (1u << (X86::VR256XRegClassID - 96)) | 137 (1u << (X86::VR512_0_15RegClassID - 96)) | 138 (1u << (X86::VR128RegClassID - 96)) | 139 (1u << (X86::VR256RegClassID - 96)) | 140 0, 141}; 142 143RegisterBank GPRRegBank(/* ID */ X86::GPRRegBankID, /* Name */ "GPR", /* Size */ 64, /* CoveredRegClasses */ GPRRegBankCoverageData, /* NumRegClasses */ 123); 144RegisterBank VECRRegBank(/* ID */ X86::VECRRegBankID, /* Name */ "VECR", /* Size */ 512, /* CoveredRegClasses */ VECRRegBankCoverageData, /* NumRegClasses */ 123); 145} // end namespace X86 146 147RegisterBank *X86GenRegisterBankInfo::RegBanks[] = { 148 &X86::GPRRegBank, 149 &X86::VECRRegBank, 150}; 151 152X86GenRegisterBankInfo::X86GenRegisterBankInfo() 153 : RegisterBankInfo(RegBanks, X86::NumRegisterBanks) { 154 // Assert that RegBank indices match their ID's 155#ifndef NDEBUG 156 for (auto RB : enumerate(RegBanks)) 157 assert(RB.index() == RB.value()->getID() && "Index != ID"); 158#endif // NDEBUG 159} 160} // end namespace llvm 161#endif // GET_TARGET_REGBANK_IMPL 162