1 //===-- AArch64TargetMachine.cpp - Define TargetMachine for AArch64 -------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 //
10 //===----------------------------------------------------------------------===//
11
12 #include "AArch64TargetMachine.h"
13 #include "AArch64.h"
14 #include "AArch64MachineFunctionInfo.h"
15 #include "AArch64MachineScheduler.h"
16 #include "AArch64MacroFusion.h"
17 #include "AArch64Subtarget.h"
18 #include "AArch64TargetObjectFile.h"
19 #include "AArch64TargetTransformInfo.h"
20 #include "MCTargetDesc/AArch64MCTargetDesc.h"
21 #include "TargetInfo/AArch64TargetInfo.h"
22 #include "llvm/ADT/STLExtras.h"
23 #include "llvm/ADT/Triple.h"
24 #include "llvm/Analysis/TargetTransformInfo.h"
25 #include "llvm/CodeGen/CFIFixup.h"
26 #include "llvm/CodeGen/CSEConfigBase.h"
27 #include "llvm/CodeGen/GlobalISel/CSEInfo.h"
28 #include "llvm/CodeGen/GlobalISel/IRTranslator.h"
29 #include "llvm/CodeGen/GlobalISel/InstructionSelect.h"
30 #include "llvm/CodeGen/GlobalISel/Legalizer.h"
31 #include "llvm/CodeGen/GlobalISel/LoadStoreOpt.h"
32 #include "llvm/CodeGen/GlobalISel/Localizer.h"
33 #include "llvm/CodeGen/GlobalISel/RegBankSelect.h"
34 #include "llvm/CodeGen/MIRParser/MIParser.h"
35 #include "llvm/CodeGen/MachineScheduler.h"
36 #include "llvm/CodeGen/Passes.h"
37 #include "llvm/CodeGen/TargetInstrInfo.h"
38 #include "llvm/CodeGen/TargetPassConfig.h"
39 #include "llvm/IR/Attributes.h"
40 #include "llvm/IR/Function.h"
41 #include "llvm/InitializePasses.h"
42 #include "llvm/MC/MCAsmInfo.h"
43 #include "llvm/MC/MCTargetOptions.h"
44 #include "llvm/MC/TargetRegistry.h"
45 #include "llvm/Pass.h"
46 #include "llvm/Support/CodeGen.h"
47 #include "llvm/Support/CommandLine.h"
48 #include "llvm/Target/TargetLoweringObjectFile.h"
49 #include "llvm/Target/TargetOptions.h"
50 #include "llvm/Transforms/CFGuard.h"
51 #include "llvm/Transforms/Scalar.h"
52 #include <memory>
53 #include <optional>
54 #include <string>
55
56 using namespace llvm;
57
58 static cl::opt<bool> EnableCCMP("aarch64-enable-ccmp",
59 cl::desc("Enable the CCMP formation pass"),
60 cl::init(true), cl::Hidden);
61
62 static cl::opt<bool>
63 EnableCondBrTuning("aarch64-enable-cond-br-tune",
64 cl::desc("Enable the conditional branch tuning pass"),
65 cl::init(true), cl::Hidden);
66
67 static cl::opt<bool> EnableAArch64CopyPropagation(
68 "aarch64-enable-copy-propagation",
69 cl::desc("Enable the copy propagation with AArch64 copy instr"),
70 cl::init(true), cl::Hidden);
71
72 static cl::opt<bool> EnableMCR("aarch64-enable-mcr",
73 cl::desc("Enable the machine combiner pass"),
74 cl::init(true), cl::Hidden);
75
76 static cl::opt<bool> EnableStPairSuppress("aarch64-enable-stp-suppress",
77 cl::desc("Suppress STP for AArch64"),
78 cl::init(true), cl::Hidden);
79
80 static cl::opt<bool> EnableAdvSIMDScalar(
81 "aarch64-enable-simd-scalar",
82 cl::desc("Enable use of AdvSIMD scalar integer instructions"),
83 cl::init(false), cl::Hidden);
84
85 static cl::opt<bool>
86 EnablePromoteConstant("aarch64-enable-promote-const",
87 cl::desc("Enable the promote constant pass"),
88 cl::init(true), cl::Hidden);
89
90 static cl::opt<bool> EnableCollectLOH(
91 "aarch64-enable-collect-loh",
92 cl::desc("Enable the pass that emits the linker optimization hints (LOH)"),
93 cl::init(true), cl::Hidden);
94
95 static cl::opt<bool>
96 EnableDeadRegisterElimination("aarch64-enable-dead-defs", cl::Hidden,
97 cl::desc("Enable the pass that removes dead"
98 " definitons and replaces stores to"
99 " them with stores to the zero"
100 " register"),
101 cl::init(true));
102
103 static cl::opt<bool> EnableRedundantCopyElimination(
104 "aarch64-enable-copyelim",
105 cl::desc("Enable the redundant copy elimination pass"), cl::init(true),
106 cl::Hidden);
107
108 static cl::opt<bool> EnableLoadStoreOpt("aarch64-enable-ldst-opt",
109 cl::desc("Enable the load/store pair"
110 " optimization pass"),
111 cl::init(true), cl::Hidden);
112
113 static cl::opt<bool> EnableAtomicTidy(
114 "aarch64-enable-atomic-cfg-tidy", cl::Hidden,
115 cl::desc("Run SimplifyCFG after expanding atomic operations"
116 " to make use of cmpxchg flow-based information"),
117 cl::init(true));
118
119 static cl::opt<bool>
120 EnableEarlyIfConversion("aarch64-enable-early-ifcvt", cl::Hidden,
121 cl::desc("Run early if-conversion"),
122 cl::init(true));
123
124 static cl::opt<bool>
125 EnableCondOpt("aarch64-enable-condopt",
126 cl::desc("Enable the condition optimizer pass"),
127 cl::init(true), cl::Hidden);
128
129 static cl::opt<bool>
130 EnableGEPOpt("aarch64-enable-gep-opt", cl::Hidden,
131 cl::desc("Enable optimizations on complex GEPs"),
132 cl::init(false));
133
134 static cl::opt<bool>
135 EnableSelectOpt("aarch64-select-opt", cl::Hidden,
136 cl::desc("Enable select to branch optimizations"),
137 cl::init(true));
138
139 static cl::opt<bool>
140 BranchRelaxation("aarch64-enable-branch-relax", cl::Hidden, cl::init(true),
141 cl::desc("Relax out of range conditional branches"));
142
143 static cl::opt<bool> EnableCompressJumpTables(
144 "aarch64-enable-compress-jump-tables", cl::Hidden, cl::init(true),
145 cl::desc("Use smallest entry possible for jump tables"));
146
147 // FIXME: Unify control over GlobalMerge.
148 static cl::opt<cl::boolOrDefault>
149 EnableGlobalMerge("aarch64-enable-global-merge", cl::Hidden,
150 cl::desc("Enable the global merge pass"));
151
152 static cl::opt<bool>
153 EnableLoopDataPrefetch("aarch64-enable-loop-data-prefetch", cl::Hidden,
154 cl::desc("Enable the loop data prefetch pass"),
155 cl::init(true));
156
157 static cl::opt<int> EnableGlobalISelAtO(
158 "aarch64-enable-global-isel-at-O", cl::Hidden,
159 cl::desc("Enable GlobalISel at or below an opt level (-1 to disable)"),
160 cl::init(0));
161
162 static cl::opt<bool>
163 EnableSVEIntrinsicOpts("aarch64-enable-sve-intrinsic-opts", cl::Hidden,
164 cl::desc("Enable SVE intrinsic opts"),
165 cl::init(true));
166
167 static cl::opt<bool> EnableFalkorHWPFFix("aarch64-enable-falkor-hwpf-fix",
168 cl::init(true), cl::Hidden);
169
170 static cl::opt<bool>
171 EnableBranchTargets("aarch64-enable-branch-targets", cl::Hidden,
172 cl::desc("Enable the AArch64 branch target pass"),
173 cl::init(true));
174
175 static cl::opt<unsigned> SVEVectorBitsMaxOpt(
176 "aarch64-sve-vector-bits-max",
177 cl::desc("Assume SVE vector registers are at most this big, "
178 "with zero meaning no maximum size is assumed."),
179 cl::init(0), cl::Hidden);
180
181 static cl::opt<unsigned> SVEVectorBitsMinOpt(
182 "aarch64-sve-vector-bits-min",
183 cl::desc("Assume SVE vector registers are at least this big, "
184 "with zero meaning no minimum size is assumed."),
185 cl::init(0), cl::Hidden);
186
187 extern cl::opt<bool> EnableHomogeneousPrologEpilog;
188
189 static cl::opt<bool> EnableGISelLoadStoreOptPreLegal(
190 "aarch64-enable-gisel-ldst-prelegal",
191 cl::desc("Enable GlobalISel's pre-legalizer load/store optimization pass"),
192 cl::init(true), cl::Hidden);
193
194 static cl::opt<bool> EnableGISelLoadStoreOptPostLegal(
195 "aarch64-enable-gisel-ldst-postlegal",
196 cl::desc("Enable GlobalISel's post-legalizer load/store optimization pass"),
197 cl::init(false), cl::Hidden);
198
LLVMInitializeAArch64Target()199 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAArch64Target() {
200 // Register the target.
201 RegisterTargetMachine<AArch64leTargetMachine> X(getTheAArch64leTarget());
202 RegisterTargetMachine<AArch64beTargetMachine> Y(getTheAArch64beTarget());
203 RegisterTargetMachine<AArch64leTargetMachine> Z(getTheARM64Target());
204 RegisterTargetMachine<AArch64leTargetMachine> W(getTheARM64_32Target());
205 RegisterTargetMachine<AArch64leTargetMachine> V(getTheAArch64_32Target());
206 auto PR = PassRegistry::getPassRegistry();
207 initializeGlobalISel(*PR);
208 initializeAArch64A53Fix835769Pass(*PR);
209 initializeAArch64A57FPLoadBalancingPass(*PR);
210 initializeAArch64AdvSIMDScalarPass(*PR);
211 initializeAArch64BranchTargetsPass(*PR);
212 initializeAArch64CollectLOHPass(*PR);
213 initializeAArch64CompressJumpTablesPass(*PR);
214 initializeAArch64ConditionalComparesPass(*PR);
215 initializeAArch64ConditionOptimizerPass(*PR);
216 initializeAArch64DeadRegisterDefinitionsPass(*PR);
217 initializeAArch64ExpandPseudoPass(*PR);
218 initializeAArch64KCFIPass(*PR);
219 initializeAArch64LoadStoreOptPass(*PR);
220 initializeAArch64MIPeepholeOptPass(*PR);
221 initializeAArch64SIMDInstrOptPass(*PR);
222 initializeAArch64O0PreLegalizerCombinerPass(*PR);
223 initializeAArch64PreLegalizerCombinerPass(*PR);
224 initializeAArch64PostLegalizerCombinerPass(*PR);
225 initializeAArch64PostLegalizerLoweringPass(*PR);
226 initializeAArch64PostSelectOptimizePass(*PR);
227 initializeAArch64PromoteConstantPass(*PR);
228 initializeAArch64RedundantCopyEliminationPass(*PR);
229 initializeAArch64StorePairSuppressPass(*PR);
230 initializeFalkorHWPFFixPass(*PR);
231 initializeFalkorMarkStridedAccessesLegacyPass(*PR);
232 initializeLDTLSCleanupPass(*PR);
233 initializeSMEABIPass(*PR);
234 initializeSVEIntrinsicOptsPass(*PR);
235 initializeAArch64SpeculationHardeningPass(*PR);
236 initializeAArch64SLSHardeningPass(*PR);
237 initializeAArch64StackTaggingPass(*PR);
238 initializeAArch64StackTaggingPreRAPass(*PR);
239 initializeAArch64LowerHomogeneousPrologEpilogPass(*PR);
240 initializeAArch64DAGToDAGISelPass(*PR);
241 }
242
243 //===----------------------------------------------------------------------===//
244 // AArch64 Lowering public interface.
245 //===----------------------------------------------------------------------===//
createTLOF(const Triple & TT)246 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
247 if (TT.isOSBinFormatMachO())
248 return std::make_unique<AArch64_MachoTargetObjectFile>();
249 if (TT.isOSBinFormatCOFF())
250 return std::make_unique<AArch64_COFFTargetObjectFile>();
251
252 return std::make_unique<AArch64_ELFTargetObjectFile>();
253 }
254
255 // Helper function to build a DataLayout string
computeDataLayout(const Triple & TT,const MCTargetOptions & Options,bool LittleEndian)256 static std::string computeDataLayout(const Triple &TT,
257 const MCTargetOptions &Options,
258 bool LittleEndian) {
259 if (TT.isOSBinFormatMachO()) {
260 if (TT.getArch() == Triple::aarch64_32)
261 return "e-m:o-p:32:32-i64:64-i128:128-n32:64-S128";
262 return "e-m:o-i64:64-i128:128-n32:64-S128";
263 }
264 if (TT.isOSBinFormatCOFF())
265 return "e-m:w-p:64:64-i32:32-i64:64-i128:128-n32:64-S128";
266 std::string Endian = LittleEndian ? "e" : "E";
267 std::string Ptr32 = TT.getEnvironment() == Triple::GNUILP32 ? "-p:32:32" : "";
268 return Endian + "-m:e" + Ptr32 +
269 "-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128";
270 }
271
computeDefaultCPU(const Triple & TT,StringRef CPU)272 static StringRef computeDefaultCPU(const Triple &TT, StringRef CPU) {
273 if (CPU.empty() && TT.isArm64e())
274 return "apple-a12";
275 return CPU;
276 }
277
getEffectiveRelocModel(const Triple & TT,std::optional<Reloc::Model> RM)278 static Reloc::Model getEffectiveRelocModel(const Triple &TT,
279 std::optional<Reloc::Model> RM) {
280 // AArch64 Darwin and Windows are always PIC.
281 if (TT.isOSDarwin() || TT.isOSWindows())
282 return Reloc::PIC_;
283 // On ELF platforms the default static relocation model has a smart enough
284 // linker to cope with referencing external symbols defined in a shared
285 // library. Hence DynamicNoPIC doesn't need to be promoted to PIC.
286 if (!RM || *RM == Reloc::DynamicNoPIC)
287 return Reloc::Static;
288 return *RM;
289 }
290
291 static CodeModel::Model
getEffectiveAArch64CodeModel(const Triple & TT,std::optional<CodeModel::Model> CM,bool JIT)292 getEffectiveAArch64CodeModel(const Triple &TT,
293 std::optional<CodeModel::Model> CM, bool JIT) {
294 if (CM) {
295 if (*CM != CodeModel::Small && *CM != CodeModel::Tiny &&
296 *CM != CodeModel::Large) {
297 report_fatal_error(
298 "Only small, tiny and large code models are allowed on AArch64");
299 } else if (*CM == CodeModel::Tiny && !TT.isOSBinFormatELF())
300 report_fatal_error("tiny code model is only supported on ELF");
301 return *CM;
302 }
303 // The default MCJIT memory managers make no guarantees about where they can
304 // find an executable page; JITed code needs to be able to refer to globals
305 // no matter how far away they are.
306 // We should set the CodeModel::Small for Windows ARM64 in JIT mode,
307 // since with large code model LLVM generating 4 MOV instructions, and
308 // Windows doesn't support relocating these long branch (4 MOVs).
309 if (JIT && !TT.isOSWindows())
310 return CodeModel::Large;
311 return CodeModel::Small;
312 }
313
314 /// Create an AArch64 architecture model.
315 ///
AArch64TargetMachine(const Target & T,const Triple & TT,StringRef CPU,StringRef FS,const TargetOptions & Options,std::optional<Reloc::Model> RM,std::optional<CodeModel::Model> CM,CodeGenOpt::Level OL,bool JIT,bool LittleEndian)316 AArch64TargetMachine::AArch64TargetMachine(const Target &T, const Triple &TT,
317 StringRef CPU, StringRef FS,
318 const TargetOptions &Options,
319 std::optional<Reloc::Model> RM,
320 std::optional<CodeModel::Model> CM,
321 CodeGenOpt::Level OL, bool JIT,
322 bool LittleEndian)
323 : LLVMTargetMachine(T,
324 computeDataLayout(TT, Options.MCOptions, LittleEndian),
325 TT, computeDefaultCPU(TT, CPU), FS, Options,
326 getEffectiveRelocModel(TT, RM),
327 getEffectiveAArch64CodeModel(TT, CM, JIT), OL),
328 TLOF(createTLOF(getTargetTriple())), isLittle(LittleEndian) {
329 initAsmInfo();
330
331 if (TT.isOSBinFormatMachO()) {
332 this->Options.TrapUnreachable = true;
333 this->Options.NoTrapAfterNoreturn = true;
334 }
335
336 if (getMCAsmInfo()->usesWindowsCFI()) {
337 // Unwinding can get confused if the last instruction in an
338 // exception-handling region (function, funclet, try block, etc.)
339 // is a call.
340 //
341 // FIXME: We could elide the trap if the next instruction would be in
342 // the same region anyway.
343 this->Options.TrapUnreachable = true;
344 }
345
346 if (this->Options.TLSSize == 0) // default
347 this->Options.TLSSize = 24;
348 if ((getCodeModel() == CodeModel::Small ||
349 getCodeModel() == CodeModel::Kernel) &&
350 this->Options.TLSSize > 32)
351 // for the small (and kernel) code model, the maximum TLS size is 4GiB
352 this->Options.TLSSize = 32;
353 else if (getCodeModel() == CodeModel::Tiny && this->Options.TLSSize > 24)
354 // for the tiny code model, the maximum TLS size is 1MiB (< 16MiB)
355 this->Options.TLSSize = 24;
356
357 // Enable GlobalISel at or below EnableGlobalISelAt0, unless this is
358 // MachO/CodeModel::Large, which GlobalISel does not support.
359 if (getOptLevel() <= EnableGlobalISelAtO &&
360 TT.getArch() != Triple::aarch64_32 &&
361 TT.getEnvironment() != Triple::GNUILP32 &&
362 !(getCodeModel() == CodeModel::Large && TT.isOSBinFormatMachO())) {
363 setGlobalISel(true);
364 setGlobalISelAbort(GlobalISelAbortMode::Disable);
365 }
366
367 // AArch64 supports the MachineOutliner.
368 setMachineOutliner(true);
369
370 // AArch64 supports default outlining behaviour.
371 setSupportsDefaultOutlining(true);
372
373 // AArch64 supports the debug entry values.
374 setSupportsDebugEntryValues(true);
375
376 // AArch64 supports fixing up the DWARF unwind information.
377 if (!getMCAsmInfo()->usesWindowsCFI())
378 setCFIFixup(true);
379 }
380
381 AArch64TargetMachine::~AArch64TargetMachine() = default;
382
383 const AArch64Subtarget *
getSubtargetImpl(const Function & F) const384 AArch64TargetMachine::getSubtargetImpl(const Function &F) const {
385 Attribute CPUAttr = F.getFnAttribute("target-cpu");
386 Attribute TuneAttr = F.getFnAttribute("tune-cpu");
387 Attribute FSAttr = F.getFnAttribute("target-features");
388
389 StringRef CPU = CPUAttr.isValid() ? CPUAttr.getValueAsString() : TargetCPU;
390 StringRef TuneCPU = TuneAttr.isValid() ? TuneAttr.getValueAsString() : CPU;
391 StringRef FS = FSAttr.isValid() ? FSAttr.getValueAsString() : TargetFS;
392
393 bool StreamingSVEModeDisabled =
394 !F.hasFnAttribute("aarch64_pstate_sm_enabled") &&
395 !F.hasFnAttribute("aarch64_pstate_sm_compatible") &&
396 !F.hasFnAttribute("aarch64_pstate_sm_body");
397
398 unsigned MinSVEVectorSize = 0;
399 unsigned MaxSVEVectorSize = 0;
400 Attribute VScaleRangeAttr = F.getFnAttribute(Attribute::VScaleRange);
401 if (VScaleRangeAttr.isValid()) {
402 std::optional<unsigned> VScaleMax = VScaleRangeAttr.getVScaleRangeMax();
403 MinSVEVectorSize = VScaleRangeAttr.getVScaleRangeMin() * 128;
404 MaxSVEVectorSize = VScaleMax ? *VScaleMax * 128 : 0;
405 } else {
406 MinSVEVectorSize = SVEVectorBitsMinOpt;
407 MaxSVEVectorSize = SVEVectorBitsMaxOpt;
408 }
409
410 assert(MinSVEVectorSize % 128 == 0 &&
411 "SVE requires vector length in multiples of 128!");
412 assert(MaxSVEVectorSize % 128 == 0 &&
413 "SVE requires vector length in multiples of 128!");
414 assert((MaxSVEVectorSize >= MinSVEVectorSize || MaxSVEVectorSize == 0) &&
415 "Minimum SVE vector size should not be larger than its maximum!");
416
417 // Sanitize user input in case of no asserts
418 if (MaxSVEVectorSize == 0)
419 MinSVEVectorSize = (MinSVEVectorSize / 128) * 128;
420 else {
421 MinSVEVectorSize =
422 (std::min(MinSVEVectorSize, MaxSVEVectorSize) / 128) * 128;
423 MaxSVEVectorSize =
424 (std::max(MinSVEVectorSize, MaxSVEVectorSize) / 128) * 128;
425 }
426
427 SmallString<512> Key;
428 raw_svector_ostream(Key) << "SVEMin" << MinSVEVectorSize << "SVEMax"
429 << MaxSVEVectorSize << "StreamingSVEModeDisabled="
430 << StreamingSVEModeDisabled << CPU << TuneCPU << FS;
431
432 auto &I = SubtargetMap[Key];
433 if (!I) {
434 // This needs to be done before we create a new subtarget since any
435 // creation will depend on the TM and the code generation flags on the
436 // function that reside in TargetOptions.
437 resetTargetOptions(F);
438 I = std::make_unique<AArch64Subtarget>(
439 TargetTriple, CPU, TuneCPU, FS, *this, isLittle, MinSVEVectorSize,
440 MaxSVEVectorSize, StreamingSVEModeDisabled);
441 }
442 return I.get();
443 }
444
anchor()445 void AArch64leTargetMachine::anchor() { }
446
AArch64leTargetMachine(const Target & T,const Triple & TT,StringRef CPU,StringRef FS,const TargetOptions & Options,std::optional<Reloc::Model> RM,std::optional<CodeModel::Model> CM,CodeGenOpt::Level OL,bool JIT)447 AArch64leTargetMachine::AArch64leTargetMachine(
448 const Target &T, const Triple &TT, StringRef CPU, StringRef FS,
449 const TargetOptions &Options, std::optional<Reloc::Model> RM,
450 std::optional<CodeModel::Model> CM, CodeGenOpt::Level OL, bool JIT)
451 : AArch64TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, JIT, true) {}
452
anchor()453 void AArch64beTargetMachine::anchor() { }
454
AArch64beTargetMachine(const Target & T,const Triple & TT,StringRef CPU,StringRef FS,const TargetOptions & Options,std::optional<Reloc::Model> RM,std::optional<CodeModel::Model> CM,CodeGenOpt::Level OL,bool JIT)455 AArch64beTargetMachine::AArch64beTargetMachine(
456 const Target &T, const Triple &TT, StringRef CPU, StringRef FS,
457 const TargetOptions &Options, std::optional<Reloc::Model> RM,
458 std::optional<CodeModel::Model> CM, CodeGenOpt::Level OL, bool JIT)
459 : AArch64TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, JIT, false) {}
460
461 namespace {
462
463 /// AArch64 Code Generator Pass Configuration Options.
464 class AArch64PassConfig : public TargetPassConfig {
465 public:
AArch64PassConfig(AArch64TargetMachine & TM,PassManagerBase & PM)466 AArch64PassConfig(AArch64TargetMachine &TM, PassManagerBase &PM)
467 : TargetPassConfig(TM, PM) {
468 if (TM.getOptLevel() != CodeGenOpt::None)
469 substitutePass(&PostRASchedulerID, &PostMachineSchedulerID);
470 }
471
getAArch64TargetMachine() const472 AArch64TargetMachine &getAArch64TargetMachine() const {
473 return getTM<AArch64TargetMachine>();
474 }
475
476 ScheduleDAGInstrs *
createMachineScheduler(MachineSchedContext * C) const477 createMachineScheduler(MachineSchedContext *C) const override {
478 const AArch64Subtarget &ST = C->MF->getSubtarget<AArch64Subtarget>();
479 ScheduleDAGMILive *DAG = createGenericSchedLive(C);
480 DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
481 DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
482 if (ST.hasFusion())
483 DAG->addMutation(createAArch64MacroFusionDAGMutation());
484 return DAG;
485 }
486
487 ScheduleDAGInstrs *
createPostMachineScheduler(MachineSchedContext * C) const488 createPostMachineScheduler(MachineSchedContext *C) const override {
489 const AArch64Subtarget &ST = C->MF->getSubtarget<AArch64Subtarget>();
490 ScheduleDAGMI *DAG =
491 new ScheduleDAGMI(C, std::make_unique<AArch64PostRASchedStrategy>(C),
492 /* RemoveKillFlags=*/true);
493 if (ST.hasFusion()) {
494 // Run the Macro Fusion after RA again since literals are expanded from
495 // pseudos then (v. addPreSched2()).
496 DAG->addMutation(createAArch64MacroFusionDAGMutation());
497 return DAG;
498 }
499
500 return DAG;
501 }
502
503 void addIRPasses() override;
504 bool addPreISel() override;
505 void addCodeGenPrepare() override;
506 bool addInstSelector() override;
507 bool addIRTranslator() override;
508 void addPreLegalizeMachineIR() override;
509 bool addLegalizeMachineIR() override;
510 void addPreRegBankSelect() override;
511 bool addRegBankSelect() override;
512 void addPreGlobalInstructionSelect() override;
513 bool addGlobalInstructionSelect() override;
514 void addMachineSSAOptimization() override;
515 bool addILPOpts() override;
516 void addPreRegAlloc() override;
517 void addPostRegAlloc() override;
518 void addPreSched2() override;
519 void addPreEmitPass() override;
520 void addPreEmitPass2() override;
521
522 std::unique_ptr<CSEConfigBase> getCSEConfig() const override;
523 };
524
525 } // end anonymous namespace
526
527 TargetTransformInfo
getTargetTransformInfo(const Function & F) const528 AArch64TargetMachine::getTargetTransformInfo(const Function &F) const {
529 return TargetTransformInfo(AArch64TTIImpl(this, F));
530 }
531
createPassConfig(PassManagerBase & PM)532 TargetPassConfig *AArch64TargetMachine::createPassConfig(PassManagerBase &PM) {
533 return new AArch64PassConfig(*this, PM);
534 }
535
getCSEConfig() const536 std::unique_ptr<CSEConfigBase> AArch64PassConfig::getCSEConfig() const {
537 return getStandardCSEConfigForOpt(TM->getOptLevel());
538 }
539
addIRPasses()540 void AArch64PassConfig::addIRPasses() {
541 // Always expand atomic operations, we don't deal with atomicrmw or cmpxchg
542 // ourselves.
543 addPass(createAtomicExpandPass());
544
545 // Expand any SVE vector library calls that we can't code generate directly.
546 if (EnableSVEIntrinsicOpts && TM->getOptLevel() == CodeGenOpt::Aggressive)
547 addPass(createSVEIntrinsicOptsPass());
548
549 // Cmpxchg instructions are often used with a subsequent comparison to
550 // determine whether it succeeded. We can exploit existing control-flow in
551 // ldrex/strex loops to simplify this, but it needs tidying up.
552 if (TM->getOptLevel() != CodeGenOpt::None && EnableAtomicTidy)
553 addPass(createCFGSimplificationPass(SimplifyCFGOptions()
554 .forwardSwitchCondToPhi(true)
555 .convertSwitchRangeToICmp(true)
556 .convertSwitchToLookupTable(true)
557 .needCanonicalLoops(false)
558 .hoistCommonInsts(true)
559 .sinkCommonInsts(true)));
560
561 // Run LoopDataPrefetch
562 //
563 // Run this before LSR to remove the multiplies involved in computing the
564 // pointer values N iterations ahead.
565 if (TM->getOptLevel() != CodeGenOpt::None) {
566 if (EnableLoopDataPrefetch)
567 addPass(createLoopDataPrefetchPass());
568 if (EnableFalkorHWPFFix)
569 addPass(createFalkorMarkStridedAccessesPass());
570 }
571
572 if (TM->getOptLevel() == CodeGenOpt::Aggressive && EnableGEPOpt) {
573 // Call SeparateConstOffsetFromGEP pass to extract constants within indices
574 // and lower a GEP with multiple indices to either arithmetic operations or
575 // multiple GEPs with single index.
576 addPass(createSeparateConstOffsetFromGEPPass(true));
577 // Call EarlyCSE pass to find and remove subexpressions in the lowered
578 // result.
579 addPass(createEarlyCSEPass());
580 // Do loop invariant code motion in case part of the lowered result is
581 // invariant.
582 addPass(createLICMPass());
583 }
584
585 TargetPassConfig::addIRPasses();
586
587 if (getOptLevel() == CodeGenOpt::Aggressive && EnableSelectOpt)
588 addPass(createSelectOptimizePass());
589
590 addPass(createAArch64StackTaggingPass(
591 /*IsOptNone=*/TM->getOptLevel() == CodeGenOpt::None));
592
593 // Match complex arithmetic patterns
594 if (TM->getOptLevel() >= CodeGenOpt::Default)
595 addPass(createComplexDeinterleavingPass(TM));
596
597 // Match interleaved memory accesses to ldN/stN intrinsics.
598 if (TM->getOptLevel() != CodeGenOpt::None) {
599 addPass(createInterleavedLoadCombinePass());
600 addPass(createInterleavedAccessPass());
601 }
602
603 // Expand any functions marked with SME attributes which require special
604 // changes for the calling convention or that require the lazy-saving
605 // mechanism specified in the SME ABI.
606 addPass(createSMEABIPass());
607
608 // Add Control Flow Guard checks.
609 if (TM->getTargetTriple().isOSWindows())
610 addPass(createCFGuardCheckPass());
611
612 if (TM->Options.JMCInstrument)
613 addPass(createJMCInstrumenterPass());
614 }
615
616 // Pass Pipeline Configuration
addPreISel()617 bool AArch64PassConfig::addPreISel() {
618 // Run promote constant before global merge, so that the promoted constants
619 // get a chance to be merged
620 if (TM->getOptLevel() != CodeGenOpt::None && EnablePromoteConstant)
621 addPass(createAArch64PromoteConstantPass());
622 // FIXME: On AArch64, this depends on the type.
623 // Basically, the addressable offsets are up to 4095 * Ty.getSizeInBytes().
624 // and the offset has to be a multiple of the related size in bytes.
625 if ((TM->getOptLevel() != CodeGenOpt::None &&
626 EnableGlobalMerge == cl::BOU_UNSET) ||
627 EnableGlobalMerge == cl::BOU_TRUE) {
628 bool OnlyOptimizeForSize = (TM->getOptLevel() < CodeGenOpt::Aggressive) &&
629 (EnableGlobalMerge == cl::BOU_UNSET);
630
631 // Merging of extern globals is enabled by default on non-Mach-O as we
632 // expect it to be generally either beneficial or harmless. On Mach-O it
633 // is disabled as we emit the .subsections_via_symbols directive which
634 // means that merging extern globals is not safe.
635 bool MergeExternalByDefault = !TM->getTargetTriple().isOSBinFormatMachO();
636
637 // FIXME: extern global merging is only enabled when we optimise for size
638 // because there are some regressions with it also enabled for performance.
639 if (!OnlyOptimizeForSize)
640 MergeExternalByDefault = false;
641
642 addPass(createGlobalMergePass(TM, 4095, OnlyOptimizeForSize,
643 MergeExternalByDefault));
644 }
645
646 return false;
647 }
648
addCodeGenPrepare()649 void AArch64PassConfig::addCodeGenPrepare() {
650 if (getOptLevel() != CodeGenOpt::None)
651 addPass(createTypePromotionLegacyPass());
652 TargetPassConfig::addCodeGenPrepare();
653 }
654
addInstSelector()655 bool AArch64PassConfig::addInstSelector() {
656 addPass(createAArch64ISelDag(getAArch64TargetMachine(), getOptLevel()));
657
658 // For ELF, cleanup any local-dynamic TLS accesses (i.e. combine as many
659 // references to _TLS_MODULE_BASE_ as possible.
660 if (TM->getTargetTriple().isOSBinFormatELF() &&
661 getOptLevel() != CodeGenOpt::None)
662 addPass(createAArch64CleanupLocalDynamicTLSPass());
663
664 return false;
665 }
666
addIRTranslator()667 bool AArch64PassConfig::addIRTranslator() {
668 addPass(new IRTranslator(getOptLevel()));
669 return false;
670 }
671
addPreLegalizeMachineIR()672 void AArch64PassConfig::addPreLegalizeMachineIR() {
673 if (getOptLevel() == CodeGenOpt::None)
674 addPass(createAArch64O0PreLegalizerCombiner());
675 else {
676 addPass(createAArch64PreLegalizerCombiner());
677 if (EnableGISelLoadStoreOptPreLegal)
678 addPass(new LoadStoreOpt());
679 }
680 }
681
addLegalizeMachineIR()682 bool AArch64PassConfig::addLegalizeMachineIR() {
683 addPass(new Legalizer());
684 return false;
685 }
686
addPreRegBankSelect()687 void AArch64PassConfig::addPreRegBankSelect() {
688 bool IsOptNone = getOptLevel() == CodeGenOpt::None;
689 if (!IsOptNone) {
690 addPass(createAArch64PostLegalizerCombiner(IsOptNone));
691 if (EnableGISelLoadStoreOptPostLegal)
692 addPass(new LoadStoreOpt());
693 }
694 addPass(createAArch64PostLegalizerLowering());
695 }
696
addRegBankSelect()697 bool AArch64PassConfig::addRegBankSelect() {
698 addPass(new RegBankSelect());
699 return false;
700 }
701
addPreGlobalInstructionSelect()702 void AArch64PassConfig::addPreGlobalInstructionSelect() {
703 addPass(new Localizer());
704 }
705
addGlobalInstructionSelect()706 bool AArch64PassConfig::addGlobalInstructionSelect() {
707 addPass(new InstructionSelect(getOptLevel()));
708 if (getOptLevel() != CodeGenOpt::None)
709 addPass(createAArch64PostSelectOptimize());
710 return false;
711 }
712
addMachineSSAOptimization()713 void AArch64PassConfig::addMachineSSAOptimization() {
714 // Run default MachineSSAOptimization first.
715 TargetPassConfig::addMachineSSAOptimization();
716
717 if (TM->getOptLevel() != CodeGenOpt::None)
718 addPass(createAArch64MIPeepholeOptPass());
719 }
720
addILPOpts()721 bool AArch64PassConfig::addILPOpts() {
722 if (EnableCondOpt)
723 addPass(createAArch64ConditionOptimizerPass());
724 if (EnableCCMP)
725 addPass(createAArch64ConditionalCompares());
726 if (EnableMCR)
727 addPass(&MachineCombinerID);
728 if (EnableCondBrTuning)
729 addPass(createAArch64CondBrTuning());
730 if (EnableEarlyIfConversion)
731 addPass(&EarlyIfConverterID);
732 if (EnableStPairSuppress)
733 addPass(createAArch64StorePairSuppressPass());
734 addPass(createAArch64SIMDInstrOptPass());
735 if (TM->getOptLevel() != CodeGenOpt::None)
736 addPass(createAArch64StackTaggingPreRAPass());
737 return true;
738 }
739
addPreRegAlloc()740 void AArch64PassConfig::addPreRegAlloc() {
741 // Change dead register definitions to refer to the zero register.
742 if (TM->getOptLevel() != CodeGenOpt::None && EnableDeadRegisterElimination)
743 addPass(createAArch64DeadRegisterDefinitions());
744
745 // Use AdvSIMD scalar instructions whenever profitable.
746 if (TM->getOptLevel() != CodeGenOpt::None && EnableAdvSIMDScalar) {
747 addPass(createAArch64AdvSIMDScalar());
748 // The AdvSIMD pass may produce copies that can be rewritten to
749 // be register coalescer friendly.
750 addPass(&PeepholeOptimizerID);
751 }
752 }
753
addPostRegAlloc()754 void AArch64PassConfig::addPostRegAlloc() {
755 // Remove redundant copy instructions.
756 if (TM->getOptLevel() != CodeGenOpt::None && EnableRedundantCopyElimination)
757 addPass(createAArch64RedundantCopyEliminationPass());
758
759 if (TM->getOptLevel() != CodeGenOpt::None && usingDefaultRegAlloc())
760 // Improve performance for some FP/SIMD code for A57.
761 addPass(createAArch64A57FPLoadBalancing());
762 }
763
addPreSched2()764 void AArch64PassConfig::addPreSched2() {
765 // Lower homogeneous frame instructions
766 if (EnableHomogeneousPrologEpilog)
767 addPass(createAArch64LowerHomogeneousPrologEpilogPass());
768 // Expand some pseudo instructions to allow proper scheduling.
769 addPass(createAArch64ExpandPseudoPass());
770 // Use load/store pair instructions when possible.
771 if (TM->getOptLevel() != CodeGenOpt::None) {
772 if (EnableLoadStoreOpt)
773 addPass(createAArch64LoadStoreOptimizationPass());
774 }
775 // Emit KCFI checks for indirect calls.
776 addPass(createAArch64KCFIPass());
777
778 // The AArch64SpeculationHardeningPass destroys dominator tree and natural
779 // loop info, which is needed for the FalkorHWPFFixPass and also later on.
780 // Therefore, run the AArch64SpeculationHardeningPass before the
781 // FalkorHWPFFixPass to avoid recomputing dominator tree and natural loop
782 // info.
783 addPass(createAArch64SpeculationHardeningPass());
784
785 addPass(createAArch64IndirectThunks());
786 addPass(createAArch64SLSHardeningPass());
787
788 if (TM->getOptLevel() != CodeGenOpt::None) {
789 if (EnableFalkorHWPFFix)
790 addPass(createFalkorHWPFFixPass());
791 }
792 }
793
addPreEmitPass()794 void AArch64PassConfig::addPreEmitPass() {
795 // Machine Block Placement might have created new opportunities when run
796 // at O3, where the Tail Duplication Threshold is set to 4 instructions.
797 // Run the load/store optimizer once more.
798 if (TM->getOptLevel() >= CodeGenOpt::Aggressive && EnableLoadStoreOpt)
799 addPass(createAArch64LoadStoreOptimizationPass());
800
801 if (TM->getOptLevel() >= CodeGenOpt::Aggressive &&
802 EnableAArch64CopyPropagation)
803 addPass(createMachineCopyPropagationPass(true));
804
805 addPass(createAArch64A53Fix835769());
806
807 if (EnableBranchTargets)
808 addPass(createAArch64BranchTargetsPass());
809
810 // Relax conditional branch instructions if they're otherwise out of
811 // range of their destination.
812 if (BranchRelaxation)
813 addPass(&BranchRelaxationPassID);
814
815 if (TM->getTargetTriple().isOSWindows()) {
816 // Identify valid longjmp targets for Windows Control Flow Guard.
817 addPass(createCFGuardLongjmpPass());
818 // Identify valid eh continuation targets for Windows EHCont Guard.
819 addPass(createEHContGuardCatchretPass());
820 }
821
822 if (TM->getOptLevel() != CodeGenOpt::None && EnableCompressJumpTables)
823 addPass(createAArch64CompressJumpTablesPass());
824
825 if (TM->getOptLevel() != CodeGenOpt::None && EnableCollectLOH &&
826 TM->getTargetTriple().isOSBinFormatMachO())
827 addPass(createAArch64CollectLOHPass());
828 }
829
addPreEmitPass2()830 void AArch64PassConfig::addPreEmitPass2() {
831 // SVE bundles move prefixes with destructive operations. BLR_RVMARKER pseudo
832 // instructions are lowered to bundles as well.
833 addPass(createUnpackMachineBundles(nullptr));
834 }
835
createMachineFunctionInfo(BumpPtrAllocator & Allocator,const Function & F,const TargetSubtargetInfo * STI) const836 MachineFunctionInfo *AArch64TargetMachine::createMachineFunctionInfo(
837 BumpPtrAllocator &Allocator, const Function &F,
838 const TargetSubtargetInfo *STI) const {
839 return AArch64FunctionInfo::create<AArch64FunctionInfo>(
840 Allocator, F, static_cast<const AArch64Subtarget *>(STI));
841 }
842
843 yaml::MachineFunctionInfo *
createDefaultFuncInfoYAML() const844 AArch64TargetMachine::createDefaultFuncInfoYAML() const {
845 return new yaml::AArch64FunctionInfo();
846 }
847
848 yaml::MachineFunctionInfo *
convertFuncInfoToYAML(const MachineFunction & MF) const849 AArch64TargetMachine::convertFuncInfoToYAML(const MachineFunction &MF) const {
850 const auto *MFI = MF.getInfo<AArch64FunctionInfo>();
851 return new yaml::AArch64FunctionInfo(*MFI);
852 }
853
parseMachineFunctionInfo(const yaml::MachineFunctionInfo & MFI,PerFunctionMIParsingState & PFS,SMDiagnostic & Error,SMRange & SourceRange) const854 bool AArch64TargetMachine::parseMachineFunctionInfo(
855 const yaml::MachineFunctionInfo &MFI, PerFunctionMIParsingState &PFS,
856 SMDiagnostic &Error, SMRange &SourceRange) const {
857 const auto &YamlMFI = static_cast<const yaml::AArch64FunctionInfo &>(MFI);
858 MachineFunction &MF = PFS.MF;
859 MF.getInfo<AArch64FunctionInfo>()->initializeBaseYamlFields(YamlMFI);
860 return false;
861 }
862