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1//===-- X86.td - Target definition file for the Intel X86 --*- tablegen -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This is a target description file for the Intel i386 architecture, referred
10// to here as the "X86" architecture.
11//
12//===----------------------------------------------------------------------===//
13
14// Get the target-independent interfaces which we are implementing...
15//
16include "llvm/Target/Target.td"
17
18//===----------------------------------------------------------------------===//
19// X86 Subtarget state
20//
21// disregarding specific ABI / programming model
22def Is64Bit : SubtargetFeature<"64bit-mode", "Is64Bit", "true",
23                               "64-bit mode (x86_64)">;
24def Is32Bit : SubtargetFeature<"32bit-mode", "Is32Bit", "true",
25                               "32-bit mode (80386)">;
26def Is16Bit : SubtargetFeature<"16bit-mode", "Is16Bit", "true",
27                               "16-bit mode (i8086)">;
28
29//===----------------------------------------------------------------------===//
30// X86 Subtarget ISA features
31//===----------------------------------------------------------------------===//
32
33def FeatureX87     : SubtargetFeature<"x87","HasX87", "true",
34                                      "Enable X87 float instructions">;
35
36def FeatureNOPL    : SubtargetFeature<"nopl", "HasNOPL", "true",
37                                      "Enable NOPL instruction (generally pentium pro+)">;
38
39def FeatureCMOV    : SubtargetFeature<"cmov","HasCMOV", "true",
40                                      "Enable conditional move instructions">;
41
42def FeatureCX8     : SubtargetFeature<"cx8", "HasCX8", "true",
43                                      "Support CMPXCHG8B instructions">;
44
45def FeatureCRC32   : SubtargetFeature<"crc32", "HasCRC32", "true",
46                                      "Enable SSE 4.2 CRC32 instruction (used when SSE4.2 is supported but function is GPR only)">;
47
48def FeaturePOPCNT   : SubtargetFeature<"popcnt", "HasPOPCNT", "true",
49                                       "Support POPCNT instruction">;
50
51def FeatureFXSR    : SubtargetFeature<"fxsr", "HasFXSR", "true",
52                                      "Support fxsave/fxrestore instructions">;
53
54def FeatureXSAVE   : SubtargetFeature<"xsave", "HasXSAVE", "true",
55                                       "Support xsave instructions">;
56
57def FeatureXSAVEOPT: SubtargetFeature<"xsaveopt", "HasXSAVEOPT", "true",
58                                       "Support xsaveopt instructions",
59                                       [FeatureXSAVE]>;
60
61def FeatureXSAVEC  : SubtargetFeature<"xsavec", "HasXSAVEC", "true",
62                                       "Support xsavec instructions",
63                                       [FeatureXSAVE]>;
64
65def FeatureXSAVES  : SubtargetFeature<"xsaves", "HasXSAVES", "true",
66                                       "Support xsaves instructions",
67                                       [FeatureXSAVE]>;
68
69def FeatureSSE1    : SubtargetFeature<"sse", "X86SSELevel", "SSE1",
70                                      "Enable SSE instructions">;
71def FeatureSSE2    : SubtargetFeature<"sse2", "X86SSELevel", "SSE2",
72                                      "Enable SSE2 instructions",
73                                      [FeatureSSE1]>;
74def FeatureSSE3    : SubtargetFeature<"sse3", "X86SSELevel", "SSE3",
75                                      "Enable SSE3 instructions",
76                                      [FeatureSSE2]>;
77def FeatureSSSE3   : SubtargetFeature<"ssse3", "X86SSELevel", "SSSE3",
78                                      "Enable SSSE3 instructions",
79                                      [FeatureSSE3]>;
80def FeatureSSE41   : SubtargetFeature<"sse4.1", "X86SSELevel", "SSE41",
81                                      "Enable SSE 4.1 instructions",
82                                      [FeatureSSSE3]>;
83def FeatureSSE42   : SubtargetFeature<"sse4.2", "X86SSELevel", "SSE42",
84                                      "Enable SSE 4.2 instructions",
85                                      [FeatureSSE41]>;
86// The MMX subtarget feature is separate from the rest of the SSE features
87// because it's important (for odd compatibility reasons) to be able to
88// turn it off explicitly while allowing SSE+ to be on.
89def FeatureMMX     : SubtargetFeature<"mmx","X863DNowLevel", "MMX",
90                                      "Enable MMX instructions">;
91def Feature3DNow   : SubtargetFeature<"3dnow", "X863DNowLevel", "ThreeDNow",
92                                      "Enable 3DNow! instructions",
93                                      [FeatureMMX]>;
94def Feature3DNowA  : SubtargetFeature<"3dnowa", "X863DNowLevel", "ThreeDNowA",
95                                      "Enable 3DNow! Athlon instructions",
96                                      [Feature3DNow]>;
97// All x86-64 hardware has SSE2, but we don't mark SSE2 as an implied
98// feature, because SSE2 can be disabled (e.g. for compiling OS kernels)
99// without disabling 64-bit mode. Nothing should imply this feature bit. It
100// is used to enforce that only 64-bit capable CPUs are used in 64-bit mode.
101def FeatureX86_64   : SubtargetFeature<"64bit", "HasX86_64", "true",
102                                      "Support 64-bit instructions">;
103def FeatureCX16     : SubtargetFeature<"cx16", "HasCX16", "true",
104                                       "64-bit with cmpxchg16b (this is true for most x86-64 chips, but not the first AMD chips)",
105                                       [FeatureCX8]>;
106def FeatureSSE4A   : SubtargetFeature<"sse4a", "HasSSE4A", "true",
107                                      "Support SSE 4a instructions",
108                                      [FeatureSSE3]>;
109
110def FeatureAVX     : SubtargetFeature<"avx", "X86SSELevel", "AVX",
111                                      "Enable AVX instructions",
112                                      [FeatureSSE42]>;
113def FeatureAVX2    : SubtargetFeature<"avx2", "X86SSELevel", "AVX2",
114                                      "Enable AVX2 instructions",
115                                      [FeatureAVX]>;
116def FeatureFMA     : SubtargetFeature<"fma", "HasFMA", "true",
117                                      "Enable three-operand fused multiple-add",
118                                      [FeatureAVX]>;
119def FeatureF16C    : SubtargetFeature<"f16c", "HasF16C", "true",
120                       "Support 16-bit floating point conversion instructions",
121                       [FeatureAVX]>;
122def FeatureAVX512   : SubtargetFeature<"avx512f", "X86SSELevel", "AVX512",
123                                      "Enable AVX-512 instructions",
124                                      [FeatureAVX2, FeatureFMA, FeatureF16C]>;
125def FeatureERI      : SubtargetFeature<"avx512er", "HasERI", "true",
126                      "Enable AVX-512 Exponential and Reciprocal Instructions",
127                                      [FeatureAVX512]>;
128def FeatureCDI      : SubtargetFeature<"avx512cd", "HasCDI", "true",
129                      "Enable AVX-512 Conflict Detection Instructions",
130                                      [FeatureAVX512]>;
131def FeatureVPOPCNTDQ : SubtargetFeature<"avx512vpopcntdq", "HasVPOPCNTDQ",
132                       "true", "Enable AVX-512 Population Count Instructions",
133                                      [FeatureAVX512]>;
134def FeaturePFI      : SubtargetFeature<"avx512pf", "HasPFI", "true",
135                      "Enable AVX-512 PreFetch Instructions",
136                                      [FeatureAVX512]>;
137def FeaturePREFETCHI  : SubtargetFeature<"prefetchi", "HasPREFETCHI",
138                                   "true",
139                                   "Prefetch instruction with T0 or T1 Hint">;
140def FeaturePREFETCHWT1  : SubtargetFeature<"prefetchwt1", "HasPREFETCHWT1",
141                                   "true",
142                                   "Prefetch with Intent to Write and T1 Hint">;
143def FeatureDQI     : SubtargetFeature<"avx512dq", "HasDQI", "true",
144                      "Enable AVX-512 Doubleword and Quadword Instructions",
145                                      [FeatureAVX512]>;
146def FeatureBWI     : SubtargetFeature<"avx512bw", "HasBWI", "true",
147                      "Enable AVX-512 Byte and Word Instructions",
148                                      [FeatureAVX512]>;
149def FeatureVLX     : SubtargetFeature<"avx512vl", "HasVLX", "true",
150                      "Enable AVX-512 Vector Length eXtensions",
151                                      [FeatureAVX512]>;
152def FeatureVBMI     : SubtargetFeature<"avx512vbmi", "HasVBMI", "true",
153                      "Enable AVX-512 Vector Byte Manipulation Instructions",
154                                      [FeatureBWI]>;
155def FeatureVBMI2    : SubtargetFeature<"avx512vbmi2", "HasVBMI2", "true",
156                      "Enable AVX-512 further Vector Byte Manipulation Instructions",
157                                      [FeatureBWI]>;
158def FeatureAVXIFMA    : SubtargetFeature<"avxifma", "HasAVXIFMA", "true",
159                           "Enable AVX-IFMA",
160                           [FeatureAVX2]>;
161def FeatureIFMA     : SubtargetFeature<"avx512ifma", "HasIFMA", "true",
162                      "Enable AVX-512 Integer Fused Multiple-Add",
163                                      [FeatureAVX512]>;
164def FeaturePKU   : SubtargetFeature<"pku", "HasPKU", "true",
165                      "Enable protection keys">;
166def FeatureVNNI    : SubtargetFeature<"avx512vnni", "HasVNNI", "true",
167                          "Enable AVX-512 Vector Neural Network Instructions",
168                                      [FeatureAVX512]>;
169def FeatureAVXVNNI    : SubtargetFeature<"avxvnni", "HasAVXVNNI", "true",
170                           "Support AVX_VNNI encoding",
171                                      [FeatureAVX2]>;
172def FeatureBF16    : SubtargetFeature<"avx512bf16", "HasBF16", "true",
173                           "Support bfloat16 floating point",
174                                      [FeatureBWI]>;
175def FeatureBITALG  : SubtargetFeature<"avx512bitalg", "HasBITALG", "true",
176                       "Enable AVX-512 Bit Algorithms",
177                        [FeatureBWI]>;
178def FeatureVP2INTERSECT  : SubtargetFeature<"avx512vp2intersect",
179                                            "HasVP2INTERSECT", "true",
180                                            "Enable AVX-512 vp2intersect",
181                                            [FeatureAVX512]>;
182// FIXME: FP16 scalar intrinsics use the type v8f16, which is supposed to be
183// guarded under condition hasVLX. So we imply it in FeatureFP16 currently.
184// FIXME: FP16 conversion between f16 and i64 customize type v8i64, which is
185// supposed to be guarded under condition hasDQI. So we imply it in FeatureFP16
186// currently.
187def FeatureFP16    : SubtargetFeature<"avx512fp16", "HasFP16", "true",
188                           "Support 16-bit floating point",
189                           [FeatureBWI, FeatureVLX, FeatureDQI]>;
190def FeatureAVXVNNIINT8  : SubtargetFeature<"avxvnniint8",
191                             "HasAVXVNNIINT8", "true",
192                             "Enable AVX-VNNI-INT8",
193                             [FeatureAVX2]>;
194def FeaturePCLMUL  : SubtargetFeature<"pclmul", "HasPCLMUL", "true",
195                         "Enable packed carry-less multiplication instructions",
196                               [FeatureSSE2]>;
197def FeatureGFNI    : SubtargetFeature<"gfni", "HasGFNI", "true",
198                         "Enable Galois Field Arithmetic Instructions",
199                               [FeatureSSE2]>;
200def FeatureVPCLMULQDQ : SubtargetFeature<"vpclmulqdq", "HasVPCLMULQDQ", "true",
201                                         "Enable vpclmulqdq instructions",
202                                         [FeatureAVX, FeaturePCLMUL]>;
203def FeatureFMA4    : SubtargetFeature<"fma4", "HasFMA4", "true",
204                                      "Enable four-operand fused multiple-add",
205                                      [FeatureAVX, FeatureSSE4A]>;
206def FeatureXOP     : SubtargetFeature<"xop", "HasXOP", "true",
207                                      "Enable XOP instructions",
208                                      [FeatureFMA4]>;
209def FeatureSSEUnalignedMem : SubtargetFeature<"sse-unaligned-mem",
210                                          "HasSSEUnalignedMem", "true",
211                      "Allow unaligned memory operands with SSE instructions (this may require setting a configuration bit in the processor)">;
212def FeatureAES     : SubtargetFeature<"aes", "HasAES", "true",
213                                      "Enable AES instructions",
214                                      [FeatureSSE2]>;
215def FeatureVAES    : SubtargetFeature<"vaes", "HasVAES", "true",
216                       "Promote selected AES instructions to AVX512/AVX registers",
217                        [FeatureAVX, FeatureAES]>;
218def FeatureTBM     : SubtargetFeature<"tbm", "HasTBM", "true",
219                                      "Enable TBM instructions">;
220def FeatureLWP     : SubtargetFeature<"lwp", "HasLWP", "true",
221                                      "Enable LWP instructions">;
222def FeatureMOVBE   : SubtargetFeature<"movbe", "HasMOVBE", "true",
223                                      "Support MOVBE instruction">;
224def FeatureRDRAND  : SubtargetFeature<"rdrnd", "HasRDRAND", "true",
225                                      "Support RDRAND instruction">;
226def FeatureFSGSBase : SubtargetFeature<"fsgsbase", "HasFSGSBase", "true",
227                                       "Support FS/GS Base instructions">;
228def FeatureLZCNT   : SubtargetFeature<"lzcnt", "HasLZCNT", "true",
229                                      "Support LZCNT instruction">;
230def FeatureBMI     : SubtargetFeature<"bmi", "HasBMI", "true",
231                                      "Support BMI instructions">;
232def FeatureBMI2    : SubtargetFeature<"bmi2", "HasBMI2", "true",
233                                      "Support BMI2 instructions">;
234def FeatureRTM     : SubtargetFeature<"rtm", "HasRTM", "true",
235                                      "Support RTM instructions">;
236def FeatureADX     : SubtargetFeature<"adx", "HasADX", "true",
237                                      "Support ADX instructions">;
238def FeatureSHA     : SubtargetFeature<"sha", "HasSHA", "true",
239                                      "Enable SHA instructions",
240                                      [FeatureSSE2]>;
241// Processor supports CET SHSTK - Control-Flow Enforcement Technology
242// using Shadow Stack
243def FeatureSHSTK   : SubtargetFeature<"shstk", "HasSHSTK", "true",
244                       "Support CET Shadow-Stack instructions">;
245def FeaturePRFCHW  : SubtargetFeature<"prfchw", "HasPRFCHW", "true",
246                                      "Support PRFCHW instructions">;
247def FeatureRDSEED  : SubtargetFeature<"rdseed", "HasRDSEED", "true",
248                                      "Support RDSEED instruction">;
249def FeatureLAHFSAHF64 : SubtargetFeature<"sahf", "HasLAHFSAHF64", "true",
250                           "Support LAHF and SAHF instructions in 64-bit mode">;
251def FeatureMWAITX  : SubtargetFeature<"mwaitx", "HasMWAITX", "true",
252                                      "Enable MONITORX/MWAITX timer functionality">;
253def FeatureCLZERO  : SubtargetFeature<"clzero", "HasCLZERO", "true",
254                                      "Enable Cache Line Zero">;
255def FeatureCLDEMOTE  : SubtargetFeature<"cldemote", "HasCLDEMOTE", "true",
256                                      "Enable Cache Line Demote">;
257def FeaturePTWRITE  : SubtargetFeature<"ptwrite", "HasPTWRITE", "true",
258                                      "Support ptwrite instruction">;
259def FeatureAMXTILE     : SubtargetFeature<"amx-tile", "HasAMXTILE", "true",
260                                      "Support AMX-TILE instructions">;
261def FeatureAMXINT8     : SubtargetFeature<"amx-int8", "HasAMXINT8", "true",
262                                      "Support AMX-INT8 instructions",
263                                      [FeatureAMXTILE]>;
264def FeatureAMXBF16     : SubtargetFeature<"amx-bf16", "HasAMXBF16", "true",
265                                      "Support AMX-BF16 instructions",
266                                      [FeatureAMXTILE]>;
267def FeatureAMXFP16     : SubtargetFeature<"amx-fp16", "HasAMXFP16", "true",
268                                      "Support AMX amx-fp16 instructions",
269                                      [FeatureAMXTILE]>;
270def FeatureCMPCCXADD : SubtargetFeature<"cmpccxadd", "HasCMPCCXADD", "true",
271                                        "Support CMPCCXADD instructions">;
272def FeatureRAOINT : SubtargetFeature<"raoint", "HasRAOINT", "true",
273                                     "Support RAO-INT instructions",
274                                     []>;
275def FeatureAVXNECONVERT : SubtargetFeature<"avxneconvert", "HasAVXNECONVERT", "true",
276                                           "Support AVX-NE-CONVERT instructions",
277                                           [FeatureAVX2]>;
278def FeatureINVPCID : SubtargetFeature<"invpcid", "HasINVPCID", "true",
279                                      "Invalidate Process-Context Identifier">;
280def FeatureSGX     : SubtargetFeature<"sgx", "HasSGX", "true",
281                                      "Enable Software Guard Extensions">;
282def FeatureCLFLUSHOPT : SubtargetFeature<"clflushopt", "HasCLFLUSHOPT", "true",
283                                      "Flush A Cache Line Optimized">;
284def FeatureCLWB    : SubtargetFeature<"clwb", "HasCLWB", "true",
285                                      "Cache Line Write Back">;
286def FeatureWBNOINVD    : SubtargetFeature<"wbnoinvd", "HasWBNOINVD", "true",
287                                      "Write Back No Invalidate">;
288def FeatureRDPID : SubtargetFeature<"rdpid", "HasRDPID", "true",
289                                    "Support RDPID instructions">;
290def FeatureRDPRU : SubtargetFeature<"rdpru", "HasRDPRU", "true",
291                                    "Support RDPRU instructions">;
292def FeatureWAITPKG  : SubtargetFeature<"waitpkg", "HasWAITPKG", "true",
293                                      "Wait and pause enhancements">;
294def FeatureENQCMD : SubtargetFeature<"enqcmd", "HasENQCMD", "true",
295                                     "Has ENQCMD instructions">;
296def FeatureKL  : SubtargetFeature<"kl", "HasKL", "true",
297                                  "Support Key Locker kl Instructions",
298                                  [FeatureSSE2]>;
299def FeatureWIDEKL  : SubtargetFeature<"widekl", "HasWIDEKL", "true",
300                                      "Support Key Locker wide Instructions",
301                                      [FeatureKL]>;
302def FeatureHRESET : SubtargetFeature<"hreset", "HasHRESET", "true",
303                                      "Has hreset instruction">;
304def FeatureSERIALIZE : SubtargetFeature<"serialize", "HasSERIALIZE", "true",
305                                        "Has serialize instruction">;
306def FeatureTSXLDTRK : SubtargetFeature<"tsxldtrk", "HasTSXLDTRK", "true",
307                                       "Support TSXLDTRK instructions">;
308def FeatureUINTR : SubtargetFeature<"uintr", "HasUINTR", "true",
309                                    "Has UINTR Instructions">;
310def FeaturePCONFIG : SubtargetFeature<"pconfig", "HasPCONFIG", "true",
311                                      "platform configuration instruction">;
312def FeatureMOVDIRI  : SubtargetFeature<"movdiri", "HasMOVDIRI", "true",
313                                       "Support movdiri instruction (direct store integer)">;
314def FeatureMOVDIR64B : SubtargetFeature<"movdir64b", "HasMOVDIR64B", "true",
315                                        "Support movdir64b instruction (direct store 64 bytes)">;
316
317// Ivy Bridge and newer processors have enhanced REP MOVSB and STOSB (aka
318// "string operations"). See "REP String Enhancement" in the Intel Software
319// Development Manual. This feature essentially means that REP MOVSB will copy
320// using the largest available size instead of copying bytes one by one, making
321// it at least as fast as REPMOVS{W,D,Q}.
322def FeatureERMSB
323    : SubtargetFeature<
324          "ermsb", "HasERMSB", "true",
325          "REP MOVS/STOS are fast">;
326
327// Icelake and newer processors have Fast Short REP MOV.
328def FeatureFSRM
329    : SubtargetFeature<
330          "fsrm", "HasFSRM", "true",
331          "REP MOVSB of short lengths is faster">;
332
333def FeatureSoftFloat
334    : SubtargetFeature<"soft-float", "UseSoftFloat", "true",
335                       "Use software floating point features">;
336
337//===----------------------------------------------------------------------===//
338// X86 Subtarget Security Mitigation features
339//===----------------------------------------------------------------------===//
340
341// Lower indirect calls using a special construct called a `retpoline` to
342// mitigate potential Spectre v2 attacks against them.
343def FeatureRetpolineIndirectCalls
344    : SubtargetFeature<
345          "retpoline-indirect-calls", "UseRetpolineIndirectCalls", "true",
346          "Remove speculation of indirect calls from the generated code">;
347
348// Lower indirect branches and switches either using conditional branch trees
349// or using a special construct called a `retpoline` to mitigate potential
350// Spectre v2 attacks against them.
351def FeatureRetpolineIndirectBranches
352    : SubtargetFeature<
353          "retpoline-indirect-branches", "UseRetpolineIndirectBranches", "true",
354          "Remove speculation of indirect branches from the generated code">;
355
356// Deprecated umbrella feature for enabling both `retpoline-indirect-calls` and
357// `retpoline-indirect-branches` above.
358def FeatureRetpoline
359    : SubtargetFeature<"retpoline", "DeprecatedUseRetpoline", "true",
360                       "Remove speculation of indirect branches from the "
361                       "generated code, either by avoiding them entirely or "
362                       "lowering them with a speculation blocking construct",
363                       [FeatureRetpolineIndirectCalls,
364                        FeatureRetpolineIndirectBranches]>;
365
366// Rely on external thunks for the emitted retpoline calls. This allows users
367// to provide their own custom thunk definitions in highly specialized
368// environments such as a kernel that does boot-time hot patching.
369def FeatureRetpolineExternalThunk
370    : SubtargetFeature<
371          "retpoline-external-thunk", "UseRetpolineExternalThunk", "true",
372          "When lowering an indirect call or branch using a `retpoline`, rely "
373          "on the specified user provided thunk rather than emitting one "
374          "ourselves. Only has effect when combined with some other retpoline "
375          "feature", [FeatureRetpolineIndirectCalls]>;
376
377// Mitigate LVI attacks against indirect calls/branches and call returns
378def FeatureLVIControlFlowIntegrity
379    : SubtargetFeature<
380          "lvi-cfi", "UseLVIControlFlowIntegrity", "true",
381          "Prevent indirect calls/branches from using a memory operand, and "
382          "precede all indirect calls/branches from a register with an "
383          "LFENCE instruction to serialize control flow. Also decompose RET "
384          "instructions into a POP+LFENCE+JMP sequence.">;
385
386// Enable SESES to mitigate speculative execution attacks
387def FeatureSpeculativeExecutionSideEffectSuppression
388    : SubtargetFeature<
389          "seses", "UseSpeculativeExecutionSideEffectSuppression", "true",
390          "Prevent speculative execution side channel timing attacks by "
391          "inserting a speculation barrier before memory reads, memory writes, "
392          "and conditional branches. Implies LVI Control Flow integrity.",
393          [FeatureLVIControlFlowIntegrity]>;
394
395// Mitigate LVI attacks against data loads
396def FeatureLVILoadHardening
397    : SubtargetFeature<
398          "lvi-load-hardening", "UseLVILoadHardening", "true",
399          "Insert LFENCE instructions to prevent data speculatively injected "
400          "into loads from being used maliciously.">;
401
402def FeatureTaggedGlobals
403    : SubtargetFeature<
404          "tagged-globals", "AllowTaggedGlobals", "true",
405          "Use an instruction sequence for taking the address of a global "
406          "that allows a memory tag in the upper address bits.">;
407
408// Control codegen mitigation against Straight Line Speculation vulnerability.
409def FeatureHardenSlsRet
410    : SubtargetFeature<
411          "harden-sls-ret", "HardenSlsRet", "true",
412          "Harden against straight line speculation across RET instructions.">;
413
414def FeatureHardenSlsIJmp
415    : SubtargetFeature<
416          "harden-sls-ijmp", "HardenSlsIJmp", "true",
417          "Harden against straight line speculation across indirect JMP instructions.">;
418
419//===----------------------------------------------------------------------===//
420// X86 Subtarget Tuning features
421//===----------------------------------------------------------------------===//
422
423def TuningSlowSHLD : SubtargetFeature<"slow-shld", "IsSHLDSlow", "true",
424                                       "SHLD instruction is slow">;
425
426def TuningSlowPMULLD : SubtargetFeature<"slow-pmulld", "IsPMULLDSlow", "true",
427                                        "PMULLD instruction is slow (compared to PMULLW/PMULHW and PMULUDQ)">;
428
429def TuningSlowPMADDWD : SubtargetFeature<"slow-pmaddwd", "IsPMADDWDSlow",
430                                          "true",
431                                          "PMADDWD is slower than PMULLD">;
432
433// FIXME: This should not apply to CPUs that do not have SSE.
434def TuningSlowUAMem16 : SubtargetFeature<"slow-unaligned-mem-16",
435                                "IsUnalignedMem16Slow", "true",
436                                "Slow unaligned 16-byte memory access">;
437
438def TuningSlowUAMem32 : SubtargetFeature<"slow-unaligned-mem-32",
439                                "IsUnalignedMem32Slow", "true",
440                                "Slow unaligned 32-byte memory access">;
441
442def TuningLEAForSP : SubtargetFeature<"lea-sp", "UseLeaForSP", "true",
443                                     "Use LEA for adjusting the stack pointer (this is an optimization for Intel Atom processors)">;
444
445// True if 8-bit divisions are significantly faster than
446// 32-bit divisions and should be used when possible.
447def TuningSlowDivide32 : SubtargetFeature<"idivl-to-divb",
448                                     "HasSlowDivide32", "true",
449                                     "Use 8-bit divide for positive values less than 256">;
450
451// True if 32-bit divides are significantly faster than
452// 64-bit divisions and should be used when possible.
453def TuningSlowDivide64 : SubtargetFeature<"idivq-to-divl",
454                                     "HasSlowDivide64", "true",
455                                     "Use 32-bit divide for positive values less than 2^32">;
456
457def TuningPadShortFunctions : SubtargetFeature<"pad-short-functions",
458                                     "PadShortFunctions", "true",
459                                     "Pad short functions (to prevent a stall when returning too early)">;
460
461// On some processors, instructions that implicitly take two memory operands are
462// slow. In practice, this means that CALL, PUSH, and POP with memory operands
463// should be avoided in favor of a MOV + register CALL/PUSH/POP.
464def TuningSlowTwoMemOps : SubtargetFeature<"slow-two-mem-ops",
465                                     "SlowTwoMemOps", "true",
466                                     "Two memory operand instructions are slow">;
467
468// True if the LEA instruction inputs have to be ready at address generation
469// (AG) time.
470def TuningLEAUsesAG : SubtargetFeature<"lea-uses-ag", "LeaUsesAG", "true",
471                                   "LEA instruction needs inputs at AG stage">;
472
473def TuningSlowLEA : SubtargetFeature<"slow-lea", "SlowLEA", "true",
474                                   "LEA instruction with certain arguments is slow">;
475
476// True if the LEA instruction has all three source operands: base, index,
477// and offset or if the LEA instruction uses base and index registers where
478// the base is EBP, RBP,or R13
479def TuningSlow3OpsLEA : SubtargetFeature<"slow-3ops-lea", "Slow3OpsLEA", "true",
480                                   "LEA instruction with 3 ops or certain registers is slow">;
481
482// True if INC and DEC instructions are slow when writing to flags
483def TuningSlowIncDec : SubtargetFeature<"slow-incdec", "SlowIncDec", "true",
484                                   "INC and DEC instructions are slower than ADD and SUB">;
485
486def TuningPOPCNTFalseDeps : SubtargetFeature<"false-deps-popcnt",
487                                     "HasPOPCNTFalseDeps", "true",
488                                     "POPCNT has a false dependency on dest register">;
489
490def TuningLZCNTFalseDeps : SubtargetFeature<"false-deps-lzcnt-tzcnt",
491                                     "HasLZCNTFalseDeps", "true",
492                                     "LZCNT/TZCNT have a false dependency on dest register">;
493
494def TuningMULCFalseDeps : SubtargetFeature<"false-deps-mulc",
495                               "HasMULCFalseDeps", "true",
496                               "VF[C]MULCPH/SH has a false dependency on dest register">;
497
498def TuningPERMFalseDeps : SubtargetFeature<"false-deps-perm",
499                               "HasPERMFalseDeps", "true",
500                               "VPERMD/Q/PS/PD has a false dependency on dest register">;
501
502def TuningRANGEFalseDeps : SubtargetFeature<"false-deps-range",
503                               "HasRANGEFalseDeps", "true",
504                               "VRANGEPD/PS/SD/SS has a false dependency on dest register">;
505
506def TuningGETMANTFalseDeps : SubtargetFeature<"false-deps-getmant",
507                               "HasGETMANTFalseDeps", "true",
508                               "VGETMANTSS/SD/SH and VGETMANDPS/PD(memory version) has a"
509                               " false dependency on dest register">;
510
511def TuningMULLQFalseDeps : SubtargetFeature<"false-deps-mullq",
512                               "HasMULLQFalseDeps", "true",
513                               "VPMULLQ has a false dependency on dest register">;
514
515def TuningSBBDepBreaking : SubtargetFeature<"sbb-dep-breaking",
516                                     "HasSBBDepBreaking", "true",
517                                     "SBB with same register has no source dependency">;
518
519// On recent X86 (port bound) processors, its preferable to combine to a single shuffle
520// using a variable mask over multiple fixed shuffles.
521def TuningFastVariableCrossLaneShuffle
522    : SubtargetFeature<"fast-variable-crosslane-shuffle",
523                       "HasFastVariableCrossLaneShuffle",
524                       "true", "Cross-lane shuffles with variable masks are fast">;
525def TuningFastVariablePerLaneShuffle
526    : SubtargetFeature<"fast-variable-perlane-shuffle",
527                       "HasFastVariablePerLaneShuffle",
528                       "true", "Per-lane shuffles with variable masks are fast">;
529
530// On some X86 processors, a vzeroupper instruction should be inserted after
531// using ymm/zmm registers before executing code that may use SSE instructions.
532def TuningInsertVZEROUPPER
533    : SubtargetFeature<"vzeroupper",
534                       "InsertVZEROUPPER",
535                       "true", "Should insert vzeroupper instructions">;
536
537// TuningFastScalarFSQRT should be enabled if scalar FSQRT has shorter latency
538// than the corresponding NR code. TuningFastVectorFSQRT should be enabled if
539// vector FSQRT has higher throughput than the corresponding NR code.
540// The idea is that throughput bound code is likely to be vectorized, so for
541// vectorized code we should care about the throughput of SQRT operations.
542// But if the code is scalar that probably means that the code has some kind of
543// dependency and we should care more about reducing the latency.
544
545// True if hardware SQRTSS instruction is at least as fast (latency) as
546// RSQRTSS followed by a Newton-Raphson iteration.
547def TuningFastScalarFSQRT
548    : SubtargetFeature<"fast-scalar-fsqrt", "HasFastScalarFSQRT",
549                       "true", "Scalar SQRT is fast (disable Newton-Raphson)">;
550// True if hardware SQRTPS/VSQRTPS instructions are at least as fast
551// (throughput) as RSQRTPS/VRSQRTPS followed by a Newton-Raphson iteration.
552def TuningFastVectorFSQRT
553    : SubtargetFeature<"fast-vector-fsqrt", "HasFastVectorFSQRT",
554                       "true", "Vector SQRT is fast (disable Newton-Raphson)">;
555
556// If lzcnt has equivalent latency/throughput to most simple integer ops, it can
557// be used to replace test/set sequences.
558def TuningFastLZCNT
559    : SubtargetFeature<
560          "fast-lzcnt", "HasFastLZCNT", "true",
561          "LZCNT instructions are as fast as most simple integer ops">;
562
563// If the target can efficiently decode NOPs upto 7-bytes in length.
564def TuningFast7ByteNOP
565    : SubtargetFeature<
566          "fast-7bytenop", "HasFast7ByteNOP", "true",
567          "Target can quickly decode up to 7 byte NOPs">;
568
569// If the target can efficiently decode NOPs upto 11-bytes in length.
570def TuningFast11ByteNOP
571    : SubtargetFeature<
572          "fast-11bytenop", "HasFast11ByteNOP", "true",
573          "Target can quickly decode up to 11 byte NOPs">;
574
575// If the target can efficiently decode NOPs upto 15-bytes in length.
576def TuningFast15ByteNOP
577    : SubtargetFeature<
578          "fast-15bytenop", "HasFast15ByteNOP", "true",
579          "Target can quickly decode up to 15 byte NOPs">;
580
581// Sandy Bridge and newer processors can use SHLD with the same source on both
582// inputs to implement rotate to avoid the partial flag update of the normal
583// rotate instructions.
584def TuningFastSHLDRotate
585    : SubtargetFeature<
586          "fast-shld-rotate", "HasFastSHLDRotate", "true",
587          "SHLD can be used as a faster rotate">;
588
589// Bulldozer and newer processors can merge CMP/TEST (but not other
590// instructions) with conditional branches.
591def TuningBranchFusion
592    : SubtargetFeature<"branchfusion", "HasBranchFusion", "true",
593                 "CMP/TEST can be fused with conditional branches">;
594
595// Sandy Bridge and newer processors have many instructions that can be
596// fused with conditional branches and pass through the CPU as a single
597// operation.
598def TuningMacroFusion
599    : SubtargetFeature<"macrofusion", "HasMacroFusion", "true",
600                 "Various instructions can be fused with conditional branches">;
601
602// Gather is available since Haswell (AVX2 set). So technically, we can
603// generate Gathers on all AVX2 processors. But the overhead on HSW is high.
604// Skylake Client processor has faster Gathers than HSW and performance is
605// similar to Skylake Server (AVX-512).
606def TuningFastGather
607    : SubtargetFeature<"fast-gather", "HasFastGather", "true",
608                       "Indicates if gather is reasonably fast (this is true for Skylake client and all AVX-512 CPUs)">;
609
610def TuningPrefer128Bit
611    : SubtargetFeature<"prefer-128-bit", "Prefer128Bit", "true",
612                       "Prefer 128-bit AVX instructions">;
613
614def TuningPrefer256Bit
615    : SubtargetFeature<"prefer-256-bit", "Prefer256Bit", "true",
616                       "Prefer 256-bit AVX instructions">;
617
618def TuningAllowLight256Bit
619    : SubtargetFeature<"allow-light-256-bit", "AllowLight256Bit", "true",
620                       "Enable generation of 256-bit load/stores even if we prefer 128-bit">;
621
622def TuningPreferMaskRegisters
623    : SubtargetFeature<"prefer-mask-registers", "PreferMaskRegisters", "true",
624                       "Prefer AVX512 mask registers over PTEST/MOVMSK">;
625
626def TuningFastBEXTR : SubtargetFeature<"fast-bextr", "HasFastBEXTR", "true",
627          "Indicates that the BEXTR instruction is implemented as a single uop "
628          "with good throughput">;
629
630// Combine vector math operations with shuffles into horizontal math
631// instructions if a CPU implements horizontal operations (introduced with
632// SSE3) with better latency/throughput than the alternative sequence.
633def TuningFastHorizontalOps
634    : SubtargetFeature<
635        "fast-hops", "HasFastHorizontalOps", "true",
636        "Prefer horizontal vector math instructions (haddp, phsub, etc.) over "
637        "normal vector instructions with shuffles">;
638
639def TuningFastScalarShiftMasks
640    : SubtargetFeature<
641        "fast-scalar-shift-masks", "HasFastScalarShiftMasks", "true",
642        "Prefer a left/right scalar logical shift pair over a shift+and pair">;
643
644def TuningFastVectorShiftMasks
645    : SubtargetFeature<
646        "fast-vector-shift-masks", "HasFastVectorShiftMasks", "true",
647        "Prefer a left/right vector logical shift pair over a shift+and pair">;
648
649def TuningFastMOVBE
650    : SubtargetFeature<"fast-movbe", "HasFastMOVBE", "true",
651    "Prefer a movbe over a single-use load + bswap / single-use bswap + store">;
652
653def TuningUseSLMArithCosts
654    : SubtargetFeature<"use-slm-arith-costs", "UseSLMArithCosts", "true",
655        "Use Silvermont specific arithmetic costs">;
656
657def TuningUseGLMDivSqrtCosts
658    : SubtargetFeature<"use-glm-div-sqrt-costs", "UseGLMDivSqrtCosts", "true",
659        "Use Goldmont specific floating point div/sqrt costs">;
660
661//===----------------------------------------------------------------------===//
662// X86 CPU Families
663// TODO: Remove these - use general tuning features to determine codegen.
664//===----------------------------------------------------------------------===//
665
666// Bonnell
667def ProcIntelAtom : SubtargetFeature<"", "IsAtom", "true", "Is Intel Atom processor">;
668
669//===----------------------------------------------------------------------===//
670// Register File Description
671//===----------------------------------------------------------------------===//
672
673include "X86RegisterInfo.td"
674include "X86RegisterBanks.td"
675
676//===----------------------------------------------------------------------===//
677// Instruction Descriptions
678//===----------------------------------------------------------------------===//
679
680include "X86Schedule.td"
681include "X86InstrInfo.td"
682include "X86SchedPredicates.td"
683
684def X86InstrInfo : InstrInfo;
685
686//===----------------------------------------------------------------------===//
687// X86 Scheduler Models
688//===----------------------------------------------------------------------===//
689
690include "X86ScheduleAtom.td"
691include "X86SchedSandyBridge.td"
692include "X86SchedHaswell.td"
693include "X86SchedBroadwell.td"
694include "X86ScheduleSLM.td"
695include "X86ScheduleZnver1.td"
696include "X86ScheduleZnver2.td"
697include "X86ScheduleZnver3.td"
698include "X86ScheduleBdVer2.td"
699include "X86ScheduleBtVer2.td"
700include "X86SchedSkylakeClient.td"
701include "X86SchedSkylakeServer.td"
702include "X86SchedIceLake.td"
703include "X86SchedAlderlakeP.td"
704
705//===----------------------------------------------------------------------===//
706// X86 Processor Feature Lists
707//===----------------------------------------------------------------------===//
708
709def ProcessorFeatures {
710  // x86-64 and x86-64-v[234]
711  list<SubtargetFeature> X86_64V1Features = [
712    FeatureX87, FeatureCX8, FeatureCMOV, FeatureMMX, FeatureSSE2,
713    FeatureFXSR, FeatureNOPL, FeatureX86_64,
714  ];
715  list<SubtargetFeature> X86_64V2Features = !listconcat(X86_64V1Features, [
716    FeatureCX16, FeatureLAHFSAHF64, FeatureCRC32, FeaturePOPCNT,
717    FeatureSSE42
718  ]);
719  list<SubtargetFeature> X86_64V3Features = !listconcat(X86_64V2Features, [
720    FeatureAVX2, FeatureBMI, FeatureBMI2, FeatureF16C, FeatureFMA, FeatureLZCNT,
721    FeatureMOVBE, FeatureXSAVE
722  ]);
723  list<SubtargetFeature> X86_64V4Features = !listconcat(X86_64V3Features, [
724    FeatureBWI,
725    FeatureCDI,
726    FeatureDQI,
727    FeatureVLX,
728  ]);
729
730  // Nehalem
731  list<SubtargetFeature> NHMFeatures = X86_64V2Features;
732  list<SubtargetFeature> NHMTuning = [TuningMacroFusion,
733                                      TuningInsertVZEROUPPER];
734
735  // Westmere
736  list<SubtargetFeature> WSMAdditionalFeatures = [FeaturePCLMUL];
737  list<SubtargetFeature> WSMTuning = NHMTuning;
738  list<SubtargetFeature> WSMFeatures =
739    !listconcat(NHMFeatures, WSMAdditionalFeatures);
740
741  // Sandybridge
742  list<SubtargetFeature> SNBAdditionalFeatures = [FeatureAVX,
743                                                  FeatureXSAVE,
744                                                  FeatureXSAVEOPT];
745  list<SubtargetFeature> SNBTuning = [TuningMacroFusion,
746                                      TuningSlow3OpsLEA,
747                                      TuningSlowDivide64,
748                                      TuningSlowUAMem32,
749                                      TuningFastScalarFSQRT,
750                                      TuningFastSHLDRotate,
751                                      TuningFast15ByteNOP,
752                                      TuningPOPCNTFalseDeps,
753                                      TuningInsertVZEROUPPER];
754  list<SubtargetFeature> SNBFeatures =
755    !listconcat(WSMFeatures, SNBAdditionalFeatures);
756
757  // Ivybridge
758  list<SubtargetFeature> IVBAdditionalFeatures = [FeatureRDRAND,
759                                                  FeatureF16C,
760                                                  FeatureFSGSBase];
761  list<SubtargetFeature> IVBTuning = SNBTuning;
762  list<SubtargetFeature> IVBFeatures =
763    !listconcat(SNBFeatures, IVBAdditionalFeatures);
764
765  // Haswell
766  list<SubtargetFeature> HSWAdditionalFeatures = [FeatureAVX2,
767                                                  FeatureBMI,
768                                                  FeatureBMI2,
769                                                  FeatureERMSB,
770                                                  FeatureFMA,
771                                                  FeatureINVPCID,
772                                                  FeatureLZCNT,
773                                                  FeatureMOVBE];
774  list<SubtargetFeature> HSWTuning = [TuningMacroFusion,
775                                      TuningSlow3OpsLEA,
776                                      TuningSlowDivide64,
777                                      TuningFastScalarFSQRT,
778                                      TuningFastSHLDRotate,
779                                      TuningFast15ByteNOP,
780                                      TuningFastVariableCrossLaneShuffle,
781                                      TuningFastVariablePerLaneShuffle,
782                                      TuningPOPCNTFalseDeps,
783                                      TuningLZCNTFalseDeps,
784                                      TuningInsertVZEROUPPER,
785                                      TuningAllowLight256Bit];
786  list<SubtargetFeature> HSWFeatures =
787    !listconcat(IVBFeatures, HSWAdditionalFeatures);
788
789  // Broadwell
790  list<SubtargetFeature> BDWAdditionalFeatures = [FeatureADX,
791                                                  FeatureRDSEED,
792                                                  FeaturePRFCHW];
793  list<SubtargetFeature> BDWTuning = HSWTuning;
794  list<SubtargetFeature> BDWFeatures =
795    !listconcat(HSWFeatures, BDWAdditionalFeatures);
796
797  // Skylake
798  list<SubtargetFeature> SKLAdditionalFeatures = [FeatureAES,
799                                                  FeatureXSAVEC,
800                                                  FeatureXSAVES,
801                                                  FeatureCLFLUSHOPT];
802  list<SubtargetFeature> SKLTuning = [TuningFastGather,
803                                      TuningMacroFusion,
804                                      TuningSlow3OpsLEA,
805                                      TuningSlowDivide64,
806                                      TuningFastScalarFSQRT,
807                                      TuningFastVectorFSQRT,
808                                      TuningFastSHLDRotate,
809                                      TuningFast15ByteNOP,
810                                      TuningFastVariableCrossLaneShuffle,
811                                      TuningFastVariablePerLaneShuffle,
812                                      TuningPOPCNTFalseDeps,
813                                      TuningInsertVZEROUPPER,
814                                      TuningAllowLight256Bit];
815  list<SubtargetFeature> SKLFeatures =
816    !listconcat(BDWFeatures, SKLAdditionalFeatures);
817
818  // Skylake-AVX512
819  list<SubtargetFeature> SKXAdditionalFeatures = [FeatureAES,
820                                                  FeatureXSAVEC,
821                                                  FeatureXSAVES,
822                                                  FeatureCLFLUSHOPT,
823                                                  FeatureAVX512,
824                                                  FeatureCDI,
825                                                  FeatureDQI,
826                                                  FeatureBWI,
827                                                  FeatureVLX,
828                                                  FeaturePKU,
829                                                  FeatureCLWB];
830  list<SubtargetFeature> SKXTuning = [TuningFastGather,
831                                      TuningMacroFusion,
832                                      TuningSlow3OpsLEA,
833                                      TuningSlowDivide64,
834                                      TuningFastScalarFSQRT,
835                                      TuningFastVectorFSQRT,
836                                      TuningFastSHLDRotate,
837                                      TuningFast15ByteNOP,
838                                      TuningFastVariableCrossLaneShuffle,
839                                      TuningFastVariablePerLaneShuffle,
840                                      TuningPrefer256Bit,
841                                      TuningPOPCNTFalseDeps,
842                                      TuningInsertVZEROUPPER,
843                                      TuningAllowLight256Bit];
844  list<SubtargetFeature> SKXFeatures =
845    !listconcat(BDWFeatures, SKXAdditionalFeatures);
846
847  // Cascadelake
848  list<SubtargetFeature> CLXAdditionalFeatures = [FeatureVNNI];
849  list<SubtargetFeature> CLXTuning = SKXTuning;
850  list<SubtargetFeature> CLXFeatures =
851    !listconcat(SKXFeatures, CLXAdditionalFeatures);
852
853  // Cooperlake
854  list<SubtargetFeature> CPXAdditionalFeatures = [FeatureBF16];
855  list<SubtargetFeature> CPXTuning = SKXTuning;
856  list<SubtargetFeature> CPXFeatures =
857    !listconcat(CLXFeatures, CPXAdditionalFeatures);
858
859  // Cannonlake
860  list<SubtargetFeature> CNLAdditionalFeatures = [FeatureAVX512,
861                                                  FeatureCDI,
862                                                  FeatureDQI,
863                                                  FeatureBWI,
864                                                  FeatureVLX,
865                                                  FeaturePKU,
866                                                  FeatureVBMI,
867                                                  FeatureIFMA,
868                                                  FeatureSHA];
869  list<SubtargetFeature> CNLTuning = [TuningFastGather,
870                                      TuningMacroFusion,
871                                      TuningSlow3OpsLEA,
872                                      TuningSlowDivide64,
873                                      TuningFastScalarFSQRT,
874                                      TuningFastVectorFSQRT,
875                                      TuningFastSHLDRotate,
876                                      TuningFast15ByteNOP,
877                                      TuningFastVariableCrossLaneShuffle,
878                                      TuningFastVariablePerLaneShuffle,
879                                      TuningPrefer256Bit,
880                                      TuningInsertVZEROUPPER,
881                                      TuningAllowLight256Bit];
882  list<SubtargetFeature> CNLFeatures =
883    !listconcat(SKLFeatures, CNLAdditionalFeatures);
884
885  // Icelake
886  list<SubtargetFeature> ICLAdditionalFeatures = [FeatureBITALG,
887                                                  FeatureVAES,
888                                                  FeatureVBMI2,
889                                                  FeatureVNNI,
890                                                  FeatureVPCLMULQDQ,
891                                                  FeatureVPOPCNTDQ,
892                                                  FeatureGFNI,
893                                                  FeatureRDPID,
894                                                  FeatureFSRM];
895  list<SubtargetFeature> ICLTuning = [TuningFastGather,
896                                      TuningMacroFusion,
897                                      TuningSlowDivide64,
898                                      TuningFastScalarFSQRT,
899                                      TuningFastVectorFSQRT,
900                                      TuningFastSHLDRotate,
901                                      TuningFast15ByteNOP,
902                                      TuningFastVariableCrossLaneShuffle,
903                                      TuningFastVariablePerLaneShuffle,
904                                      TuningPrefer256Bit,
905                                      TuningInsertVZEROUPPER,
906                                      TuningAllowLight256Bit];
907  list<SubtargetFeature> ICLFeatures =
908    !listconcat(CNLFeatures, ICLAdditionalFeatures);
909
910  // Icelake Server
911  list<SubtargetFeature> ICXAdditionalFeatures = [FeaturePCONFIG,
912                                                  FeatureCLWB,
913                                                  FeatureWBNOINVD];
914  list<SubtargetFeature> ICXTuning = ICLTuning;
915  list<SubtargetFeature> ICXFeatures =
916    !listconcat(ICLFeatures, ICXAdditionalFeatures);
917
918  // Tigerlake
919  list<SubtargetFeature> TGLAdditionalFeatures = [FeatureVP2INTERSECT,
920                                                  FeatureCLWB,
921                                                  FeatureMOVDIRI,
922                                                  FeatureMOVDIR64B,
923                                                  FeatureSHSTK];
924  list<SubtargetFeature> TGLTuning = ICLTuning;
925  list<SubtargetFeature> TGLFeatures =
926    !listconcat(ICLFeatures, TGLAdditionalFeatures );
927
928  // Sapphirerapids
929  list<SubtargetFeature> SPRAdditionalFeatures = [FeatureAMXTILE,
930                                                  FeatureAMXINT8,
931                                                  FeatureAMXBF16,
932                                                  FeatureBF16,
933                                                  FeatureSERIALIZE,
934                                                  FeatureCLDEMOTE,
935                                                  FeatureWAITPKG,
936                                                  FeaturePTWRITE,
937                                                  FeatureFP16,
938                                                  FeatureAVXVNNI,
939                                                  FeatureTSXLDTRK,
940                                                  FeatureENQCMD,
941                                                  FeatureSHSTK,
942                                                  FeatureMOVDIRI,
943                                                  FeatureMOVDIR64B,
944                                                  FeatureUINTR];
945  list<SubtargetFeature> SPRAdditionalTuning = [TuningMULCFalseDeps,
946                                                TuningPERMFalseDeps,
947                                                TuningRANGEFalseDeps,
948                                                TuningGETMANTFalseDeps,
949                                                TuningMULLQFalseDeps];
950  list<SubtargetFeature> SPRTuning = !listconcat(ICXTuning, SPRAdditionalTuning);
951  list<SubtargetFeature> SPRFeatures =
952    !listconcat(ICXFeatures, SPRAdditionalFeatures);
953
954  // Graniterapids
955  list<SubtargetFeature> GNRAdditionalFeatures = [FeatureAMXFP16,
956                                                  FeaturePREFETCHI];
957  list<SubtargetFeature> GNRFeatures =
958    !listconcat(SPRFeatures, GNRAdditionalFeatures);
959
960  // Atom
961  list<SubtargetFeature> AtomFeatures = [FeatureX87,
962                                         FeatureCX8,
963                                         FeatureCMOV,
964                                         FeatureMMX,
965                                         FeatureSSSE3,
966                                         FeatureFXSR,
967                                         FeatureNOPL,
968                                         FeatureX86_64,
969                                         FeatureCX16,
970                                         FeatureMOVBE,
971                                         FeatureLAHFSAHF64];
972  list<SubtargetFeature> AtomTuning = [ProcIntelAtom,
973                                       TuningSlowUAMem16,
974                                       TuningLEAForSP,
975                                       TuningSlowDivide32,
976                                       TuningSlowDivide64,
977                                       TuningSlowTwoMemOps,
978                                       TuningLEAUsesAG,
979                                       TuningPadShortFunctions,
980                                       TuningInsertVZEROUPPER];
981
982  // Silvermont
983  list<SubtargetFeature> SLMAdditionalFeatures = [FeatureSSE42,
984                                                  FeatureCRC32,
985                                                  FeaturePOPCNT,
986                                                  FeaturePCLMUL,
987                                                  FeaturePRFCHW,
988                                                  FeatureRDRAND];
989  list<SubtargetFeature> SLMTuning = [TuningUseSLMArithCosts,
990                                      TuningSlowTwoMemOps,
991                                      TuningSlowLEA,
992                                      TuningSlowIncDec,
993                                      TuningSlowDivide64,
994                                      TuningSlowPMULLD,
995                                      TuningFast7ByteNOP,
996                                      TuningFastMOVBE,
997                                      TuningPOPCNTFalseDeps,
998                                      TuningInsertVZEROUPPER];
999  list<SubtargetFeature> SLMFeatures =
1000    !listconcat(AtomFeatures, SLMAdditionalFeatures);
1001
1002  // Goldmont
1003  list<SubtargetFeature> GLMAdditionalFeatures = [FeatureAES,
1004                                                  FeatureSHA,
1005                                                  FeatureRDSEED,
1006                                                  FeatureXSAVE,
1007                                                  FeatureXSAVEOPT,
1008                                                  FeatureXSAVEC,
1009                                                  FeatureXSAVES,
1010                                                  FeatureCLFLUSHOPT,
1011                                                  FeatureFSGSBase];
1012  list<SubtargetFeature> GLMTuning = [TuningUseGLMDivSqrtCosts,
1013                                      TuningSlowTwoMemOps,
1014                                      TuningSlowLEA,
1015                                      TuningSlowIncDec,
1016                                      TuningFastMOVBE,
1017                                      TuningPOPCNTFalseDeps,
1018                                      TuningInsertVZEROUPPER];
1019  list<SubtargetFeature> GLMFeatures =
1020    !listconcat(SLMFeatures, GLMAdditionalFeatures);
1021
1022  // Goldmont Plus
1023  list<SubtargetFeature> GLPAdditionalFeatures = [FeaturePTWRITE,
1024                                                  FeatureRDPID];
1025  list<SubtargetFeature> GLPTuning = [TuningUseGLMDivSqrtCosts,
1026                                      TuningSlowTwoMemOps,
1027                                      TuningSlowLEA,
1028                                      TuningSlowIncDec,
1029                                      TuningFastMOVBE,
1030                                      TuningInsertVZEROUPPER];
1031  list<SubtargetFeature> GLPFeatures =
1032    !listconcat(GLMFeatures, GLPAdditionalFeatures);
1033
1034  // Tremont
1035  list<SubtargetFeature> TRMAdditionalFeatures = [FeatureCLWB,
1036                                                  FeatureGFNI];
1037  list<SubtargetFeature> TRMTuning = GLPTuning;
1038  list<SubtargetFeature> TRMFeatures =
1039    !listconcat(GLPFeatures, TRMAdditionalFeatures);
1040
1041  // Alderlake
1042  list<SubtargetFeature> ADLAdditionalFeatures = [FeatureSERIALIZE,
1043                                                  FeaturePCONFIG,
1044                                                  FeatureSHSTK,
1045                                                  FeatureWIDEKL,
1046                                                  FeatureINVPCID,
1047                                                  FeatureADX,
1048                                                  FeatureFMA,
1049                                                  FeatureVAES,
1050                                                  FeatureVPCLMULQDQ,
1051                                                  FeatureF16C,
1052                                                  FeatureBMI,
1053                                                  FeatureBMI2,
1054                                                  FeatureLZCNT,
1055                                                  FeatureAVXVNNI,
1056                                                  FeaturePKU,
1057                                                  FeatureHRESET,
1058                                                  FeatureCLDEMOTE,
1059                                                  FeatureMOVDIRI,
1060                                                  FeatureMOVDIR64B,
1061                                                  FeatureWAITPKG];
1062  list<SubtargetFeature> ADLAdditionalTuning = [TuningPERMFalseDeps];
1063  list<SubtargetFeature> ADLTuning = !listconcat(SKLTuning, ADLAdditionalTuning);
1064  list<SubtargetFeature> ADLFeatures =
1065    !listconcat(TRMFeatures, ADLAdditionalFeatures);
1066
1067  // Sierraforest
1068  list<SubtargetFeature> SRFAdditionalFeatures = [FeatureCMPCCXADD,
1069                                                  FeatureAVXIFMA,
1070                                                  FeatureAVXNECONVERT,
1071                                                  FeatureAVXVNNIINT8];
1072  list<SubtargetFeature> SRFFeatures =
1073    !listconcat(ADLFeatures, SRFAdditionalFeatures);
1074
1075  // Grandridge
1076  list<SubtargetFeature> GRRAdditionalFeatures = [FeatureRAOINT];
1077  list<SubtargetFeature> GRRFeatures =
1078    !listconcat(SRFFeatures, GRRAdditionalFeatures);
1079
1080  // Knights Landing
1081  list<SubtargetFeature> KNLFeatures = [FeatureX87,
1082                                        FeatureCX8,
1083                                        FeatureCMOV,
1084                                        FeatureMMX,
1085                                        FeatureFXSR,
1086                                        FeatureNOPL,
1087                                        FeatureX86_64,
1088                                        FeatureCX16,
1089                                        FeatureCRC32,
1090                                        FeaturePOPCNT,
1091                                        FeaturePCLMUL,
1092                                        FeatureXSAVE,
1093                                        FeatureXSAVEOPT,
1094                                        FeatureLAHFSAHF64,
1095                                        FeatureAES,
1096                                        FeatureRDRAND,
1097                                        FeatureF16C,
1098                                        FeatureFSGSBase,
1099                                        FeatureAVX512,
1100                                        FeatureERI,
1101                                        FeatureCDI,
1102                                        FeaturePFI,
1103                                        FeaturePREFETCHWT1,
1104                                        FeatureADX,
1105                                        FeatureRDSEED,
1106                                        FeatureMOVBE,
1107                                        FeatureLZCNT,
1108                                        FeatureBMI,
1109                                        FeatureBMI2,
1110                                        FeatureFMA,
1111                                        FeaturePRFCHW];
1112  list<SubtargetFeature> KNLTuning = [TuningSlowDivide64,
1113                                      TuningSlow3OpsLEA,
1114                                      TuningSlowIncDec,
1115                                      TuningSlowTwoMemOps,
1116                                      TuningPreferMaskRegisters,
1117                                      TuningFastGather,
1118                                      TuningFastMOVBE,
1119                                      TuningSlowPMADDWD];
1120  // TODO Add AVX5124FMAPS/AVX5124VNNIW features
1121  list<SubtargetFeature> KNMFeatures =
1122    !listconcat(KNLFeatures, [FeatureVPOPCNTDQ]);
1123
1124  // Barcelona
1125  list<SubtargetFeature> BarcelonaFeatures = [FeatureX87,
1126                                              FeatureCX8,
1127                                              FeatureSSE4A,
1128                                              Feature3DNowA,
1129                                              FeatureFXSR,
1130                                              FeatureNOPL,
1131                                              FeatureCX16,
1132                                              FeaturePRFCHW,
1133                                              FeatureLZCNT,
1134                                              FeaturePOPCNT,
1135                                              FeatureLAHFSAHF64,
1136                                              FeatureCMOV,
1137                                              FeatureX86_64];
1138  list<SubtargetFeature> BarcelonaTuning = [TuningFastScalarShiftMasks,
1139                                            TuningSlowSHLD,
1140                                            TuningSBBDepBreaking,
1141                                            TuningInsertVZEROUPPER];
1142
1143  // Bobcat
1144  list<SubtargetFeature> BtVer1Features = [FeatureX87,
1145                                           FeatureCX8,
1146                                           FeatureCMOV,
1147                                           FeatureMMX,
1148                                           FeatureSSSE3,
1149                                           FeatureSSE4A,
1150                                           FeatureFXSR,
1151                                           FeatureNOPL,
1152                                           FeatureX86_64,
1153                                           FeatureCX16,
1154                                           FeaturePRFCHW,
1155                                           FeatureLZCNT,
1156                                           FeaturePOPCNT,
1157                                           FeatureLAHFSAHF64];
1158  list<SubtargetFeature> BtVer1Tuning = [TuningFast15ByteNOP,
1159                                         TuningFastScalarShiftMasks,
1160                                         TuningFastVectorShiftMasks,
1161                                         TuningSlowSHLD,
1162                                         TuningSBBDepBreaking,
1163                                         TuningInsertVZEROUPPER];
1164
1165  // Jaguar
1166  list<SubtargetFeature> BtVer2AdditionalFeatures = [FeatureAVX,
1167                                                     FeatureAES,
1168                                                     FeatureCRC32,
1169                                                     FeaturePCLMUL,
1170                                                     FeatureBMI,
1171                                                     FeatureF16C,
1172                                                     FeatureMOVBE,
1173                                                     FeatureXSAVE,
1174                                                     FeatureXSAVEOPT];
1175  list<SubtargetFeature> BtVer2Tuning = [TuningFastLZCNT,
1176                                         TuningFastBEXTR,
1177                                         TuningFastHorizontalOps,
1178                                         TuningFast15ByteNOP,
1179                                         TuningFastScalarShiftMasks,
1180                                         TuningFastVectorShiftMasks,
1181                                         TuningFastMOVBE,
1182                                         TuningSBBDepBreaking,
1183                                         TuningSlowSHLD];
1184  list<SubtargetFeature> BtVer2Features =
1185    !listconcat(BtVer1Features, BtVer2AdditionalFeatures);
1186
1187  // Bulldozer
1188  list<SubtargetFeature> BdVer1Features = [FeatureX87,
1189                                           FeatureCX8,
1190                                           FeatureCMOV,
1191                                           FeatureXOP,
1192                                           FeatureX86_64,
1193                                           FeatureCX16,
1194                                           FeatureAES,
1195                                           FeatureCRC32,
1196                                           FeaturePRFCHW,
1197                                           FeaturePCLMUL,
1198                                           FeatureMMX,
1199                                           FeatureFXSR,
1200                                           FeatureNOPL,
1201                                           FeatureLZCNT,
1202                                           FeaturePOPCNT,
1203                                           FeatureXSAVE,
1204                                           FeatureLWP,
1205                                           FeatureLAHFSAHF64];
1206  list<SubtargetFeature> BdVer1Tuning = [TuningSlowSHLD,
1207                                         TuningFast11ByteNOP,
1208                                         TuningFastScalarShiftMasks,
1209                                         TuningBranchFusion,
1210                                         TuningSBBDepBreaking,
1211                                         TuningInsertVZEROUPPER];
1212
1213  // PileDriver
1214  list<SubtargetFeature> BdVer2AdditionalFeatures = [FeatureF16C,
1215                                                     FeatureBMI,
1216                                                     FeatureTBM,
1217                                                     FeatureFMA];
1218  list<SubtargetFeature> BdVer2AdditionalTuning = [TuningFastBEXTR,
1219                                                   TuningFastMOVBE];
1220  list<SubtargetFeature> BdVer2Tuning =
1221    !listconcat(BdVer1Tuning, BdVer2AdditionalTuning);
1222  list<SubtargetFeature> BdVer2Features =
1223    !listconcat(BdVer1Features, BdVer2AdditionalFeatures);
1224
1225  // Steamroller
1226  list<SubtargetFeature> BdVer3AdditionalFeatures = [FeatureXSAVEOPT,
1227                                                     FeatureFSGSBase];
1228  list<SubtargetFeature> BdVer3Tuning = BdVer2Tuning;
1229  list<SubtargetFeature> BdVer3Features =
1230    !listconcat(BdVer2Features, BdVer3AdditionalFeatures);
1231
1232  // Excavator
1233  list<SubtargetFeature> BdVer4AdditionalFeatures = [FeatureAVX2,
1234                                                     FeatureBMI2,
1235                                                     FeatureMOVBE,
1236                                                     FeatureRDRAND,
1237                                                     FeatureMWAITX];
1238  list<SubtargetFeature> BdVer4Tuning = BdVer3Tuning;
1239  list<SubtargetFeature> BdVer4Features =
1240    !listconcat(BdVer3Features, BdVer4AdditionalFeatures);
1241
1242
1243  // AMD Zen Processors common ISAs
1244  list<SubtargetFeature> ZNFeatures = [FeatureADX,
1245                                       FeatureAES,
1246                                       FeatureAVX2,
1247                                       FeatureBMI,
1248                                       FeatureBMI2,
1249                                       FeatureCLFLUSHOPT,
1250                                       FeatureCLZERO,
1251                                       FeatureCMOV,
1252                                       FeatureX86_64,
1253                                       FeatureCX16,
1254                                       FeatureCRC32,
1255                                       FeatureF16C,
1256                                       FeatureFMA,
1257                                       FeatureFSGSBase,
1258                                       FeatureFXSR,
1259                                       FeatureNOPL,
1260                                       FeatureLAHFSAHF64,
1261                                       FeatureLZCNT,
1262                                       FeatureMMX,
1263                                       FeatureMOVBE,
1264                                       FeatureMWAITX,
1265                                       FeaturePCLMUL,
1266                                       FeaturePOPCNT,
1267                                       FeaturePRFCHW,
1268                                       FeatureRDRAND,
1269                                       FeatureRDSEED,
1270                                       FeatureSHA,
1271                                       FeatureSSE4A,
1272                                       FeatureX87,
1273                                       FeatureXSAVE,
1274                                       FeatureXSAVEC,
1275                                       FeatureXSAVEOPT,
1276                                       FeatureXSAVES];
1277  list<SubtargetFeature> ZNTuning = [TuningFastLZCNT,
1278                                     TuningFastBEXTR,
1279                                     TuningFast15ByteNOP,
1280                                     TuningBranchFusion,
1281                                     TuningFastScalarFSQRT,
1282                                     TuningFastVectorFSQRT,
1283                                     TuningFastScalarShiftMasks,
1284                                     TuningFastVariablePerLaneShuffle,
1285                                     TuningFastMOVBE,
1286                                     TuningSlowSHLD,
1287                                     TuningSBBDepBreaking,
1288                                     TuningInsertVZEROUPPER,
1289                                     TuningAllowLight256Bit];
1290  list<SubtargetFeature> ZN2AdditionalFeatures = [FeatureCLWB,
1291                                                  FeatureRDPID,
1292                                                  FeatureRDPRU,
1293                                                  FeatureWBNOINVD];
1294  list<SubtargetFeature> ZN2Tuning = ZNTuning;
1295  list<SubtargetFeature> ZN2Features =
1296    !listconcat(ZNFeatures, ZN2AdditionalFeatures);
1297  list<SubtargetFeature> ZN3AdditionalFeatures = [FeatureFSRM,
1298                                                  FeatureINVPCID,
1299                                                  FeaturePKU,
1300                                                  FeatureVAES,
1301                                                  FeatureVPCLMULQDQ];
1302  list<SubtargetFeature> ZN3AdditionalTuning = [TuningMacroFusion];
1303  list<SubtargetFeature> ZN3Tuning =
1304    !listconcat(ZN2Tuning, ZN3AdditionalTuning);
1305  list<SubtargetFeature> ZN3Features =
1306    !listconcat(ZN2Features, ZN3AdditionalFeatures);
1307  list<SubtargetFeature> ZN4Tuning = ZN3Tuning;
1308  list<SubtargetFeature> ZN4AdditionalFeatures = [FeatureAVX512,
1309                                                  FeatureCDI,
1310                                                  FeatureDQI,
1311                                                  FeatureBWI,
1312                                                  FeatureVLX,
1313                                                  FeatureVBMI,
1314                                                  FeatureVBMI2,
1315                                                  FeatureIFMA,
1316                                                  FeatureVNNI,
1317                                                  FeatureBITALG,
1318                                                  FeatureGFNI,
1319                                                  FeatureBF16,
1320                                                  FeatureSHSTK,
1321                                                  FeatureVPOPCNTDQ];
1322  list<SubtargetFeature> ZN4Features =
1323    !listconcat(ZN3Features, ZN4AdditionalFeatures);
1324}
1325
1326//===----------------------------------------------------------------------===//
1327// X86 processors supported.
1328//===----------------------------------------------------------------------===//
1329
1330class Proc<string Name, list<SubtargetFeature> Features,
1331           list<SubtargetFeature> TuneFeatures>
1332 : ProcessorModel<Name, GenericModel, Features, TuneFeatures>;
1333
1334class ProcModel<string Name, SchedMachineModel Model,
1335                list<SubtargetFeature> Features,
1336                list<SubtargetFeature> TuneFeatures>
1337 : ProcessorModel<Name, Model, Features, TuneFeatures>;
1338
1339// NOTE: CMPXCHG8B is here for legacy compatibility so that it is only disabled
1340// if i386/i486 is specifically requested.
1341// NOTE: 64Bit is here as "generic" is the default llc CPU. The X86Subtarget
1342// constructor checks that any CPU used in 64-bit mode has FeatureX86_64
1343// enabled. It has no effect on code generation.
1344// NOTE: As a default tuning, "generic" aims to produce code optimized for the
1345// most common X86 processors. The tunings might be changed over time. It is
1346// recommended to use "tune-cpu"="x86-64" in function attribute for consistency.
1347def : ProcModel<"generic", SandyBridgeModel,
1348                [FeatureX87, FeatureCX8, FeatureX86_64],
1349                [TuningSlow3OpsLEA,
1350                 TuningSlowDivide64,
1351                 TuningMacroFusion,
1352                 TuningFastScalarFSQRT,
1353                 TuningFast15ByteNOP,
1354                 TuningInsertVZEROUPPER]>;
1355
1356def : Proc<"i386",            [FeatureX87],
1357                              [TuningSlowUAMem16, TuningInsertVZEROUPPER]>;
1358def : Proc<"i486",            [FeatureX87],
1359                              [TuningSlowUAMem16, TuningInsertVZEROUPPER]>;
1360def : Proc<"i586",            [FeatureX87, FeatureCX8],
1361                              [TuningSlowUAMem16, TuningInsertVZEROUPPER]>;
1362def : Proc<"pentium",         [FeatureX87, FeatureCX8],
1363                              [TuningSlowUAMem16, TuningInsertVZEROUPPER]>;
1364def : Proc<"pentium-mmx",     [FeatureX87, FeatureCX8, FeatureMMX],
1365                              [TuningSlowUAMem16, TuningInsertVZEROUPPER]>;
1366
1367def : Proc<"i686", [FeatureX87, FeatureCX8, FeatureCMOV],
1368                   [TuningSlowUAMem16, TuningInsertVZEROUPPER]>;
1369def : Proc<"pentiumpro", [FeatureX87, FeatureCX8, FeatureCMOV,
1370                          FeatureNOPL],
1371                         [TuningSlowUAMem16, TuningInsertVZEROUPPER]>;
1372
1373def : Proc<"pentium2", [FeatureX87, FeatureCX8, FeatureMMX, FeatureCMOV,
1374                        FeatureFXSR, FeatureNOPL],
1375                       [TuningSlowUAMem16, TuningInsertVZEROUPPER]>;
1376
1377foreach P = ["pentium3", "pentium3m"] in {
1378  def : Proc<P, [FeatureX87, FeatureCX8, FeatureMMX,
1379                 FeatureSSE1, FeatureFXSR, FeatureNOPL, FeatureCMOV],
1380                [TuningSlowUAMem16, TuningInsertVZEROUPPER]>;
1381}
1382
1383// Enable the PostRAScheduler for SSE2 and SSE3 class cpus.
1384// The intent is to enable it for pentium4 which is the current default
1385// processor in a vanilla 32-bit clang compilation when no specific
1386// architecture is specified.  This generally gives a nice performance
1387// increase on silvermont, with largely neutral behavior on other
1388// contemporary large core processors.
1389// pentium-m, pentium4m, prescott and nocona are included as a preventative
1390// measure to avoid performance surprises, in case clang's default cpu
1391// changes slightly.
1392
1393def : ProcModel<"pentium-m", GenericPostRAModel,
1394                [FeatureX87, FeatureCX8, FeatureMMX, FeatureSSE2,
1395                FeatureFXSR, FeatureNOPL, FeatureCMOV],
1396                [TuningSlowUAMem16, TuningInsertVZEROUPPER]>;
1397
1398foreach P = ["pentium4", "pentium4m"] in {
1399  def : ProcModel<P, GenericPostRAModel,
1400                  [FeatureX87, FeatureCX8, FeatureMMX, FeatureSSE2,
1401                   FeatureFXSR, FeatureNOPL, FeatureCMOV],
1402                  [TuningSlowUAMem16, TuningInsertVZEROUPPER]>;
1403}
1404
1405// Intel Quark.
1406def : Proc<"lakemont", [FeatureCX8],
1407                       [TuningSlowUAMem16, TuningInsertVZEROUPPER]>;
1408
1409// Intel Core Duo.
1410def : ProcModel<"yonah", SandyBridgeModel,
1411                [FeatureX87, FeatureCX8, FeatureMMX, FeatureSSE3,
1412                 FeatureFXSR, FeatureNOPL, FeatureCMOV],
1413                [TuningSlowUAMem16, TuningInsertVZEROUPPER]>;
1414
1415// NetBurst.
1416def : ProcModel<"prescott", GenericPostRAModel,
1417                [FeatureX87, FeatureCX8, FeatureMMX, FeatureSSE3,
1418                 FeatureFXSR, FeatureNOPL, FeatureCMOV],
1419                [TuningSlowUAMem16, TuningInsertVZEROUPPER]>;
1420def : ProcModel<"nocona", GenericPostRAModel, [
1421  FeatureX87,
1422  FeatureCX8,
1423  FeatureCMOV,
1424  FeatureMMX,
1425  FeatureSSE3,
1426  FeatureFXSR,
1427  FeatureNOPL,
1428  FeatureX86_64,
1429  FeatureCX16,
1430],
1431[
1432  TuningSlowUAMem16,
1433  TuningInsertVZEROUPPER
1434]>;
1435
1436// Intel Core 2 Solo/Duo.
1437def : ProcModel<"core2", SandyBridgeModel, [
1438  FeatureX87,
1439  FeatureCX8,
1440  FeatureCMOV,
1441  FeatureMMX,
1442  FeatureSSSE3,
1443  FeatureFXSR,
1444  FeatureNOPL,
1445  FeatureX86_64,
1446  FeatureCX16,
1447  FeatureLAHFSAHF64
1448],
1449[
1450  TuningMacroFusion,
1451  TuningSlowUAMem16,
1452  TuningInsertVZEROUPPER
1453]>;
1454def : ProcModel<"penryn", SandyBridgeModel, [
1455  FeatureX87,
1456  FeatureCX8,
1457  FeatureCMOV,
1458  FeatureMMX,
1459  FeatureSSE41,
1460  FeatureFXSR,
1461  FeatureNOPL,
1462  FeatureX86_64,
1463  FeatureCX16,
1464  FeatureLAHFSAHF64
1465],
1466[
1467  TuningMacroFusion,
1468  TuningSlowUAMem16,
1469  TuningInsertVZEROUPPER
1470]>;
1471
1472// Atom CPUs.
1473foreach P = ["bonnell", "atom"] in {
1474  def : ProcModel<P, AtomModel, ProcessorFeatures.AtomFeatures,
1475                  ProcessorFeatures.AtomTuning>;
1476}
1477
1478foreach P = ["silvermont", "slm"] in {
1479  def : ProcModel<P, SLMModel, ProcessorFeatures.SLMFeatures,
1480                  ProcessorFeatures.SLMTuning>;
1481}
1482
1483def : ProcModel<"goldmont", SLMModel, ProcessorFeatures.GLMFeatures,
1484                ProcessorFeatures.GLMTuning>;
1485def : ProcModel<"goldmont-plus", SLMModel, ProcessorFeatures.GLPFeatures,
1486                ProcessorFeatures.GLPTuning>;
1487def : ProcModel<"tremont", SLMModel, ProcessorFeatures.TRMFeatures,
1488                ProcessorFeatures.TRMTuning>;
1489def : ProcModel<"sierraforest", AlderlakePModel, ProcessorFeatures.SRFFeatures,
1490                ProcessorFeatures.TRMTuning>;
1491def : ProcModel<"grandridge", AlderlakePModel, ProcessorFeatures.GRRFeatures,
1492                ProcessorFeatures.TRMTuning>;
1493
1494// "Arrandale" along with corei3 and corei5
1495foreach P = ["nehalem", "corei7"] in {
1496  def : ProcModel<P, SandyBridgeModel, ProcessorFeatures.NHMFeatures,
1497                  ProcessorFeatures.NHMTuning>;
1498}
1499
1500// Westmere is the corei3/i5/i7 path from nehalem to sandybridge
1501def : ProcModel<"westmere", SandyBridgeModel, ProcessorFeatures.WSMFeatures,
1502                ProcessorFeatures.WSMTuning>;
1503
1504foreach P = ["sandybridge", "corei7-avx"] in {
1505  def : ProcModel<P, SandyBridgeModel, ProcessorFeatures.SNBFeatures,
1506                  ProcessorFeatures.SNBTuning>;
1507}
1508
1509foreach P = ["ivybridge", "core-avx-i"] in {
1510  def : ProcModel<P, SandyBridgeModel, ProcessorFeatures.IVBFeatures,
1511                  ProcessorFeatures.IVBTuning>;
1512}
1513
1514foreach P = ["haswell", "core-avx2"] in {
1515  def : ProcModel<P, HaswellModel, ProcessorFeatures.HSWFeatures,
1516                  ProcessorFeatures.HSWTuning>;
1517}
1518
1519def : ProcModel<"broadwell", BroadwellModel, ProcessorFeatures.BDWFeatures,
1520                ProcessorFeatures.BDWTuning>;
1521
1522def : ProcModel<"skylake", SkylakeClientModel, ProcessorFeatures.SKLFeatures,
1523                ProcessorFeatures.SKLTuning>;
1524
1525// FIXME: define KNL scheduler model
1526def : ProcModel<"knl", HaswellModel, ProcessorFeatures.KNLFeatures,
1527                ProcessorFeatures.KNLTuning>;
1528def : ProcModel<"knm", HaswellModel, ProcessorFeatures.KNMFeatures,
1529                ProcessorFeatures.KNLTuning>;
1530
1531foreach P = ["skylake-avx512", "skx"] in {
1532  def : ProcModel<P, SkylakeServerModel, ProcessorFeatures.SKXFeatures,
1533                  ProcessorFeatures.SKXTuning>;
1534}
1535
1536def : ProcModel<"cascadelake", SkylakeServerModel,
1537                ProcessorFeatures.CLXFeatures, ProcessorFeatures.CLXTuning>;
1538def : ProcModel<"cooperlake", SkylakeServerModel,
1539                ProcessorFeatures.CPXFeatures, ProcessorFeatures.CPXTuning>;
1540def : ProcModel<"cannonlake", SkylakeServerModel,
1541                ProcessorFeatures.CNLFeatures, ProcessorFeatures.CNLTuning>;
1542def : ProcModel<"icelake-client", IceLakeModel,
1543                ProcessorFeatures.ICLFeatures, ProcessorFeatures.ICLTuning>;
1544def : ProcModel<"rocketlake", IceLakeModel,
1545                ProcessorFeatures.ICLFeatures, ProcessorFeatures.ICLTuning>;
1546def : ProcModel<"icelake-server", IceLakeModel,
1547                ProcessorFeatures.ICXFeatures, ProcessorFeatures.ICXTuning>;
1548def : ProcModel<"tigerlake", IceLakeModel,
1549                ProcessorFeatures.TGLFeatures, ProcessorFeatures.TGLTuning>;
1550def : ProcModel<"sapphirerapids", SkylakeServerModel,
1551                ProcessorFeatures.SPRFeatures, ProcessorFeatures.SPRTuning>;
1552def : ProcModel<"alderlake", AlderlakePModel,
1553                ProcessorFeatures.ADLFeatures, ProcessorFeatures.ADLTuning>;
1554def : ProcModel<"raptorlake", AlderlakePModel,
1555                ProcessorFeatures.ADLFeatures, ProcessorFeatures.ADLTuning>;
1556def : ProcModel<"meteorlake", AlderlakePModel,
1557                ProcessorFeatures.ADLFeatures, ProcessorFeatures.ADLTuning>;
1558def : ProcModel<"graniterapids", SkylakeServerModel,
1559                ProcessorFeatures.GNRFeatures, ProcessorFeatures.SPRTuning>;
1560def : ProcModel<"emeraldrapids", SkylakeServerModel,
1561                ProcessorFeatures.SPRFeatures, ProcessorFeatures.SPRTuning>;
1562
1563// AMD CPUs.
1564
1565def : Proc<"k6",   [FeatureX87, FeatureCX8, FeatureMMX],
1566                   [TuningSlowUAMem16, TuningInsertVZEROUPPER]>;
1567def : Proc<"k6-2", [FeatureX87, FeatureCX8, Feature3DNow],
1568                   [TuningSlowUAMem16, TuningInsertVZEROUPPER]>;
1569def : Proc<"k6-3", [FeatureX87, FeatureCX8, Feature3DNow],
1570                   [TuningSlowUAMem16, TuningInsertVZEROUPPER]>;
1571
1572foreach P = ["athlon", "athlon-tbird"] in {
1573  def : Proc<P, [FeatureX87, FeatureCX8, FeatureCMOV, Feature3DNowA,
1574                 FeatureNOPL],
1575                [TuningSlowSHLD, TuningSlowUAMem16, TuningInsertVZEROUPPER]>;
1576}
1577
1578foreach P = ["athlon-4", "athlon-xp", "athlon-mp"] in {
1579  def : Proc<P, [FeatureX87, FeatureCX8, FeatureCMOV,
1580                 FeatureSSE1, Feature3DNowA, FeatureFXSR, FeatureNOPL],
1581                [TuningSlowSHLD, TuningSlowUAMem16, TuningInsertVZEROUPPER]>;
1582}
1583
1584foreach P = ["k8", "opteron", "athlon64", "athlon-fx"] in {
1585  def : Proc<P, [FeatureX87, FeatureCX8, FeatureSSE2, Feature3DNowA,
1586                 FeatureFXSR, FeatureNOPL, FeatureX86_64, FeatureCMOV],
1587                [TuningFastScalarShiftMasks, TuningSlowSHLD, TuningSlowUAMem16,
1588                 TuningSBBDepBreaking, TuningInsertVZEROUPPER]>;
1589}
1590
1591foreach P = ["k8-sse3", "opteron-sse3", "athlon64-sse3"] in {
1592  def : Proc<P, [FeatureX87, FeatureCX8, FeatureSSE3, Feature3DNowA,
1593                 FeatureFXSR, FeatureNOPL, FeatureCX16, FeatureCMOV,
1594                 FeatureX86_64],
1595                [TuningFastScalarShiftMasks, TuningSlowSHLD, TuningSlowUAMem16,
1596                 TuningSBBDepBreaking, TuningInsertVZEROUPPER]>;
1597}
1598
1599foreach P = ["amdfam10", "barcelona"] in {
1600  def : Proc<P, ProcessorFeatures.BarcelonaFeatures,
1601             ProcessorFeatures.BarcelonaTuning>;
1602}
1603
1604// Bobcat
1605def : Proc<"btver1", ProcessorFeatures.BtVer1Features,
1606           ProcessorFeatures.BtVer1Tuning>;
1607// Jaguar
1608def : ProcModel<"btver2", BtVer2Model, ProcessorFeatures.BtVer2Features,
1609                ProcessorFeatures.BtVer2Tuning>;
1610
1611// Bulldozer
1612def : ProcModel<"bdver1", BdVer2Model, ProcessorFeatures.BdVer1Features,
1613                ProcessorFeatures.BdVer1Tuning>;
1614// Piledriver
1615def : ProcModel<"bdver2", BdVer2Model, ProcessorFeatures.BdVer2Features,
1616                ProcessorFeatures.BdVer2Tuning>;
1617// Steamroller
1618def : Proc<"bdver3", ProcessorFeatures.BdVer3Features,
1619           ProcessorFeatures.BdVer3Tuning>;
1620// Excavator
1621def : Proc<"bdver4", ProcessorFeatures.BdVer4Features,
1622           ProcessorFeatures.BdVer4Tuning>;
1623
1624def : ProcModel<"znver1", Znver1Model, ProcessorFeatures.ZNFeatures,
1625                ProcessorFeatures.ZNTuning>;
1626def : ProcModel<"znver2", Znver2Model, ProcessorFeatures.ZN2Features,
1627                ProcessorFeatures.ZN2Tuning>;
1628def : ProcModel<"znver3", Znver3Model, ProcessorFeatures.ZN3Features,
1629                ProcessorFeatures.ZN3Tuning>;
1630def : Proc<"znver4",ProcessorFeatures.ZN4Features,
1631           ProcessorFeatures.ZN4Tuning>;
1632
1633def : Proc<"geode",           [FeatureX87, FeatureCX8, Feature3DNowA],
1634                              [TuningSlowUAMem16, TuningInsertVZEROUPPER]>;
1635
1636def : Proc<"winchip-c6",      [FeatureX87, FeatureMMX],
1637                              [TuningSlowUAMem16, TuningInsertVZEROUPPER]>;
1638def : Proc<"winchip2",        [FeatureX87, Feature3DNow],
1639                              [TuningSlowUAMem16, TuningInsertVZEROUPPER]>;
1640def : Proc<"c3",              [FeatureX87, Feature3DNow],
1641                              [TuningSlowUAMem16, TuningInsertVZEROUPPER]>;
1642def : Proc<"c3-2",            [FeatureX87, FeatureCX8, FeatureMMX,
1643                               FeatureSSE1, FeatureFXSR, FeatureCMOV],
1644                              [TuningSlowUAMem16, TuningInsertVZEROUPPER]>;
1645
1646// We also provide a generic 64-bit specific x86 processor model which tries to
1647// be good for modern chips without enabling instruction set encodings past the
1648// basic SSE2 and 64-bit ones. It disables slow things from any mainstream and
1649// modern 64-bit x86 chip, and enables features that are generally beneficial.
1650//
1651// We currently use the Sandy Bridge model as the default scheduling model as
1652// we use it across Nehalem, Westmere, Sandy Bridge, and Ivy Bridge which
1653// covers a huge swath of x86 processors. If there are specific scheduling
1654// knobs which need to be tuned differently for AMD chips, we might consider
1655// forming a common base for them.
1656def : ProcModel<"x86-64", SandyBridgeModel, ProcessorFeatures.X86_64V1Features,
1657[
1658  TuningSlow3OpsLEA,
1659  TuningSlowDivide64,
1660  TuningSlowIncDec,
1661  TuningMacroFusion,
1662  TuningInsertVZEROUPPER
1663]>;
1664
1665// x86-64 micro-architecture levels.
1666def : ProcModel<"x86-64-v2", SandyBridgeModel, ProcessorFeatures.X86_64V2Features,
1667                ProcessorFeatures.SNBTuning>;
1668// Close to Haswell.
1669def : ProcModel<"x86-64-v3", HaswellModel, ProcessorFeatures.X86_64V3Features,
1670                ProcessorFeatures.HSWTuning>;
1671// Close to the AVX-512 level implemented by Xeon Scalable Processors.
1672def : ProcModel<"x86-64-v4", SkylakeServerModel, ProcessorFeatures.X86_64V4Features,
1673                ProcessorFeatures.SKXTuning>;
1674
1675//===----------------------------------------------------------------------===//
1676// Calling Conventions
1677//===----------------------------------------------------------------------===//
1678
1679include "X86CallingConv.td"
1680
1681
1682//===----------------------------------------------------------------------===//
1683// Assembly Parser
1684//===----------------------------------------------------------------------===//
1685
1686def ATTAsmParserVariant : AsmParserVariant {
1687  int Variant = 0;
1688
1689  // Variant name.
1690  string Name = "att";
1691
1692  // Discard comments in assembly strings.
1693  string CommentDelimiter = "#";
1694
1695  // Recognize hard coded registers.
1696  string RegisterPrefix = "%";
1697}
1698
1699def IntelAsmParserVariant : AsmParserVariant {
1700  int Variant = 1;
1701
1702  // Variant name.
1703  string Name = "intel";
1704
1705  // Discard comments in assembly strings.
1706  string CommentDelimiter = ";";
1707
1708  // Recognize hard coded registers.
1709  string RegisterPrefix = "";
1710}
1711
1712//===----------------------------------------------------------------------===//
1713// Assembly Printers
1714//===----------------------------------------------------------------------===//
1715
1716// The X86 target supports two different syntaxes for emitting machine code.
1717// This is controlled by the -x86-asm-syntax={att|intel}
1718def ATTAsmWriter : AsmWriter {
1719  string AsmWriterClassName  = "ATTInstPrinter";
1720  int Variant = 0;
1721}
1722def IntelAsmWriter : AsmWriter {
1723  string AsmWriterClassName  = "IntelInstPrinter";
1724  int Variant = 1;
1725}
1726
1727def X86 : Target {
1728  // Information about the instructions...
1729  let InstructionSet = X86InstrInfo;
1730  let AssemblyParserVariants = [ATTAsmParserVariant, IntelAsmParserVariant];
1731  let AssemblyWriters = [ATTAsmWriter, IntelAsmWriter];
1732  let AllowRegisterRenaming = 1;
1733}
1734
1735//===----------------------------------------------------------------------===//
1736// Pfm Counters
1737//===----------------------------------------------------------------------===//
1738
1739include "X86PfmCounters.td"
1740