1# Copyright (c) 2020-2023, Arm Limited and Contributors. All rights reserved. 2# 3# SPDX-License-Identifier: BSD-3-Clause 4# 5 6RD_N2_VARIANTS := 0 1 2 3 7ifneq ($(CSS_SGI_PLATFORM_VARIANT),\ 8 $(filter $(CSS_SGI_PLATFORM_VARIANT),$(RD_N2_VARIANTS))) 9 $(error "CSS_SGI_PLATFORM_VARIANT for RD-N2 should be 0, 1, 2 or 3, currently \ 10 set to ${CSS_SGI_PLATFORM_VARIANT}.") 11endif 12 13$(eval $(call CREATE_SEQ,SEQ,4)) 14ifneq ($(CSS_SGI_CHIP_COUNT),$(filter $(CSS_SGI_CHIP_COUNT),$(SEQ))) 15 $(error "Chip count for RD-N2-MC should be either $(SEQ) \ 16 currently it is set to ${CSS_SGI_CHIP_COUNT}.") 17endif 18 19# RD-N2 platform uses GIC-700 which is based on GICv4.1 20GIC_ENABLE_V4_EXTN := 1 21GIC_EXT_INTID := 1 22 23#Enable GIC Multichip Extension only for Multichip Platforms 24ifeq (${CSS_SGI_PLATFORM_VARIANT}, 2) 25GICV3_IMPL_GIC600_MULTICHIP := 1 26endif 27 28override CSS_SYSTEM_GRACEFUL_RESET := 1 29override EL3_EXCEPTION_HANDLING := 1 30 31include plat/arm/css/sgi/sgi-common.mk 32 33RDN2_BASE = plat/arm/board/rdn2 34 35PLAT_INCLUDES += -I${RDN2_BASE}/include/ 36 37SGI_CPU_SOURCES := lib/cpus/aarch64/neoverse_n2.S \ 38 lib/cpus/aarch64/neoverse_v2.S 39 40PLAT_BL_COMMON_SOURCES += ${CSS_ENT_BASE}/sgi_plat_v2.c 41 42BL1_SOURCES += ${SGI_CPU_SOURCES} \ 43 ${RDN2_BASE}/rdn2_err.c 44 45BL2_SOURCES += ${RDN2_BASE}/rdn2_plat.c \ 46 ${RDN2_BASE}/rdn2_security.c \ 47 ${RDN2_BASE}/rdn2_err.c \ 48 lib/utils/mem_region.c \ 49 drivers/arm/tzc/tzc400.c \ 50 plat/arm/common/arm_tzc400.c \ 51 plat/arm/common/arm_nor_psci_mem_protect.c 52 53BL31_SOURCES += ${SGI_CPU_SOURCES} \ 54 ${RDN2_BASE}/rdn2_plat.c \ 55 ${RDN2_BASE}/rdn2_topology.c \ 56 drivers/cfi/v2m/v2m_flash.c \ 57 lib/utils/mem_region.c \ 58 plat/arm/common/arm_nor_psci_mem_protect.c 59 60ifeq (${TRUSTED_BOARD_BOOT}, 1) 61BL1_SOURCES += ${RDN2_BASE}/rdn2_trusted_boot.c 62BL2_SOURCES += ${RDN2_BASE}/rdn2_trusted_boot.c 63endif 64 65ifeq (${CSS_SGI_PLATFORM_VARIANT}, 2) 66BL31_SOURCES += drivers/arm/gic/v3/gic600_multichip.c 67 68# Enable dynamic addition of MMAP regions in BL31 69BL31_CFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC 70endif 71 72ifeq (${ENABLE_FEAT_RAS}-${HANDLE_EA_EL3_FIRST_NS},1-1) 73BL31_SOURCES += ${RDN2_BASE}/rdn2_ras.c \ 74 ${CSS_ENT_BASE}/ras/sgi_ras_common.c \ 75 ${CSS_ENT_BASE}/ras/sgi_ras_sram.c \ 76 ${CSS_ENT_BASE}/ras/sgi_ras_cpu.c 77endif 78 79# Add the FDT_SOURCES and options for Dynamic Config 80FDT_SOURCES += ${RDN2_BASE}/fdts/${PLAT}_fw_config.dts \ 81 ${RDN2_BASE}/fdts/${PLAT}_tb_fw_config.dts 82FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_fw_config.dtb 83TB_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_tb_fw_config.dtb 84 85# Add the FW_CONFIG to FIP and specify the same to certtool 86$(eval $(call TOOL_ADD_PAYLOAD,${FW_CONFIG},--fw-config,${FW_CONFIG})) 87# Add the TB_FW_CONFIG to FIP and specify the same to certtool 88$(eval $(call TOOL_ADD_PAYLOAD,${TB_FW_CONFIG},--tb-fw-config,${TB_FW_CONFIG})) 89 90FDT_SOURCES += ${RDN2_BASE}/fdts/${PLAT}_nt_fw_config.dts 91NT_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_nt_fw_config.dtb 92 93# Add the NT_FW_CONFIG to FIP and specify the same to certtool 94$(eval $(call TOOL_ADD_PAYLOAD,${NT_FW_CONFIG},--nt-fw-config)) 95 96override CTX_INCLUDE_AARCH32_REGS := 0 97override ENABLE_FEAT_AMU := 1 98