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1OUTPUT_FORMAT("elf64-littleaarch64", "elf64-bigaarch64", "elf64-littleaarch64")
2OUTPUT_ARCH(aarch64)
3
4_start_phys = _start - %KERNEL_BASE% + %MEMBASE%;
5ENTRY(_start_phys)
6
7SECTIONS
8{
9    . = %KERNEL_BASE% + %KERNEL_LOAD_OFFSET%;
10
11    /*
12     * LLVM introduced a static constructor, init_have_lse_atomics, to
13     * compiler-rt that we don't want and that breaks our build. Until we compile
14     * our own compiler-rt and either provide getauxval and enable CFI, or remove
15     * this function, we can remove it during linking here
16     */
17    /DISCARD/ : {
18        *libclang_rt.builtins-aarch64-android.a:cpu_model.c.o(
19            .text.init_cpu_features
20            .text.init_have_lse_atomics
21            .init_array*
22        )
23    }
24
25    /* text/read-only data */
26    /* set the load address to physical MEMBASE */
27    .text : AT(%MEMBASE% + %KERNEL_LOAD_OFFSET%) {
28        __code_start = .;
29        KEEP(*(.text.boot))
30        KEEP(*(.text.boot.early.vectab))
31        KEEP(*(.text.boot.vectab))
32        *(.text* .sram.text.glue_7* .gnu.linkonce.t.*)
33    }
34
35    .interp : { *(.interp) }
36    .hash : { *(.hash) }
37    .dynsym : { *(.dynsym) }
38    .dynstr : { *(.dynstr) }
39    .init : { *(.init) } =0x9090
40    .plt : { *(.plt) }
41
42    /*
43     * .plt needs to be empty because its entries might call into the dynamic
44     * loader, which doesn't exist for Trusty (or any kernel).
45     */
46    ASSERT(SIZEOF(.plt) == 0, ".plt section should be empty")
47
48    /* .ARM.exidx is sorted, so has to go in its own output section.  */
49    __exidx_start = .;
50    .ARM.exidx : { *(.ARM.exidx* .gnu.linkonce.armexidx.*) }
51    __exidx_end = .;
52
53    .fake_post_text : {
54	    __code_end = .;
55    }
56
57    .rodata : ALIGN(4096) {
58        __rodata_start = .;
59        __fault_handler_table_start = .;
60        KEEP(*(.rodata.fault_handler_table))
61        __fault_handler_table_end = .;
62        *(.rodata .rodata.* .gnu.linkonce.r.*)
63    }
64
65    .rel.dyn : {
66        *(.rel.text) *(.rel.gnu.linkonce.t*)
67        *(.rel.init)
68        *(.rel.plt)
69        *(.rel.rodata) *(.rel.gnu.linkonce.r*)
70        *(.rel.lk_init)
71        *(.rel.apps)
72        *(.rel.drivers)
73        *(.rel.data) *(.rel.gnu.linkonce.d*)
74        *(.rel.devices)
75        *(.rel.ctors)
76        *(.rel.dtors)
77        *(.rel.got)
78        *(.rel.bss) *(.rel.bss.*) *(.rel.gnu.linkonce.b*)
79    }
80
81    .rela.dyn : {
82        *(.rela.text) *(.rela.gnu.linkonce.t*)
83        *(.rela.init)
84        *(.rela.plt)
85        *(.rela.rodata) *(.rela.gnu.linkonce.r*)
86        *(.rela.lk_init)
87        *(.rela.apps)
88        *(.rela.drivers)
89        *(.rela.data) *(.rela.gnu.linkonce.d*)
90        *(.rela.devices)
91        *(.rela.ctors)
92        *(.rela.dtors)
93        *(.rela.got)
94        *(.rela.bss) *(.rela.bss.*) *(.rela.gnu.linkonce.b*)
95    }
96
97    /*
98     * Non-RELR dynamic relocations are not implemented yet.
99     * .rel.dyn should not ever appear on AArch64 anyway.
100     */
101    ASSERT(SIZEOF(.rel.dyn) == 0, "Found non-RELR relocations in .rel.dyn")
102    ASSERT(SIZEOF(.rela.dyn) == 0, "Found non-RELR relocations in .rel.dyn")
103
104    .relr.dyn : ALIGN(8) {
105        __relr_start = .;
106        *(.relr.dyn)
107        __relr_end = .;
108    }
109
110    .ctors : ALIGN(8) {
111        __ctor_list = .;
112        KEEP(*(.ctors .init_array))
113        __ctor_end = .;
114    }
115    .dtors : ALIGN(8) {
116        __dtor_list = .;
117        KEEP(*(.dtors .fini_array))
118        __dtor_end = .;
119    }
120
121    /*
122     * .got and .dynamic need to follow .ctors and .dtors because the linker
123     * puts them all in the RELRO segment and wants them contiguous
124     */
125    .dynamic : { *(.dynamic) }
126    .got : { *(.got.plt) *(.got) }
127
128    /*
129     * extra linker scripts tend to insert sections just after .rodata,
130     * so we want to make sure this symbol comes after anything inserted above,
131     * but not aligned to the next section necessarily.
132     */
133    .fake_post_rodata : {
134        __rodata_end = .;
135    }
136
137    .data : ALIGN(4096) {
138        /* writable data  */
139        __data_start_rom = .;
140        /* in one segment binaries, the rom data address is on top of the ram data address */
141        __data_start = .;
142        *(.data .data.* .gnu.linkonce.d.*)
143    }
144
145    /*
146     * extra linker scripts tend to insert sections just after .data,
147     * so we want to make sure this symbol comes after anything inserted above,
148     * but not aligned to the next section necessarily.
149     */
150    .fake_post_data : {
151        __data_end = .;
152    }
153
154    /* unintialized data (in same segment as writable data) */
155    .bss : ALIGN(4096) {
156        __bss_start = .;
157        KEEP(*(.bss.prebss.*))
158        . = ALIGN(8);
159        __post_prebss_bss_start = .;
160        *(.bss .bss.*)
161        *(.gnu.linkonce.b.*)
162        *(COMMON)
163        . = ALIGN(8);
164        __bss_end = .;
165    }
166
167    /* Align the end to ensure anything after the kernel ends up on its own pages */
168    . = ALIGN(4096);
169    _end = .;
170
171    . = %KERNEL_BASE% + %MEMSIZE%;
172    _end_of_ram = .;
173
174    /* Strip unnecessary stuff */
175    /DISCARD/ : { *(.comment .note .eh_frame) }
176}
177