1 /* 2 * Copyright (C) 2016 Freescale Semiconductor, Inc. 3 * Copyright 2017 NXP 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright notice, 10 * this list of conditions and the following disclaimer. 11 * 12 * 2. Redistributions in binary form must reproduce the above copyright notice, 13 * this list of conditions and the following disclaimer in the documentation 14 * and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 17 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 20 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #ifndef _IMX_REGS_H_ 30 #define _IMX_REGS_H_ 31 32 #define MACH_IMX7 33 34 #define GIC_BASE_PHY 0x31001000 35 #define GIC_BASE_VIRT 0x71001000 36 37 #define SOC_REGS_PHY 0x30000000 38 #define SOC_REGS_VIRT 0x70000000 39 #define SOC_REGS_SIZE 0x01000000 40 41 #define CAAM_PHY_BASE_ADDR 0x30900000 42 #define CAAM_REG_SIZE 0x40000 43 44 #define CAAM_PHY_ARB_BASE_ADDR 0x00100000 45 #define CAAM_SEC_RAM_SIZE 0x8000 46 47 #define CCM_PHY_BASE_ADDR 0x30380000 48 #define CCM_REG_SIZE 0x10000 49 50 #define CCM_CAAM_CCGR_OFFSET (0x4000 + 16 * 36) /* CAAM CCGR is CCGR36 */ 51 52 /* Registers for GIC */ 53 #define MAX_INT 160 54 #define GICBASE(b) (GIC_BASE_VIRT) 55 56 #define GICC_SIZE (0x1000) 57 #define GICD_SIZE (0x100) 58 59 #define GICC_OFFSET (0x1000) 60 #define GICD_OFFSET (0x0000) 61 62 #define GICC_BASE_VIRT (GIC_BASE_VIRT + GICC_OFFSET) 63 #define GICD_BASE_VIRT (GIC_BASE_VIRT + GICD_OFFSET) 64 65 #define GIC_REG_SIZE 0x2000 66 67 /* Registers for TZASC */ 68 #define TZ_BASE 0x30780000 69 #define TZ_BASE_VIRT (0x40000000 + TZ_BASE) 70 #define TZ_REG_SIZE 0x4000 71 #define TZ_BYPASS_GPR_BASE 0x30340024 72 #define TZ_BYPASS_GPR_BASE_VIRT (0x40000000 + TZ_BYPASS_GPR_BASE) 73 74 #define SRC_A7RCR1_PHY 0x30390008 75 #define SRC_A7RCR1 (0x40000000 + SRC_A7RCR1_PHY) 76 #define SRC_GPR3_PHY 0x3039007C 77 #define SRC_GPR3 (0x40000000 + SRC_GPR3_PHY) 78 #define SRC_GPR4_PHY 0x30390080 79 #define SRC_GPR4 (0x40000000 + SRC_GPR4_PHY) 80 81 #endif 82