1/* 2 * Copyright (c) 2017, Google Inc. All rights reserved 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining 5 * a copy of this software and associated documentation files 6 * (the "Software"), to deal in the Software without restriction, 7 * including without limitation the rights to use, copy, modify, merge, 8 * publish, distribute, sublicense, and/or sell copies of the Software, 9 * and to permit persons to whom the Software is furnished to do so, 10 * subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be 13 * included in all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 16 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 17 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 18 * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY 19 * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 20 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 21 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 22 */ 23 24#include <asm.h> 25#include <lib/sm/monitor.h> 26 27#define CPUID_ARM_GENTIMER_EXT_MASK (0xF << 16) 28 29/* 30 * Reset CNTVOFF register to zero as inittial state is undefined on ARM v7 31 * 32 * Must be in Secure Monitor Mode with NS bit set. 33 */ 34FUNCTION(virt_timer_init) 35 push {r0} 36 cps #MODE_MON 37 38 SWITCH_SCR_TO_NONSECURE r0 39 40 mrc p15, 0, r0, c0, c1, 1 /* read ID_PFR1 */ 41 ands r0, r0, #CPUID_ARM_GENTIMER_EXT_MASK /* test arch timer bits */ 42 movne r0, #0 43 mcrrne p15, 4, r0, r0, c14 /* Reset CNTVOFF to zero */ 44 45 SWITCH_SCR_TO_SECURE r0 46 47 cps #MODE_SVC 48 pop {r0} 49 bx lr 50