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/external/google-smali/dexlib2/src/main/java/com/android/tools/smali/dexlib2/
DOpcode.java41 public enum Opcode enum
43 NOP(0x00, "nop", ReferenceType.NONE, Format.Format10x, Opcode.CAN_CONTINUE),
44 …MOVE(0x01, "move", ReferenceType.NONE, Format.Format12x, Opcode.CAN_CONTINUE | Opcode.SETS_REGISTE…
45 …16(0x02, "move/from16", ReferenceType.NONE, Format.Format22x, Opcode.CAN_CONTINUE | Opcode.SETS_RE…
46 …MOVE_16(0x03, "move/16", ReferenceType.NONE, Format.Format32x, Opcode.CAN_CONTINUE | Opcode.SETS_R…
47 …"move-wide", ReferenceType.NONE, Format.Format12x, Opcode.CAN_CONTINUE | Opcode.SETS_REGISTER | Op…
48 …ide/from16", ReferenceType.NONE, Format.Format22x, Opcode.CAN_CONTINUE | Opcode.SETS_REGISTER | Op…
49 …ve-wide/16", ReferenceType.NONE, Format.Format32x, Opcode.CAN_CONTINUE | Opcode.SETS_REGISTER | Op…
50 …CT(0x07, "move-object", ReferenceType.NONE, Format.Format12x, Opcode.CAN_CONTINUE | Opcode.SETS_RE…
51 …, "move-object/from16", ReferenceType.NONE, Format.Format22x, Opcode.CAN_CONTINUE | Opcode.SETS_RE…
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/external/google-smali/dexlib2/src/main/java/com/android/tools/smali/dexlib2/analysis/
DOdexedFieldInstructionMapper.java33 import com.android.tools.smali.dexlib2.Opcode;
55 @Nonnull public final Opcode normalOpcode;
56 @Nullable public final Opcode quickOpcode;
57 @Nullable public final Opcode volatileOpcode;
59 public FieldOpcode(char type, @Nonnull Opcode normalOpcode, @Nullable Opcode quickOpcode, in FieldOpcode()
60 @Nullable Opcode volatileOpcode) { in FieldOpcode()
68 …public FieldOpcode(char type, boolean isStatic, @Nonnull Opcode normalOpcode, @Nullable Opcode vol… in FieldOpcode()
76 public FieldOpcode(char type, @Nonnull Opcode normalOpcode, @Nullable Opcode quickOpcode) { in FieldOpcode()
86 new FieldOpcode('Z', Opcode.IGET_BOOLEAN, Opcode.IGET_QUICK, Opcode.IGET_VOLATILE),
87 new FieldOpcode('B', Opcode.IGET_BYTE, Opcode.IGET_QUICK, Opcode.IGET_VOLATILE),
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/external/javassist/src/main/javassist/bytecode/stackmap/
DTracer.java24 import javassist.bytecode.Opcode;
133 case Opcode.NOP : in doOpcode0_53()
135 case Opcode.ACONST_NULL : in doOpcode0_53()
138 case Opcode.ICONST_M1 : in doOpcode0_53()
139 case Opcode.ICONST_0 : in doOpcode0_53()
140 case Opcode.ICONST_1 : in doOpcode0_53()
141 case Opcode.ICONST_2 : in doOpcode0_53()
142 case Opcode.ICONST_3 : in doOpcode0_53()
143 case Opcode.ICONST_4 : in doOpcode0_53()
144 case Opcode.ICONST_5 : in doOpcode0_53()
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/external/swiftshader/third_party/subzero/src/
DIceAssemblerMIPS32.cpp207 void AssemblerMIPS32::emitRsRt(IValueT Opcode, const Operand *OpRs, in emitRsRt() argument
212 Opcode |= Rs << 21; in emitRsRt()
213 Opcode |= Rt << 16; in emitRsRt()
215 emitInst(Opcode); in emitRsRt()
218 void AssemblerMIPS32::emitRtRsImm16(IValueT Opcode, const Operand *OpRt, in emitRtRsImm16() argument
224 Opcode |= Rs << 21; in emitRtRsImm16()
225 Opcode |= Rt << 16; in emitRtRsImm16()
226 Opcode |= Imm & 0xffff; in emitRtRsImm16()
228 emitInst(Opcode); in emitRtRsImm16()
231 void AssemblerMIPS32::emitRtRsImm16Rel(IValueT Opcode, const Operand *OpRt, in emitRtRsImm16Rel() argument
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/external/mesa3d/src/gallium/drivers/r300/compiler/
Dradeon_opcodes.c15 .Opcode = RC_OPCODE_NOP,
19 .Opcode = RC_OPCODE_ILLEGAL_OPCODE,
23 .Opcode = RC_OPCODE_ADD,
30 .Opcode = RC_OPCODE_ARL,
36 .Opcode = RC_OPCODE_ARR,
42 .Opcode = RC_OPCODE_CMP,
49 .Opcode = RC_OPCODE_CND,
56 .Opcode = RC_OPCODE_COS,
63 .Opcode = RC_OPCODE_DDX,
70 .Opcode = RC_OPCODE_DDY,
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/external/swiftshader/third_party/llvm-16.0/configs/common/lib/Target/X86/
DX86GenMnemonicTables.inc15 bool isPCMPISTRM(unsigned Opcode);
16 bool isVALIGND(unsigned Opcode);
17 bool isVFMULCPH(unsigned Opcode);
18 bool isVPDPBSSD(unsigned Opcode);
19 bool isVFIXUPIMMPS(unsigned Opcode);
20 bool isVPMOVQ2M(unsigned Opcode);
21 bool isLDTILECFG(unsigned Opcode);
22 bool isFADD(unsigned Opcode);
23 bool isVALIGNQ(unsigned Opcode);
24 bool isAESENC128KL(unsigned Opcode);
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/external/rust/android-crates-io/crates/rustix/src/ioctl/
Dpatterns.rs3 use super::{Ioctl, IoctlOutput, Opcode, RawOpcode};
13 pub struct NoArg<Opcode> {
15 _opcode: PhantomData<Opcode>,
18 impl<Opcode: CompileTimeOpcode> fmt::Debug for NoArg<Opcode> {
20 f.debug_tuple("NoArg").field(&Opcode::OPCODE).finish() in fmt()
24 impl<Opcode: CompileTimeOpcode> NoArg<Opcode> {
38 unsafe impl<Opcode: CompileTimeOpcode> Ioctl for NoArg<Opcode> {
42 const OPCODE: self::Opcode = Opcode::OPCODE;
57 pub struct Getter<Opcode, Output> {
62 _opcode: PhantomData<Opcode>,
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/external/capstone/arch/XCore/
DXCoreGenDisassemblerTables.inc32 /* 15 */ MCD_OPC_Decode, 243, 1, 0, // Opcode: WAITEU_0R
34 /* 24 */ MCD_OPC_Decode, 59, 0, // Opcode: CLRE_0R
36 /* 32 */ MCD_OPC_Decode, 218, 1, 0, // Opcode: SSYNC_0r
38 /* 41 */ MCD_OPC_Decode, 93, 0, // Opcode: FREET_0R
40 /* 49 */ MCD_OPC_Decode, 68, 0, // Opcode: DCALL_0R
42 /* 57 */ MCD_OPC_Decode, 125, 0, // Opcode: KRET_0R
44 /* 65 */ MCD_OPC_Decode, 74, 0, // Opcode: DRET_0R
46 /* 73 */ MCD_OPC_Decode, 199, 1, 0, // Opcode: SETKEP_0R
49 /* 84 */ MCD_OPC_Decode, 77, 1, // Opcode: EDU_1r
51 /* 91 */ MCD_OPC_Decode, 80, 1, // Opcode: EEU_1r
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/external/google-smali/dexlib2/src/test/java/com/android/tools/smali/dexlib2/builder/
DPayloadAlignmentTest.java44 import com.android.tools.smali.dexlib2.Opcode;
61 implBuilder.addInstruction(new BuilderInstruction10x(Opcode.NOP)); in testPayloadAlignmentRemoveNop()
71 Assert.assertEquals(instruction.getOpcode(), Opcode.ARRAY_PAYLOAD); in testPayloadAlignmentRemoveNop()
78 implBuilder.addInstruction(new BuilderInstruction12x(Opcode.MOVE, 0, 0)); in testPayloadAlignmentAddNop()
87 Assert.assertEquals(instruction.getOpcode(), Opcode.MOVE); in testPayloadAlignmentAddNop()
90 Assert.assertEquals(instruction.getOpcode(), Opcode.NOP); in testPayloadAlignmentAddNop()
93 Assert.assertEquals(instruction.getOpcode(), Opcode.ARRAY_PAYLOAD); in testPayloadAlignmentAddNop()
101 implBuilder.addInstruction(new BuilderInstruction31t(Opcode.FILL_ARRAY_DATA, 0, label)); in testPayloadAlignmentRemoveNopWithReferent()
102 implBuilder.addInstruction(new BuilderInstruction12x(Opcode.MOVE, 0, 0)); in testPayloadAlignmentRemoveNopWithReferent()
103 implBuilder.addInstruction(new BuilderInstruction12x(Opcode.MOVE, 0, 0)); in testPayloadAlignmentRemoveNopWithReferent()
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/external/capstone/arch/PowerPC/
DPPCGenDisassemblerTables.inc35 /* 14 */ MCD_OPC_Decode, 119, 0, // Opcode: ATTN
37 /* 21 */ MCD_OPC_Decode, 247, 8, 1, // Opcode: TDI
39 /* 29 */ MCD_OPC_Decode, 136, 9, 2, // Opcode: TWI
45 /* 51 */ MCD_OPC_Decode, 144, 9, 3, // Opcode: VADDUBM
47 /* 59 */ MCD_OPC_Decode, 147, 9, 3, // Opcode: VADDUHM
49 /* 67 */ MCD_OPC_Decode, 149, 9, 3, // Opcode: VADDUWM
51 /* 75 */ MCD_OPC_Decode, 146, 9, 3, // Opcode: VADDUDM
53 /* 83 */ MCD_OPC_Decode, 139, 9, 3, // Opcode: VADDCUW
55 /* 91 */ MCD_OPC_Decode, 145, 9, 3, // Opcode: VADDUBS
57 /* 99 */ MCD_OPC_Decode, 148, 9, 3, // Opcode: VADDUHS
[all …]
/external/capstone/arch/Sparc/
DSparcGenDisassemblerTables.inc33 /* 20 */ MCD_OPC_Decode, 211, 3, 0, // Opcode: UNIMP
40 /* 46 */ MCD_OPC_Decode, 94, 1, // Opcode: BPICCNT
43 /* 57 */ MCD_OPC_Decode, 93, 1, // Opcode: BPICCANT
48 /* 75 */ MCD_OPC_Decode, 91, 1, // Opcode: BPICC
51 /* 86 */ MCD_OPC_Decode, 92, 1, // Opcode: BPICCA
55 /* 100 */ MCD_OPC_Decode, 110, 1, // Opcode: BPXCCNT
57 /* 107 */ MCD_OPC_Decode, 109, 1, // Opcode: BPXCCANT
61 /* 121 */ MCD_OPC_Decode, 107, 1, // Opcode: BPXCC
63 /* 128 */ MCD_OPC_Decode, 108, 1, // Opcode: BPXCCA
68 /* 148 */ MCD_OPC_Decode, 73, 0, // Opcode: BA
[all …]
/external/capstone/arch/SystemZ/
DSystemZGenDisassemblerTables.inc32 /* 14 */ MCD_OPC_Decode, 149, 14, 0, // Opcode: PR
34 /* 22 */ MCD_OPC_Decode, 209, 16, 0, // Opcode: UPT
36 /* 30 */ MCD_OPC_Decode, 153, 14, 0, // Opcode: PTFF
38 /* 38 */ MCD_OPC_Decode, 189, 14, 0, // Opcode: SCKPF
40 /* 46 */ MCD_OPC_Decode, 140, 14, 0, // Opcode: PFPO
42 /* 54 */ MCD_OPC_Decode, 156, 16, 0, // Opcode: TAM
44 /* 62 */ MCD_OPC_Decode, 181, 14, 0, // Opcode: SAM24
46 /* 70 */ MCD_OPC_Decode, 182, 14, 0, // Opcode: SAM31
48 /* 78 */ MCD_OPC_Decode, 183, 14, 0, // Opcode: SAM64
50 /* 87 */ MCD_OPC_Decode, 187, 16, 0, // Opcode: TRAP2
[all …]
/external/capstone/arch/Mips/
DMipsGenDisassemblerTables.inc31 /* 11 */ MCD_OPC_Decode, 220, 7, 10, // Opcode: LWC3
34 /* 23 */ MCD_OPC_Decode, 167, 7, 10, // Opcode: LDC3
37 /* 35 */ MCD_OPC_Decode, 242, 12, 10, // Opcode: SWC3
40 /* 47 */ MCD_OPC_Decode, 161, 11, 10, // Opcode: SDC3
51 /* 18 */ MCD_OPC_Decode, 52, 11, // Opcode: ADDU16_MM
54 /* 29 */ MCD_OPC_Decode, 214, 12, 11, // Opcode: SUBU16_MM
57 /* 41 */ MCD_OPC_Decode, 155, 7, 12, // Opcode: LBU16_MM
60 /* 53 */ MCD_OPC_Decode, 233, 8, 13, // Opcode: MOVE16_MM
65 /* 72 */ MCD_OPC_Decode, 226, 11, 14, // Opcode: SLL16_MM
68 /* 84 */ MCD_OPC_Decode, 160, 12, 14, // Opcode: SRL16_MM
[all …]
/external/swiftshader/third_party/SPIRV-Tools/utils/vscode/src/schema/
Dschema.go21 type Opcode struct { struct
24 Opcode int member
101 type OpcodeMap map[string]*Opcode
952 OpNop = &Opcode {
955 Opcode: 0,
959 OpUndef = &Opcode {
962 Opcode: 1,
976 OpSourceContinued = &Opcode {
979 Opcode: 2,
988 OpSource = &Opcode {
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/external/deqp-deps/SPIRV-Tools/utils/vscode/src/schema/
Dschema.go21 type Opcode struct { struct
24 Opcode int member
101 type OpcodeMap map[string]*Opcode
952 OpNop = &Opcode {
955 Opcode: 0,
959 OpUndef = &Opcode {
962 Opcode: 1,
976 OpSourceContinued = &Opcode {
979 Opcode: 2,
988 OpSource = &Opcode {
[all …]
/external/capstone/arch/AArch64/
DAArch64GenDisassemblerTables.inc38 /* 35 */ MCD_OPC_Decode, 147, 15, 0, // Opcode: STXRB
40 /* 43 */ MCD_OPC_Decode, 191, 14, 0, // Opcode: STLXRB
44 /* 58 */ MCD_OPC_Decode, 171, 8, 0, // Opcode: LDXRB
46 /* 66 */ MCD_OPC_Decode, 171, 7, 0, // Opcode: LDAXRB
49 /* 80 */ MCD_OPC_Decode, 185, 14, 0, // Opcode: STLRB
52 /* 94 */ MCD_OPC_Decode, 165, 7, 0, // Opcode: LDARB
56 /* 109 */ MCD_OPC_Decode, 95, 1, // Opcode: ANDWrs
58 /* 116 */ MCD_OPC_Decode, 111, 1, // Opcode: BICWrs
62 /* 130 */ MCD_OPC_Decode, 64, 1, // Opcode: ADDWrs
65 /* 143 */ MCD_OPC_Decode, 65, 2, // Opcode: ADDWrx
[all …]
/external/google-smali/dexlib2/src/main/java/com/android/tools/smali/dexlib2/writer/
DInstructionFactory.java34 import com.android.tools.smali.dexlib2.Opcode;
44 Instruction makeInstruction10t(@Nonnull Opcode opcode, int codeOffset); in makeInstruction10t()
45 Instruction makeInstruction10x(@Nonnull Opcode opcode); in makeInstruction10x()
46 Instruction makeInstruction11n(@Nonnull Opcode opcode, int registerA, int literal); in makeInstruction11n()
47 Instruction makeInstruction11x(@Nonnull Opcode opcode, int registerA); in makeInstruction11x()
48 Instruction makeInstruction12x(@Nonnull Opcode opcode, int registerA, int registerB); in makeInstruction12x()
49 …Instruction makeInstruction20bc(@Nonnull Opcode opcode, int verificationError, @Nonnull Ref refere… in makeInstruction20bc()
50 Instruction makeInstruction20t(@Nonnull Opcode opcode, int codeOffset); in makeInstruction20t()
51 Instruction makeInstruction21c(@Nonnull Opcode opcode, int registerA, @Nonnull Ref reference); in makeInstruction21c()
52 Instruction makeInstruction21ih(@Nonnull Opcode opcode, int registerA, int literal); in makeInstruction21ih()
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/external/angle/third_party/spirv-tools/src/utils/vscode/src/schema/
Dschema.go21 type Opcode struct { struct
24 Opcode int argument
101 type OpcodeMap map[string]*Opcode
1157 OpNop = &Opcode {
1160 Opcode: 0,
1164 OpUndef = &Opcode {
1167 Opcode: 1,
1181 OpSourceContinued = &Opcode {
1184 Opcode: 2,
1193 OpSource = &Opcode {
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/external/llvm/lib/Target/AMDGPU/
DSIInstrInfo.h42 static BranchPredicate getBranchPredicate(unsigned Opcode);
63 MachineInstr &Inst, unsigned Opcode) const;
66 MachineInstr &Inst, unsigned Opcode) const;
187 bool isSALU(uint16_t Opcode) const { in isSALU() argument
188 return get(Opcode).TSFlags & SIInstrFlags::SALU; in isSALU()
195 bool isVALU(uint16_t Opcode) const { in isVALU() argument
196 return get(Opcode).TSFlags & SIInstrFlags::VALU; in isVALU()
203 bool isVMEM(uint16_t Opcode) const { in isVMEM() argument
204 return isMUBUF(Opcode) || isMTBUF(Opcode) || isMIMG(Opcode); in isVMEM()
211 bool isSOP1(uint16_t Opcode) const { in isSOP1() argument
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/external/capstone/arch/ARM/
DARMGenDisassemblerTables.inc40 /* 45 */ MCD_OPC_Decode, 43, 0, // Opcode: ANDrr
42 /* 52 */ MCD_OPC_Decode, 44, 1, // Opcode: ANDrsi
46 /* 69 */ MCD_OPC_Decode, 205, 3, 0, // Opcode: SUBrr
48 /* 77 */ MCD_OPC_Decode, 206, 3, 1, // Opcode: SUBrsi
52 /* 95 */ MCD_OPC_Decode, 32, 0, // Opcode: ADDrr
54 /* 102 */ MCD_OPC_Decode, 33, 1, // Opcode: ADDrsi
58 /* 119 */ MCD_OPC_Decode, 185, 2, 0, // Opcode: SBCrr
60 /* 127 */ MCD_OPC_Decode, 186, 2, 1, // Opcode: SBCrsi
67 /* 153 */ MCD_OPC_Decode, 45, 2, // Opcode: ANDrsr
70 /* 164 */ MCD_OPC_Decode, 207, 3, 2, // Opcode: SUBrsr
[all …]
/external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/PowerPC/
DPPCGenDisassemblerTables.inc65 /* 16 */ MCD::OPC_Decode, 133, 3, 0, // Opcode: ATTN
67 /* 25 */ MCD::OPC_Decode, 168, 13, 1, // Opcode: TDI
69 /* 34 */ MCD::OPC_Decode, 189, 13, 2, // Opcode: TWI
75 /* 59 */ MCD::OPC_Decode, 204, 13, 3, // Opcode: VADDUBM
77 /* 68 */ MCD::OPC_Decode, 207, 13, 3, // Opcode: VADDUHM
79 /* 77 */ MCD::OPC_Decode, 210, 13, 3, // Opcode: VADDUWM
81 /* 86 */ MCD::OPC_Decode, 206, 13, 3, // Opcode: VADDUDM
83 /* 95 */ MCD::OPC_Decode, 209, 13, 3, // Opcode: VADDUQM
85 /* 104 */ MCD::OPC_Decode, 196, 13, 3, // Opcode: VADDCUQ
87 /* 113 */ MCD::OPC_Decode, 197, 13, 3, // Opcode: VADDCUW
[all …]
/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/AMDGPU/
DSIInstrInfo.h65 static BranchPredicate getBranchPredicate(unsigned Opcode);
98 unsigned Opcode) const;
102 unsigned Opcode) const;
105 MachineInstr &Inst, unsigned Opcode,
112 unsigned Opcode,
358 bool isSALU(uint16_t Opcode) const { in isSALU() argument
359 return get(Opcode).TSFlags & SIInstrFlags::SALU; in isSALU()
366 bool isVALU(uint16_t Opcode) const { in isVALU() argument
367 return get(Opcode).TSFlags & SIInstrFlags::VALU; in isVALU()
374 bool isVMEM(uint16_t Opcode) const { in isVMEM() argument
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/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/BPF/
DBPFMISimplifyPatchable.cpp62 bool isLoadInst(unsigned Opcode);
76 unsigned Opcode);
96 bool BPFMISimplifyPatchable::isLoadInst(unsigned Opcode) { in isLoadInst() argument
97 return Opcode == BPF::LDD || Opcode == BPF::LDW || Opcode == BPF::LDH || in isLoadInst()
98 Opcode == BPF::LDB || Opcode == BPF::LDW32 || Opcode == BPF::LDH32 || in isLoadInst()
99 Opcode == BPF::LDB32; in isLoadInst()
118 unsigned Opcode = DefInst->getOpcode(); in checkADDrr() local
120 if (Opcode == BPF::LDB || Opcode == BPF::LDH || Opcode == BPF::LDW || in checkADDrr()
121 Opcode == BPF::LDD || Opcode == BPF::STB || Opcode == BPF::STH || in checkADDrr()
122 Opcode == BPF::STW || Opcode == BPF::STD) in checkADDrr()
[all …]
/external/swiftshader/third_party/llvm-16.0/configs/common/lib/Target/PowerPC/
DPPCGenDisassemblerTables.inc78 /* 16 */ MCD::OPC_Decode, 220, 3, 0, // Opcode: ATTN
80 /* 25 */ MCD::OPC_Decode, 194, 14, 1, // Opcode: TDI
82 /* 34 */ MCD::OPC_Decode, 217, 14, 2, // Opcode: TWI
92 /* 75 */ MCD::OPC_Decode, 231, 14, 3, // Opcode: VADDUBM
94 /* 84 */ MCD::OPC_Decode, 232, 14, 3, // Opcode: VADDUBS
96 /* 93 */ MCD::OPC_Decode, 199, 17, 3, // Opcode: VSUBUBM
98 /* 102 */ MCD::OPC_Decode, 200, 17, 3, // Opcode: VSUBUBS
105 /* 134 */ MCD::OPC_Decode, 194, 16, 4, // Opcode: VMUL10CUQ
108 /* 150 */ MCD::OPC_Decode, 197, 16, 4, // Opcode: VMUL10UQ
110 /* 159 */ MCD::OPC_Decode, 242, 3, 5, // Opcode: BCDADD_rec
[all …]
/external/swiftshader/third_party/llvm-16.0/configs/common/lib/Target/RISCV/
DRISCVGenDisassemblerTables.inc81 /* 28 */ MCD::OPC_Decode, 248, 94, 0, // Opcode: C_UNIMP
83 /* 37 */ MCD::OPC_Decode, 198, 94, 1, // Opcode: C_ADDI4SPN
87 /* 58 */ MCD::OPC_Decode, 232, 94, 0, // Opcode: C_NOP
90 /* 74 */ MCD::OPC_Decode, 233, 94, 2, // Opcode: C_NOP_HINT
92 /* 83 */ MCD::OPC_Decode, 196, 94, 3, // Opcode: C_ADDI
97 /* 111 */ MCD::OPC_Decode, 238, 94, 4, // Opcode: C_SLLI64_HINT
100 /* 127 */ MCD::OPC_Decode, 239, 94, 5, // Opcode: C_SLLI_HINT
102 /* 136 */ MCD::OPC_Decode, 237, 94, 6, // Opcode: C_SLLI
107 /* 158 */ MCD::OPC_Decode, 210, 94, 7, // Opcode: C_FLD
110 /* 172 */ MCD::OPC_Decode, 199, 94, 3, // Opcode: C_ADDIW
[all …]

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