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1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|*                                                                            *|
3|* X86 Mnemonic tables                                                        *|
4|*                                                                            *|
5|* Automatically generated file, do not edit!                                 *|
6|*                                                                            *|
7\*===----------------------------------------------------------------------===*/
8
9namespace llvm {
10namespace X86 {
11
12#ifdef GET_X86_MNEMONIC_TABLES_H
13#undef GET_X86_MNEMONIC_TABLES_H
14
15bool isPCMPISTRM(unsigned Opcode);
16bool isVALIGND(unsigned Opcode);
17bool isVFMULCPH(unsigned Opcode);
18bool isVPDPBSSD(unsigned Opcode);
19bool isVFIXUPIMMPS(unsigned Opcode);
20bool isVPMOVQ2M(unsigned Opcode);
21bool isLDTILECFG(unsigned Opcode);
22bool isFADD(unsigned Opcode);
23bool isVALIGNQ(unsigned Opcode);
24bool isAESENC128KL(unsigned Opcode);
25bool isVPMAXUB(unsigned Opcode);
26bool isFMULP(unsigned Opcode);
27bool isVPMAXUD(unsigned Opcode);
28bool isCMPCC(unsigned Opcode);
29bool isVSHUFI32X4(unsigned Opcode);
30bool isLOOPNE(unsigned Opcode);
31bool isVPMAXUQ(unsigned Opcode);
32bool isVCOMPRESSPD(unsigned Opcode);
33bool isVPMAXUW(unsigned Opcode);
34bool isVPMOVB2M(unsigned Opcode);
35bool isVANDPD(unsigned Opcode);
36bool isVCOMPRESSPS(unsigned Opcode);
37bool isVPDPBSUD(unsigned Opcode);
38bool isPFRCPIT1(unsigned Opcode);
39bool isPFRCPIT2(unsigned Opcode);
40bool isWRPKRU(unsigned Opcode);
41bool isVANDPS(unsigned Opcode);
42bool isWRUSSD(unsigned Opcode);
43bool isVMPTRLD(unsigned Opcode);
44bool isWRUSSQ(unsigned Opcode);
45bool isAESDECLAST(unsigned Opcode);
46bool isSYSCALL(unsigned Opcode);
47bool isVFIXUPIMMSD(unsigned Opcode);
48bool isVPRORD(unsigned Opcode);
49bool isTEST(unsigned Opcode);
50bool isSHA1MSG1(unsigned Opcode);
51bool isSHA1MSG2(unsigned Opcode);
52bool isVFMULCSH(unsigned Opcode);
53bool isMOVNTDQA(unsigned Opcode);
54bool isVFIXUPIMMSS(unsigned Opcode);
55bool isADOX(unsigned Opcode);
56bool isVPRORQ(unsigned Opcode);
57bool isVSCATTERPF1DPD(unsigned Opcode);
58bool isVPSRLDQ(unsigned Opcode);
59bool isVPMOVUSWB(unsigned Opcode);
60bool isVSCATTERPF1DPS(unsigned Opcode);
61bool isFICOMP(unsigned Opcode);
62bool isFBSTP(unsigned Opcode);
63bool isVPSHUFLW(unsigned Opcode);
64bool isVPSCATTERDD(unsigned Opcode);
65bool isFNINIT(unsigned Opcode);
66bool isMOVNTPD(unsigned Opcode);
67bool isUIRET(unsigned Opcode);
68bool isPINSRB(unsigned Opcode);
69bool isPINSRD(unsigned Opcode);
70bool isSHRD(unsigned Opcode);
71bool isVPSCATTERDQ(unsigned Opcode);
72bool isMOVNTPS(unsigned Opcode);
73bool isVGETEXPPD(unsigned Opcode);
74bool isVRANGEPD(unsigned Opcode);
75bool isPFRCP(unsigned Opcode);
76bool isVGETEXPPH(unsigned Opcode);
77bool isPINSRQ(unsigned Opcode);
78bool isVPROTB(unsigned Opcode);
79bool isVPROTD(unsigned Opcode);
80bool isSEAMCALL(unsigned Opcode);
81bool isPINSRW(unsigned Opcode);
82bool isSHRX(unsigned Opcode);
83bool isVGETEXPPS(unsigned Opcode);
84bool isVRANGEPS(unsigned Opcode);
85bool isPABSB(unsigned Opcode);
86bool isPABSD(unsigned Opcode);
87bool isVPROTQ(unsigned Opcode);
88bool isVPROTW(unsigned Opcode);
89bool isVCVTTPS2UDQ(unsigned Opcode);
90bool isFXRSTOR(unsigned Opcode);
91bool isVMOVDQU16(unsigned Opcode);
92bool isPABSW(unsigned Opcode);
93bool isCVTDQ2PD(unsigned Opcode);
94bool isCVTDQ2PS(unsigned Opcode);
95bool isXOR(unsigned Opcode);
96bool isINC(unsigned Opcode);
97bool isVMCALL(unsigned Opcode);
98bool isPACKSSDW(unsigned Opcode);
99bool isPSUBUSB(unsigned Opcode);
100bool isINT(unsigned Opcode);
101bool isMOVNTSD(unsigned Opcode);
102bool isVPMOVZXBD(unsigned Opcode);
103bool isVCVTUDQ2PD(unsigned Opcode);
104bool isVCVTUDQ2PH(unsigned Opcode);
105bool isVMOVDQU32(unsigned Opcode);
106bool isPSUBUSW(unsigned Opcode);
107bool isMOVNTSS(unsigned Opcode);
108bool isVGETEXPSD(unsigned Opcode);
109bool isVPMOVZXBQ(unsigned Opcode);
110bool isVGETEXPSH(unsigned Opcode);
111bool isVCVTNEEBF162PS(unsigned Opcode);
112bool isVRANGESD(unsigned Opcode);
113bool isVCVTUDQ2PS(unsigned Opcode);
114bool isVPMOVZXBW(unsigned Opcode);
115bool isVGETEXPSS(unsigned Opcode);
116bool isSHUFPD(unsigned Opcode);
117bool isVCVTTSS2SI(unsigned Opcode);
118bool isVINSERTF128(unsigned Opcode);
119bool isKANDNB(unsigned Opcode);
120bool isPADDSB(unsigned Opcode);
121bool isKANDND(unsigned Opcode);
122bool isVPCMPISTRI(unsigned Opcode);
123bool isRDPID(unsigned Opcode);
124bool isVPCMPISTRM(unsigned Opcode);
125bool isVRANGESS(unsigned Opcode);
126bool isSHUFPS(unsigned Opcode);
127bool isVPDPBSSDS(unsigned Opcode);
128bool isKANDNQ(unsigned Opcode);
129bool isKANDNW(unsigned Opcode);
130bool isPADDSW(unsigned Opcode);
131bool isVCVTTPD2UDQ(unsigned Opcode);
132bool isVANDNPD(unsigned Opcode);
133bool isXEND(unsigned Opcode);
134bool isVUNPCKHPD(unsigned Opcode);
135bool isPSRAD(unsigned Opcode);
136bool isVANDNPS(unsigned Opcode);
137bool isVPMOVZXDQ(unsigned Opcode);
138bool isVMPTRST(unsigned Opcode);
139bool isVUNPCKHPS(unsigned Opcode);
140bool isPSRAW(unsigned Opcode);
141bool isVPLZCNTD(unsigned Opcode);
142bool isWRMSRLIST(unsigned Opcode);
143bool isVPADDUSB(unsigned Opcode);
144bool isVMOVDQU64(unsigned Opcode);
145bool isSUBPD(unsigned Opcode);
146bool isMOVDDUP(unsigned Opcode);
147bool isVPLZCNTQ(unsigned Opcode);
148bool isSTAC(unsigned Opcode);
149bool isSUBPS(unsigned Opcode);
150bool isVPADDUSW(unsigned Opcode);
151bool isFCMOVNBE(unsigned Opcode);
152bool isSHA1RNDS4(unsigned Opcode);
153bool isPAUSE(unsigned Opcode);
154bool isSAHF(unsigned Opcode);
155bool isVREDUCEPD(unsigned Opcode);
156bool isVREDUCEPH(unsigned Opcode);
157bool isFXAM(unsigned Opcode);
158bool isLGDTD(unsigned Opcode);
159bool isPMULHRW(unsigned Opcode);
160bool isVREDUCEPS(unsigned Opcode);
161bool isRDPMC(unsigned Opcode);
162bool isVGATHERPF1QPD(unsigned Opcode);
163bool isLGDTW(unsigned Opcode);
164bool isVAESKEYGENASSIST(unsigned Opcode);
165bool isRDFSBASE(unsigned Opcode);
166bool isVGATHERPF1QPS(unsigned Opcode);
167bool isSUBSD(unsigned Opcode);
168bool isVCVTNEOBF162PS(unsigned Opcode);
169bool isAESENCWIDE128KL(unsigned Opcode);
170bool isFXCH(unsigned Opcode);
171bool isSUBSS(unsigned Opcode);
172bool isPANDN(unsigned Opcode);
173bool isVPERMT2B(unsigned Opcode);
174bool isLJMP(unsigned Opcode);
175bool isCMPPD(unsigned Opcode);
176bool isVPERMT2D(unsigned Opcode);
177bool isVPMADD52HUQ(unsigned Opcode);
178bool isVPERMT2Q(unsigned Opcode);
179bool isCMPPS(unsigned Opcode);
180bool isVCVTPH2W(unsigned Opcode);
181bool isVREDUCESD(unsigned Opcode);
182bool isVPERMT2W(unsigned Opcode);
183bool isWBNOINVD(unsigned Opcode);
184bool isVREDUCESH(unsigned Opcode);
185bool isTILEZERO(unsigned Opcode);
186bool isPMULHUW(unsigned Opcode);
187bool isVREDUCESS(unsigned Opcode);
188bool isVCVTUW2PH(unsigned Opcode);
189bool isVPBLENDMB(unsigned Opcode);
190bool isVPBLENDMD(unsigned Opcode);
191bool isVFMSUB132PD(unsigned Opcode);
192bool isVFMSUB132PH(unsigned Opcode);
193bool isMWAIT(unsigned Opcode);
194bool isSALC(unsigned Opcode);
195bool isPMADDUBSW(unsigned Opcode);
196bool isVFCMULCPH(unsigned Opcode);
197bool isVPBLENDMQ(unsigned Opcode);
198bool isRORX(unsigned Opcode);
199bool isVFMSUB132PS(unsigned Opcode);
200bool isVPBLENDMW(unsigned Opcode);
201bool isMOV(unsigned Opcode);
202bool isFXSAVE64(unsigned Opcode);
203bool isRMPADJUST(unsigned Opcode);
204bool isAADD(unsigned Opcode);
205bool isVLDDQU(unsigned Opcode);
206bool isVPSCATTERQD(unsigned Opcode);
207bool isVPHADDUBD(unsigned Opcode);
208bool isCMPSB(unsigned Opcode);
209bool isCMPSD(unsigned Opcode);
210bool isSTGI(unsigned Opcode);
211bool isVUNPCKLPD(unsigned Opcode);
212bool isVPSCATTERQQ(unsigned Opcode);
213bool isFADDP(unsigned Opcode);
214bool isVPHADDUBQ(unsigned Opcode);
215bool isCMPSQ(unsigned Opcode);
216bool isVPHADDUBW(unsigned Opcode);
217bool isCMPSS(unsigned Opcode);
218bool isVUNPCKLPS(unsigned Opcode);
219bool isLCALL(unsigned Opcode);
220bool isPSHUFB(unsigned Opcode);
221bool isCMPSW(unsigned Opcode);
222bool isPSHUFD(unsigned Opcode);
223bool isRDPRU(unsigned Opcode);
224bool isFRNDINT(unsigned Opcode);
225bool isVPACKUSWB(unsigned Opcode);
226bool isDIVPD(unsigned Opcode);
227bool isVAESDEC(unsigned Opcode);
228bool isPSHUFW(unsigned Opcode);
229bool isVPDPBUUDS(unsigned Opcode);
230bool isKMOVB(unsigned Opcode);
231bool isVFMSUB132SD(unsigned Opcode);
232bool isKMOVD(unsigned Opcode);
233bool isVCVTTPS2UQQ(unsigned Opcode);
234bool isVFMSUB132SH(unsigned Opcode);
235bool isDIVPS(unsigned Opcode);
236bool isVFCMULCSH(unsigned Opcode);
237bool isFICOM(unsigned Opcode);
238bool isKMOVQ(unsigned Opcode);
239bool isVFMSUB132SS(unsigned Opcode);
240bool isENCODEKEY128(unsigned Opcode);
241bool isKMOVW(unsigned Opcode);
242bool isPREFETCHT0(unsigned Opcode);
243bool isPREFETCHT1(unsigned Opcode);
244bool isPREFETCHT2(unsigned Opcode);
245bool isSWAPGS(unsigned Opcode);
246bool isVPTESTMD(unsigned Opcode);
247bool isVPTESTMB(unsigned Opcode);
248bool isVPHADDUDQ(unsigned Opcode);
249bool isVPTESTMQ(unsigned Opcode);
250bool isXRSTORS(unsigned Opcode);
251bool isVPMULDQ(unsigned Opcode);
252bool isUD1(unsigned Opcode);
253bool isUD2(unsigned Opcode);
254bool isVPTESTMW(unsigned Opcode);
255bool isSEAMOPS(unsigned Opcode);
256bool isMWAITX(unsigned Opcode);
257bool isVFMADD132PD(unsigned Opcode);
258bool isWRMSRNS(unsigned Opcode);
259bool isVMOVNTDQ(unsigned Opcode);
260bool isVFMADD132PH(unsigned Opcode);
261bool isPSRLD(unsigned Opcode);
262bool isVBROADCASTI64X2(unsigned Opcode);
263bool isVBROADCASTI64X4(unsigned Opcode);
264bool isVFMADD132PS(unsigned Opcode);
265bool isIDIV(unsigned Opcode);
266bool isPREFETCHWT1(unsigned Opcode);
267bool isVPSRLVD(unsigned Opcode);
268bool isPSRLQ(unsigned Opcode);
269bool isPSRLW(unsigned Opcode);
270bool isDIVSD(unsigned Opcode);
271bool isVPMOVDB(unsigned Opcode);
272bool isVPSRLVQ(unsigned Opcode);
273bool isVPSRLVW(unsigned Opcode);
274bool isDIVSS(unsigned Opcode);
275bool isMUL(unsigned Opcode);
276bool isVPMOVDW(unsigned Opcode);
277bool isVCVTTPD2UQQ(unsigned Opcode);
278bool isFSINCOS(unsigned Opcode);
279bool isVPMADD52LUQ(unsigned Opcode);
280bool isLWPINS(unsigned Opcode);
281bool isMOVDIR64B(unsigned Opcode);
282bool isLOOPE(unsigned Opcode);
283bool isPUSH(unsigned Opcode);
284bool isPSADBW(unsigned Opcode);
285bool isFTST(unsigned Opcode);
286bool isSETSSBSY(unsigned Opcode);
287bool isSARX(unsigned Opcode);
288bool isVADDSUBPD(unsigned Opcode);
289bool isVADDSUBPS(unsigned Opcode);
290bool isVMINPD(unsigned Opcode);
291bool isCLZERO(unsigned Opcode);
292bool isVMINPH(unsigned Opcode);
293bool isXCRYPTCBC(unsigned Opcode);
294bool isFXTRACT(unsigned Opcode);
295bool isVMINPS(unsigned Opcode);
296bool isVFMADD132SD(unsigned Opcode);
297bool isVFMADD132SH(unsigned Opcode);
298bool isVPERMI2B(unsigned Opcode);
299bool isVPERMI2D(unsigned Opcode);
300bool isVFMADD132SS(unsigned Opcode);
301bool isVRSQRT28PD(unsigned Opcode);
302bool isVPMULHW(unsigned Opcode);
303bool isSIDT(unsigned Opcode);
304bool isTDCALL(unsigned Opcode);
305bool isVPERMI2Q(unsigned Opcode);
306bool isVPERMI2W(unsigned Opcode);
307bool isVPERM2F128(unsigned Opcode);
308bool isVMLAUNCH(unsigned Opcode);
309bool isFILD(unsigned Opcode);
310bool isVRSQRT28PS(unsigned Opcode);
311bool isVPBLENDVB(unsigned Opcode);
312bool isVPMADDUBSW(unsigned Opcode);
313bool isVSTMXCSR(unsigned Opcode);
314bool isVCVTTPH2UDQ(unsigned Opcode);
315bool isXSHA256(unsigned Opcode);
316bool isWAIT(unsigned Opcode);
317bool isPACKSSWB(unsigned Opcode);
318bool isPMULHRSW(unsigned Opcode);
319bool isMASKMOVQ(unsigned Opcode);
320bool isVMINSD(unsigned Opcode);
321bool isVMINSH(unsigned Opcode);
322bool isRDTSC(unsigned Opcode);
323bool isVMINSS(unsigned Opcode);
324bool isVRSQRT28SD(unsigned Opcode);
325bool isAAND(unsigned Opcode);
326bool isXCRYPTCFB(unsigned Opcode);
327bool isVSCALEFPD(unsigned Opcode);
328bool isVPBROADCASTB(unsigned Opcode);
329bool isVSCALEFPH(unsigned Opcode);
330bool isVPBROADCASTD(unsigned Opcode);
331bool isVRSQRT28SS(unsigned Opcode);
332bool isVPMULLD(unsigned Opcode);
333bool isVSCALEFPS(unsigned Opcode);
334bool isMOVQ2DQ(unsigned Opcode);
335bool isVPBROADCASTQ(unsigned Opcode);
336bool isPALIGNR(unsigned Opcode);
337bool isPUSHAL(unsigned Opcode);
338bool isVPBROADCASTW(unsigned Opcode);
339bool isVPMULLQ(unsigned Opcode);
340bool isFINCSTP(unsigned Opcode);
341bool isPUSHAW(unsigned Opcode);
342bool isVPMULLW(unsigned Opcode);
343bool isPFPNACC(unsigned Opcode);
344bool isTESTUI(unsigned Opcode);
345bool isVPMOVZXWD(unsigned Opcode);
346bool isVPDPWSSDS(unsigned Opcode);
347bool isINVLPG(unsigned Opcode);
348bool isJCC(unsigned Opcode);
349bool isVPMOVZXWQ(unsigned Opcode);
350bool isBSF(unsigned Opcode);
351bool isROUNDPD(unsigned Opcode);
352bool isSAVEPREVSSP(unsigned Opcode);
353bool isVSCATTERDPD(unsigned Opcode);
354bool isBSR(unsigned Opcode);
355bool isROUNDPS(unsigned Opcode);
356bool isCVTPI2PD(unsigned Opcode);
357bool isKTESTB(unsigned Opcode);
358bool isKTESTD(unsigned Opcode);
359bool isVSCATTERDPS(unsigned Opcode);
360bool isFLD(unsigned Opcode);
361bool isBTC(unsigned Opcode);
362bool isVBCSTNEBF162PS(unsigned Opcode);
363bool isCVTPI2PS(unsigned Opcode);
364bool isKTESTQ(unsigned Opcode);
365bool isVSCALEFSD(unsigned Opcode);
366bool isVSCALEFSH(unsigned Opcode);
367bool isKTESTW(unsigned Opcode);
368bool isXSTORE(unsigned Opcode);
369bool isVFMADDSUB132PD(unsigned Opcode);
370bool isVPSRAVD(unsigned Opcode);
371bool isBTR(unsigned Opcode);
372bool isBTS(unsigned Opcode);
373bool isVFMADDSUB132PH(unsigned Opcode);
374bool isLGDT(unsigned Opcode);
375bool isVSCALEFSS(unsigned Opcode);
376bool isVEXTRACTF128(unsigned Opcode);
377bool isPMOVSXBD(unsigned Opcode);
378bool isKXNORB(unsigned Opcode);
379bool isVFMADDSUB132PS(unsigned Opcode);
380bool isKXNORD(unsigned Opcode);
381bool isXRSTOR(unsigned Opcode);
382bool isVPSRAVQ(unsigned Opcode);
383bool isVPSRAVW(unsigned Opcode);
384bool isVPDPWSSD(unsigned Opcode);
385bool isSQRTPD(unsigned Opcode);
386bool isVDPPD(unsigned Opcode);
387bool isPMOVSXBQ(unsigned Opcode);
388bool isPMADDWD(unsigned Opcode);
389bool isKXNORQ(unsigned Opcode);
390bool isSTUI(unsigned Opcode);
391bool isINSERTQ(unsigned Opcode);
392bool isPMOVSXBW(unsigned Opcode);
393bool isVCVTSI2SD(unsigned Opcode);
394bool isKXNORW(unsigned Opcode);
395bool isVSCATTERPF0DPD(unsigned Opcode);
396bool isVCVTSI2SH(unsigned Opcode);
397bool isSQRTPS(unsigned Opcode);
398bool isVDPPS(unsigned Opcode);
399bool isPSUBSB(unsigned Opcode);
400bool isVPSHRDVD(unsigned Opcode);
401bool isFIST(unsigned Opcode);
402bool isVCVTSI2SS(unsigned Opcode);
403bool isVSCATTERPF0DPS(unsigned Opcode);
404bool isVMOVNTPD(unsigned Opcode);
405bool isROUNDSD(unsigned Opcode);
406bool isVPSHRDVQ(unsigned Opcode);
407bool isPSIGNB(unsigned Opcode);
408bool isJECXZ(unsigned Opcode);
409bool isPSIGND(unsigned Opcode);
410bool isPSUBSW(unsigned Opcode);
411bool isMOVDQ2Q(unsigned Opcode);
412bool isPUSHFD(unsigned Opcode);
413bool isVMOVNTPS(unsigned Opcode);
414bool isROUNDSS(unsigned Opcode);
415bool isVAESDECLAST(unsigned Opcode);
416bool isPAVGB(unsigned Opcode);
417bool isVPSUBB(unsigned Opcode);
418bool isVPSHRDVW(unsigned Opcode);
419bool isVPSUBD(unsigned Opcode);
420bool isPUSHFQ(unsigned Opcode);
421bool isPSIGNW(unsigned Opcode);
422bool isVBROADCASTSD(unsigned Opcode);
423bool isVPSUBQ(unsigned Opcode);
424bool isPMOVSXDQ(unsigned Opcode);
425bool isPAVGW(unsigned Opcode);
426bool isVFMSUBADD132PD(unsigned Opcode);
427bool isVPSUBW(unsigned Opcode);
428bool isVCVTPS2PHX(unsigned Opcode);
429bool isMOVHLPS(unsigned Opcode);
430bool isVFMSUBADD132PH(unsigned Opcode);
431bool isVSHUFF64X2(unsigned Opcode);
432bool isVBROADCASTSS(unsigned Opcode);
433bool isVFMSUBADD132PS(unsigned Opcode);
434bool isMAXPD(unsigned Opcode);
435bool isSQRTSD(unsigned Opcode);
436bool isCVTPD2DQ(unsigned Opcode);
437bool isMAXPS(unsigned Opcode);
438bool isVPMOVQB(unsigned Opcode);
439bool isINVPCID(unsigned Opcode);
440bool isVCVTPS2DQ(unsigned Opcode);
441bool isSQRTSS(unsigned Opcode);
442bool isVADDPD(unsigned Opcode);
443bool isLODSB(unsigned Opcode);
444bool isLODSD(unsigned Opcode);
445bool isV4FNMADDPS(unsigned Opcode);
446bool isIRETD(unsigned Opcode);
447bool isVADDPH(unsigned Opcode);
448bool isVHADDPD(unsigned Opcode);
449bool isVPMOVQD(unsigned Opcode);
450bool isVPSUBUSB(unsigned Opcode);
451bool isVPMOVQW(unsigned Opcode);
452bool isVADDPS(unsigned Opcode);
453bool isLODSQ(unsigned Opcode);
454bool isFIDIVR(unsigned Opcode);
455bool isIRETQ(unsigned Opcode);
456bool isLODSW(unsigned Opcode);
457bool isVHADDPS(unsigned Opcode);
458bool isCVTTPS2DQ(unsigned Opcode);
459bool isVPORD(unsigned Opcode);
460bool isVP2INTERSECTD(unsigned Opcode);
461bool isVPSUBUSW(unsigned Opcode);
462bool isVPERMILPD(unsigned Opcode);
463bool isVPSHLDD(unsigned Opcode);
464bool isMOVD(unsigned Opcode);
465bool isVPORQ(unsigned Opcode);
466bool isVP2INTERSECTQ(unsigned Opcode);
467bool isCRC32(unsigned Opcode);
468bool isVPERMILPS(unsigned Opcode);
469bool isMOVQ(unsigned Opcode);
470bool isVPSHLDQ(unsigned Opcode);
471bool isVPMASKMOVD(unsigned Opcode);
472bool isVPSHLDW(unsigned Opcode);
473bool isSLWPCB(unsigned Opcode);
474bool isVORPD(unsigned Opcode);
475bool isPCMPGTB(unsigned Opcode);
476bool isPCMPGTD(unsigned Opcode);
477bool isVPMASKMOVQ(unsigned Opcode);
478bool isPFRSQIT1(unsigned Opcode);
479bool isVORPS(unsigned Opcode);
480bool isPCMPGTQ(unsigned Opcode);
481bool isBLCIC(unsigned Opcode);
482bool isMAXSD(unsigned Opcode);
483bool isPCMPGTW(unsigned Opcode);
484bool isVBCSTNESH2PS(unsigned Opcode);
485bool isMOVLHPS(unsigned Opcode);
486bool isXSAVEC(unsigned Opcode);
487bool isMAXSS(unsigned Opcode);
488bool isFST(unsigned Opcode);
489bool isVCVTSS2USI(unsigned Opcode);
490bool isVADDSD(unsigned Opcode);
491bool isVRNDSCALEPD(unsigned Opcode);
492bool isVCVTTPH2UQQ(unsigned Opcode);
493bool isV4FNMADDSS(unsigned Opcode);
494bool isVADDSH(unsigned Opcode);
495bool isVRNDSCALEPH(unsigned Opcode);
496bool isXSAVES(unsigned Opcode);
497bool isXRESLDTRK(unsigned Opcode);
498bool isVADDSS(unsigned Opcode);
499bool isVRNDSCALEPS(unsigned Opcode);
500bool isVPHADDUWD(unsigned Opcode);
501bool isRDSSPD(unsigned Opcode);
502bool isVPHADDUWQ(unsigned Opcode);
503bool isVMOVDDUP(unsigned Opcode);
504bool isINSERTPS(unsigned Opcode);
505bool isNEG(unsigned Opcode);
506bool isMOVUPD(unsigned Opcode);
507bool isRDSSPQ(unsigned Opcode);
508bool isVFRCZPD(unsigned Opcode);
509bool isPHMINPOSUW(unsigned Opcode);
510bool isVBROADCASTI32X2(unsigned Opcode);
511bool isVBROADCASTI32X4(unsigned Opcode);
512bool isJMP(unsigned Opcode);
513bool isVBROADCASTI32X8(unsigned Opcode);
514bool isMOVUPS(unsigned Opcode);
515bool isVPANDND(unsigned Opcode);
516bool isVCVTNE2PS2BF16(unsigned Opcode);
517bool isVPROLVD(unsigned Opcode);
518bool isVFRCZPS(unsigned Opcode);
519bool isJRCXZ(unsigned Opcode);
520bool isFNSTCW(unsigned Opcode);
521bool isFFREEP(unsigned Opcode);
522bool isVPANDNQ(unsigned Opcode);
523bool isVPROLVQ(unsigned Opcode);
524bool isAESDECWIDE128KL(unsigned Opcode);
525bool isSTTILECFG(unsigned Opcode);
526bool isVPMOVWB(unsigned Opcode);
527bool isVRNDSCALESD(unsigned Opcode);
528bool isVGATHERPF0QPD(unsigned Opcode);
529bool isVPHSUBD(unsigned Opcode);
530bool isVCVTSD2USI(unsigned Opcode);
531bool isWRGSBASE(unsigned Opcode);
532bool isVRNDSCALESH(unsigned Opcode);
533bool isAESENC256KL(unsigned Opcode);
534bool isVRNDSCALESS(unsigned Opcode);
535bool isVGATHERPF0QPS(unsigned Opcode);
536bool isVPHSUBW(unsigned Opcode);
537bool isSHA1NEXTE(unsigned Opcode);
538bool isXCRYPTCTR(unsigned Opcode);
539bool isFMUL(unsigned Opcode);
540bool isFBLD(unsigned Opcode);
541bool isVMXON(unsigned Opcode);
542bool isPUNPCKHQDQ(unsigned Opcode);
543bool isVFRCZSD(unsigned Opcode);
544bool isVFRCZSS(unsigned Opcode);
545bool isRMPUPDATE(unsigned Opcode);
546bool isVFNMADDPD(unsigned Opcode);
547bool isVCOMISD(unsigned Opcode);
548bool isVCOMISH(unsigned Opcode);
549bool isAXOR(unsigned Opcode);
550bool isVFNMADDPS(unsigned Opcode);
551bool isVCOMISS(unsigned Opcode);
552bool isPHADDD(unsigned Opcode);
553bool isVPMULHUW(unsigned Opcode);
554bool isVFNMSUB132PD(unsigned Opcode);
555bool isPMOVMSKB(unsigned Opcode);
556bool isVFNMSUB132PH(unsigned Opcode);
557bool isPHADDW(unsigned Opcode);
558bool isVFNMSUB132PS(unsigned Opcode);
559bool isVMOVDQA(unsigned Opcode);
560bool isSENDUIPI(unsigned Opcode);
561bool isVCVTTPS2DQ(unsigned Opcode);
562bool isRCPPS(unsigned Opcode);
563bool isRDMSR(unsigned Opcode);
564bool isVCVTQQ2PD(unsigned Opcode);
565bool isVRSQRT14PD(unsigned Opcode);
566bool isXORPD(unsigned Opcode);
567bool isVCVTQQ2PH(unsigned Opcode);
568bool isVMOVDQU(unsigned Opcode);
569bool isBLENDPD(unsigned Opcode);
570bool isVCVTQQ2PS(unsigned Opcode);
571bool isVRSQRT14PS(unsigned Opcode);
572bool isXORPS(unsigned Opcode);
573bool isRCL(unsigned Opcode);
574bool isRCR(unsigned Opcode);
575bool isBLENDPS(unsigned Opcode);
576bool isVPEXPANDB(unsigned Opcode);
577bool isVEXPANDPD(unsigned Opcode);
578bool isVPEXPANDD(unsigned Opcode);
579bool isBLSMSK(unsigned Opcode);
580bool isXSUSLDTRK(unsigned Opcode);
581bool isGF2P8MULB(unsigned Opcode);
582bool isSIDTD(unsigned Opcode);
583bool isVEXPANDPS(unsigned Opcode);
584bool isVFNMADDSD(unsigned Opcode);
585bool isCBW(unsigned Opcode);
586bool isVPEXPANDW(unsigned Opcode);
587bool isVPEXPANDQ(unsigned Opcode);
588bool isFXRSTOR64(unsigned Opcode);
589bool isVFNMADDSS(unsigned Opcode);
590bool isSIDTW(unsigned Opcode);
591bool isCVTPD2PI(unsigned Opcode);
592bool isVCVTPS2PD(unsigned Opcode);
593bool isVFNMSUB132SD(unsigned Opcode);
594bool isVCVTPS2PH(unsigned Opcode);
595bool isFIDIV(unsigned Opcode);
596bool isVFNMSUB132SH(unsigned Opcode);
597bool isCVTPD2PS(unsigned Opcode);
598bool isINVEPT(unsigned Opcode);
599bool isVPERMI2PD(unsigned Opcode);
600bool isVFMSUB213PD(unsigned Opcode);
601bool isVFNMSUB132SS(unsigned Opcode);
602bool isINVVPID(unsigned Opcode);
603bool isVFMSUB213PH(unsigned Opcode);
604bool isVPCOMB(unsigned Opcode);
605bool isVPERMI2PS(unsigned Opcode);
606bool isVPCOMD(unsigned Opcode);
607bool isSMSW(unsigned Opcode);
608bool isRCPSS(unsigned Opcode);
609bool isRET(unsigned Opcode);
610bool isVFMSUB213PS(unsigned Opcode);
611bool isVRSQRT14SD(unsigned Opcode);
612bool isCVTTPS2PI(unsigned Opcode);
613bool isVMCLEAR(unsigned Opcode);
614bool isVPCOMQ(unsigned Opcode);
615bool isCDQ(unsigned Opcode);
616bool isFLDL2E(unsigned Opcode);
617bool isVCVTPS2QQ(unsigned Opcode);
618bool isVPCOMW(unsigned Opcode);
619bool isVRSQRT14SS(unsigned Opcode);
620bool isVP4DPWSSDS(unsigned Opcode);
621bool isVPSLLDQ(unsigned Opcode);
622bool isVCVTSD2SH(unsigned Opcode);
623bool isFLDL2T(unsigned Opcode);
624bool isVEXP2PD(unsigned Opcode);
625bool isVFNMADD132PD(unsigned Opcode);
626bool isVCVTSD2SI(unsigned Opcode);
627bool isVPOPCNTB(unsigned Opcode);
628bool isVFNMADD132PH(unsigned Opcode);
629bool isVINSERTI128(unsigned Opcode);
630bool isVPOPCNTD(unsigned Opcode);
631bool isSETCC(unsigned Opcode);
632bool isVCVTSD2SS(unsigned Opcode);
633bool isVEXP2PS(unsigned Opcode);
634bool isVFNMADD132PS(unsigned Opcode);
635bool isMOVDIRI(unsigned Opcode);
636bool isVPOPCNTQ(unsigned Opcode);
637bool isVFMSUB231PD(unsigned Opcode);
638bool isVFMSUB231PH(unsigned Opcode);
639bool isFCMOVBE(unsigned Opcode);
640bool isVPOPCNTW(unsigned Opcode);
641bool isCVTTSD2SI(unsigned Opcode);
642bool isVFMSUB231PS(unsigned Opcode);
643bool isNOP(unsigned Opcode);
644bool isNOT(unsigned Opcode);
645bool isTPAUSE(unsigned Opcode);
646bool isVCVTNEPS2BF16(unsigned Opcode);
647bool isVFMSUB213SD(unsigned Opcode);
648bool isVFMSUB213SH(unsigned Opcode);
649bool isVFMADDCPH(unsigned Opcode);
650bool isVEXTRACTI64X2(unsigned Opcode);
651bool isVFMSUB213SS(unsigned Opcode);
652bool isVEXTRACTI64X4(unsigned Opcode);
653bool isXSAVEC64(unsigned Opcode);
654bool isBLCFILL(unsigned Opcode);
655bool isXBEGIN(unsigned Opcode);
656bool isXCRYPTOFB(unsigned Opcode);
657bool isFUCOMI(unsigned Opcode);
658bool isVMOVHPD(unsigned Opcode);
659bool isMASKMOVDQU(unsigned Opcode);
660bool isFUCOMP(unsigned Opcode);
661bool isVFNMADD132SD(unsigned Opcode);
662bool isMFENCE(unsigned Opcode);
663bool isVFNMADD132SH(unsigned Opcode);
664bool isVMOVHPS(unsigned Opcode);
665bool isVPBROADCASTMW2D(unsigned Opcode);
666bool isVFMADD213PD(unsigned Opcode);
667bool isVFNMADD132SS(unsigned Opcode);
668bool isVFMADD213PH(unsigned Opcode);
669bool isVFMSUB231SD(unsigned Opcode);
670bool isVPMULTISHIFTQB(unsigned Opcode);
671bool isFNSAVE(unsigned Opcode);
672bool isVFMSUB231SH(unsigned Opcode);
673bool isVSHUFF32X4(unsigned Opcode);
674bool isPMOVSXWD(unsigned Opcode);
675bool isVFMADD213PS(unsigned Opcode);
676bool isVFMSUB231SS(unsigned Opcode);
677bool isVPCOMPRESSB(unsigned Opcode);
678bool isPMOVSXWQ(unsigned Opcode);
679bool isVPCOMPRESSD(unsigned Opcode);
680bool isVPABSB(unsigned Opcode);
681bool isVMOVNTDQA(unsigned Opcode);
682bool isVPABSD(unsigned Opcode);
683bool isVPCOMPRESSQ(unsigned Opcode);
684bool isVINSERTI64X2(unsigned Opcode);
685bool isVPCOMPRESSW(unsigned Opcode);
686bool isVINSERTI64X4(unsigned Opcode);
687bool isVPABSQ(unsigned Opcode);
688bool isVFMADDCSH(unsigned Opcode);
689bool isVPABSW(unsigned Opcode);
690bool isPVALIDATE(unsigned Opcode);
691bool isVFMADD231PD(unsigned Opcode);
692bool isVFMADD231PH(unsigned Opcode);
693bool isPUNPCKLQDQ(unsigned Opcode);
694bool isVCVTNEEPH2PS(unsigned Opcode);
695bool isVFMADD231PS(unsigned Opcode);
696bool isAESENCWIDE256KL(unsigned Opcode);
697bool isVGF2P8MULB(unsigned Opcode);
698bool isWRSSD(unsigned Opcode);
699bool isMOVSHDUP(unsigned Opcode);
700bool isTZMSK(unsigned Opcode);
701bool isFPATAN(unsigned Opcode);
702bool isFUCOM(unsigned Opcode);
703bool isVFMADD213SD(unsigned Opcode);
704bool isWRSSQ(unsigned Opcode);
705bool isVFMADD213SH(unsigned Opcode);
706bool isVPTESTNMB(unsigned Opcode);
707bool isVPTESTNMD(unsigned Opcode);
708bool isPMULUDQ(unsigned Opcode);
709bool isHRESET(unsigned Opcode);
710bool isPMAXSB(unsigned Opcode);
711bool isPMAXSD(unsigned Opcode);
712bool isVFMADD213SS(unsigned Opcode);
713bool isCLC(unsigned Opcode);
714bool isCLD(unsigned Opcode);
715bool isENCODEKEY256(unsigned Opcode);
716bool isVPTESTNMQ(unsigned Opcode);
717bool isVGATHERQPD(unsigned Opcode);
718bool isBOUND(unsigned Opcode);
719bool isCLI(unsigned Opcode);
720bool isVPTESTNMW(unsigned Opcode);
721bool isPREFETCHIT0(unsigned Opcode);
722bool isPREFETCHIT1(unsigned Opcode);
723bool isPMAXSW(unsigned Opcode);
724bool isPFSUB(unsigned Opcode);
725bool isVCVTDQ2PH(unsigned Opcode);
726bool isVPALIGNR(unsigned Opcode);
727bool isVCVTDQ2PD(unsigned Opcode);
728bool isFNSTSW(unsigned Opcode);
729bool isFISTP(unsigned Opcode);
730bool isVFMADDPD(unsigned Opcode);
731bool isVGATHERQPS(unsigned Opcode);
732bool isPBLENDW(unsigned Opcode);
733bool isVCVTDQ2PS(unsigned Opcode);
734bool isPREFETCH(unsigned Opcode);
735bool isSKINIT(unsigned Opcode);
736bool isCMC(unsigned Opcode);
737bool isVFMADDPS(unsigned Opcode);
738bool isVPACKSSDW(unsigned Opcode);
739bool isFISUB(unsigned Opcode);
740bool isPADDB(unsigned Opcode);
741bool isPOPAL(unsigned Opcode);
742bool isPADDD(unsigned Opcode);
743bool isVFMADD231SD(unsigned Opcode);
744bool isCMP(unsigned Opcode);
745bool isKANDB(unsigned Opcode);
746bool isKANDD(unsigned Opcode);
747bool isVFMADD231SH(unsigned Opcode);
748bool isVCVTSH2USI(unsigned Opcode);
749bool isPCONFIG(unsigned Opcode);
750bool isPOPAW(unsigned Opcode);
751bool isPADDQ(unsigned Opcode);
752bool isPMAXUB(unsigned Opcode);
753bool isROL(unsigned Opcode);
754bool isKANDQ(unsigned Opcode);
755bool isPADDW(unsigned Opcode);
756bool isVCVTTPS2QQ(unsigned Opcode);
757bool isPMAXUD(unsigned Opcode);
758bool isROR(unsigned Opcode);
759bool isVFMADD231SS(unsigned Opcode);
760bool isKANDW(unsigned Opcode);
761bool isVPSRAD(unsigned Opcode);
762bool isVROUNDPD(unsigned Opcode);
763bool isMOVBE(unsigned Opcode);
764bool isLOOP(unsigned Opcode);
765bool isVCVTTSD2SI(unsigned Opcode);
766bool isVPSRAQ(unsigned Opcode);
767bool isVROUNDPS(unsigned Opcode);
768bool isPMAXUW(unsigned Opcode);
769bool isVPSRAW(unsigned Opcode);
770bool isVPOR(unsigned Opcode);
771bool isVPEXTRB(unsigned Opcode);
772bool isVPEXTRD(unsigned Opcode);
773bool isXGETBV(unsigned Opcode);
774bool isVSUBPD(unsigned Opcode);
775bool isENCLS(unsigned Opcode);
776bool isENCLU(unsigned Opcode);
777bool isENCLV(unsigned Opcode);
778bool isVSUBPH(unsigned Opcode);
779bool isVPEXTRQ(unsigned Opcode);
780bool isVHSUBPD(unsigned Opcode);
781bool isVPEXTRW(unsigned Opcode);
782bool isVSUBPS(unsigned Opcode);
783bool isVGF2P8AFFINEINVQB(unsigned Opcode);
784bool isVMOVLPD(unsigned Opcode);
785bool isVFMADDSD(unsigned Opcode);
786bool isVHSUBPS(unsigned Opcode);
787bool isPSRLDQ(unsigned Opcode);
788bool isVMOVLPS(unsigned Opcode);
789bool isVFMADDSS(unsigned Opcode);
790bool isVRCP28PD(unsigned Opcode);
791bool isFPREM(unsigned Opcode);
792bool isVPMADDWD(unsigned Opcode);
793bool isVCVTSH2SD(unsigned Opcode);
794bool isSERIALIZE(unsigned Opcode);
795bool isV4FMADDPS(unsigned Opcode);
796bool isVRCP28PS(unsigned Opcode);
797bool isVCVTSH2SI(unsigned Opcode);
798bool isRETF(unsigned Opcode);
799bool isVROUNDSD(unsigned Opcode);
800bool isVCVTSH2SS(unsigned Opcode);
801bool isVSCATTERPF1QPD(unsigned Opcode);
802bool isVPCONFLICTD(unsigned Opcode);
803bool isMOVNTI(unsigned Opcode);
804bool isCQO(unsigned Opcode);
805bool isVROUNDSS(unsigned Opcode);
806bool isMOVNTQ(unsigned Opcode);
807bool isVAESENC(unsigned Opcode);
808bool isVSCATTERPF1QPS(unsigned Opcode);
809bool isVPCONFLICTQ(unsigned Opcode);
810bool isFCMOVNB(unsigned Opcode);
811bool isLZCNT(unsigned Opcode);
812bool isFCMOVNE(unsigned Opcode);
813bool isRSM(unsigned Opcode);
814bool isPOPCNT(unsigned Opcode);
815bool isVSUBSD(unsigned Opcode);
816bool isPOPFD(unsigned Opcode);
817bool isVSUBSH(unsigned Opcode);
818bool isVPANDD(unsigned Opcode);
819bool isFCMOVNU(unsigned Opcode);
820bool isVMOVHLPS(unsigned Opcode);
821bool isPOPFQ(unsigned Opcode);
822bool isVPANDN(unsigned Opcode);
823bool isVFMADDSUB213PD(unsigned Opcode);
824bool isVCMPPD(unsigned Opcode);
825bool isVFMADDSUB213PH(unsigned Opcode);
826bool isVSUBSS(unsigned Opcode);
827bool isVPANDQ(unsigned Opcode);
828bool isVCMPPH(unsigned Opcode);
829bool isVP4DPWSSD(unsigned Opcode);
830bool isENDBR32(unsigned Opcode);
831bool isEMMS(unsigned Opcode);
832bool isXCHG(unsigned Opcode);
833bool isVFMADDSUB213PS(unsigned Opcode);
834bool isTDPBUSD(unsigned Opcode);
835bool isRDSEED(unsigned Opcode);
836bool isVCMPPS(unsigned Opcode);
837bool isVRCP28SD(unsigned Opcode);
838bool isRDMSRLIST(unsigned Opcode);
839bool isVRCP28SS(unsigned Opcode);
840bool isV4FMADDSS(unsigned Opcode);
841bool isAESKEYGENASSIST(unsigned Opcode);
842bool isFUCOMPI(unsigned Opcode);
843bool isTDPBF16PS(unsigned Opcode);
844bool isFUCOMPP(unsigned Opcode);
845bool isVFMADDSUB231PD(unsigned Opcode);
846bool isVCVTPH2PSX(unsigned Opcode);
847bool isVFMADDSUB231PH(unsigned Opcode);
848bool isBLENDVPD(unsigned Opcode);
849bool isPSWAPD(unsigned Opcode);
850bool isVMSAVE(unsigned Opcode);
851bool isVFMADDSUB231PS(unsigned Opcode);
852bool isTDPBUUD(unsigned Opcode);
853bool isVBLENDMPD(unsigned Opcode);
854bool isPFACC(unsigned Opcode);
855bool isBLENDVPS(unsigned Opcode);
856bool isVPERM2I128(unsigned Opcode);
857bool isVPCMPGTB(unsigned Opcode);
858bool isLLWPCB(unsigned Opcode);
859bool isVPCMPGTD(unsigned Opcode);
860bool isVFMSUBADD213PD(unsigned Opcode);
861bool isVFMSUBADD213PH(unsigned Opcode);
862bool isVBLENDMPS(unsigned Opcode);
863bool isVCMPSD(unsigned Opcode);
864bool isVCMPSH(unsigned Opcode);
865bool isVPCMPGTQ(unsigned Opcode);
866bool isANDNPD(unsigned Opcode);
867bool isENDBR64(unsigned Opcode);
868bool isVFMSUBADD213PS(unsigned Opcode);
869bool isVPCMPGTW(unsigned Opcode);
870bool isVCMPSS(unsigned Opcode);
871bool isPFADD(unsigned Opcode);
872bool isVMOVLHPS(unsigned Opcode);
873bool isVPMINSD(unsigned Opcode);
874bool isVPMINSB(unsigned Opcode);
875bool isANDNPS(unsigned Opcode);
876bool isPHADDSW(unsigned Opcode);
877bool isVPSLLVD(unsigned Opcode);
878bool isVDIVPD(unsigned Opcode);
879bool isVPMINSQ(unsigned Opcode);
880bool isVDIVPH(unsigned Opcode);
881bool isVPMINSW(unsigned Opcode);
882bool isVFNMSUBPD(unsigned Opcode);
883bool isLWPVAL(unsigned Opcode);
884bool isAESDEC128KL(unsigned Opcode);
885bool isFIADD(unsigned Opcode);
886bool isVPAND(unsigned Opcode);
887bool isMOVSLDUP(unsigned Opcode);
888bool isVPSLLVQ(unsigned Opcode);
889bool isVDIVPS(unsigned Opcode);
890bool isCWD(unsigned Opcode);
891bool isVPSLLVW(unsigned Opcode);
892bool isCWDE(unsigned Opcode);
893bool isVFNMSUBPS(unsigned Opcode);
894bool isVFMSUBADD231PD(unsigned Opcode);
895bool isVPDPBUSD(unsigned Opcode);
896bool isVFMSUBADD231PH(unsigned Opcode);
897bool isPFNACC(unsigned Opcode);
898bool isPFRSQRT(unsigned Opcode);
899bool isVPMACSDD(unsigned Opcode);
900bool isVFMSUBADD231PS(unsigned Opcode);
901bool isFRSTOR(unsigned Opcode);
902bool isVPMINUB(unsigned Opcode);
903bool isVPMINUD(unsigned Opcode);
904bool isKUNPCKBW(unsigned Opcode);
905bool isDPPD(unsigned Opcode);
906bool isVAESIMC(unsigned Opcode);
907bool isPTEST(unsigned Opcode);
908bool isVPMINUQ(unsigned Opcode);
909bool isUCOMISD(unsigned Opcode);
910bool isVPMINUW(unsigned Opcode);
911bool isDPPS(unsigned Opcode);
912bool isFLDLG2(unsigned Opcode);
913bool isVPMOVD2M(unsigned Opcode);
914bool isVMOVAPD(unsigned Opcode);
915bool isVPSRLD(unsigned Opcode);
916bool isTLBSYNC(unsigned Opcode);
917bool isXLATB(unsigned Opcode);
918bool isUCOMISS(unsigned Opcode);
919bool isVPSRLQ(unsigned Opcode);
920bool isPDEP(unsigned Opcode);
921bool isVPDPBUUD(unsigned Opcode);
922bool isVEXTRACTI32X4(unsigned Opcode);
923bool isPFCMPEQ(unsigned Opcode);
924bool isBLSIC(unsigned Opcode);
925bool isVPSRLW(unsigned Opcode);
926bool isVEXTRACTI32X8(unsigned Opcode);
927bool isVDIVSD(unsigned Opcode);
928bool isVFCMADDCPH(unsigned Opcode);
929bool isVMOVAPS(unsigned Opcode);
930bool isFNOP(unsigned Opcode);
931bool isVDIVSH(unsigned Opcode);
932bool isBT(unsigned Opcode);
933bool isVFNMSUBSD(unsigned Opcode);
934bool isVPHMINPOSUW(unsigned Opcode);
935bool isVDIVSS(unsigned Opcode);
936bool isVCVTTSH2SI(unsigned Opcode);
937bool isKUNPCKDQ(unsigned Opcode);
938bool isMULPD(unsigned Opcode);
939bool isBEXTR(unsigned Opcode);
940bool isVFNMSUBSS(unsigned Opcode);
941bool isMPSADBW(unsigned Opcode);
942bool isMULPS(unsigned Opcode);
943bool isSHA256MSG1(unsigned Opcode);
944bool isSHA256MSG2(unsigned Opcode);
945bool isPOPF(unsigned Opcode);
946bool isVERR(unsigned Opcode);
947bool isPFCMPGE(unsigned Opcode);
948bool isVCVTPS2UDQ(unsigned Opcode);
949bool isVERW(unsigned Opcode);
950bool isVFMSUBADDPD(unsigned Opcode);
951bool isPFCMPGT(unsigned Opcode);
952bool isVEXTRACTI128(unsigned Opcode);
953bool isVGF2P8AFFINEQB(unsigned Opcode);
954bool isPSLLD(unsigned Opcode);
955bool isFSUBP(unsigned Opcode);
956bool isFSUBR(unsigned Opcode);
957bool isVBROADCASTF64X2(unsigned Opcode);
958bool isFCHS(unsigned Opcode);
959bool isCMPXCHG8B(unsigned Opcode);
960bool isVBROADCASTF64X4(unsigned Opcode);
961bool isVINSERTI32X4(unsigned Opcode);
962bool isVFMSUBADDPS(unsigned Opcode);
963bool isVBROADCASTF128(unsigned Opcode);
964bool isVPERMIL2PD(unsigned Opcode);
965bool isPSLLQ(unsigned Opcode);
966bool isVINSERTI32X8(unsigned Opcode);
967bool isLLDT(unsigned Opcode);
968bool isMOVMSKPD(unsigned Opcode);
969bool isPSLLW(unsigned Opcode);
970bool isVFCMADDCSH(unsigned Opcode);
971bool isVPERMIL2PS(unsigned Opcode);
972bool isPF2ID(unsigned Opcode);
973bool isVPUNPCKHQDQ(unsigned Opcode);
974bool isMOVMSKPS(unsigned Opcode);
975bool isMULSD(unsigned Opcode);
976bool isPF2IW(unsigned Opcode);
977bool isVBLENDPD(unsigned Opcode);
978bool isCLAC(unsigned Opcode);
979bool isMULSS(unsigned Opcode);
980bool isORPD(unsigned Opcode);
981bool isCDQE(unsigned Opcode);
982bool isVBLENDPS(unsigned Opcode);
983bool isTILESTORED(unsigned Opcode);
984bool isORPS(unsigned Opcode);
985bool isVPINSRB(unsigned Opcode);
986bool isVPINSRD(unsigned Opcode);
987bool isBZHI(unsigned Opcode);
988bool isPUNPCKHBW(unsigned Opcode);
989bool isVCVTPD2UDQ(unsigned Opcode);
990bool isVPINSRQ(unsigned Opcode);
991bool isVPINSRW(unsigned Opcode);
992bool isVPMACSSDQH(unsigned Opcode);
993bool isGETSEC(unsigned Opcode);
994bool isCVTSS2SD(unsigned Opcode);
995bool isVPMACSSDQL(unsigned Opcode);
996bool isANDN(unsigned Opcode);
997bool isCVTSS2SI(unsigned Opcode);
998bool isAESDEC(unsigned Opcode);
999bool isMOVSB(unsigned Opcode);
1000bool isMOVSD(unsigned Opcode);
1001bool isVFNMSUB213PD(unsigned Opcode);
1002bool isVPMOVW2M(unsigned Opcode);
1003bool isVFNMSUB213PH(unsigned Opcode);
1004bool isVPACKSSWB(unsigned Opcode);
1005bool isMOVSQ(unsigned Opcode);
1006bool isMOVSS(unsigned Opcode);
1007bool isVPMULHRSW(unsigned Opcode);
1008bool isVFNMSUB213PS(unsigned Opcode);
1009bool isCMOVCC(unsigned Opcode);
1010bool isMOVSW(unsigned Opcode);
1011bool isMOVSX(unsigned Opcode);
1012bool isVPCOMUD(unsigned Opcode);
1013bool isVPCOMUB(unsigned Opcode);
1014bool isVPDPBSUDS(unsigned Opcode);
1015bool isFLDLN2(unsigned Opcode);
1016bool isPACKUSDW(unsigned Opcode);
1017bool isVPCOMUQ(unsigned Opcode);
1018bool isMONTMUL(unsigned Opcode);
1019bool isPUNPCKHDQ(unsigned Opcode);
1020bool isVPCOMUW(unsigned Opcode);
1021bool isPMULDQ(unsigned Opcode);
1022bool isT1MSKC(unsigned Opcode);
1023bool isIN(unsigned Opcode);
1024bool isVPHADDBD(unsigned Opcode);
1025bool isSAR(unsigned Opcode);
1026bool isVPHADDBQ(unsigned Opcode);
1027bool isVFNMSUB231PD(unsigned Opcode);
1028bool isVPSHLDVD(unsigned Opcode);
1029bool isFSCALE(unsigned Opcode);
1030bool isVFNMSUB231PH(unsigned Opcode);
1031bool isVPHADDBW(unsigned Opcode);
1032bool isSBB(unsigned Opcode);
1033bool isVPSHLDVQ(unsigned Opcode);
1034bool isVFNMSUB231PS(unsigned Opcode);
1035bool isVPDPBUSDS(unsigned Opcode);
1036bool isFCOMPI(unsigned Opcode);
1037bool isRSQRTPS(unsigned Opcode);
1038bool isVSHUFPD(unsigned Opcode);
1039bool isVPSHLDVW(unsigned Opcode);
1040bool isVPADDSB(unsigned Opcode);
1041bool isFCOMPP(unsigned Opcode);
1042bool isDAA(unsigned Opcode);
1043bool isVFNMSUB213SD(unsigned Opcode);
1044bool isVSHUFPS(unsigned Opcode);
1045bool isINVLPGA(unsigned Opcode);
1046bool isINVLPGB(unsigned Opcode);
1047bool isVFNMSUB213SH(unsigned Opcode);
1048bool isDAS(unsigned Opcode);
1049bool isVPADDSW(unsigned Opcode);
1050bool isVFNMSUB213SS(unsigned Opcode);
1051bool isFCOM(unsigned Opcode);
1052bool isKXORB(unsigned Opcode);
1053bool isKXORD(unsigned Opcode);
1054bool isFCOS(unsigned Opcode);
1055bool isVPHADDDQ(unsigned Opcode);
1056bool isCLDEMOTE(unsigned Opcode);
1057bool isKXORQ(unsigned Opcode);
1058bool isKXORW(unsigned Opcode);
1059bool isVDPBF16PS(unsigned Opcode);
1060bool isCLGI(unsigned Opcode);
1061bool isVMREAD(unsigned Opcode);
1062bool isANDPD(unsigned Opcode);
1063bool isVFMSUBPD(unsigned Opcode);
1064bool isVFNMADD213PD(unsigned Opcode);
1065bool isVFNMADD213PH(unsigned Opcode);
1066bool isVFNMSUB231SD(unsigned Opcode);
1067bool isFSQRT(unsigned Opcode);
1068bool isVFNMSUB231SH(unsigned Opcode);
1069bool isPCLMULQDQ(unsigned Opcode);
1070bool isVRCP14PD(unsigned Opcode);
1071bool isANDPS(unsigned Opcode);
1072bool isVFMSUBPS(unsigned Opcode);
1073bool isVFNMADD213PS(unsigned Opcode);
1074bool isPMULHW(unsigned Opcode);
1075bool isVFNMSUB231SS(unsigned Opcode);
1076bool isAESDECWIDE256KL(unsigned Opcode);
1077bool isRSQRTSS(unsigned Opcode);
1078bool isVRCP14PS(unsigned Opcode);
1079bool isVZEROUPPER(unsigned Opcode);
1080bool isVPAVGB(unsigned Opcode);
1081bool isVPMOVSXBD(unsigned Opcode);
1082bool isRDGSBASE(unsigned Opcode);
1083bool isFLDCW(unsigned Opcode);
1084bool isLIDTD(unsigned Opcode);
1085bool isVGATHERPF1DPD(unsigned Opcode);
1086bool isSFENCE(unsigned Opcode);
1087bool isVPMOVSXBQ(unsigned Opcode);
1088bool isVPAVGW(unsigned Opcode);
1089bool isVPMOVSXBW(unsigned Opcode);
1090bool isFCMOVB(unsigned Opcode);
1091bool isVMASKMOVDQU(unsigned Opcode);
1092bool isVGATHERPF1DPS(unsigned Opcode);
1093bool isFCMOVE(unsigned Opcode);
1094bool isVMLOAD(unsigned Opcode);
1095bool isLIDTW(unsigned Opcode);
1096bool isVFNMADD231PD(unsigned Opcode);
1097bool isDEC(unsigned Opcode);
1098bool isVFNMADD231PH(unsigned Opcode);
1099bool isFCMOVU(unsigned Opcode);
1100bool isRSTORSSP(unsigned Opcode);
1101bool isVMAXPD(unsigned Opcode);
1102bool isVMAXPH(unsigned Opcode);
1103bool isPUNPCKLBW(unsigned Opcode);
1104bool isIMUL(unsigned Opcode);
1105bool isTILELOADDT1(unsigned Opcode);
1106bool isVFNMADD231PS(unsigned Opcode);
1107bool isVMAXPS(unsigned Opcode);
1108bool isVPXOR(unsigned Opcode);
1109bool isOR(unsigned Opcode);
1110bool isMOVZX(unsigned Opcode);
1111bool isXSAVES64(unsigned Opcode);
1112bool isVPUNPCKHBW(unsigned Opcode);
1113bool isSYSRET(unsigned Opcode);
1114bool isVFMSUBSD(unsigned Opcode);
1115bool isVFNMADD213SD(unsigned Opcode);
1116bool isVFNMADD213SH(unsigned Opcode);
1117bool isSGDT(unsigned Opcode);
1118bool isVRCP14SD(unsigned Opcode);
1119bool isVPMOVSXDQ(unsigned Opcode);
1120bool isSYSEXIT(unsigned Opcode);
1121bool isPMOVZXBD(unsigned Opcode);
1122bool isVFNMADD213SS(unsigned Opcode);
1123bool isVPMADCSSWD(unsigned Opcode);
1124bool isVPMULUDQ(unsigned Opcode);
1125bool isVFMSUBSS(unsigned Opcode);
1126bool isVPXORD(unsigned Opcode);
1127bool isXSAVEOPT64(unsigned Opcode);
1128bool isXSHA1(unsigned Opcode);
1129bool isVRCP14SS(unsigned Opcode);
1130bool isPMOVZXBQ(unsigned Opcode);
1131bool isSHL(unsigned Opcode);
1132bool isPMOVZXBW(unsigned Opcode);
1133bool isPMULLD(unsigned Opcode);
1134bool isVCVTPS2UQQ(unsigned Opcode);
1135bool isVPBLENDD(unsigned Opcode);
1136bool isVPXORQ(unsigned Opcode);
1137bool isPUNPCKLDQ(unsigned Opcode);
1138bool isSHR(unsigned Opcode);
1139bool isVPUNPCKLQDQ(unsigned Opcode);
1140bool isVCVTPD2DQ(unsigned Opcode);
1141bool isPMULLW(unsigned Opcode);
1142bool isVPBLENDW(unsigned Opcode);
1143bool isAESENCLAST(unsigned Opcode);
1144bool isVPUNPCKHDQ(unsigned Opcode);
1145bool isVFNMADD231SD(unsigned Opcode);
1146bool isVFNMADD231SH(unsigned Opcode);
1147bool isVPMOVSDB(unsigned Opcode);
1148bool isVMAXSD(unsigned Opcode);
1149bool isVMAXSH(unsigned Opcode);
1150bool isLAHF(unsigned Opcode);
1151bool isCVTTPD2DQ(unsigned Opcode);
1152bool isUNPCKHPD(unsigned Opcode);
1153bool isVFNMADD231SS(unsigned Opcode);
1154bool isVMAXSS(unsigned Opcode);
1155bool isVPMACSSDD(unsigned Opcode);
1156bool isVPMOVSDW(unsigned Opcode);
1157bool isPMOVZXDQ(unsigned Opcode);
1158bool isUNPCKHPS(unsigned Opcode);
1159bool isFCOMI(unsigned Opcode);
1160bool isCLFLUSH(unsigned Opcode);
1161bool isTILELOADD(unsigned Opcode);
1162bool isFCOMP(unsigned Opcode);
1163bool isDIV(unsigned Opcode);
1164bool isVPMACSWD(unsigned Opcode);
1165bool isFPREM1(unsigned Opcode);
1166bool isVSCATTERQPD(unsigned Opcode);
1167bool isFYL2X(unsigned Opcode);
1168bool isVPMACSWW(unsigned Opcode);
1169bool isPFMAX(unsigned Opcode);
1170bool isVPSHUFB(unsigned Opcode);
1171bool isVCVTPD2UQQ(unsigned Opcode);
1172bool isVPSHUFD(unsigned Opcode);
1173bool isVSCATTERQPS(unsigned Opcode);
1174bool isGF2P8AFFINEINVQB(unsigned Opcode);
1175bool isFEMMS(unsigned Opcode);
1176bool isKUNPCKWD(unsigned Opcode);
1177bool isVPCLMULQDQ(unsigned Opcode);
1178bool isKORB(unsigned Opcode);
1179bool isVINSERTPS(unsigned Opcode);
1180bool isKORD(unsigned Opcode);
1181bool isVMFUNC(unsigned Opcode);
1182bool isCPUID(unsigned Opcode);
1183bool isVSCATTERPF0QPD(unsigned Opcode);
1184bool isOUT(unsigned Opcode);
1185bool isKORQ(unsigned Opcode);
1186bool isKORW(unsigned Opcode);
1187bool isVSCATTERPF0QPS(unsigned Opcode);
1188bool isPHSUBSW(unsigned Opcode);
1189bool isPFSUBR(unsigned Opcode);
1190bool isVCVTPH2UDQ(unsigned Opcode);
1191bool isVBROADCASTF32X2(unsigned Opcode);
1192bool isVBROADCASTF32X4(unsigned Opcode);
1193bool isSHA256RNDS2(unsigned Opcode);
1194bool isVBROADCASTF32X8(unsigned Opcode);
1195bool isVPERMB(unsigned Opcode);
1196bool isVPUNPCKLBW(unsigned Opcode);
1197bool isVPERMD(unsigned Opcode);
1198bool isXCRYPTECB(unsigned Opcode);
1199bool isVPERMQ(unsigned Opcode);
1200bool isEXTRACTPS(unsigned Opcode);
1201bool isVPERMW(unsigned Opcode);
1202bool isHADDPD(unsigned Opcode);
1203bool isFXSAVE(unsigned Opcode);
1204bool isVRCPPH(unsigned Opcode);
1205bool isHADDPS(unsigned Opcode);
1206bool isVPSADBW(unsigned Opcode);
1207bool isRDRAND(unsigned Opcode);
1208bool isVRCPPS(unsigned Opcode);
1209bool isVXORPD(unsigned Opcode);
1210bool isFFREE(unsigned Opcode);
1211bool isPCMPEQB(unsigned Opcode);
1212bool isPCMPEQD(unsigned Opcode);
1213bool isVPUNPCKLDQ(unsigned Opcode);
1214bool isVTESTPD(unsigned Opcode);
1215bool isVXORPS(unsigned Opcode);
1216bool isTZCNT(unsigned Opcode);
1217bool isCLTS(unsigned Opcode);
1218bool isPCMPEQQ(unsigned Opcode);
1219bool isVFPCLASSPD(unsigned Opcode);
1220bool isVFPCLASSPH(unsigned Opcode);
1221bool isVTESTPS(unsigned Opcode);
1222bool isPCMPEQW(unsigned Opcode);
1223bool isUNPCKLPD(unsigned Opcode);
1224bool isVMOVDQA32(unsigned Opcode);
1225bool isVFPCLASSPS(unsigned Opcode);
1226bool isVPMOVMSKB(unsigned Opcode);
1227bool isFDECSTP(unsigned Opcode);
1228bool isCLUI(unsigned Opcode);
1229bool isFLDPI(unsigned Opcode);
1230bool isUNPCKLPS(unsigned Opcode);
1231bool isVCVTTPD2DQ(unsigned Opcode);
1232bool isPAVGUSB(unsigned Opcode);
1233bool isCALL(unsigned Opcode);
1234bool isFLDENV(unsigned Opcode);
1235bool isPACKUSWB(unsigned Opcode);
1236bool isVPHADDSW(unsigned Opcode);
1237bool isLAR(unsigned Opcode);
1238bool isCLFLUSHOPT(unsigned Opcode);
1239bool isVMMCALL(unsigned Opcode);
1240bool isARPL(unsigned Opcode);
1241bool isXABORT(unsigned Opcode);
1242bool isPUNPCKHWD(unsigned Opcode);
1243bool isVRCPSH(unsigned Opcode);
1244bool isLDDQU(unsigned Opcode);
1245bool isPFMIN(unsigned Opcode);
1246bool isSYSRETQ(unsigned Opcode);
1247bool isVRCPSS(unsigned Opcode);
1248bool isCLWB(unsigned Opcode);
1249bool isSTC(unsigned Opcode);
1250bool isSTD(unsigned Opcode);
1251bool isVMOVDQU8(unsigned Opcode);
1252bool isSTI(unsigned Opcode);
1253bool isSTR(unsigned Opcode);
1254bool isVFPCLASSSD(unsigned Opcode);
1255bool isLDMXCSR(unsigned Opcode);
1256bool isVFPCLASSSH(unsigned Opcode);
1257bool isVCVTPD2PH(unsigned Opcode);
1258bool isVCVTPH2DQ(unsigned Opcode);
1259bool isVFPCLASSSS(unsigned Opcode);
1260bool isVMOVDQA64(unsigned Opcode);
1261bool isSUB(unsigned Opcode);
1262bool isVUCOMISD(unsigned Opcode);
1263bool isVCVTPD2PS(unsigned Opcode);
1264bool isLEAVE(unsigned Opcode);
1265bool isOUTSB(unsigned Opcode);
1266bool isOUTSD(unsigned Opcode);
1267bool isVUCOMISH(unsigned Opcode);
1268bool isEXTRQ(unsigned Opcode);
1269bool isVUCOMISS(unsigned Opcode);
1270bool isCVTTPD2PI(unsigned Opcode);
1271bool isOUTSW(unsigned Opcode);
1272bool isLDS(unsigned Opcode);
1273bool isPSHUFHW(unsigned Opcode);
1274bool isPHSUBD(unsigned Opcode);
1275bool isHLT(unsigned Opcode);
1276bool isVCVTPD2QQ(unsigned Opcode);
1277bool isLIDT(unsigned Opcode);
1278bool isVPTERNLOGD(unsigned Opcode);
1279bool isLEA(unsigned Opcode);
1280bool isVPHADDWD(unsigned Opcode);
1281bool isPREFETCHNTA(unsigned Opcode);
1282bool isVPTERNLOGQ(unsigned Opcode);
1283bool isKSHIFTLB(unsigned Opcode);
1284bool isKSHIFTLD(unsigned Opcode);
1285bool isPHSUBW(unsigned Opcode);
1286bool isVPMOVSQB(unsigned Opcode);
1287bool isVPHADDWQ(unsigned Opcode);
1288bool isVCVTTSS2USI(unsigned Opcode);
1289bool isVPMOVSQD(unsigned Opcode);
1290bool isLES(unsigned Opcode);
1291bool isVMPSADBW(unsigned Opcode);
1292bool isKSHIFTLQ(unsigned Opcode);
1293bool isADDSUBPD(unsigned Opcode);
1294bool isKSHIFTLW(unsigned Opcode);
1295bool isXSAVE64(unsigned Opcode);
1296bool isVPMOVSQW(unsigned Opcode);
1297bool isADDSUBPS(unsigned Opcode);
1298bool isENQCMD(unsigned Opcode);
1299bool isVCVTTPH2W(unsigned Opcode);
1300bool isVMRUN(unsigned Opcode);
1301bool isWRFSBASE(unsigned Opcode);
1302bool isCOMISD(unsigned Opcode);
1303bool isLFS(unsigned Opcode);
1304bool isSTOSB(unsigned Opcode);
1305bool isSTOSD(unsigned Opcode);
1306bool isCOMISS(unsigned Opcode);
1307bool isVZEROALL(unsigned Opcode);
1308bool isVFMADDSUBPD(unsigned Opcode);
1309bool isVEXTRACTPS(unsigned Opcode);
1310bool isKADDB(unsigned Opcode);
1311bool isKADDD(unsigned Opcode);
1312bool isXTEST(unsigned Opcode);
1313bool isFISTTP(unsigned Opcode);
1314bool isSTOSQ(unsigned Opcode);
1315bool isJCXZ(unsigned Opcode);
1316bool isSTOSW(unsigned Opcode);
1317bool isVFMADDSUBPS(unsigned Opcode);
1318bool isVPSHAB(unsigned Opcode);
1319bool isKADDQ(unsigned Opcode);
1320bool isLGS(unsigned Opcode);
1321bool isVPMACSDQH(unsigned Opcode);
1322bool isMOVDQA(unsigned Opcode);
1323bool isVPSHAD(unsigned Opcode);
1324bool isKADDW(unsigned Opcode);
1325bool isPSMASH(unsigned Opcode);
1326bool isPBLENDVB(unsigned Opcode);
1327bool isVPMACSDQL(unsigned Opcode);
1328bool isVPHSUBBW(unsigned Opcode);
1329bool isVPSHAQ(unsigned Opcode);
1330bool isVSQRTPD(unsigned Opcode);
1331bool isCLRSSBSY(unsigned Opcode);
1332bool isMINPD(unsigned Opcode);
1333bool isVPSHAW(unsigned Opcode);
1334bool isVSQRTPH(unsigned Opcode);
1335bool isMOVDQU(unsigned Opcode);
1336bool isVSQRTPS(unsigned Opcode);
1337bool isVPSUBSB(unsigned Opcode);
1338bool isMULX(unsigned Opcode);
1339bool isMINPS(unsigned Opcode);
1340bool isPSHUFLW(unsigned Opcode);
1341bool isVEXTRACTF64X2(unsigned Opcode);
1342bool isVEXTRACTF64X4(unsigned Opcode);
1343bool isVCVTTSD2USI(unsigned Opcode);
1344bool isINCSSPD(unsigned Opcode);
1345bool isVPSIGNB(unsigned Opcode);
1346bool isVPSUBSW(unsigned Opcode);
1347bool isVPSIGND(unsigned Opcode);
1348bool isXSAVEOPT(unsigned Opcode);
1349bool isVPMOVSXWD(unsigned Opcode);
1350bool isINCSSPQ(unsigned Opcode);
1351bool isGF2P8AFFINEQB(unsigned Opcode);
1352bool isVPMOVSXWQ(unsigned Opcode);
1353bool isVPHSUBDQ(unsigned Opcode);
1354bool isVPSIGNW(unsigned Opcode);
1355bool isSGDTD(unsigned Opcode);
1356bool isPUNPCKLWD(unsigned Opcode);
1357bool isVPPERM(unsigned Opcode);
1358bool isAAA(unsigned Opcode);
1359bool isPAND(unsigned Opcode);
1360bool isVCVTPH2UQQ(unsigned Opcode);
1361bool isAAD(unsigned Opcode);
1362bool isSGDTW(unsigned Opcode);
1363bool isVPUNPCKHWD(unsigned Opcode);
1364bool isAAM(unsigned Opcode);
1365bool isVCVTNEOPH2PS(unsigned Opcode);
1366bool isAAS(unsigned Opcode);
1367bool isVSQRTSD(unsigned Opcode);
1368bool isBLCI(unsigned Opcode);
1369bool isMINSD(unsigned Opcode);
1370bool isVPSHUFBITQMB(unsigned Opcode);
1371bool isKSHIFTRB(unsigned Opcode);
1372bool isUMONITOR(unsigned Opcode);
1373bool isKSHIFTRD(unsigned Opcode);
1374bool isFNCLEX(unsigned Opcode);
1375bool isVSQRTSH(unsigned Opcode);
1376bool isBLCS(unsigned Opcode);
1377bool isVINSERTF64X2(unsigned Opcode);
1378bool isVSQRTSS(unsigned Opcode);
1379bool isVINSERTF64X4(unsigned Opcode);
1380bool isMINSS(unsigned Opcode);
1381bool isVPBROADCASTMB2Q(unsigned Opcode);
1382bool isKSHIFTRQ(unsigned Opcode);
1383bool isVMOVSHDUP(unsigned Opcode);
1384bool isVPMOVSWB(unsigned Opcode);
1385bool isPMOVZXWD(unsigned Opcode);
1386bool isFSIN(unsigned Opcode);
1387bool isPSLLDQ(unsigned Opcode);
1388bool isKSHIFTRW(unsigned Opcode);
1389bool isVPADDD(unsigned Opcode);
1390bool isVPADDB(unsigned Opcode);
1391bool isVPMACSSWD(unsigned Opcode);
1392bool isPMOVZXWQ(unsigned Opcode);
1393bool isVPADDQ(unsigned Opcode);
1394bool isVPADDW(unsigned Opcode);
1395bool isVRSQRTPH(unsigned Opcode);
1396bool isVPMACSSWW(unsigned Opcode);
1397bool isVRSQRTPS(unsigned Opcode);
1398bool isVCVTTPH2DQ(unsigned Opcode);
1399bool isWRMSR(unsigned Opcode);
1400bool isXSETBV(unsigned Opcode);
1401bool isMOVSXD(unsigned Opcode);
1402bool isADC(unsigned Opcode);
1403bool isADD(unsigned Opcode);
1404bool isFDIV(unsigned Opcode);
1405bool isAESDEC256KL(unsigned Opcode);
1406bool isVPCMPUB(unsigned Opcode);
1407bool isVCVTTPD2QQ(unsigned Opcode);
1408bool isVPCMPUD(unsigned Opcode);
1409bool isPFMUL(unsigned Opcode);
1410bool isPREFETCHW(unsigned Opcode);
1411bool isVPCMPUQ(unsigned Opcode);
1412bool isKORTESTB(unsigned Opcode);
1413bool isMOVHPD(unsigned Opcode);
1414bool isKORTESTD(unsigned Opcode);
1415bool isCVTSI2SD(unsigned Opcode);
1416bool isFSUBRP(unsigned Opcode);
1417bool isIRET(unsigned Opcode);
1418bool isPTWRITE(unsigned Opcode);
1419bool isVPCMPUW(unsigned Opcode);
1420bool isKORTESTQ(unsigned Opcode);
1421bool isMOVHPS(unsigned Opcode);
1422bool isFIMUL(unsigned Opcode);
1423bool isCVTSI2SS(unsigned Opcode);
1424bool isVCVTPH2PD(unsigned Opcode);
1425bool isKORTESTW(unsigned Opcode);
1426bool isPADDUSB(unsigned Opcode);
1427bool isVSHUFI64X2(unsigned Opcode);
1428bool isVRSQRTSH(unsigned Opcode);
1429bool isVMWRITE(unsigned Opcode);
1430bool isTILERELEASE(unsigned Opcode);
1431bool isVCVTPH2PS(unsigned Opcode);
1432bool isVMOVUPD(unsigned Opcode);
1433bool isPADDUSW(unsigned Opcode);
1434bool isVRSQRTSS(unsigned Opcode);
1435bool isVPCMOV(unsigned Opcode);
1436bool isVCVTUSI2SD(unsigned Opcode);
1437bool isVMOVUPS(unsigned Opcode);
1438bool isVCVTUSI2SH(unsigned Opcode);
1439bool isVPCMPB(unsigned Opcode);
1440bool isVPGATHERDD(unsigned Opcode);
1441bool isVPCMPD(unsigned Opcode);
1442bool isVCVTUSI2SS(unsigned Opcode);
1443bool isLFENCE(unsigned Opcode);
1444bool isVCVTPH2QQ(unsigned Opcode);
1445bool isVGATHERPF0DPD(unsigned Opcode);
1446bool isSEAMRET(unsigned Opcode);
1447bool isPI2FD(unsigned Opcode);
1448bool isVPGATHERDQ(unsigned Opcode);
1449bool isPCMPESTRI(unsigned Opcode);
1450bool isVPCMPQ(unsigned Opcode);
1451bool isPCMPESTRM(unsigned Opcode);
1452bool isVPCMPW(unsigned Opcode);
1453bool isVGATHERPF0DPS(unsigned Opcode);
1454bool isVPMOVUSDB(unsigned Opcode);
1455bool isPI2FW(unsigned Opcode);
1456bool isSYSEXITQ(unsigned Opcode);
1457bool isCVTPS2DQ(unsigned Opcode);
1458bool isRDPKRU(unsigned Opcode);
1459bool isVPMOVUSDW(unsigned Opcode);
1460bool isPSUBB(unsigned Opcode);
1461bool isPSUBD(unsigned Opcode);
1462bool isVPSHRDD(unsigned Opcode);
1463bool isRETFQ(unsigned Opcode);
1464bool isVPERMT2PD(unsigned Opcode);
1465bool isMOVABS(unsigned Opcode);
1466bool isVPSHRDQ(unsigned Opcode);
1467bool isPSUBQ(unsigned Opcode);
1468bool isVPSHRDW(unsigned Opcode);
1469bool isVPSHLB(unsigned Opcode);
1470bool isPSUBW(unsigned Opcode);
1471bool isVPSHLD(unsigned Opcode);
1472bool isVPERMT2PS(unsigned Opcode);
1473bool isVPUNPCKLWD(unsigned Opcode);
1474bool isVPSHLQ(unsigned Opcode);
1475bool isVPSHLW(unsigned Opcode);
1476bool isLSL(unsigned Opcode);
1477bool isVBROADCASTI128(unsigned Opcode);
1478bool isLSS(unsigned Opcode);
1479bool isVPHADDD(unsigned Opcode);
1480bool isADDPD(unsigned Opcode);
1481bool isVMASKMOVPD(unsigned Opcode);
1482bool isADDPS(unsigned Opcode);
1483bool isINSB(unsigned Opcode);
1484bool isINSD(unsigned Opcode);
1485bool isVPHADDW(unsigned Opcode);
1486bool isLTR(unsigned Opcode);
1487bool isVMASKMOVPS(unsigned Opcode);
1488bool isVCVTPH2UW(unsigned Opcode);
1489bool isINT3(unsigned Opcode);
1490bool isKNOTB(unsigned Opcode);
1491bool isKNOTD(unsigned Opcode);
1492bool isINSW(unsigned Opcode);
1493bool isVBLENDVPD(unsigned Opcode);
1494bool isBLSFILL(unsigned Opcode);
1495bool isMONITOR(unsigned Opcode);
1496bool isKNOTQ(unsigned Opcode);
1497bool isCMPXCHG16B(unsigned Opcode);
1498bool isKNOTW(unsigned Opcode);
1499bool isPEXTRB(unsigned Opcode);
1500bool isVPRORVD(unsigned Opcode);
1501bool isPEXTRD(unsigned Opcode);
1502bool isVAESENCLAST(unsigned Opcode);
1503bool isINTO(unsigned Opcode);
1504bool isVBLENDVPS(unsigned Opcode);
1505bool isVPRORVQ(unsigned Opcode);
1506bool isPEXTRQ(unsigned Opcode);
1507bool isHSUBPD(unsigned Opcode);
1508bool isPEXTRW(unsigned Opcode);
1509bool isFDIVRP(unsigned Opcode);
1510bool isSCASB(unsigned Opcode);
1511bool isF2XM1(unsigned Opcode);
1512bool isSCASD(unsigned Opcode);
1513bool isFISUBR(unsigned Opcode);
1514bool isMOVLPD(unsigned Opcode);
1515bool isHSUBPS(unsigned Opcode);
1516bool isSCASQ(unsigned Opcode);
1517bool isFSTP(unsigned Opcode);
1518bool isVDBPSADBW(unsigned Opcode);
1519bool isADDSD(unsigned Opcode);
1520bool isMOVLPS(unsigned Opcode);
1521bool isSCASW(unsigned Opcode);
1522bool isVCVTW2PH(unsigned Opcode);
1523bool isVPTEST(unsigned Opcode);
1524bool isFLD1(unsigned Opcode);
1525bool isWBINVD(unsigned Opcode);
1526bool isADDSS(unsigned Opcode);
1527bool isPOP(unsigned Opcode);
1528bool isINVD(unsigned Opcode);
1529bool isPOR(unsigned Opcode);
1530bool isAND(unsigned Opcode);
1531bool isFYL2XP1(unsigned Opcode);
1532bool isFSUB(unsigned Opcode);
1533bool isENTER(unsigned Opcode);
1534bool isVMOVSLDUP(unsigned Opcode);
1535bool isADCX(unsigned Opcode);
1536bool isXADD(unsigned Opcode);
1537bool isAESENC(unsigned Opcode);
1538bool isFLDZ(unsigned Opcode);
1539bool isXRSTORS64(unsigned Opcode);
1540bool isVCVTTSH2USI(unsigned Opcode);
1541bool isVMULPD(unsigned Opcode);
1542bool isFDIVP(unsigned Opcode);
1543bool isVGETMANTPD(unsigned Opcode);
1544bool isFDIVR(unsigned Opcode);
1545bool isVPMOVM2D(unsigned Opcode);
1546bool isVMULPH(unsigned Opcode);
1547bool isVGETMANTPH(unsigned Opcode);
1548bool isVPMOVM2B(unsigned Opcode);
1549bool isAOR(unsigned Opcode);
1550bool isVPHSUBSW(unsigned Opcode);
1551bool isVMULPS(unsigned Opcode);
1552bool isVPMOVM2Q(unsigned Opcode);
1553bool isMOVNTDQ(unsigned Opcode);
1554bool isVGETMANTPS(unsigned Opcode);
1555bool isVPCMPESTRI(unsigned Opcode);
1556bool isVPMOVM2W(unsigned Opcode);
1557bool isVPCMPESTRM(unsigned Opcode);
1558bool isSYSENTER(unsigned Opcode);
1559bool isVPERMPD(unsigned Opcode);
1560bool isVCVTTPH2QQ(unsigned Opcode);
1561bool isPUSHF(unsigned Opcode);
1562bool isPXOR(unsigned Opcode);
1563bool isCMPXCHG(unsigned Opcode);
1564bool isVPERMPS(unsigned Opcode);
1565bool isVMRESUME(unsigned Opcode);
1566bool isVPSLLD(unsigned Opcode);
1567bool isVPSLLQ(unsigned Opcode);
1568bool isVEXTRACTF32X4(unsigned Opcode);
1569bool isVPSLLW(unsigned Opcode);
1570bool isBLSI(unsigned Opcode);
1571bool isVEXTRACTF32X8(unsigned Opcode);
1572bool isBLSR(unsigned Opcode);
1573bool isVMULSD(unsigned Opcode);
1574bool isVGETMANTSD(unsigned Opcode);
1575bool isVPCMPEQB(unsigned Opcode);
1576bool isVMULSH(unsigned Opcode);
1577bool isVPCMPEQD(unsigned Opcode);
1578bool isVGETMANTSH(unsigned Opcode);
1579bool isLMSW(unsigned Opcode);
1580bool isFNSTENV(unsigned Opcode);
1581bool isVMULSS(unsigned Opcode);
1582bool isVGETMANTSS(unsigned Opcode);
1583bool isVPCMPEQQ(unsigned Opcode);
1584bool isVPCMPEQW(unsigned Opcode);
1585bool isTDPBSSD(unsigned Opcode);
1586bool isVPHSUBWD(unsigned Opcode);
1587bool isUMWAIT(unsigned Opcode);
1588bool isBSWAP(unsigned Opcode);
1589bool isVCVTUQQ2PD(unsigned Opcode);
1590bool isPEXT(unsigned Opcode);
1591bool isVCVTUQQ2PH(unsigned Opcode);
1592bool isVMOVMSKPD(unsigned Opcode);
1593bool isLOADIWKEY(unsigned Opcode);
1594bool isPMINSB(unsigned Opcode);
1595bool isPMINSD(unsigned Opcode);
1596bool isVCVTUQQ2PS(unsigned Opcode);
1597bool isSTMXCSR(unsigned Opcode);
1598bool isCVTPS2PD(unsigned Opcode);
1599bool isVMOVMSKPS(unsigned Opcode);
1600bool isVPROLD(unsigned Opcode);
1601bool isFPTAN(unsigned Opcode);
1602bool isCVTPS2PI(unsigned Opcode);
1603bool isVMXOFF(unsigned Opcode);
1604bool isXRSTOR64(unsigned Opcode);
1605bool isPMINSW(unsigned Opcode);
1606bool isVMOVSD(unsigned Opcode);
1607bool isVPGATHERQD(unsigned Opcode);
1608bool isVINSERTF32X4(unsigned Opcode);
1609bool isVMOVSH(unsigned Opcode);
1610bool isVPGATHERQQ(unsigned Opcode);
1611bool isVPROLQ(unsigned Opcode);
1612bool isVINSERTF32X8(unsigned Opcode);
1613bool isXSAVE(unsigned Opcode);
1614bool isTDPFP16PS(unsigned Opcode);
1615bool isVCVTTPH2UW(unsigned Opcode);
1616bool isVMOVSS(unsigned Opcode);
1617bool isRDTSCP(unsigned Opcode);
1618bool isVPMOVUSQB(unsigned Opcode);
1619bool isVPMOVUSQD(unsigned Opcode);
1620bool isTDPBSUD(unsigned Opcode);
1621bool isBLCMSK(unsigned Opcode);
1622bool isVPMOVUSQW(unsigned Opcode);
1623bool isVPMADCSWD(unsigned Opcode);
1624bool isVGATHERDPD(unsigned Opcode);
1625bool isSHLD(unsigned Opcode);
1626bool isPMINUB(unsigned Opcode);
1627bool isPMINUD(unsigned Opcode);
1628bool isAESIMC(unsigned Opcode);
1629bool isCVTSD2SI(unsigned Opcode);
1630bool isVLDMXCSR(unsigned Opcode);
1631bool isVCVTSS2SD(unsigned Opcode);
1632bool isVCVTSS2SH(unsigned Opcode);
1633bool isSLDT(unsigned Opcode);
1634bool isVCVTSS2SI(unsigned Opcode);
1635bool isVGATHERDPS(unsigned Opcode);
1636bool isFABS(unsigned Opcode);
1637bool isCVTSD2SS(unsigned Opcode);
1638bool isSHLX(unsigned Opcode);
1639bool isMONITORX(unsigned Opcode);
1640bool isPMINUW(unsigned Opcode);
1641bool isVPMAXSB(unsigned Opcode);
1642bool isVPMAXSD(unsigned Opcode);
1643bool isMOVAPD(unsigned Opcode);
1644bool isENQCMDS(unsigned Opcode);
1645bool isVMOVD(unsigned Opcode);
1646bool isVPMAXSQ(unsigned Opcode);
1647bool isCVTTSS2SI(unsigned Opcode);
1648bool isVPMAXSW(unsigned Opcode);
1649bool isMOVAPS(unsigned Opcode);
1650bool isVPACKUSDW(unsigned Opcode);
1651bool isVFIXUPIMMPD(unsigned Opcode);
1652bool isVMOVQ(unsigned Opcode);
1653bool isVPSHUFHW(unsigned Opcode);
1654bool isPCMPISTRI(unsigned Opcode);
1655bool isVMOVW(unsigned Opcode);
1656#endif // GET_X86_MNEMONIC_TABLES_H
1657
1658#ifdef GET_X86_MNEMONIC_TABLES_CPP
1659#undef GET_X86_MNEMONIC_TABLES_CPP
1660
1661bool isPCMPISTRM(unsigned Opcode) {
1662	switch (Opcode) {
1663	case PCMPISTRMrm:
1664	case PCMPISTRMrr:
1665		return true;
1666	}
1667	return false;
1668}
1669
1670bool isVALIGND(unsigned Opcode) {
1671	switch (Opcode) {
1672	case VALIGNDZ128rmbi:
1673	case VALIGNDZ128rmbik:
1674	case VALIGNDZ128rmbikz:
1675	case VALIGNDZ128rmi:
1676	case VALIGNDZ128rmik:
1677	case VALIGNDZ128rmikz:
1678	case VALIGNDZ128rri:
1679	case VALIGNDZ128rrik:
1680	case VALIGNDZ128rrikz:
1681	case VALIGNDZ256rmbi:
1682	case VALIGNDZ256rmbik:
1683	case VALIGNDZ256rmbikz:
1684	case VALIGNDZ256rmi:
1685	case VALIGNDZ256rmik:
1686	case VALIGNDZ256rmikz:
1687	case VALIGNDZ256rri:
1688	case VALIGNDZ256rrik:
1689	case VALIGNDZ256rrikz:
1690	case VALIGNDZrmbi:
1691	case VALIGNDZrmbik:
1692	case VALIGNDZrmbikz:
1693	case VALIGNDZrmi:
1694	case VALIGNDZrmik:
1695	case VALIGNDZrmikz:
1696	case VALIGNDZrri:
1697	case VALIGNDZrrik:
1698	case VALIGNDZrrikz:
1699		return true;
1700	}
1701	return false;
1702}
1703
1704bool isVFMULCPH(unsigned Opcode) {
1705	switch (Opcode) {
1706	case VFMULCPHZ128rm:
1707	case VFMULCPHZ128rmb:
1708	case VFMULCPHZ128rmbk:
1709	case VFMULCPHZ128rmbkz:
1710	case VFMULCPHZ128rmk:
1711	case VFMULCPHZ128rmkz:
1712	case VFMULCPHZ128rr:
1713	case VFMULCPHZ128rrk:
1714	case VFMULCPHZ128rrkz:
1715	case VFMULCPHZ256rm:
1716	case VFMULCPHZ256rmb:
1717	case VFMULCPHZ256rmbk:
1718	case VFMULCPHZ256rmbkz:
1719	case VFMULCPHZ256rmk:
1720	case VFMULCPHZ256rmkz:
1721	case VFMULCPHZ256rr:
1722	case VFMULCPHZ256rrk:
1723	case VFMULCPHZ256rrkz:
1724	case VFMULCPHZrm:
1725	case VFMULCPHZrmb:
1726	case VFMULCPHZrmbk:
1727	case VFMULCPHZrmbkz:
1728	case VFMULCPHZrmk:
1729	case VFMULCPHZrmkz:
1730	case VFMULCPHZrr:
1731	case VFMULCPHZrrb:
1732	case VFMULCPHZrrbk:
1733	case VFMULCPHZrrbkz:
1734	case VFMULCPHZrrk:
1735	case VFMULCPHZrrkz:
1736		return true;
1737	}
1738	return false;
1739}
1740
1741bool isVPDPBSSD(unsigned Opcode) {
1742	switch (Opcode) {
1743	case VPDPBSSDYrm:
1744	case VPDPBSSDYrr:
1745	case VPDPBSSDrm:
1746	case VPDPBSSDrr:
1747		return true;
1748	}
1749	return false;
1750}
1751
1752bool isVFIXUPIMMPS(unsigned Opcode) {
1753	switch (Opcode) {
1754	case VFIXUPIMMPSZ128rmbi:
1755	case VFIXUPIMMPSZ128rmbik:
1756	case VFIXUPIMMPSZ128rmbikz:
1757	case VFIXUPIMMPSZ128rmi:
1758	case VFIXUPIMMPSZ128rmik:
1759	case VFIXUPIMMPSZ128rmikz:
1760	case VFIXUPIMMPSZ128rri:
1761	case VFIXUPIMMPSZ128rrik:
1762	case VFIXUPIMMPSZ128rrikz:
1763	case VFIXUPIMMPSZ256rmbi:
1764	case VFIXUPIMMPSZ256rmbik:
1765	case VFIXUPIMMPSZ256rmbikz:
1766	case VFIXUPIMMPSZ256rmi:
1767	case VFIXUPIMMPSZ256rmik:
1768	case VFIXUPIMMPSZ256rmikz:
1769	case VFIXUPIMMPSZ256rri:
1770	case VFIXUPIMMPSZ256rrik:
1771	case VFIXUPIMMPSZ256rrikz:
1772	case VFIXUPIMMPSZrmbi:
1773	case VFIXUPIMMPSZrmbik:
1774	case VFIXUPIMMPSZrmbikz:
1775	case VFIXUPIMMPSZrmi:
1776	case VFIXUPIMMPSZrmik:
1777	case VFIXUPIMMPSZrmikz:
1778	case VFIXUPIMMPSZrri:
1779	case VFIXUPIMMPSZrrib:
1780	case VFIXUPIMMPSZrribk:
1781	case VFIXUPIMMPSZrribkz:
1782	case VFIXUPIMMPSZrrik:
1783	case VFIXUPIMMPSZrrikz:
1784		return true;
1785	}
1786	return false;
1787}
1788
1789bool isVPMOVQ2M(unsigned Opcode) {
1790	switch (Opcode) {
1791	case VPMOVQ2MZ128rr:
1792	case VPMOVQ2MZ256rr:
1793	case VPMOVQ2MZrr:
1794		return true;
1795	}
1796	return false;
1797}
1798
1799bool isLDTILECFG(unsigned Opcode) {
1800	return Opcode == LDTILECFG;
1801}
1802
1803bool isFADD(unsigned Opcode) {
1804	switch (Opcode) {
1805	case ADD_F32m:
1806	case ADD_F64m:
1807	case ADD_FST0r:
1808	case ADD_FrST0:
1809		return true;
1810	}
1811	return false;
1812}
1813
1814bool isVALIGNQ(unsigned Opcode) {
1815	switch (Opcode) {
1816	case VALIGNQZ128rmbi:
1817	case VALIGNQZ128rmbik:
1818	case VALIGNQZ128rmbikz:
1819	case VALIGNQZ128rmi:
1820	case VALIGNQZ128rmik:
1821	case VALIGNQZ128rmikz:
1822	case VALIGNQZ128rri:
1823	case VALIGNQZ128rrik:
1824	case VALIGNQZ128rrikz:
1825	case VALIGNQZ256rmbi:
1826	case VALIGNQZ256rmbik:
1827	case VALIGNQZ256rmbikz:
1828	case VALIGNQZ256rmi:
1829	case VALIGNQZ256rmik:
1830	case VALIGNQZ256rmikz:
1831	case VALIGNQZ256rri:
1832	case VALIGNQZ256rrik:
1833	case VALIGNQZ256rrikz:
1834	case VALIGNQZrmbi:
1835	case VALIGNQZrmbik:
1836	case VALIGNQZrmbikz:
1837	case VALIGNQZrmi:
1838	case VALIGNQZrmik:
1839	case VALIGNQZrmikz:
1840	case VALIGNQZrri:
1841	case VALIGNQZrrik:
1842	case VALIGNQZrrikz:
1843		return true;
1844	}
1845	return false;
1846}
1847
1848bool isAESENC128KL(unsigned Opcode) {
1849	return Opcode == AESENC128KL;
1850}
1851
1852bool isVPMAXUB(unsigned Opcode) {
1853	switch (Opcode) {
1854	case VPMAXUBYrm:
1855	case VPMAXUBYrr:
1856	case VPMAXUBZ128rm:
1857	case VPMAXUBZ128rmk:
1858	case VPMAXUBZ128rmkz:
1859	case VPMAXUBZ128rr:
1860	case VPMAXUBZ128rrk:
1861	case VPMAXUBZ128rrkz:
1862	case VPMAXUBZ256rm:
1863	case VPMAXUBZ256rmk:
1864	case VPMAXUBZ256rmkz:
1865	case VPMAXUBZ256rr:
1866	case VPMAXUBZ256rrk:
1867	case VPMAXUBZ256rrkz:
1868	case VPMAXUBZrm:
1869	case VPMAXUBZrmk:
1870	case VPMAXUBZrmkz:
1871	case VPMAXUBZrr:
1872	case VPMAXUBZrrk:
1873	case VPMAXUBZrrkz:
1874	case VPMAXUBrm:
1875	case VPMAXUBrr:
1876		return true;
1877	}
1878	return false;
1879}
1880
1881bool isFMULP(unsigned Opcode) {
1882	return Opcode == MUL_FPrST0;
1883}
1884
1885bool isVPMAXUD(unsigned Opcode) {
1886	switch (Opcode) {
1887	case VPMAXUDYrm:
1888	case VPMAXUDYrr:
1889	case VPMAXUDZ128rm:
1890	case VPMAXUDZ128rmb:
1891	case VPMAXUDZ128rmbk:
1892	case VPMAXUDZ128rmbkz:
1893	case VPMAXUDZ128rmk:
1894	case VPMAXUDZ128rmkz:
1895	case VPMAXUDZ128rr:
1896	case VPMAXUDZ128rrk:
1897	case VPMAXUDZ128rrkz:
1898	case VPMAXUDZ256rm:
1899	case VPMAXUDZ256rmb:
1900	case VPMAXUDZ256rmbk:
1901	case VPMAXUDZ256rmbkz:
1902	case VPMAXUDZ256rmk:
1903	case VPMAXUDZ256rmkz:
1904	case VPMAXUDZ256rr:
1905	case VPMAXUDZ256rrk:
1906	case VPMAXUDZ256rrkz:
1907	case VPMAXUDZrm:
1908	case VPMAXUDZrmb:
1909	case VPMAXUDZrmbk:
1910	case VPMAXUDZrmbkz:
1911	case VPMAXUDZrmk:
1912	case VPMAXUDZrmkz:
1913	case VPMAXUDZrr:
1914	case VPMAXUDZrrk:
1915	case VPMAXUDZrrkz:
1916	case VPMAXUDrm:
1917	case VPMAXUDrr:
1918		return true;
1919	}
1920	return false;
1921}
1922
1923bool isCMPCC(unsigned Opcode) {
1924	switch (Opcode) {
1925	case CMPCCXADDmr32:
1926	case CMPCCXADDmr64:
1927		return true;
1928	}
1929	return false;
1930}
1931
1932bool isVSHUFI32X4(unsigned Opcode) {
1933	switch (Opcode) {
1934	case VSHUFI32X4Z256rmbi:
1935	case VSHUFI32X4Z256rmbik:
1936	case VSHUFI32X4Z256rmbikz:
1937	case VSHUFI32X4Z256rmi:
1938	case VSHUFI32X4Z256rmik:
1939	case VSHUFI32X4Z256rmikz:
1940	case VSHUFI32X4Z256rri:
1941	case VSHUFI32X4Z256rrik:
1942	case VSHUFI32X4Z256rrikz:
1943	case VSHUFI32X4Zrmbi:
1944	case VSHUFI32X4Zrmbik:
1945	case VSHUFI32X4Zrmbikz:
1946	case VSHUFI32X4Zrmi:
1947	case VSHUFI32X4Zrmik:
1948	case VSHUFI32X4Zrmikz:
1949	case VSHUFI32X4Zrri:
1950	case VSHUFI32X4Zrrik:
1951	case VSHUFI32X4Zrrikz:
1952		return true;
1953	}
1954	return false;
1955}
1956
1957bool isLOOPNE(unsigned Opcode) {
1958	return Opcode == LOOPNE;
1959}
1960
1961bool isVPMAXUQ(unsigned Opcode) {
1962	switch (Opcode) {
1963	case VPMAXUQZ128rm:
1964	case VPMAXUQZ128rmb:
1965	case VPMAXUQZ128rmbk:
1966	case VPMAXUQZ128rmbkz:
1967	case VPMAXUQZ128rmk:
1968	case VPMAXUQZ128rmkz:
1969	case VPMAXUQZ128rr:
1970	case VPMAXUQZ128rrk:
1971	case VPMAXUQZ128rrkz:
1972	case VPMAXUQZ256rm:
1973	case VPMAXUQZ256rmb:
1974	case VPMAXUQZ256rmbk:
1975	case VPMAXUQZ256rmbkz:
1976	case VPMAXUQZ256rmk:
1977	case VPMAXUQZ256rmkz:
1978	case VPMAXUQZ256rr:
1979	case VPMAXUQZ256rrk:
1980	case VPMAXUQZ256rrkz:
1981	case VPMAXUQZrm:
1982	case VPMAXUQZrmb:
1983	case VPMAXUQZrmbk:
1984	case VPMAXUQZrmbkz:
1985	case VPMAXUQZrmk:
1986	case VPMAXUQZrmkz:
1987	case VPMAXUQZrr:
1988	case VPMAXUQZrrk:
1989	case VPMAXUQZrrkz:
1990		return true;
1991	}
1992	return false;
1993}
1994
1995bool isVCOMPRESSPD(unsigned Opcode) {
1996	switch (Opcode) {
1997	case VCOMPRESSPDZ128mr:
1998	case VCOMPRESSPDZ128mrk:
1999	case VCOMPRESSPDZ128rr:
2000	case VCOMPRESSPDZ128rrk:
2001	case VCOMPRESSPDZ128rrkz:
2002	case VCOMPRESSPDZ256mr:
2003	case VCOMPRESSPDZ256mrk:
2004	case VCOMPRESSPDZ256rr:
2005	case VCOMPRESSPDZ256rrk:
2006	case VCOMPRESSPDZ256rrkz:
2007	case VCOMPRESSPDZmr:
2008	case VCOMPRESSPDZmrk:
2009	case VCOMPRESSPDZrr:
2010	case VCOMPRESSPDZrrk:
2011	case VCOMPRESSPDZrrkz:
2012		return true;
2013	}
2014	return false;
2015}
2016
2017bool isVPMAXUW(unsigned Opcode) {
2018	switch (Opcode) {
2019	case VPMAXUWYrm:
2020	case VPMAXUWYrr:
2021	case VPMAXUWZ128rm:
2022	case VPMAXUWZ128rmk:
2023	case VPMAXUWZ128rmkz:
2024	case VPMAXUWZ128rr:
2025	case VPMAXUWZ128rrk:
2026	case VPMAXUWZ128rrkz:
2027	case VPMAXUWZ256rm:
2028	case VPMAXUWZ256rmk:
2029	case VPMAXUWZ256rmkz:
2030	case VPMAXUWZ256rr:
2031	case VPMAXUWZ256rrk:
2032	case VPMAXUWZ256rrkz:
2033	case VPMAXUWZrm:
2034	case VPMAXUWZrmk:
2035	case VPMAXUWZrmkz:
2036	case VPMAXUWZrr:
2037	case VPMAXUWZrrk:
2038	case VPMAXUWZrrkz:
2039	case VPMAXUWrm:
2040	case VPMAXUWrr:
2041		return true;
2042	}
2043	return false;
2044}
2045
2046bool isVPMOVB2M(unsigned Opcode) {
2047	switch (Opcode) {
2048	case VPMOVB2MZ128rr:
2049	case VPMOVB2MZ256rr:
2050	case VPMOVB2MZrr:
2051		return true;
2052	}
2053	return false;
2054}
2055
2056bool isVANDPD(unsigned Opcode) {
2057	switch (Opcode) {
2058	case VANDPDYrm:
2059	case VANDPDYrr:
2060	case VANDPDZ128rm:
2061	case VANDPDZ128rmb:
2062	case VANDPDZ128rmbk:
2063	case VANDPDZ128rmbkz:
2064	case VANDPDZ128rmk:
2065	case VANDPDZ128rmkz:
2066	case VANDPDZ128rr:
2067	case VANDPDZ128rrk:
2068	case VANDPDZ128rrkz:
2069	case VANDPDZ256rm:
2070	case VANDPDZ256rmb:
2071	case VANDPDZ256rmbk:
2072	case VANDPDZ256rmbkz:
2073	case VANDPDZ256rmk:
2074	case VANDPDZ256rmkz:
2075	case VANDPDZ256rr:
2076	case VANDPDZ256rrk:
2077	case VANDPDZ256rrkz:
2078	case VANDPDZrm:
2079	case VANDPDZrmb:
2080	case VANDPDZrmbk:
2081	case VANDPDZrmbkz:
2082	case VANDPDZrmk:
2083	case VANDPDZrmkz:
2084	case VANDPDZrr:
2085	case VANDPDZrrk:
2086	case VANDPDZrrkz:
2087	case VANDPDrm:
2088	case VANDPDrr:
2089		return true;
2090	}
2091	return false;
2092}
2093
2094bool isVCOMPRESSPS(unsigned Opcode) {
2095	switch (Opcode) {
2096	case VCOMPRESSPSZ128mr:
2097	case VCOMPRESSPSZ128mrk:
2098	case VCOMPRESSPSZ128rr:
2099	case VCOMPRESSPSZ128rrk:
2100	case VCOMPRESSPSZ128rrkz:
2101	case VCOMPRESSPSZ256mr:
2102	case VCOMPRESSPSZ256mrk:
2103	case VCOMPRESSPSZ256rr:
2104	case VCOMPRESSPSZ256rrk:
2105	case VCOMPRESSPSZ256rrkz:
2106	case VCOMPRESSPSZmr:
2107	case VCOMPRESSPSZmrk:
2108	case VCOMPRESSPSZrr:
2109	case VCOMPRESSPSZrrk:
2110	case VCOMPRESSPSZrrkz:
2111		return true;
2112	}
2113	return false;
2114}
2115
2116bool isVPDPBSUD(unsigned Opcode) {
2117	switch (Opcode) {
2118	case VPDPBSUDYrm:
2119	case VPDPBSUDYrr:
2120	case VPDPBSUDrm:
2121	case VPDPBSUDrr:
2122		return true;
2123	}
2124	return false;
2125}
2126
2127bool isPFRCPIT1(unsigned Opcode) {
2128	switch (Opcode) {
2129	case PFRCPIT1rm:
2130	case PFRCPIT1rr:
2131		return true;
2132	}
2133	return false;
2134}
2135
2136bool isPFRCPIT2(unsigned Opcode) {
2137	switch (Opcode) {
2138	case PFRCPIT2rm:
2139	case PFRCPIT2rr:
2140		return true;
2141	}
2142	return false;
2143}
2144
2145bool isWRPKRU(unsigned Opcode) {
2146	return Opcode == WRPKRUr;
2147}
2148
2149bool isVANDPS(unsigned Opcode) {
2150	switch (Opcode) {
2151	case VANDPSYrm:
2152	case VANDPSYrr:
2153	case VANDPSZ128rm:
2154	case VANDPSZ128rmb:
2155	case VANDPSZ128rmbk:
2156	case VANDPSZ128rmbkz:
2157	case VANDPSZ128rmk:
2158	case VANDPSZ128rmkz:
2159	case VANDPSZ128rr:
2160	case VANDPSZ128rrk:
2161	case VANDPSZ128rrkz:
2162	case VANDPSZ256rm:
2163	case VANDPSZ256rmb:
2164	case VANDPSZ256rmbk:
2165	case VANDPSZ256rmbkz:
2166	case VANDPSZ256rmk:
2167	case VANDPSZ256rmkz:
2168	case VANDPSZ256rr:
2169	case VANDPSZ256rrk:
2170	case VANDPSZ256rrkz:
2171	case VANDPSZrm:
2172	case VANDPSZrmb:
2173	case VANDPSZrmbk:
2174	case VANDPSZrmbkz:
2175	case VANDPSZrmk:
2176	case VANDPSZrmkz:
2177	case VANDPSZrr:
2178	case VANDPSZrrk:
2179	case VANDPSZrrkz:
2180	case VANDPSrm:
2181	case VANDPSrr:
2182		return true;
2183	}
2184	return false;
2185}
2186
2187bool isWRUSSD(unsigned Opcode) {
2188	return Opcode == WRUSSD;
2189}
2190
2191bool isVMPTRLD(unsigned Opcode) {
2192	return Opcode == VMPTRLDm;
2193}
2194
2195bool isWRUSSQ(unsigned Opcode) {
2196	return Opcode == WRUSSQ;
2197}
2198
2199bool isAESDECLAST(unsigned Opcode) {
2200	switch (Opcode) {
2201	case AESDECLASTrm:
2202	case AESDECLASTrr:
2203		return true;
2204	}
2205	return false;
2206}
2207
2208bool isSYSCALL(unsigned Opcode) {
2209	return Opcode == SYSCALL;
2210}
2211
2212bool isVFIXUPIMMSD(unsigned Opcode) {
2213	switch (Opcode) {
2214	case VFIXUPIMMSDZrmi:
2215	case VFIXUPIMMSDZrmik:
2216	case VFIXUPIMMSDZrmikz:
2217	case VFIXUPIMMSDZrri:
2218	case VFIXUPIMMSDZrrib:
2219	case VFIXUPIMMSDZrribk:
2220	case VFIXUPIMMSDZrribkz:
2221	case VFIXUPIMMSDZrrik:
2222	case VFIXUPIMMSDZrrikz:
2223		return true;
2224	}
2225	return false;
2226}
2227
2228bool isVPRORD(unsigned Opcode) {
2229	switch (Opcode) {
2230	case VPRORDZ128mbi:
2231	case VPRORDZ128mbik:
2232	case VPRORDZ128mbikz:
2233	case VPRORDZ128mi:
2234	case VPRORDZ128mik:
2235	case VPRORDZ128mikz:
2236	case VPRORDZ128ri:
2237	case VPRORDZ128rik:
2238	case VPRORDZ128rikz:
2239	case VPRORDZ256mbi:
2240	case VPRORDZ256mbik:
2241	case VPRORDZ256mbikz:
2242	case VPRORDZ256mi:
2243	case VPRORDZ256mik:
2244	case VPRORDZ256mikz:
2245	case VPRORDZ256ri:
2246	case VPRORDZ256rik:
2247	case VPRORDZ256rikz:
2248	case VPRORDZmbi:
2249	case VPRORDZmbik:
2250	case VPRORDZmbikz:
2251	case VPRORDZmi:
2252	case VPRORDZmik:
2253	case VPRORDZmikz:
2254	case VPRORDZri:
2255	case VPRORDZrik:
2256	case VPRORDZrikz:
2257		return true;
2258	}
2259	return false;
2260}
2261
2262bool isTEST(unsigned Opcode) {
2263	switch (Opcode) {
2264	case TEST16i16:
2265	case TEST16mi:
2266	case TEST16mr:
2267	case TEST16ri:
2268	case TEST16rr:
2269	case TEST32i32:
2270	case TEST32mi:
2271	case TEST32mr:
2272	case TEST32ri:
2273	case TEST32rr:
2274	case TEST64i32:
2275	case TEST64mi32:
2276	case TEST64mr:
2277	case TEST64ri32:
2278	case TEST64rr:
2279	case TEST8i8:
2280	case TEST8mi:
2281	case TEST8mr:
2282	case TEST8ri:
2283	case TEST8rr:
2284		return true;
2285	}
2286	return false;
2287}
2288
2289bool isSHA1MSG1(unsigned Opcode) {
2290	switch (Opcode) {
2291	case SHA1MSG1rm:
2292	case SHA1MSG1rr:
2293		return true;
2294	}
2295	return false;
2296}
2297
2298bool isSHA1MSG2(unsigned Opcode) {
2299	switch (Opcode) {
2300	case SHA1MSG2rm:
2301	case SHA1MSG2rr:
2302		return true;
2303	}
2304	return false;
2305}
2306
2307bool isVFMULCSH(unsigned Opcode) {
2308	switch (Opcode) {
2309	case VFMULCSHZrm:
2310	case VFMULCSHZrmk:
2311	case VFMULCSHZrmkz:
2312	case VFMULCSHZrr:
2313	case VFMULCSHZrrb:
2314	case VFMULCSHZrrbk:
2315	case VFMULCSHZrrbkz:
2316	case VFMULCSHZrrk:
2317	case VFMULCSHZrrkz:
2318		return true;
2319	}
2320	return false;
2321}
2322
2323bool isMOVNTDQA(unsigned Opcode) {
2324	return Opcode == MOVNTDQArm;
2325}
2326
2327bool isVFIXUPIMMSS(unsigned Opcode) {
2328	switch (Opcode) {
2329	case VFIXUPIMMSSZrmi:
2330	case VFIXUPIMMSSZrmik:
2331	case VFIXUPIMMSSZrmikz:
2332	case VFIXUPIMMSSZrri:
2333	case VFIXUPIMMSSZrrib:
2334	case VFIXUPIMMSSZrribk:
2335	case VFIXUPIMMSSZrribkz:
2336	case VFIXUPIMMSSZrrik:
2337	case VFIXUPIMMSSZrrikz:
2338		return true;
2339	}
2340	return false;
2341}
2342
2343bool isADOX(unsigned Opcode) {
2344	switch (Opcode) {
2345	case ADOX32rm:
2346	case ADOX32rr:
2347	case ADOX64rm:
2348	case ADOX64rr:
2349		return true;
2350	}
2351	return false;
2352}
2353
2354bool isVPRORQ(unsigned Opcode) {
2355	switch (Opcode) {
2356	case VPRORQZ128mbi:
2357	case VPRORQZ128mbik:
2358	case VPRORQZ128mbikz:
2359	case VPRORQZ128mi:
2360	case VPRORQZ128mik:
2361	case VPRORQZ128mikz:
2362	case VPRORQZ128ri:
2363	case VPRORQZ128rik:
2364	case VPRORQZ128rikz:
2365	case VPRORQZ256mbi:
2366	case VPRORQZ256mbik:
2367	case VPRORQZ256mbikz:
2368	case VPRORQZ256mi:
2369	case VPRORQZ256mik:
2370	case VPRORQZ256mikz:
2371	case VPRORQZ256ri:
2372	case VPRORQZ256rik:
2373	case VPRORQZ256rikz:
2374	case VPRORQZmbi:
2375	case VPRORQZmbik:
2376	case VPRORQZmbikz:
2377	case VPRORQZmi:
2378	case VPRORQZmik:
2379	case VPRORQZmikz:
2380	case VPRORQZri:
2381	case VPRORQZrik:
2382	case VPRORQZrikz:
2383		return true;
2384	}
2385	return false;
2386}
2387
2388bool isVSCATTERPF1DPD(unsigned Opcode) {
2389	return Opcode == VSCATTERPF1DPDm;
2390}
2391
2392bool isVPSRLDQ(unsigned Opcode) {
2393	switch (Opcode) {
2394	case VPSRLDQYri:
2395	case VPSRLDQZ128mi:
2396	case VPSRLDQZ128ri:
2397	case VPSRLDQZ256mi:
2398	case VPSRLDQZ256ri:
2399	case VPSRLDQZmi:
2400	case VPSRLDQZri:
2401	case VPSRLDQri:
2402		return true;
2403	}
2404	return false;
2405}
2406
2407bool isVPMOVUSWB(unsigned Opcode) {
2408	switch (Opcode) {
2409	case VPMOVUSWBZ128mr:
2410	case VPMOVUSWBZ128mrk:
2411	case VPMOVUSWBZ128rr:
2412	case VPMOVUSWBZ128rrk:
2413	case VPMOVUSWBZ128rrkz:
2414	case VPMOVUSWBZ256mr:
2415	case VPMOVUSWBZ256mrk:
2416	case VPMOVUSWBZ256rr:
2417	case VPMOVUSWBZ256rrk:
2418	case VPMOVUSWBZ256rrkz:
2419	case VPMOVUSWBZmr:
2420	case VPMOVUSWBZmrk:
2421	case VPMOVUSWBZrr:
2422	case VPMOVUSWBZrrk:
2423	case VPMOVUSWBZrrkz:
2424		return true;
2425	}
2426	return false;
2427}
2428
2429bool isVSCATTERPF1DPS(unsigned Opcode) {
2430	return Opcode == VSCATTERPF1DPSm;
2431}
2432
2433bool isFICOMP(unsigned Opcode) {
2434	switch (Opcode) {
2435	case FICOMP16m:
2436	case FICOMP32m:
2437		return true;
2438	}
2439	return false;
2440}
2441
2442bool isFBSTP(unsigned Opcode) {
2443	return Opcode == FBSTPm;
2444}
2445
2446bool isVPSHUFLW(unsigned Opcode) {
2447	switch (Opcode) {
2448	case VPSHUFLWYmi:
2449	case VPSHUFLWYri:
2450	case VPSHUFLWZ128mi:
2451	case VPSHUFLWZ128mik:
2452	case VPSHUFLWZ128mikz:
2453	case VPSHUFLWZ128ri:
2454	case VPSHUFLWZ128rik:
2455	case VPSHUFLWZ128rikz:
2456	case VPSHUFLWZ256mi:
2457	case VPSHUFLWZ256mik:
2458	case VPSHUFLWZ256mikz:
2459	case VPSHUFLWZ256ri:
2460	case VPSHUFLWZ256rik:
2461	case VPSHUFLWZ256rikz:
2462	case VPSHUFLWZmi:
2463	case VPSHUFLWZmik:
2464	case VPSHUFLWZmikz:
2465	case VPSHUFLWZri:
2466	case VPSHUFLWZrik:
2467	case VPSHUFLWZrikz:
2468	case VPSHUFLWmi:
2469	case VPSHUFLWri:
2470		return true;
2471	}
2472	return false;
2473}
2474
2475bool isVPSCATTERDD(unsigned Opcode) {
2476	switch (Opcode) {
2477	case VPSCATTERDDZ128mr:
2478	case VPSCATTERDDZ256mr:
2479	case VPSCATTERDDZmr:
2480		return true;
2481	}
2482	return false;
2483}
2484
2485bool isFNINIT(unsigned Opcode) {
2486	return Opcode == FNINIT;
2487}
2488
2489bool isMOVNTPD(unsigned Opcode) {
2490	return Opcode == MOVNTPDmr;
2491}
2492
2493bool isUIRET(unsigned Opcode) {
2494	return Opcode == UIRET;
2495}
2496
2497bool isPINSRB(unsigned Opcode) {
2498	switch (Opcode) {
2499	case PINSRBrm:
2500	case PINSRBrr:
2501		return true;
2502	}
2503	return false;
2504}
2505
2506bool isPINSRD(unsigned Opcode) {
2507	switch (Opcode) {
2508	case PINSRDrm:
2509	case PINSRDrr:
2510		return true;
2511	}
2512	return false;
2513}
2514
2515bool isSHRD(unsigned Opcode) {
2516	switch (Opcode) {
2517	case SHRD16mrCL:
2518	case SHRD16mri8:
2519	case SHRD16rrCL:
2520	case SHRD16rri8:
2521	case SHRD32mrCL:
2522	case SHRD32mri8:
2523	case SHRD32rrCL:
2524	case SHRD32rri8:
2525	case SHRD64mrCL:
2526	case SHRD64mri8:
2527	case SHRD64rrCL:
2528	case SHRD64rri8:
2529		return true;
2530	}
2531	return false;
2532}
2533
2534bool isVPSCATTERDQ(unsigned Opcode) {
2535	switch (Opcode) {
2536	case VPSCATTERDQZ128mr:
2537	case VPSCATTERDQZ256mr:
2538	case VPSCATTERDQZmr:
2539		return true;
2540	}
2541	return false;
2542}
2543
2544bool isMOVNTPS(unsigned Opcode) {
2545	return Opcode == MOVNTPSmr;
2546}
2547
2548bool isVGETEXPPD(unsigned Opcode) {
2549	switch (Opcode) {
2550	case VGETEXPPDZ128m:
2551	case VGETEXPPDZ128mb:
2552	case VGETEXPPDZ128mbk:
2553	case VGETEXPPDZ128mbkz:
2554	case VGETEXPPDZ128mk:
2555	case VGETEXPPDZ128mkz:
2556	case VGETEXPPDZ128r:
2557	case VGETEXPPDZ128rk:
2558	case VGETEXPPDZ128rkz:
2559	case VGETEXPPDZ256m:
2560	case VGETEXPPDZ256mb:
2561	case VGETEXPPDZ256mbk:
2562	case VGETEXPPDZ256mbkz:
2563	case VGETEXPPDZ256mk:
2564	case VGETEXPPDZ256mkz:
2565	case VGETEXPPDZ256r:
2566	case VGETEXPPDZ256rk:
2567	case VGETEXPPDZ256rkz:
2568	case VGETEXPPDZm:
2569	case VGETEXPPDZmb:
2570	case VGETEXPPDZmbk:
2571	case VGETEXPPDZmbkz:
2572	case VGETEXPPDZmk:
2573	case VGETEXPPDZmkz:
2574	case VGETEXPPDZr:
2575	case VGETEXPPDZrb:
2576	case VGETEXPPDZrbk:
2577	case VGETEXPPDZrbkz:
2578	case VGETEXPPDZrk:
2579	case VGETEXPPDZrkz:
2580		return true;
2581	}
2582	return false;
2583}
2584
2585bool isVRANGEPD(unsigned Opcode) {
2586	switch (Opcode) {
2587	case VRANGEPDZ128rmbi:
2588	case VRANGEPDZ128rmbik:
2589	case VRANGEPDZ128rmbikz:
2590	case VRANGEPDZ128rmi:
2591	case VRANGEPDZ128rmik:
2592	case VRANGEPDZ128rmikz:
2593	case VRANGEPDZ128rri:
2594	case VRANGEPDZ128rrik:
2595	case VRANGEPDZ128rrikz:
2596	case VRANGEPDZ256rmbi:
2597	case VRANGEPDZ256rmbik:
2598	case VRANGEPDZ256rmbikz:
2599	case VRANGEPDZ256rmi:
2600	case VRANGEPDZ256rmik:
2601	case VRANGEPDZ256rmikz:
2602	case VRANGEPDZ256rri:
2603	case VRANGEPDZ256rrik:
2604	case VRANGEPDZ256rrikz:
2605	case VRANGEPDZrmbi:
2606	case VRANGEPDZrmbik:
2607	case VRANGEPDZrmbikz:
2608	case VRANGEPDZrmi:
2609	case VRANGEPDZrmik:
2610	case VRANGEPDZrmikz:
2611	case VRANGEPDZrri:
2612	case VRANGEPDZrrib:
2613	case VRANGEPDZrribk:
2614	case VRANGEPDZrribkz:
2615	case VRANGEPDZrrik:
2616	case VRANGEPDZrrikz:
2617		return true;
2618	}
2619	return false;
2620}
2621
2622bool isPFRCP(unsigned Opcode) {
2623	switch (Opcode) {
2624	case PFRCPrm:
2625	case PFRCPrr:
2626		return true;
2627	}
2628	return false;
2629}
2630
2631bool isVGETEXPPH(unsigned Opcode) {
2632	switch (Opcode) {
2633	case VGETEXPPHZ128m:
2634	case VGETEXPPHZ128mb:
2635	case VGETEXPPHZ128mbk:
2636	case VGETEXPPHZ128mbkz:
2637	case VGETEXPPHZ128mk:
2638	case VGETEXPPHZ128mkz:
2639	case VGETEXPPHZ128r:
2640	case VGETEXPPHZ128rk:
2641	case VGETEXPPHZ128rkz:
2642	case VGETEXPPHZ256m:
2643	case VGETEXPPHZ256mb:
2644	case VGETEXPPHZ256mbk:
2645	case VGETEXPPHZ256mbkz:
2646	case VGETEXPPHZ256mk:
2647	case VGETEXPPHZ256mkz:
2648	case VGETEXPPHZ256r:
2649	case VGETEXPPHZ256rk:
2650	case VGETEXPPHZ256rkz:
2651	case VGETEXPPHZm:
2652	case VGETEXPPHZmb:
2653	case VGETEXPPHZmbk:
2654	case VGETEXPPHZmbkz:
2655	case VGETEXPPHZmk:
2656	case VGETEXPPHZmkz:
2657	case VGETEXPPHZr:
2658	case VGETEXPPHZrb:
2659	case VGETEXPPHZrbk:
2660	case VGETEXPPHZrbkz:
2661	case VGETEXPPHZrk:
2662	case VGETEXPPHZrkz:
2663		return true;
2664	}
2665	return false;
2666}
2667
2668bool isPINSRQ(unsigned Opcode) {
2669	switch (Opcode) {
2670	case PINSRQrm:
2671	case PINSRQrr:
2672		return true;
2673	}
2674	return false;
2675}
2676
2677bool isVPROTB(unsigned Opcode) {
2678	switch (Opcode) {
2679	case VPROTBmi:
2680	case VPROTBmr:
2681	case VPROTBri:
2682	case VPROTBrm:
2683	case VPROTBrr:
2684	case VPROTBrr_REV:
2685		return true;
2686	}
2687	return false;
2688}
2689
2690bool isVPROTD(unsigned Opcode) {
2691	switch (Opcode) {
2692	case VPROTDmi:
2693	case VPROTDmr:
2694	case VPROTDri:
2695	case VPROTDrm:
2696	case VPROTDrr:
2697	case VPROTDrr_REV:
2698		return true;
2699	}
2700	return false;
2701}
2702
2703bool isSEAMCALL(unsigned Opcode) {
2704	return Opcode == SEAMCALL;
2705}
2706
2707bool isPINSRW(unsigned Opcode) {
2708	switch (Opcode) {
2709	case MMX_PINSRWrm:
2710	case MMX_PINSRWrr:
2711	case PINSRWrm:
2712	case PINSRWrr:
2713		return true;
2714	}
2715	return false;
2716}
2717
2718bool isSHRX(unsigned Opcode) {
2719	switch (Opcode) {
2720	case SHRX32rm:
2721	case SHRX32rr:
2722	case SHRX64rm:
2723	case SHRX64rr:
2724		return true;
2725	}
2726	return false;
2727}
2728
2729bool isVGETEXPPS(unsigned Opcode) {
2730	switch (Opcode) {
2731	case VGETEXPPSZ128m:
2732	case VGETEXPPSZ128mb:
2733	case VGETEXPPSZ128mbk:
2734	case VGETEXPPSZ128mbkz:
2735	case VGETEXPPSZ128mk:
2736	case VGETEXPPSZ128mkz:
2737	case VGETEXPPSZ128r:
2738	case VGETEXPPSZ128rk:
2739	case VGETEXPPSZ128rkz:
2740	case VGETEXPPSZ256m:
2741	case VGETEXPPSZ256mb:
2742	case VGETEXPPSZ256mbk:
2743	case VGETEXPPSZ256mbkz:
2744	case VGETEXPPSZ256mk:
2745	case VGETEXPPSZ256mkz:
2746	case VGETEXPPSZ256r:
2747	case VGETEXPPSZ256rk:
2748	case VGETEXPPSZ256rkz:
2749	case VGETEXPPSZm:
2750	case VGETEXPPSZmb:
2751	case VGETEXPPSZmbk:
2752	case VGETEXPPSZmbkz:
2753	case VGETEXPPSZmk:
2754	case VGETEXPPSZmkz:
2755	case VGETEXPPSZr:
2756	case VGETEXPPSZrb:
2757	case VGETEXPPSZrbk:
2758	case VGETEXPPSZrbkz:
2759	case VGETEXPPSZrk:
2760	case VGETEXPPSZrkz:
2761		return true;
2762	}
2763	return false;
2764}
2765
2766bool isVRANGEPS(unsigned Opcode) {
2767	switch (Opcode) {
2768	case VRANGEPSZ128rmbi:
2769	case VRANGEPSZ128rmbik:
2770	case VRANGEPSZ128rmbikz:
2771	case VRANGEPSZ128rmi:
2772	case VRANGEPSZ128rmik:
2773	case VRANGEPSZ128rmikz:
2774	case VRANGEPSZ128rri:
2775	case VRANGEPSZ128rrik:
2776	case VRANGEPSZ128rrikz:
2777	case VRANGEPSZ256rmbi:
2778	case VRANGEPSZ256rmbik:
2779	case VRANGEPSZ256rmbikz:
2780	case VRANGEPSZ256rmi:
2781	case VRANGEPSZ256rmik:
2782	case VRANGEPSZ256rmikz:
2783	case VRANGEPSZ256rri:
2784	case VRANGEPSZ256rrik:
2785	case VRANGEPSZ256rrikz:
2786	case VRANGEPSZrmbi:
2787	case VRANGEPSZrmbik:
2788	case VRANGEPSZrmbikz:
2789	case VRANGEPSZrmi:
2790	case VRANGEPSZrmik:
2791	case VRANGEPSZrmikz:
2792	case VRANGEPSZrri:
2793	case VRANGEPSZrrib:
2794	case VRANGEPSZrribk:
2795	case VRANGEPSZrribkz:
2796	case VRANGEPSZrrik:
2797	case VRANGEPSZrrikz:
2798		return true;
2799	}
2800	return false;
2801}
2802
2803bool isPABSB(unsigned Opcode) {
2804	switch (Opcode) {
2805	case MMX_PABSBrm:
2806	case MMX_PABSBrr:
2807	case PABSBrm:
2808	case PABSBrr:
2809		return true;
2810	}
2811	return false;
2812}
2813
2814bool isPABSD(unsigned Opcode) {
2815	switch (Opcode) {
2816	case MMX_PABSDrm:
2817	case MMX_PABSDrr:
2818	case PABSDrm:
2819	case PABSDrr:
2820		return true;
2821	}
2822	return false;
2823}
2824
2825bool isVPROTQ(unsigned Opcode) {
2826	switch (Opcode) {
2827	case VPROTQmi:
2828	case VPROTQmr:
2829	case VPROTQri:
2830	case VPROTQrm:
2831	case VPROTQrr:
2832	case VPROTQrr_REV:
2833		return true;
2834	}
2835	return false;
2836}
2837
2838bool isVPROTW(unsigned Opcode) {
2839	switch (Opcode) {
2840	case VPROTWmi:
2841	case VPROTWmr:
2842	case VPROTWri:
2843	case VPROTWrm:
2844	case VPROTWrr:
2845	case VPROTWrr_REV:
2846		return true;
2847	}
2848	return false;
2849}
2850
2851bool isVCVTTPS2UDQ(unsigned Opcode) {
2852	switch (Opcode) {
2853	case VCVTTPS2UDQZ128rm:
2854	case VCVTTPS2UDQZ128rmb:
2855	case VCVTTPS2UDQZ128rmbk:
2856	case VCVTTPS2UDQZ128rmbkz:
2857	case VCVTTPS2UDQZ128rmk:
2858	case VCVTTPS2UDQZ128rmkz:
2859	case VCVTTPS2UDQZ128rr:
2860	case VCVTTPS2UDQZ128rrk:
2861	case VCVTTPS2UDQZ128rrkz:
2862	case VCVTTPS2UDQZ256rm:
2863	case VCVTTPS2UDQZ256rmb:
2864	case VCVTTPS2UDQZ256rmbk:
2865	case VCVTTPS2UDQZ256rmbkz:
2866	case VCVTTPS2UDQZ256rmk:
2867	case VCVTTPS2UDQZ256rmkz:
2868	case VCVTTPS2UDQZ256rr:
2869	case VCVTTPS2UDQZ256rrk:
2870	case VCVTTPS2UDQZ256rrkz:
2871	case VCVTTPS2UDQZrm:
2872	case VCVTTPS2UDQZrmb:
2873	case VCVTTPS2UDQZrmbk:
2874	case VCVTTPS2UDQZrmbkz:
2875	case VCVTTPS2UDQZrmk:
2876	case VCVTTPS2UDQZrmkz:
2877	case VCVTTPS2UDQZrr:
2878	case VCVTTPS2UDQZrrb:
2879	case VCVTTPS2UDQZrrbk:
2880	case VCVTTPS2UDQZrrbkz:
2881	case VCVTTPS2UDQZrrk:
2882	case VCVTTPS2UDQZrrkz:
2883		return true;
2884	}
2885	return false;
2886}
2887
2888bool isFXRSTOR(unsigned Opcode) {
2889	return Opcode == FXRSTOR;
2890}
2891
2892bool isVMOVDQU16(unsigned Opcode) {
2893	switch (Opcode) {
2894	case VMOVDQU16Z128mr:
2895	case VMOVDQU16Z128mrk:
2896	case VMOVDQU16Z128rm:
2897	case VMOVDQU16Z128rmk:
2898	case VMOVDQU16Z128rmkz:
2899	case VMOVDQU16Z128rr:
2900	case VMOVDQU16Z128rr_REV:
2901	case VMOVDQU16Z128rrk:
2902	case VMOVDQU16Z128rrk_REV:
2903	case VMOVDQU16Z128rrkz:
2904	case VMOVDQU16Z128rrkz_REV:
2905	case VMOVDQU16Z256mr:
2906	case VMOVDQU16Z256mrk:
2907	case VMOVDQU16Z256rm:
2908	case VMOVDQU16Z256rmk:
2909	case VMOVDQU16Z256rmkz:
2910	case VMOVDQU16Z256rr:
2911	case VMOVDQU16Z256rr_REV:
2912	case VMOVDQU16Z256rrk:
2913	case VMOVDQU16Z256rrk_REV:
2914	case VMOVDQU16Z256rrkz:
2915	case VMOVDQU16Z256rrkz_REV:
2916	case VMOVDQU16Zmr:
2917	case VMOVDQU16Zmrk:
2918	case VMOVDQU16Zrm:
2919	case VMOVDQU16Zrmk:
2920	case VMOVDQU16Zrmkz:
2921	case VMOVDQU16Zrr:
2922	case VMOVDQU16Zrr_REV:
2923	case VMOVDQU16Zrrk:
2924	case VMOVDQU16Zrrk_REV:
2925	case VMOVDQU16Zrrkz:
2926	case VMOVDQU16Zrrkz_REV:
2927		return true;
2928	}
2929	return false;
2930}
2931
2932bool isPABSW(unsigned Opcode) {
2933	switch (Opcode) {
2934	case MMX_PABSWrm:
2935	case MMX_PABSWrr:
2936	case PABSWrm:
2937	case PABSWrr:
2938		return true;
2939	}
2940	return false;
2941}
2942
2943bool isCVTDQ2PD(unsigned Opcode) {
2944	switch (Opcode) {
2945	case CVTDQ2PDrm:
2946	case CVTDQ2PDrr:
2947		return true;
2948	}
2949	return false;
2950}
2951
2952bool isCVTDQ2PS(unsigned Opcode) {
2953	switch (Opcode) {
2954	case CVTDQ2PSrm:
2955	case CVTDQ2PSrr:
2956		return true;
2957	}
2958	return false;
2959}
2960
2961bool isXOR(unsigned Opcode) {
2962	switch (Opcode) {
2963	case XOR16i16:
2964	case XOR16mi:
2965	case XOR16mi8:
2966	case XOR16mr:
2967	case XOR16ri:
2968	case XOR16ri8:
2969	case XOR16rm:
2970	case XOR16rr:
2971	case XOR16rr_REV:
2972	case XOR32i32:
2973	case XOR32mi:
2974	case XOR32mi8:
2975	case XOR32mr:
2976	case XOR32ri:
2977	case XOR32ri8:
2978	case XOR32rm:
2979	case XOR32rr:
2980	case XOR32rr_REV:
2981	case XOR64i32:
2982	case XOR64mi32:
2983	case XOR64mi8:
2984	case XOR64mr:
2985	case XOR64ri32:
2986	case XOR64ri8:
2987	case XOR64rm:
2988	case XOR64rr:
2989	case XOR64rr_REV:
2990	case XOR8i8:
2991	case XOR8mi:
2992	case XOR8mi8:
2993	case XOR8mr:
2994	case XOR8ri:
2995	case XOR8ri8:
2996	case XOR8rm:
2997	case XOR8rr:
2998	case XOR8rr_REV:
2999		return true;
3000	}
3001	return false;
3002}
3003
3004bool isINC(unsigned Opcode) {
3005	switch (Opcode) {
3006	case INC16m:
3007	case INC16r:
3008	case INC16r_alt:
3009	case INC32m:
3010	case INC32r:
3011	case INC32r_alt:
3012	case INC64m:
3013	case INC64r:
3014	case INC8m:
3015	case INC8r:
3016		return true;
3017	}
3018	return false;
3019}
3020
3021bool isVMCALL(unsigned Opcode) {
3022	return Opcode == VMCALL;
3023}
3024
3025bool isPACKSSDW(unsigned Opcode) {
3026	switch (Opcode) {
3027	case MMX_PACKSSDWrm:
3028	case MMX_PACKSSDWrr:
3029	case PACKSSDWrm:
3030	case PACKSSDWrr:
3031		return true;
3032	}
3033	return false;
3034}
3035
3036bool isPSUBUSB(unsigned Opcode) {
3037	switch (Opcode) {
3038	case MMX_PSUBUSBrm:
3039	case MMX_PSUBUSBrr:
3040	case PSUBUSBrm:
3041	case PSUBUSBrr:
3042		return true;
3043	}
3044	return false;
3045}
3046
3047bool isINT(unsigned Opcode) {
3048	return Opcode == INT;
3049}
3050
3051bool isMOVNTSD(unsigned Opcode) {
3052	return Opcode == MOVNTSD;
3053}
3054
3055bool isVPMOVZXBD(unsigned Opcode) {
3056	switch (Opcode) {
3057	case VPMOVZXBDYrm:
3058	case VPMOVZXBDYrr:
3059	case VPMOVZXBDZ128rm:
3060	case VPMOVZXBDZ128rmk:
3061	case VPMOVZXBDZ128rmkz:
3062	case VPMOVZXBDZ128rr:
3063	case VPMOVZXBDZ128rrk:
3064	case VPMOVZXBDZ128rrkz:
3065	case VPMOVZXBDZ256rm:
3066	case VPMOVZXBDZ256rmk:
3067	case VPMOVZXBDZ256rmkz:
3068	case VPMOVZXBDZ256rr:
3069	case VPMOVZXBDZ256rrk:
3070	case VPMOVZXBDZ256rrkz:
3071	case VPMOVZXBDZrm:
3072	case VPMOVZXBDZrmk:
3073	case VPMOVZXBDZrmkz:
3074	case VPMOVZXBDZrr:
3075	case VPMOVZXBDZrrk:
3076	case VPMOVZXBDZrrkz:
3077	case VPMOVZXBDrm:
3078	case VPMOVZXBDrr:
3079		return true;
3080	}
3081	return false;
3082}
3083
3084bool isVCVTUDQ2PD(unsigned Opcode) {
3085	switch (Opcode) {
3086	case VCVTUDQ2PDZ128rm:
3087	case VCVTUDQ2PDZ128rmb:
3088	case VCVTUDQ2PDZ128rmbk:
3089	case VCVTUDQ2PDZ128rmbkz:
3090	case VCVTUDQ2PDZ128rmk:
3091	case VCVTUDQ2PDZ128rmkz:
3092	case VCVTUDQ2PDZ128rr:
3093	case VCVTUDQ2PDZ128rrk:
3094	case VCVTUDQ2PDZ128rrkz:
3095	case VCVTUDQ2PDZ256rm:
3096	case VCVTUDQ2PDZ256rmb:
3097	case VCVTUDQ2PDZ256rmbk:
3098	case VCVTUDQ2PDZ256rmbkz:
3099	case VCVTUDQ2PDZ256rmk:
3100	case VCVTUDQ2PDZ256rmkz:
3101	case VCVTUDQ2PDZ256rr:
3102	case VCVTUDQ2PDZ256rrk:
3103	case VCVTUDQ2PDZ256rrkz:
3104	case VCVTUDQ2PDZrm:
3105	case VCVTUDQ2PDZrmb:
3106	case VCVTUDQ2PDZrmbk:
3107	case VCVTUDQ2PDZrmbkz:
3108	case VCVTUDQ2PDZrmk:
3109	case VCVTUDQ2PDZrmkz:
3110	case VCVTUDQ2PDZrr:
3111	case VCVTUDQ2PDZrrk:
3112	case VCVTUDQ2PDZrrkz:
3113		return true;
3114	}
3115	return false;
3116}
3117
3118bool isVCVTUDQ2PH(unsigned Opcode) {
3119	switch (Opcode) {
3120	case VCVTUDQ2PHZ128rm:
3121	case VCVTUDQ2PHZ128rmb:
3122	case VCVTUDQ2PHZ128rmbk:
3123	case VCVTUDQ2PHZ128rmbkz:
3124	case VCVTUDQ2PHZ128rmk:
3125	case VCVTUDQ2PHZ128rmkz:
3126	case VCVTUDQ2PHZ128rr:
3127	case VCVTUDQ2PHZ128rrk:
3128	case VCVTUDQ2PHZ128rrkz:
3129	case VCVTUDQ2PHZ256rm:
3130	case VCVTUDQ2PHZ256rmb:
3131	case VCVTUDQ2PHZ256rmbk:
3132	case VCVTUDQ2PHZ256rmbkz:
3133	case VCVTUDQ2PHZ256rmk:
3134	case VCVTUDQ2PHZ256rmkz:
3135	case VCVTUDQ2PHZ256rr:
3136	case VCVTUDQ2PHZ256rrk:
3137	case VCVTUDQ2PHZ256rrkz:
3138	case VCVTUDQ2PHZrm:
3139	case VCVTUDQ2PHZrmb:
3140	case VCVTUDQ2PHZrmbk:
3141	case VCVTUDQ2PHZrmbkz:
3142	case VCVTUDQ2PHZrmk:
3143	case VCVTUDQ2PHZrmkz:
3144	case VCVTUDQ2PHZrr:
3145	case VCVTUDQ2PHZrrb:
3146	case VCVTUDQ2PHZrrbk:
3147	case VCVTUDQ2PHZrrbkz:
3148	case VCVTUDQ2PHZrrk:
3149	case VCVTUDQ2PHZrrkz:
3150		return true;
3151	}
3152	return false;
3153}
3154
3155bool isVMOVDQU32(unsigned Opcode) {
3156	switch (Opcode) {
3157	case VMOVDQU32Z128mr:
3158	case VMOVDQU32Z128mrk:
3159	case VMOVDQU32Z128rm:
3160	case VMOVDQU32Z128rmk:
3161	case VMOVDQU32Z128rmkz:
3162	case VMOVDQU32Z128rr:
3163	case VMOVDQU32Z128rr_REV:
3164	case VMOVDQU32Z128rrk:
3165	case VMOVDQU32Z128rrk_REV:
3166	case VMOVDQU32Z128rrkz:
3167	case VMOVDQU32Z128rrkz_REV:
3168	case VMOVDQU32Z256mr:
3169	case VMOVDQU32Z256mrk:
3170	case VMOVDQU32Z256rm:
3171	case VMOVDQU32Z256rmk:
3172	case VMOVDQU32Z256rmkz:
3173	case VMOVDQU32Z256rr:
3174	case VMOVDQU32Z256rr_REV:
3175	case VMOVDQU32Z256rrk:
3176	case VMOVDQU32Z256rrk_REV:
3177	case VMOVDQU32Z256rrkz:
3178	case VMOVDQU32Z256rrkz_REV:
3179	case VMOVDQU32Zmr:
3180	case VMOVDQU32Zmrk:
3181	case VMOVDQU32Zrm:
3182	case VMOVDQU32Zrmk:
3183	case VMOVDQU32Zrmkz:
3184	case VMOVDQU32Zrr:
3185	case VMOVDQU32Zrr_REV:
3186	case VMOVDQU32Zrrk:
3187	case VMOVDQU32Zrrk_REV:
3188	case VMOVDQU32Zrrkz:
3189	case VMOVDQU32Zrrkz_REV:
3190		return true;
3191	}
3192	return false;
3193}
3194
3195bool isPSUBUSW(unsigned Opcode) {
3196	switch (Opcode) {
3197	case MMX_PSUBUSWrm:
3198	case MMX_PSUBUSWrr:
3199	case PSUBUSWrm:
3200	case PSUBUSWrr:
3201		return true;
3202	}
3203	return false;
3204}
3205
3206bool isMOVNTSS(unsigned Opcode) {
3207	return Opcode == MOVNTSS;
3208}
3209
3210bool isVGETEXPSD(unsigned Opcode) {
3211	switch (Opcode) {
3212	case VGETEXPSDZm:
3213	case VGETEXPSDZmk:
3214	case VGETEXPSDZmkz:
3215	case VGETEXPSDZr:
3216	case VGETEXPSDZrb:
3217	case VGETEXPSDZrbk:
3218	case VGETEXPSDZrbkz:
3219	case VGETEXPSDZrk:
3220	case VGETEXPSDZrkz:
3221		return true;
3222	}
3223	return false;
3224}
3225
3226bool isVPMOVZXBQ(unsigned Opcode) {
3227	switch (Opcode) {
3228	case VPMOVZXBQYrm:
3229	case VPMOVZXBQYrr:
3230	case VPMOVZXBQZ128rm:
3231	case VPMOVZXBQZ128rmk:
3232	case VPMOVZXBQZ128rmkz:
3233	case VPMOVZXBQZ128rr:
3234	case VPMOVZXBQZ128rrk:
3235	case VPMOVZXBQZ128rrkz:
3236	case VPMOVZXBQZ256rm:
3237	case VPMOVZXBQZ256rmk:
3238	case VPMOVZXBQZ256rmkz:
3239	case VPMOVZXBQZ256rr:
3240	case VPMOVZXBQZ256rrk:
3241	case VPMOVZXBQZ256rrkz:
3242	case VPMOVZXBQZrm:
3243	case VPMOVZXBQZrmk:
3244	case VPMOVZXBQZrmkz:
3245	case VPMOVZXBQZrr:
3246	case VPMOVZXBQZrrk:
3247	case VPMOVZXBQZrrkz:
3248	case VPMOVZXBQrm:
3249	case VPMOVZXBQrr:
3250		return true;
3251	}
3252	return false;
3253}
3254
3255bool isVGETEXPSH(unsigned Opcode) {
3256	switch (Opcode) {
3257	case VGETEXPSHZm:
3258	case VGETEXPSHZmk:
3259	case VGETEXPSHZmkz:
3260	case VGETEXPSHZr:
3261	case VGETEXPSHZrb:
3262	case VGETEXPSHZrbk:
3263	case VGETEXPSHZrbkz:
3264	case VGETEXPSHZrk:
3265	case VGETEXPSHZrkz:
3266		return true;
3267	}
3268	return false;
3269}
3270
3271bool isVCVTNEEBF162PS(unsigned Opcode) {
3272	switch (Opcode) {
3273	case VCVTNEEBF162PSYrm:
3274	case VCVTNEEBF162PSrm:
3275		return true;
3276	}
3277	return false;
3278}
3279
3280bool isVRANGESD(unsigned Opcode) {
3281	switch (Opcode) {
3282	case VRANGESDZrmi:
3283	case VRANGESDZrmik:
3284	case VRANGESDZrmikz:
3285	case VRANGESDZrri:
3286	case VRANGESDZrrib:
3287	case VRANGESDZrribk:
3288	case VRANGESDZrribkz:
3289	case VRANGESDZrrik:
3290	case VRANGESDZrrikz:
3291		return true;
3292	}
3293	return false;
3294}
3295
3296bool isVCVTUDQ2PS(unsigned Opcode) {
3297	switch (Opcode) {
3298	case VCVTUDQ2PSZ128rm:
3299	case VCVTUDQ2PSZ128rmb:
3300	case VCVTUDQ2PSZ128rmbk:
3301	case VCVTUDQ2PSZ128rmbkz:
3302	case VCVTUDQ2PSZ128rmk:
3303	case VCVTUDQ2PSZ128rmkz:
3304	case VCVTUDQ2PSZ128rr:
3305	case VCVTUDQ2PSZ128rrk:
3306	case VCVTUDQ2PSZ128rrkz:
3307	case VCVTUDQ2PSZ256rm:
3308	case VCVTUDQ2PSZ256rmb:
3309	case VCVTUDQ2PSZ256rmbk:
3310	case VCVTUDQ2PSZ256rmbkz:
3311	case VCVTUDQ2PSZ256rmk:
3312	case VCVTUDQ2PSZ256rmkz:
3313	case VCVTUDQ2PSZ256rr:
3314	case VCVTUDQ2PSZ256rrk:
3315	case VCVTUDQ2PSZ256rrkz:
3316	case VCVTUDQ2PSZrm:
3317	case VCVTUDQ2PSZrmb:
3318	case VCVTUDQ2PSZrmbk:
3319	case VCVTUDQ2PSZrmbkz:
3320	case VCVTUDQ2PSZrmk:
3321	case VCVTUDQ2PSZrmkz:
3322	case VCVTUDQ2PSZrr:
3323	case VCVTUDQ2PSZrrb:
3324	case VCVTUDQ2PSZrrbk:
3325	case VCVTUDQ2PSZrrbkz:
3326	case VCVTUDQ2PSZrrk:
3327	case VCVTUDQ2PSZrrkz:
3328		return true;
3329	}
3330	return false;
3331}
3332
3333bool isVPMOVZXBW(unsigned Opcode) {
3334	switch (Opcode) {
3335	case VPMOVZXBWYrm:
3336	case VPMOVZXBWYrr:
3337	case VPMOVZXBWZ128rm:
3338	case VPMOVZXBWZ128rmk:
3339	case VPMOVZXBWZ128rmkz:
3340	case VPMOVZXBWZ128rr:
3341	case VPMOVZXBWZ128rrk:
3342	case VPMOVZXBWZ128rrkz:
3343	case VPMOVZXBWZ256rm:
3344	case VPMOVZXBWZ256rmk:
3345	case VPMOVZXBWZ256rmkz:
3346	case VPMOVZXBWZ256rr:
3347	case VPMOVZXBWZ256rrk:
3348	case VPMOVZXBWZ256rrkz:
3349	case VPMOVZXBWZrm:
3350	case VPMOVZXBWZrmk:
3351	case VPMOVZXBWZrmkz:
3352	case VPMOVZXBWZrr:
3353	case VPMOVZXBWZrrk:
3354	case VPMOVZXBWZrrkz:
3355	case VPMOVZXBWrm:
3356	case VPMOVZXBWrr:
3357		return true;
3358	}
3359	return false;
3360}
3361
3362bool isVGETEXPSS(unsigned Opcode) {
3363	switch (Opcode) {
3364	case VGETEXPSSZm:
3365	case VGETEXPSSZmk:
3366	case VGETEXPSSZmkz:
3367	case VGETEXPSSZr:
3368	case VGETEXPSSZrb:
3369	case VGETEXPSSZrbk:
3370	case VGETEXPSSZrbkz:
3371	case VGETEXPSSZrk:
3372	case VGETEXPSSZrkz:
3373		return true;
3374	}
3375	return false;
3376}
3377
3378bool isSHUFPD(unsigned Opcode) {
3379	switch (Opcode) {
3380	case SHUFPDrmi:
3381	case SHUFPDrri:
3382		return true;
3383	}
3384	return false;
3385}
3386
3387bool isVCVTTSS2SI(unsigned Opcode) {
3388	switch (Opcode) {
3389	case VCVTTSS2SI64Zrm_Int:
3390	case VCVTTSS2SI64Zrr_Int:
3391	case VCVTTSS2SI64Zrrb_Int:
3392	case VCVTTSS2SI64rm_Int:
3393	case VCVTTSS2SI64rr_Int:
3394	case VCVTTSS2SIZrm_Int:
3395	case VCVTTSS2SIZrr_Int:
3396	case VCVTTSS2SIZrrb_Int:
3397	case VCVTTSS2SIrm_Int:
3398	case VCVTTSS2SIrr_Int:
3399		return true;
3400	}
3401	return false;
3402}
3403
3404bool isVINSERTF128(unsigned Opcode) {
3405	switch (Opcode) {
3406	case VINSERTF128rm:
3407	case VINSERTF128rr:
3408		return true;
3409	}
3410	return false;
3411}
3412
3413bool isKANDNB(unsigned Opcode) {
3414	return Opcode == KANDNBrr;
3415}
3416
3417bool isPADDSB(unsigned Opcode) {
3418	switch (Opcode) {
3419	case MMX_PADDSBrm:
3420	case MMX_PADDSBrr:
3421	case PADDSBrm:
3422	case PADDSBrr:
3423		return true;
3424	}
3425	return false;
3426}
3427
3428bool isKANDND(unsigned Opcode) {
3429	return Opcode == KANDNDrr;
3430}
3431
3432bool isVPCMPISTRI(unsigned Opcode) {
3433	switch (Opcode) {
3434	case VPCMPISTRIrm:
3435	case VPCMPISTRIrr:
3436		return true;
3437	}
3438	return false;
3439}
3440
3441bool isRDPID(unsigned Opcode) {
3442	switch (Opcode) {
3443	case RDPID32:
3444	case RDPID64:
3445		return true;
3446	}
3447	return false;
3448}
3449
3450bool isVPCMPISTRM(unsigned Opcode) {
3451	switch (Opcode) {
3452	case VPCMPISTRMrm:
3453	case VPCMPISTRMrr:
3454		return true;
3455	}
3456	return false;
3457}
3458
3459bool isVRANGESS(unsigned Opcode) {
3460	switch (Opcode) {
3461	case VRANGESSZrmi:
3462	case VRANGESSZrmik:
3463	case VRANGESSZrmikz:
3464	case VRANGESSZrri:
3465	case VRANGESSZrrib:
3466	case VRANGESSZrribk:
3467	case VRANGESSZrribkz:
3468	case VRANGESSZrrik:
3469	case VRANGESSZrrikz:
3470		return true;
3471	}
3472	return false;
3473}
3474
3475bool isSHUFPS(unsigned Opcode) {
3476	switch (Opcode) {
3477	case SHUFPSrmi:
3478	case SHUFPSrri:
3479		return true;
3480	}
3481	return false;
3482}
3483
3484bool isVPDPBSSDS(unsigned Opcode) {
3485	switch (Opcode) {
3486	case VPDPBSSDSYrm:
3487	case VPDPBSSDSYrr:
3488	case VPDPBSSDSrm:
3489	case VPDPBSSDSrr:
3490		return true;
3491	}
3492	return false;
3493}
3494
3495bool isKANDNQ(unsigned Opcode) {
3496	return Opcode == KANDNQrr;
3497}
3498
3499bool isKANDNW(unsigned Opcode) {
3500	return Opcode == KANDNWrr;
3501}
3502
3503bool isPADDSW(unsigned Opcode) {
3504	switch (Opcode) {
3505	case MMX_PADDSWrm:
3506	case MMX_PADDSWrr:
3507	case PADDSWrm:
3508	case PADDSWrr:
3509		return true;
3510	}
3511	return false;
3512}
3513
3514bool isVCVTTPD2UDQ(unsigned Opcode) {
3515	switch (Opcode) {
3516	case VCVTTPD2UDQZ128rm:
3517	case VCVTTPD2UDQZ128rmb:
3518	case VCVTTPD2UDQZ128rmbk:
3519	case VCVTTPD2UDQZ128rmbkz:
3520	case VCVTTPD2UDQZ128rmk:
3521	case VCVTTPD2UDQZ128rmkz:
3522	case VCVTTPD2UDQZ128rr:
3523	case VCVTTPD2UDQZ128rrk:
3524	case VCVTTPD2UDQZ128rrkz:
3525	case VCVTTPD2UDQZ256rm:
3526	case VCVTTPD2UDQZ256rmb:
3527	case VCVTTPD2UDQZ256rmbk:
3528	case VCVTTPD2UDQZ256rmbkz:
3529	case VCVTTPD2UDQZ256rmk:
3530	case VCVTTPD2UDQZ256rmkz:
3531	case VCVTTPD2UDQZ256rr:
3532	case VCVTTPD2UDQZ256rrk:
3533	case VCVTTPD2UDQZ256rrkz:
3534	case VCVTTPD2UDQZrm:
3535	case VCVTTPD2UDQZrmb:
3536	case VCVTTPD2UDQZrmbk:
3537	case VCVTTPD2UDQZrmbkz:
3538	case VCVTTPD2UDQZrmk:
3539	case VCVTTPD2UDQZrmkz:
3540	case VCVTTPD2UDQZrr:
3541	case VCVTTPD2UDQZrrb:
3542	case VCVTTPD2UDQZrrbk:
3543	case VCVTTPD2UDQZrrbkz:
3544	case VCVTTPD2UDQZrrk:
3545	case VCVTTPD2UDQZrrkz:
3546		return true;
3547	}
3548	return false;
3549}
3550
3551bool isVANDNPD(unsigned Opcode) {
3552	switch (Opcode) {
3553	case VANDNPDYrm:
3554	case VANDNPDYrr:
3555	case VANDNPDZ128rm:
3556	case VANDNPDZ128rmb:
3557	case VANDNPDZ128rmbk:
3558	case VANDNPDZ128rmbkz:
3559	case VANDNPDZ128rmk:
3560	case VANDNPDZ128rmkz:
3561	case VANDNPDZ128rr:
3562	case VANDNPDZ128rrk:
3563	case VANDNPDZ128rrkz:
3564	case VANDNPDZ256rm:
3565	case VANDNPDZ256rmb:
3566	case VANDNPDZ256rmbk:
3567	case VANDNPDZ256rmbkz:
3568	case VANDNPDZ256rmk:
3569	case VANDNPDZ256rmkz:
3570	case VANDNPDZ256rr:
3571	case VANDNPDZ256rrk:
3572	case VANDNPDZ256rrkz:
3573	case VANDNPDZrm:
3574	case VANDNPDZrmb:
3575	case VANDNPDZrmbk:
3576	case VANDNPDZrmbkz:
3577	case VANDNPDZrmk:
3578	case VANDNPDZrmkz:
3579	case VANDNPDZrr:
3580	case VANDNPDZrrk:
3581	case VANDNPDZrrkz:
3582	case VANDNPDrm:
3583	case VANDNPDrr:
3584		return true;
3585	}
3586	return false;
3587}
3588
3589bool isXEND(unsigned Opcode) {
3590	return Opcode == XEND;
3591}
3592
3593bool isVUNPCKHPD(unsigned Opcode) {
3594	switch (Opcode) {
3595	case VUNPCKHPDYrm:
3596	case VUNPCKHPDYrr:
3597	case VUNPCKHPDZ128rm:
3598	case VUNPCKHPDZ128rmb:
3599	case VUNPCKHPDZ128rmbk:
3600	case VUNPCKHPDZ128rmbkz:
3601	case VUNPCKHPDZ128rmk:
3602	case VUNPCKHPDZ128rmkz:
3603	case VUNPCKHPDZ128rr:
3604	case VUNPCKHPDZ128rrk:
3605	case VUNPCKHPDZ128rrkz:
3606	case VUNPCKHPDZ256rm:
3607	case VUNPCKHPDZ256rmb:
3608	case VUNPCKHPDZ256rmbk:
3609	case VUNPCKHPDZ256rmbkz:
3610	case VUNPCKHPDZ256rmk:
3611	case VUNPCKHPDZ256rmkz:
3612	case VUNPCKHPDZ256rr:
3613	case VUNPCKHPDZ256rrk:
3614	case VUNPCKHPDZ256rrkz:
3615	case VUNPCKHPDZrm:
3616	case VUNPCKHPDZrmb:
3617	case VUNPCKHPDZrmbk:
3618	case VUNPCKHPDZrmbkz:
3619	case VUNPCKHPDZrmk:
3620	case VUNPCKHPDZrmkz:
3621	case VUNPCKHPDZrr:
3622	case VUNPCKHPDZrrk:
3623	case VUNPCKHPDZrrkz:
3624	case VUNPCKHPDrm:
3625	case VUNPCKHPDrr:
3626		return true;
3627	}
3628	return false;
3629}
3630
3631bool isPSRAD(unsigned Opcode) {
3632	switch (Opcode) {
3633	case MMX_PSRADri:
3634	case MMX_PSRADrm:
3635	case MMX_PSRADrr:
3636	case PSRADri:
3637	case PSRADrm:
3638	case PSRADrr:
3639		return true;
3640	}
3641	return false;
3642}
3643
3644bool isVANDNPS(unsigned Opcode) {
3645	switch (Opcode) {
3646	case VANDNPSYrm:
3647	case VANDNPSYrr:
3648	case VANDNPSZ128rm:
3649	case VANDNPSZ128rmb:
3650	case VANDNPSZ128rmbk:
3651	case VANDNPSZ128rmbkz:
3652	case VANDNPSZ128rmk:
3653	case VANDNPSZ128rmkz:
3654	case VANDNPSZ128rr:
3655	case VANDNPSZ128rrk:
3656	case VANDNPSZ128rrkz:
3657	case VANDNPSZ256rm:
3658	case VANDNPSZ256rmb:
3659	case VANDNPSZ256rmbk:
3660	case VANDNPSZ256rmbkz:
3661	case VANDNPSZ256rmk:
3662	case VANDNPSZ256rmkz:
3663	case VANDNPSZ256rr:
3664	case VANDNPSZ256rrk:
3665	case VANDNPSZ256rrkz:
3666	case VANDNPSZrm:
3667	case VANDNPSZrmb:
3668	case VANDNPSZrmbk:
3669	case VANDNPSZrmbkz:
3670	case VANDNPSZrmk:
3671	case VANDNPSZrmkz:
3672	case VANDNPSZrr:
3673	case VANDNPSZrrk:
3674	case VANDNPSZrrkz:
3675	case VANDNPSrm:
3676	case VANDNPSrr:
3677		return true;
3678	}
3679	return false;
3680}
3681
3682bool isVPMOVZXDQ(unsigned Opcode) {
3683	switch (Opcode) {
3684	case VPMOVZXDQYrm:
3685	case VPMOVZXDQYrr:
3686	case VPMOVZXDQZ128rm:
3687	case VPMOVZXDQZ128rmk:
3688	case VPMOVZXDQZ128rmkz:
3689	case VPMOVZXDQZ128rr:
3690	case VPMOVZXDQZ128rrk:
3691	case VPMOVZXDQZ128rrkz:
3692	case VPMOVZXDQZ256rm:
3693	case VPMOVZXDQZ256rmk:
3694	case VPMOVZXDQZ256rmkz:
3695	case VPMOVZXDQZ256rr:
3696	case VPMOVZXDQZ256rrk:
3697	case VPMOVZXDQZ256rrkz:
3698	case VPMOVZXDQZrm:
3699	case VPMOVZXDQZrmk:
3700	case VPMOVZXDQZrmkz:
3701	case VPMOVZXDQZrr:
3702	case VPMOVZXDQZrrk:
3703	case VPMOVZXDQZrrkz:
3704	case VPMOVZXDQrm:
3705	case VPMOVZXDQrr:
3706		return true;
3707	}
3708	return false;
3709}
3710
3711bool isVMPTRST(unsigned Opcode) {
3712	return Opcode == VMPTRSTm;
3713}
3714
3715bool isVUNPCKHPS(unsigned Opcode) {
3716	switch (Opcode) {
3717	case VUNPCKHPSYrm:
3718	case VUNPCKHPSYrr:
3719	case VUNPCKHPSZ128rm:
3720	case VUNPCKHPSZ128rmb:
3721	case VUNPCKHPSZ128rmbk:
3722	case VUNPCKHPSZ128rmbkz:
3723	case VUNPCKHPSZ128rmk:
3724	case VUNPCKHPSZ128rmkz:
3725	case VUNPCKHPSZ128rr:
3726	case VUNPCKHPSZ128rrk:
3727	case VUNPCKHPSZ128rrkz:
3728	case VUNPCKHPSZ256rm:
3729	case VUNPCKHPSZ256rmb:
3730	case VUNPCKHPSZ256rmbk:
3731	case VUNPCKHPSZ256rmbkz:
3732	case VUNPCKHPSZ256rmk:
3733	case VUNPCKHPSZ256rmkz:
3734	case VUNPCKHPSZ256rr:
3735	case VUNPCKHPSZ256rrk:
3736	case VUNPCKHPSZ256rrkz:
3737	case VUNPCKHPSZrm:
3738	case VUNPCKHPSZrmb:
3739	case VUNPCKHPSZrmbk:
3740	case VUNPCKHPSZrmbkz:
3741	case VUNPCKHPSZrmk:
3742	case VUNPCKHPSZrmkz:
3743	case VUNPCKHPSZrr:
3744	case VUNPCKHPSZrrk:
3745	case VUNPCKHPSZrrkz:
3746	case VUNPCKHPSrm:
3747	case VUNPCKHPSrr:
3748		return true;
3749	}
3750	return false;
3751}
3752
3753bool isPSRAW(unsigned Opcode) {
3754	switch (Opcode) {
3755	case MMX_PSRAWri:
3756	case MMX_PSRAWrm:
3757	case MMX_PSRAWrr:
3758	case PSRAWri:
3759	case PSRAWrm:
3760	case PSRAWrr:
3761		return true;
3762	}
3763	return false;
3764}
3765
3766bool isVPLZCNTD(unsigned Opcode) {
3767	switch (Opcode) {
3768	case VPLZCNTDZ128rm:
3769	case VPLZCNTDZ128rmb:
3770	case VPLZCNTDZ128rmbk:
3771	case VPLZCNTDZ128rmbkz:
3772	case VPLZCNTDZ128rmk:
3773	case VPLZCNTDZ128rmkz:
3774	case VPLZCNTDZ128rr:
3775	case VPLZCNTDZ128rrk:
3776	case VPLZCNTDZ128rrkz:
3777	case VPLZCNTDZ256rm:
3778	case VPLZCNTDZ256rmb:
3779	case VPLZCNTDZ256rmbk:
3780	case VPLZCNTDZ256rmbkz:
3781	case VPLZCNTDZ256rmk:
3782	case VPLZCNTDZ256rmkz:
3783	case VPLZCNTDZ256rr:
3784	case VPLZCNTDZ256rrk:
3785	case VPLZCNTDZ256rrkz:
3786	case VPLZCNTDZrm:
3787	case VPLZCNTDZrmb:
3788	case VPLZCNTDZrmbk:
3789	case VPLZCNTDZrmbkz:
3790	case VPLZCNTDZrmk:
3791	case VPLZCNTDZrmkz:
3792	case VPLZCNTDZrr:
3793	case VPLZCNTDZrrk:
3794	case VPLZCNTDZrrkz:
3795		return true;
3796	}
3797	return false;
3798}
3799
3800bool isWRMSRLIST(unsigned Opcode) {
3801	return Opcode == WRMSRLIST;
3802}
3803
3804bool isVPADDUSB(unsigned Opcode) {
3805	switch (Opcode) {
3806	case VPADDUSBYrm:
3807	case VPADDUSBYrr:
3808	case VPADDUSBZ128rm:
3809	case VPADDUSBZ128rmk:
3810	case VPADDUSBZ128rmkz:
3811	case VPADDUSBZ128rr:
3812	case VPADDUSBZ128rrk:
3813	case VPADDUSBZ128rrkz:
3814	case VPADDUSBZ256rm:
3815	case VPADDUSBZ256rmk:
3816	case VPADDUSBZ256rmkz:
3817	case VPADDUSBZ256rr:
3818	case VPADDUSBZ256rrk:
3819	case VPADDUSBZ256rrkz:
3820	case VPADDUSBZrm:
3821	case VPADDUSBZrmk:
3822	case VPADDUSBZrmkz:
3823	case VPADDUSBZrr:
3824	case VPADDUSBZrrk:
3825	case VPADDUSBZrrkz:
3826	case VPADDUSBrm:
3827	case VPADDUSBrr:
3828		return true;
3829	}
3830	return false;
3831}
3832
3833bool isVMOVDQU64(unsigned Opcode) {
3834	switch (Opcode) {
3835	case VMOVDQU64Z128mr:
3836	case VMOVDQU64Z128mrk:
3837	case VMOVDQU64Z128rm:
3838	case VMOVDQU64Z128rmk:
3839	case VMOVDQU64Z128rmkz:
3840	case VMOVDQU64Z128rr:
3841	case VMOVDQU64Z128rr_REV:
3842	case VMOVDQU64Z128rrk:
3843	case VMOVDQU64Z128rrk_REV:
3844	case VMOVDQU64Z128rrkz:
3845	case VMOVDQU64Z128rrkz_REV:
3846	case VMOVDQU64Z256mr:
3847	case VMOVDQU64Z256mrk:
3848	case VMOVDQU64Z256rm:
3849	case VMOVDQU64Z256rmk:
3850	case VMOVDQU64Z256rmkz:
3851	case VMOVDQU64Z256rr:
3852	case VMOVDQU64Z256rr_REV:
3853	case VMOVDQU64Z256rrk:
3854	case VMOVDQU64Z256rrk_REV:
3855	case VMOVDQU64Z256rrkz:
3856	case VMOVDQU64Z256rrkz_REV:
3857	case VMOVDQU64Zmr:
3858	case VMOVDQU64Zmrk:
3859	case VMOVDQU64Zrm:
3860	case VMOVDQU64Zrmk:
3861	case VMOVDQU64Zrmkz:
3862	case VMOVDQU64Zrr:
3863	case VMOVDQU64Zrr_REV:
3864	case VMOVDQU64Zrrk:
3865	case VMOVDQU64Zrrk_REV:
3866	case VMOVDQU64Zrrkz:
3867	case VMOVDQU64Zrrkz_REV:
3868		return true;
3869	}
3870	return false;
3871}
3872
3873bool isSUBPD(unsigned Opcode) {
3874	switch (Opcode) {
3875	case SUBPDrm:
3876	case SUBPDrr:
3877		return true;
3878	}
3879	return false;
3880}
3881
3882bool isMOVDDUP(unsigned Opcode) {
3883	switch (Opcode) {
3884	case MOVDDUPrm:
3885	case MOVDDUPrr:
3886		return true;
3887	}
3888	return false;
3889}
3890
3891bool isVPLZCNTQ(unsigned Opcode) {
3892	switch (Opcode) {
3893	case VPLZCNTQZ128rm:
3894	case VPLZCNTQZ128rmb:
3895	case VPLZCNTQZ128rmbk:
3896	case VPLZCNTQZ128rmbkz:
3897	case VPLZCNTQZ128rmk:
3898	case VPLZCNTQZ128rmkz:
3899	case VPLZCNTQZ128rr:
3900	case VPLZCNTQZ128rrk:
3901	case VPLZCNTQZ128rrkz:
3902	case VPLZCNTQZ256rm:
3903	case VPLZCNTQZ256rmb:
3904	case VPLZCNTQZ256rmbk:
3905	case VPLZCNTQZ256rmbkz:
3906	case VPLZCNTQZ256rmk:
3907	case VPLZCNTQZ256rmkz:
3908	case VPLZCNTQZ256rr:
3909	case VPLZCNTQZ256rrk:
3910	case VPLZCNTQZ256rrkz:
3911	case VPLZCNTQZrm:
3912	case VPLZCNTQZrmb:
3913	case VPLZCNTQZrmbk:
3914	case VPLZCNTQZrmbkz:
3915	case VPLZCNTQZrmk:
3916	case VPLZCNTQZrmkz:
3917	case VPLZCNTQZrr:
3918	case VPLZCNTQZrrk:
3919	case VPLZCNTQZrrkz:
3920		return true;
3921	}
3922	return false;
3923}
3924
3925bool isSTAC(unsigned Opcode) {
3926	return Opcode == STAC;
3927}
3928
3929bool isSUBPS(unsigned Opcode) {
3930	switch (Opcode) {
3931	case SUBPSrm:
3932	case SUBPSrr:
3933		return true;
3934	}
3935	return false;
3936}
3937
3938bool isVPADDUSW(unsigned Opcode) {
3939	switch (Opcode) {
3940	case VPADDUSWYrm:
3941	case VPADDUSWYrr:
3942	case VPADDUSWZ128rm:
3943	case VPADDUSWZ128rmk:
3944	case VPADDUSWZ128rmkz:
3945	case VPADDUSWZ128rr:
3946	case VPADDUSWZ128rrk:
3947	case VPADDUSWZ128rrkz:
3948	case VPADDUSWZ256rm:
3949	case VPADDUSWZ256rmk:
3950	case VPADDUSWZ256rmkz:
3951	case VPADDUSWZ256rr:
3952	case VPADDUSWZ256rrk:
3953	case VPADDUSWZ256rrkz:
3954	case VPADDUSWZrm:
3955	case VPADDUSWZrmk:
3956	case VPADDUSWZrmkz:
3957	case VPADDUSWZrr:
3958	case VPADDUSWZrrk:
3959	case VPADDUSWZrrkz:
3960	case VPADDUSWrm:
3961	case VPADDUSWrr:
3962		return true;
3963	}
3964	return false;
3965}
3966
3967bool isFCMOVNBE(unsigned Opcode) {
3968	return Opcode == CMOVNBE_F;
3969}
3970
3971bool isSHA1RNDS4(unsigned Opcode) {
3972	switch (Opcode) {
3973	case SHA1RNDS4rmi:
3974	case SHA1RNDS4rri:
3975		return true;
3976	}
3977	return false;
3978}
3979
3980bool isPAUSE(unsigned Opcode) {
3981	return Opcode == PAUSE;
3982}
3983
3984bool isSAHF(unsigned Opcode) {
3985	return Opcode == SAHF;
3986}
3987
3988bool isVREDUCEPD(unsigned Opcode) {
3989	switch (Opcode) {
3990	case VREDUCEPDZ128rmbi:
3991	case VREDUCEPDZ128rmbik:
3992	case VREDUCEPDZ128rmbikz:
3993	case VREDUCEPDZ128rmi:
3994	case VREDUCEPDZ128rmik:
3995	case VREDUCEPDZ128rmikz:
3996	case VREDUCEPDZ128rri:
3997	case VREDUCEPDZ128rrik:
3998	case VREDUCEPDZ128rrikz:
3999	case VREDUCEPDZ256rmbi:
4000	case VREDUCEPDZ256rmbik:
4001	case VREDUCEPDZ256rmbikz:
4002	case VREDUCEPDZ256rmi:
4003	case VREDUCEPDZ256rmik:
4004	case VREDUCEPDZ256rmikz:
4005	case VREDUCEPDZ256rri:
4006	case VREDUCEPDZ256rrik:
4007	case VREDUCEPDZ256rrikz:
4008	case VREDUCEPDZrmbi:
4009	case VREDUCEPDZrmbik:
4010	case VREDUCEPDZrmbikz:
4011	case VREDUCEPDZrmi:
4012	case VREDUCEPDZrmik:
4013	case VREDUCEPDZrmikz:
4014	case VREDUCEPDZrri:
4015	case VREDUCEPDZrrib:
4016	case VREDUCEPDZrribk:
4017	case VREDUCEPDZrribkz:
4018	case VREDUCEPDZrrik:
4019	case VREDUCEPDZrrikz:
4020		return true;
4021	}
4022	return false;
4023}
4024
4025bool isVREDUCEPH(unsigned Opcode) {
4026	switch (Opcode) {
4027	case VREDUCEPHZ128rmbi:
4028	case VREDUCEPHZ128rmbik:
4029	case VREDUCEPHZ128rmbikz:
4030	case VREDUCEPHZ128rmi:
4031	case VREDUCEPHZ128rmik:
4032	case VREDUCEPHZ128rmikz:
4033	case VREDUCEPHZ128rri:
4034	case VREDUCEPHZ128rrik:
4035	case VREDUCEPHZ128rrikz:
4036	case VREDUCEPHZ256rmbi:
4037	case VREDUCEPHZ256rmbik:
4038	case VREDUCEPHZ256rmbikz:
4039	case VREDUCEPHZ256rmi:
4040	case VREDUCEPHZ256rmik:
4041	case VREDUCEPHZ256rmikz:
4042	case VREDUCEPHZ256rri:
4043	case VREDUCEPHZ256rrik:
4044	case VREDUCEPHZ256rrikz:
4045	case VREDUCEPHZrmbi:
4046	case VREDUCEPHZrmbik:
4047	case VREDUCEPHZrmbikz:
4048	case VREDUCEPHZrmi:
4049	case VREDUCEPHZrmik:
4050	case VREDUCEPHZrmikz:
4051	case VREDUCEPHZrri:
4052	case VREDUCEPHZrrib:
4053	case VREDUCEPHZrribk:
4054	case VREDUCEPHZrribkz:
4055	case VREDUCEPHZrrik:
4056	case VREDUCEPHZrrikz:
4057		return true;
4058	}
4059	return false;
4060}
4061
4062bool isFXAM(unsigned Opcode) {
4063	return Opcode == XAM_F;
4064}
4065
4066bool isLGDTD(unsigned Opcode) {
4067	return Opcode == LGDT32m;
4068}
4069
4070bool isPMULHRW(unsigned Opcode) {
4071	switch (Opcode) {
4072	case PMULHRWrm:
4073	case PMULHRWrr:
4074		return true;
4075	}
4076	return false;
4077}
4078
4079bool isVREDUCEPS(unsigned Opcode) {
4080	switch (Opcode) {
4081	case VREDUCEPSZ128rmbi:
4082	case VREDUCEPSZ128rmbik:
4083	case VREDUCEPSZ128rmbikz:
4084	case VREDUCEPSZ128rmi:
4085	case VREDUCEPSZ128rmik:
4086	case VREDUCEPSZ128rmikz:
4087	case VREDUCEPSZ128rri:
4088	case VREDUCEPSZ128rrik:
4089	case VREDUCEPSZ128rrikz:
4090	case VREDUCEPSZ256rmbi:
4091	case VREDUCEPSZ256rmbik:
4092	case VREDUCEPSZ256rmbikz:
4093	case VREDUCEPSZ256rmi:
4094	case VREDUCEPSZ256rmik:
4095	case VREDUCEPSZ256rmikz:
4096	case VREDUCEPSZ256rri:
4097	case VREDUCEPSZ256rrik:
4098	case VREDUCEPSZ256rrikz:
4099	case VREDUCEPSZrmbi:
4100	case VREDUCEPSZrmbik:
4101	case VREDUCEPSZrmbikz:
4102	case VREDUCEPSZrmi:
4103	case VREDUCEPSZrmik:
4104	case VREDUCEPSZrmikz:
4105	case VREDUCEPSZrri:
4106	case VREDUCEPSZrrib:
4107	case VREDUCEPSZrribk:
4108	case VREDUCEPSZrribkz:
4109	case VREDUCEPSZrrik:
4110	case VREDUCEPSZrrikz:
4111		return true;
4112	}
4113	return false;
4114}
4115
4116bool isRDPMC(unsigned Opcode) {
4117	return Opcode == RDPMC;
4118}
4119
4120bool isVGATHERPF1QPD(unsigned Opcode) {
4121	return Opcode == VGATHERPF1QPDm;
4122}
4123
4124bool isLGDTW(unsigned Opcode) {
4125	return Opcode == LGDT16m;
4126}
4127
4128bool isVAESKEYGENASSIST(unsigned Opcode) {
4129	switch (Opcode) {
4130	case VAESKEYGENASSIST128rm:
4131	case VAESKEYGENASSIST128rr:
4132		return true;
4133	}
4134	return false;
4135}
4136
4137bool isRDFSBASE(unsigned Opcode) {
4138	switch (Opcode) {
4139	case RDFSBASE:
4140	case RDFSBASE64:
4141		return true;
4142	}
4143	return false;
4144}
4145
4146bool isVGATHERPF1QPS(unsigned Opcode) {
4147	return Opcode == VGATHERPF1QPSm;
4148}
4149
4150bool isSUBSD(unsigned Opcode) {
4151	switch (Opcode) {
4152	case SUBSDrm_Int:
4153	case SUBSDrr_Int:
4154		return true;
4155	}
4156	return false;
4157}
4158
4159bool isVCVTNEOBF162PS(unsigned Opcode) {
4160	switch (Opcode) {
4161	case VCVTNEOBF162PSYrm:
4162	case VCVTNEOBF162PSrm:
4163		return true;
4164	}
4165	return false;
4166}
4167
4168bool isAESENCWIDE128KL(unsigned Opcode) {
4169	return Opcode == AESENCWIDE128KL;
4170}
4171
4172bool isFXCH(unsigned Opcode) {
4173	return Opcode == XCH_F;
4174}
4175
4176bool isSUBSS(unsigned Opcode) {
4177	switch (Opcode) {
4178	case SUBSSrm_Int:
4179	case SUBSSrr_Int:
4180		return true;
4181	}
4182	return false;
4183}
4184
4185bool isPANDN(unsigned Opcode) {
4186	switch (Opcode) {
4187	case MMX_PANDNrm:
4188	case MMX_PANDNrr:
4189	case PANDNrm:
4190	case PANDNrr:
4191		return true;
4192	}
4193	return false;
4194}
4195
4196bool isVPERMT2B(unsigned Opcode) {
4197	switch (Opcode) {
4198	case VPERMT2B128rm:
4199	case VPERMT2B128rmk:
4200	case VPERMT2B128rmkz:
4201	case VPERMT2B128rr:
4202	case VPERMT2B128rrk:
4203	case VPERMT2B128rrkz:
4204	case VPERMT2B256rm:
4205	case VPERMT2B256rmk:
4206	case VPERMT2B256rmkz:
4207	case VPERMT2B256rr:
4208	case VPERMT2B256rrk:
4209	case VPERMT2B256rrkz:
4210	case VPERMT2Brm:
4211	case VPERMT2Brmk:
4212	case VPERMT2Brmkz:
4213	case VPERMT2Brr:
4214	case VPERMT2Brrk:
4215	case VPERMT2Brrkz:
4216		return true;
4217	}
4218	return false;
4219}
4220
4221bool isLJMP(unsigned Opcode) {
4222	switch (Opcode) {
4223	case FARJMP16i:
4224	case FARJMP16m:
4225	case FARJMP32i:
4226	case FARJMP64m:
4227		return true;
4228	}
4229	return false;
4230}
4231
4232bool isCMPPD(unsigned Opcode) {
4233	switch (Opcode) {
4234	case CMPPDrmi:
4235	case CMPPDrri:
4236		return true;
4237	}
4238	return false;
4239}
4240
4241bool isVPERMT2D(unsigned Opcode) {
4242	switch (Opcode) {
4243	case VPERMT2D128rm:
4244	case VPERMT2D128rmb:
4245	case VPERMT2D128rmbk:
4246	case VPERMT2D128rmbkz:
4247	case VPERMT2D128rmk:
4248	case VPERMT2D128rmkz:
4249	case VPERMT2D128rr:
4250	case VPERMT2D128rrk:
4251	case VPERMT2D128rrkz:
4252	case VPERMT2D256rm:
4253	case VPERMT2D256rmb:
4254	case VPERMT2D256rmbk:
4255	case VPERMT2D256rmbkz:
4256	case VPERMT2D256rmk:
4257	case VPERMT2D256rmkz:
4258	case VPERMT2D256rr:
4259	case VPERMT2D256rrk:
4260	case VPERMT2D256rrkz:
4261	case VPERMT2Drm:
4262	case VPERMT2Drmb:
4263	case VPERMT2Drmbk:
4264	case VPERMT2Drmbkz:
4265	case VPERMT2Drmk:
4266	case VPERMT2Drmkz:
4267	case VPERMT2Drr:
4268	case VPERMT2Drrk:
4269	case VPERMT2Drrkz:
4270		return true;
4271	}
4272	return false;
4273}
4274
4275bool isVPMADD52HUQ(unsigned Opcode) {
4276	switch (Opcode) {
4277	case VPMADD52HUQYrm:
4278	case VPMADD52HUQYrr:
4279	case VPMADD52HUQZ128m:
4280	case VPMADD52HUQZ128mb:
4281	case VPMADD52HUQZ128mbk:
4282	case VPMADD52HUQZ128mbkz:
4283	case VPMADD52HUQZ128mk:
4284	case VPMADD52HUQZ128mkz:
4285	case VPMADD52HUQZ128r:
4286	case VPMADD52HUQZ128rk:
4287	case VPMADD52HUQZ128rkz:
4288	case VPMADD52HUQZ256m:
4289	case VPMADD52HUQZ256mb:
4290	case VPMADD52HUQZ256mbk:
4291	case VPMADD52HUQZ256mbkz:
4292	case VPMADD52HUQZ256mk:
4293	case VPMADD52HUQZ256mkz:
4294	case VPMADD52HUQZ256r:
4295	case VPMADD52HUQZ256rk:
4296	case VPMADD52HUQZ256rkz:
4297	case VPMADD52HUQZm:
4298	case VPMADD52HUQZmb:
4299	case VPMADD52HUQZmbk:
4300	case VPMADD52HUQZmbkz:
4301	case VPMADD52HUQZmk:
4302	case VPMADD52HUQZmkz:
4303	case VPMADD52HUQZr:
4304	case VPMADD52HUQZrk:
4305	case VPMADD52HUQZrkz:
4306	case VPMADD52HUQrm:
4307	case VPMADD52HUQrr:
4308		return true;
4309	}
4310	return false;
4311}
4312
4313bool isVPERMT2Q(unsigned Opcode) {
4314	switch (Opcode) {
4315	case VPERMT2Q128rm:
4316	case VPERMT2Q128rmb:
4317	case VPERMT2Q128rmbk:
4318	case VPERMT2Q128rmbkz:
4319	case VPERMT2Q128rmk:
4320	case VPERMT2Q128rmkz:
4321	case VPERMT2Q128rr:
4322	case VPERMT2Q128rrk:
4323	case VPERMT2Q128rrkz:
4324	case VPERMT2Q256rm:
4325	case VPERMT2Q256rmb:
4326	case VPERMT2Q256rmbk:
4327	case VPERMT2Q256rmbkz:
4328	case VPERMT2Q256rmk:
4329	case VPERMT2Q256rmkz:
4330	case VPERMT2Q256rr:
4331	case VPERMT2Q256rrk:
4332	case VPERMT2Q256rrkz:
4333	case VPERMT2Qrm:
4334	case VPERMT2Qrmb:
4335	case VPERMT2Qrmbk:
4336	case VPERMT2Qrmbkz:
4337	case VPERMT2Qrmk:
4338	case VPERMT2Qrmkz:
4339	case VPERMT2Qrr:
4340	case VPERMT2Qrrk:
4341	case VPERMT2Qrrkz:
4342		return true;
4343	}
4344	return false;
4345}
4346
4347bool isCMPPS(unsigned Opcode) {
4348	switch (Opcode) {
4349	case CMPPSrmi:
4350	case CMPPSrri:
4351		return true;
4352	}
4353	return false;
4354}
4355
4356bool isVCVTPH2W(unsigned Opcode) {
4357	switch (Opcode) {
4358	case VCVTPH2WZ128rm:
4359	case VCVTPH2WZ128rmb:
4360	case VCVTPH2WZ128rmbk:
4361	case VCVTPH2WZ128rmbkz:
4362	case VCVTPH2WZ128rmk:
4363	case VCVTPH2WZ128rmkz:
4364	case VCVTPH2WZ128rr:
4365	case VCVTPH2WZ128rrk:
4366	case VCVTPH2WZ128rrkz:
4367	case VCVTPH2WZ256rm:
4368	case VCVTPH2WZ256rmb:
4369	case VCVTPH2WZ256rmbk:
4370	case VCVTPH2WZ256rmbkz:
4371	case VCVTPH2WZ256rmk:
4372	case VCVTPH2WZ256rmkz:
4373	case VCVTPH2WZ256rr:
4374	case VCVTPH2WZ256rrk:
4375	case VCVTPH2WZ256rrkz:
4376	case VCVTPH2WZrm:
4377	case VCVTPH2WZrmb:
4378	case VCVTPH2WZrmbk:
4379	case VCVTPH2WZrmbkz:
4380	case VCVTPH2WZrmk:
4381	case VCVTPH2WZrmkz:
4382	case VCVTPH2WZrr:
4383	case VCVTPH2WZrrb:
4384	case VCVTPH2WZrrbk:
4385	case VCVTPH2WZrrbkz:
4386	case VCVTPH2WZrrk:
4387	case VCVTPH2WZrrkz:
4388		return true;
4389	}
4390	return false;
4391}
4392
4393bool isVREDUCESD(unsigned Opcode) {
4394	switch (Opcode) {
4395	case VREDUCESDZrmi:
4396	case VREDUCESDZrmik:
4397	case VREDUCESDZrmikz:
4398	case VREDUCESDZrri:
4399	case VREDUCESDZrrib:
4400	case VREDUCESDZrribk:
4401	case VREDUCESDZrribkz:
4402	case VREDUCESDZrrik:
4403	case VREDUCESDZrrikz:
4404		return true;
4405	}
4406	return false;
4407}
4408
4409bool isVPERMT2W(unsigned Opcode) {
4410	switch (Opcode) {
4411	case VPERMT2W128rm:
4412	case VPERMT2W128rmk:
4413	case VPERMT2W128rmkz:
4414	case VPERMT2W128rr:
4415	case VPERMT2W128rrk:
4416	case VPERMT2W128rrkz:
4417	case VPERMT2W256rm:
4418	case VPERMT2W256rmk:
4419	case VPERMT2W256rmkz:
4420	case VPERMT2W256rr:
4421	case VPERMT2W256rrk:
4422	case VPERMT2W256rrkz:
4423	case VPERMT2Wrm:
4424	case VPERMT2Wrmk:
4425	case VPERMT2Wrmkz:
4426	case VPERMT2Wrr:
4427	case VPERMT2Wrrk:
4428	case VPERMT2Wrrkz:
4429		return true;
4430	}
4431	return false;
4432}
4433
4434bool isWBNOINVD(unsigned Opcode) {
4435	return Opcode == WBNOINVD;
4436}
4437
4438bool isVREDUCESH(unsigned Opcode) {
4439	switch (Opcode) {
4440	case VREDUCESHZrmi:
4441	case VREDUCESHZrmik:
4442	case VREDUCESHZrmikz:
4443	case VREDUCESHZrri:
4444	case VREDUCESHZrrib:
4445	case VREDUCESHZrribk:
4446	case VREDUCESHZrribkz:
4447	case VREDUCESHZrrik:
4448	case VREDUCESHZrrikz:
4449		return true;
4450	}
4451	return false;
4452}
4453
4454bool isTILEZERO(unsigned Opcode) {
4455	return Opcode == TILEZERO;
4456}
4457
4458bool isPMULHUW(unsigned Opcode) {
4459	switch (Opcode) {
4460	case MMX_PMULHUWrm:
4461	case MMX_PMULHUWrr:
4462	case PMULHUWrm:
4463	case PMULHUWrr:
4464		return true;
4465	}
4466	return false;
4467}
4468
4469bool isVREDUCESS(unsigned Opcode) {
4470	switch (Opcode) {
4471	case VREDUCESSZrmi:
4472	case VREDUCESSZrmik:
4473	case VREDUCESSZrmikz:
4474	case VREDUCESSZrri:
4475	case VREDUCESSZrrib:
4476	case VREDUCESSZrribk:
4477	case VREDUCESSZrribkz:
4478	case VREDUCESSZrrik:
4479	case VREDUCESSZrrikz:
4480		return true;
4481	}
4482	return false;
4483}
4484
4485bool isVCVTUW2PH(unsigned Opcode) {
4486	switch (Opcode) {
4487	case VCVTUW2PHZ128rm:
4488	case VCVTUW2PHZ128rmb:
4489	case VCVTUW2PHZ128rmbk:
4490	case VCVTUW2PHZ128rmbkz:
4491	case VCVTUW2PHZ128rmk:
4492	case VCVTUW2PHZ128rmkz:
4493	case VCVTUW2PHZ128rr:
4494	case VCVTUW2PHZ128rrk:
4495	case VCVTUW2PHZ128rrkz:
4496	case VCVTUW2PHZ256rm:
4497	case VCVTUW2PHZ256rmb:
4498	case VCVTUW2PHZ256rmbk:
4499	case VCVTUW2PHZ256rmbkz:
4500	case VCVTUW2PHZ256rmk:
4501	case VCVTUW2PHZ256rmkz:
4502	case VCVTUW2PHZ256rr:
4503	case VCVTUW2PHZ256rrk:
4504	case VCVTUW2PHZ256rrkz:
4505	case VCVTUW2PHZrm:
4506	case VCVTUW2PHZrmb:
4507	case VCVTUW2PHZrmbk:
4508	case VCVTUW2PHZrmbkz:
4509	case VCVTUW2PHZrmk:
4510	case VCVTUW2PHZrmkz:
4511	case VCVTUW2PHZrr:
4512	case VCVTUW2PHZrrb:
4513	case VCVTUW2PHZrrbk:
4514	case VCVTUW2PHZrrbkz:
4515	case VCVTUW2PHZrrk:
4516	case VCVTUW2PHZrrkz:
4517		return true;
4518	}
4519	return false;
4520}
4521
4522bool isVPBLENDMB(unsigned Opcode) {
4523	switch (Opcode) {
4524	case VPBLENDMBZ128rm:
4525	case VPBLENDMBZ128rmk:
4526	case VPBLENDMBZ128rmkz:
4527	case VPBLENDMBZ128rr:
4528	case VPBLENDMBZ128rrk:
4529	case VPBLENDMBZ128rrkz:
4530	case VPBLENDMBZ256rm:
4531	case VPBLENDMBZ256rmk:
4532	case VPBLENDMBZ256rmkz:
4533	case VPBLENDMBZ256rr:
4534	case VPBLENDMBZ256rrk:
4535	case VPBLENDMBZ256rrkz:
4536	case VPBLENDMBZrm:
4537	case VPBLENDMBZrmk:
4538	case VPBLENDMBZrmkz:
4539	case VPBLENDMBZrr:
4540	case VPBLENDMBZrrk:
4541	case VPBLENDMBZrrkz:
4542		return true;
4543	}
4544	return false;
4545}
4546
4547bool isVPBLENDMD(unsigned Opcode) {
4548	switch (Opcode) {
4549	case VPBLENDMDZ128rm:
4550	case VPBLENDMDZ128rmb:
4551	case VPBLENDMDZ128rmbk:
4552	case VPBLENDMDZ128rmbkz:
4553	case VPBLENDMDZ128rmk:
4554	case VPBLENDMDZ128rmkz:
4555	case VPBLENDMDZ128rr:
4556	case VPBLENDMDZ128rrk:
4557	case VPBLENDMDZ128rrkz:
4558	case VPBLENDMDZ256rm:
4559	case VPBLENDMDZ256rmb:
4560	case VPBLENDMDZ256rmbk:
4561	case VPBLENDMDZ256rmbkz:
4562	case VPBLENDMDZ256rmk:
4563	case VPBLENDMDZ256rmkz:
4564	case VPBLENDMDZ256rr:
4565	case VPBLENDMDZ256rrk:
4566	case VPBLENDMDZ256rrkz:
4567	case VPBLENDMDZrm:
4568	case VPBLENDMDZrmb:
4569	case VPBLENDMDZrmbk:
4570	case VPBLENDMDZrmbkz:
4571	case VPBLENDMDZrmk:
4572	case VPBLENDMDZrmkz:
4573	case VPBLENDMDZrr:
4574	case VPBLENDMDZrrk:
4575	case VPBLENDMDZrrkz:
4576		return true;
4577	}
4578	return false;
4579}
4580
4581bool isVFMSUB132PD(unsigned Opcode) {
4582	switch (Opcode) {
4583	case VFMSUB132PDYm:
4584	case VFMSUB132PDYr:
4585	case VFMSUB132PDZ128m:
4586	case VFMSUB132PDZ128mb:
4587	case VFMSUB132PDZ128mbk:
4588	case VFMSUB132PDZ128mbkz:
4589	case VFMSUB132PDZ128mk:
4590	case VFMSUB132PDZ128mkz:
4591	case VFMSUB132PDZ128r:
4592	case VFMSUB132PDZ128rk:
4593	case VFMSUB132PDZ128rkz:
4594	case VFMSUB132PDZ256m:
4595	case VFMSUB132PDZ256mb:
4596	case VFMSUB132PDZ256mbk:
4597	case VFMSUB132PDZ256mbkz:
4598	case VFMSUB132PDZ256mk:
4599	case VFMSUB132PDZ256mkz:
4600	case VFMSUB132PDZ256r:
4601	case VFMSUB132PDZ256rk:
4602	case VFMSUB132PDZ256rkz:
4603	case VFMSUB132PDZm:
4604	case VFMSUB132PDZmb:
4605	case VFMSUB132PDZmbk:
4606	case VFMSUB132PDZmbkz:
4607	case VFMSUB132PDZmk:
4608	case VFMSUB132PDZmkz:
4609	case VFMSUB132PDZr:
4610	case VFMSUB132PDZrb:
4611	case VFMSUB132PDZrbk:
4612	case VFMSUB132PDZrbkz:
4613	case VFMSUB132PDZrk:
4614	case VFMSUB132PDZrkz:
4615	case VFMSUB132PDm:
4616	case VFMSUB132PDr:
4617		return true;
4618	}
4619	return false;
4620}
4621
4622bool isVFMSUB132PH(unsigned Opcode) {
4623	switch (Opcode) {
4624	case VFMSUB132PHZ128m:
4625	case VFMSUB132PHZ128mb:
4626	case VFMSUB132PHZ128mbk:
4627	case VFMSUB132PHZ128mbkz:
4628	case VFMSUB132PHZ128mk:
4629	case VFMSUB132PHZ128mkz:
4630	case VFMSUB132PHZ128r:
4631	case VFMSUB132PHZ128rk:
4632	case VFMSUB132PHZ128rkz:
4633	case VFMSUB132PHZ256m:
4634	case VFMSUB132PHZ256mb:
4635	case VFMSUB132PHZ256mbk:
4636	case VFMSUB132PHZ256mbkz:
4637	case VFMSUB132PHZ256mk:
4638	case VFMSUB132PHZ256mkz:
4639	case VFMSUB132PHZ256r:
4640	case VFMSUB132PHZ256rk:
4641	case VFMSUB132PHZ256rkz:
4642	case VFMSUB132PHZm:
4643	case VFMSUB132PHZmb:
4644	case VFMSUB132PHZmbk:
4645	case VFMSUB132PHZmbkz:
4646	case VFMSUB132PHZmk:
4647	case VFMSUB132PHZmkz:
4648	case VFMSUB132PHZr:
4649	case VFMSUB132PHZrb:
4650	case VFMSUB132PHZrbk:
4651	case VFMSUB132PHZrbkz:
4652	case VFMSUB132PHZrk:
4653	case VFMSUB132PHZrkz:
4654		return true;
4655	}
4656	return false;
4657}
4658
4659bool isMWAIT(unsigned Opcode) {
4660	return Opcode == MWAITrr;
4661}
4662
4663bool isSALC(unsigned Opcode) {
4664	return Opcode == SALC;
4665}
4666
4667bool isPMADDUBSW(unsigned Opcode) {
4668	switch (Opcode) {
4669	case MMX_PMADDUBSWrm:
4670	case MMX_PMADDUBSWrr:
4671	case PMADDUBSWrm:
4672	case PMADDUBSWrr:
4673		return true;
4674	}
4675	return false;
4676}
4677
4678bool isVFCMULCPH(unsigned Opcode) {
4679	switch (Opcode) {
4680	case VFCMULCPHZ128rm:
4681	case VFCMULCPHZ128rmb:
4682	case VFCMULCPHZ128rmbk:
4683	case VFCMULCPHZ128rmbkz:
4684	case VFCMULCPHZ128rmk:
4685	case VFCMULCPHZ128rmkz:
4686	case VFCMULCPHZ128rr:
4687	case VFCMULCPHZ128rrk:
4688	case VFCMULCPHZ128rrkz:
4689	case VFCMULCPHZ256rm:
4690	case VFCMULCPHZ256rmb:
4691	case VFCMULCPHZ256rmbk:
4692	case VFCMULCPHZ256rmbkz:
4693	case VFCMULCPHZ256rmk:
4694	case VFCMULCPHZ256rmkz:
4695	case VFCMULCPHZ256rr:
4696	case VFCMULCPHZ256rrk:
4697	case VFCMULCPHZ256rrkz:
4698	case VFCMULCPHZrm:
4699	case VFCMULCPHZrmb:
4700	case VFCMULCPHZrmbk:
4701	case VFCMULCPHZrmbkz:
4702	case VFCMULCPHZrmk:
4703	case VFCMULCPHZrmkz:
4704	case VFCMULCPHZrr:
4705	case VFCMULCPHZrrb:
4706	case VFCMULCPHZrrbk:
4707	case VFCMULCPHZrrbkz:
4708	case VFCMULCPHZrrk:
4709	case VFCMULCPHZrrkz:
4710		return true;
4711	}
4712	return false;
4713}
4714
4715bool isVPBLENDMQ(unsigned Opcode) {
4716	switch (Opcode) {
4717	case VPBLENDMQZ128rm:
4718	case VPBLENDMQZ128rmb:
4719	case VPBLENDMQZ128rmbk:
4720	case VPBLENDMQZ128rmbkz:
4721	case VPBLENDMQZ128rmk:
4722	case VPBLENDMQZ128rmkz:
4723	case VPBLENDMQZ128rr:
4724	case VPBLENDMQZ128rrk:
4725	case VPBLENDMQZ128rrkz:
4726	case VPBLENDMQZ256rm:
4727	case VPBLENDMQZ256rmb:
4728	case VPBLENDMQZ256rmbk:
4729	case VPBLENDMQZ256rmbkz:
4730	case VPBLENDMQZ256rmk:
4731	case VPBLENDMQZ256rmkz:
4732	case VPBLENDMQZ256rr:
4733	case VPBLENDMQZ256rrk:
4734	case VPBLENDMQZ256rrkz:
4735	case VPBLENDMQZrm:
4736	case VPBLENDMQZrmb:
4737	case VPBLENDMQZrmbk:
4738	case VPBLENDMQZrmbkz:
4739	case VPBLENDMQZrmk:
4740	case VPBLENDMQZrmkz:
4741	case VPBLENDMQZrr:
4742	case VPBLENDMQZrrk:
4743	case VPBLENDMQZrrkz:
4744		return true;
4745	}
4746	return false;
4747}
4748
4749bool isRORX(unsigned Opcode) {
4750	switch (Opcode) {
4751	case RORX32mi:
4752	case RORX32ri:
4753	case RORX64mi:
4754	case RORX64ri:
4755		return true;
4756	}
4757	return false;
4758}
4759
4760bool isVFMSUB132PS(unsigned Opcode) {
4761	switch (Opcode) {
4762	case VFMSUB132PSYm:
4763	case VFMSUB132PSYr:
4764	case VFMSUB132PSZ128m:
4765	case VFMSUB132PSZ128mb:
4766	case VFMSUB132PSZ128mbk:
4767	case VFMSUB132PSZ128mbkz:
4768	case VFMSUB132PSZ128mk:
4769	case VFMSUB132PSZ128mkz:
4770	case VFMSUB132PSZ128r:
4771	case VFMSUB132PSZ128rk:
4772	case VFMSUB132PSZ128rkz:
4773	case VFMSUB132PSZ256m:
4774	case VFMSUB132PSZ256mb:
4775	case VFMSUB132PSZ256mbk:
4776	case VFMSUB132PSZ256mbkz:
4777	case VFMSUB132PSZ256mk:
4778	case VFMSUB132PSZ256mkz:
4779	case VFMSUB132PSZ256r:
4780	case VFMSUB132PSZ256rk:
4781	case VFMSUB132PSZ256rkz:
4782	case VFMSUB132PSZm:
4783	case VFMSUB132PSZmb:
4784	case VFMSUB132PSZmbk:
4785	case VFMSUB132PSZmbkz:
4786	case VFMSUB132PSZmk:
4787	case VFMSUB132PSZmkz:
4788	case VFMSUB132PSZr:
4789	case VFMSUB132PSZrb:
4790	case VFMSUB132PSZrbk:
4791	case VFMSUB132PSZrbkz:
4792	case VFMSUB132PSZrk:
4793	case VFMSUB132PSZrkz:
4794	case VFMSUB132PSm:
4795	case VFMSUB132PSr:
4796		return true;
4797	}
4798	return false;
4799}
4800
4801bool isVPBLENDMW(unsigned Opcode) {
4802	switch (Opcode) {
4803	case VPBLENDMWZ128rm:
4804	case VPBLENDMWZ128rmk:
4805	case VPBLENDMWZ128rmkz:
4806	case VPBLENDMWZ128rr:
4807	case VPBLENDMWZ128rrk:
4808	case VPBLENDMWZ128rrkz:
4809	case VPBLENDMWZ256rm:
4810	case VPBLENDMWZ256rmk:
4811	case VPBLENDMWZ256rmkz:
4812	case VPBLENDMWZ256rr:
4813	case VPBLENDMWZ256rrk:
4814	case VPBLENDMWZ256rrkz:
4815	case VPBLENDMWZrm:
4816	case VPBLENDMWZrmk:
4817	case VPBLENDMWZrmkz:
4818	case VPBLENDMWZrr:
4819	case VPBLENDMWZrrk:
4820	case VPBLENDMWZrrkz:
4821		return true;
4822	}
4823	return false;
4824}
4825
4826bool isMOV(unsigned Opcode) {
4827	switch (Opcode) {
4828	case MOV16ao16:
4829	case MOV16ao32:
4830	case MOV16mi:
4831	case MOV16mr:
4832	case MOV16ms:
4833	case MOV16o16a:
4834	case MOV16o32a:
4835	case MOV16ri:
4836	case MOV16ri_alt:
4837	case MOV16rm:
4838	case MOV16rr:
4839	case MOV16rr_REV:
4840	case MOV16rs:
4841	case MOV16sm:
4842	case MOV16sr:
4843	case MOV32ao16:
4844	case MOV32ao32:
4845	case MOV32cr:
4846	case MOV32dr:
4847	case MOV32mi:
4848	case MOV32mr:
4849	case MOV32o16a:
4850	case MOV32o32a:
4851	case MOV32rc:
4852	case MOV32rd:
4853	case MOV32ri:
4854	case MOV32ri_alt:
4855	case MOV32rm:
4856	case MOV32rr:
4857	case MOV32rr_REV:
4858	case MOV32rs:
4859	case MOV32sr:
4860	case MOV64ao32:
4861	case MOV64cr:
4862	case MOV64dr:
4863	case MOV64mi32:
4864	case MOV64mr:
4865	case MOV64o32a:
4866	case MOV64rc:
4867	case MOV64rd:
4868	case MOV64ri32:
4869	case MOV64rm:
4870	case MOV64rr:
4871	case MOV64rr_REV:
4872	case MOV64rs:
4873	case MOV64sr:
4874	case MOV8ao16:
4875	case MOV8ao32:
4876	case MOV8mi:
4877	case MOV8mr:
4878	case MOV8o16a:
4879	case MOV8o32a:
4880	case MOV8ri:
4881	case MOV8ri_alt:
4882	case MOV8rm:
4883	case MOV8rr:
4884	case MOV8rr_REV:
4885		return true;
4886	}
4887	return false;
4888}
4889
4890bool isFXSAVE64(unsigned Opcode) {
4891	return Opcode == FXSAVE64;
4892}
4893
4894bool isRMPADJUST(unsigned Opcode) {
4895	return Opcode == RMPADJUST;
4896}
4897
4898bool isAADD(unsigned Opcode) {
4899	switch (Opcode) {
4900	case AADD32mr:
4901	case AADD64mr:
4902		return true;
4903	}
4904	return false;
4905}
4906
4907bool isVLDDQU(unsigned Opcode) {
4908	switch (Opcode) {
4909	case VLDDQUYrm:
4910	case VLDDQUrm:
4911		return true;
4912	}
4913	return false;
4914}
4915
4916bool isVPSCATTERQD(unsigned Opcode) {
4917	switch (Opcode) {
4918	case VPSCATTERQDZ128mr:
4919	case VPSCATTERQDZ256mr:
4920	case VPSCATTERQDZmr:
4921		return true;
4922	}
4923	return false;
4924}
4925
4926bool isVPHADDUBD(unsigned Opcode) {
4927	switch (Opcode) {
4928	case VPHADDUBDrm:
4929	case VPHADDUBDrr:
4930		return true;
4931	}
4932	return false;
4933}
4934
4935bool isCMPSB(unsigned Opcode) {
4936	return Opcode == CMPSB;
4937}
4938
4939bool isCMPSD(unsigned Opcode) {
4940	switch (Opcode) {
4941	case CMPSDrm_Int:
4942	case CMPSDrr_Int:
4943	case CMPSL:
4944		return true;
4945	}
4946	return false;
4947}
4948
4949bool isSTGI(unsigned Opcode) {
4950	return Opcode == STGI;
4951}
4952
4953bool isVUNPCKLPD(unsigned Opcode) {
4954	switch (Opcode) {
4955	case VUNPCKLPDYrm:
4956	case VUNPCKLPDYrr:
4957	case VUNPCKLPDZ128rm:
4958	case VUNPCKLPDZ128rmb:
4959	case VUNPCKLPDZ128rmbk:
4960	case VUNPCKLPDZ128rmbkz:
4961	case VUNPCKLPDZ128rmk:
4962	case VUNPCKLPDZ128rmkz:
4963	case VUNPCKLPDZ128rr:
4964	case VUNPCKLPDZ128rrk:
4965	case VUNPCKLPDZ128rrkz:
4966	case VUNPCKLPDZ256rm:
4967	case VUNPCKLPDZ256rmb:
4968	case VUNPCKLPDZ256rmbk:
4969	case VUNPCKLPDZ256rmbkz:
4970	case VUNPCKLPDZ256rmk:
4971	case VUNPCKLPDZ256rmkz:
4972	case VUNPCKLPDZ256rr:
4973	case VUNPCKLPDZ256rrk:
4974	case VUNPCKLPDZ256rrkz:
4975	case VUNPCKLPDZrm:
4976	case VUNPCKLPDZrmb:
4977	case VUNPCKLPDZrmbk:
4978	case VUNPCKLPDZrmbkz:
4979	case VUNPCKLPDZrmk:
4980	case VUNPCKLPDZrmkz:
4981	case VUNPCKLPDZrr:
4982	case VUNPCKLPDZrrk:
4983	case VUNPCKLPDZrrkz:
4984	case VUNPCKLPDrm:
4985	case VUNPCKLPDrr:
4986		return true;
4987	}
4988	return false;
4989}
4990
4991bool isVPSCATTERQQ(unsigned Opcode) {
4992	switch (Opcode) {
4993	case VPSCATTERQQZ128mr:
4994	case VPSCATTERQQZ256mr:
4995	case VPSCATTERQQZmr:
4996		return true;
4997	}
4998	return false;
4999}
5000
5001bool isFADDP(unsigned Opcode) {
5002	return Opcode == ADD_FPrST0;
5003}
5004
5005bool isVPHADDUBQ(unsigned Opcode) {
5006	switch (Opcode) {
5007	case VPHADDUBQrm:
5008	case VPHADDUBQrr:
5009		return true;
5010	}
5011	return false;
5012}
5013
5014bool isCMPSQ(unsigned Opcode) {
5015	return Opcode == CMPSQ;
5016}
5017
5018bool isVPHADDUBW(unsigned Opcode) {
5019	switch (Opcode) {
5020	case VPHADDUBWrm:
5021	case VPHADDUBWrr:
5022		return true;
5023	}
5024	return false;
5025}
5026
5027bool isCMPSS(unsigned Opcode) {
5028	switch (Opcode) {
5029	case CMPSSrm_Int:
5030	case CMPSSrr_Int:
5031		return true;
5032	}
5033	return false;
5034}
5035
5036bool isVUNPCKLPS(unsigned Opcode) {
5037	switch (Opcode) {
5038	case VUNPCKLPSYrm:
5039	case VUNPCKLPSYrr:
5040	case VUNPCKLPSZ128rm:
5041	case VUNPCKLPSZ128rmb:
5042	case VUNPCKLPSZ128rmbk:
5043	case VUNPCKLPSZ128rmbkz:
5044	case VUNPCKLPSZ128rmk:
5045	case VUNPCKLPSZ128rmkz:
5046	case VUNPCKLPSZ128rr:
5047	case VUNPCKLPSZ128rrk:
5048	case VUNPCKLPSZ128rrkz:
5049	case VUNPCKLPSZ256rm:
5050	case VUNPCKLPSZ256rmb:
5051	case VUNPCKLPSZ256rmbk:
5052	case VUNPCKLPSZ256rmbkz:
5053	case VUNPCKLPSZ256rmk:
5054	case VUNPCKLPSZ256rmkz:
5055	case VUNPCKLPSZ256rr:
5056	case VUNPCKLPSZ256rrk:
5057	case VUNPCKLPSZ256rrkz:
5058	case VUNPCKLPSZrm:
5059	case VUNPCKLPSZrmb:
5060	case VUNPCKLPSZrmbk:
5061	case VUNPCKLPSZrmbkz:
5062	case VUNPCKLPSZrmk:
5063	case VUNPCKLPSZrmkz:
5064	case VUNPCKLPSZrr:
5065	case VUNPCKLPSZrrk:
5066	case VUNPCKLPSZrrkz:
5067	case VUNPCKLPSrm:
5068	case VUNPCKLPSrr:
5069		return true;
5070	}
5071	return false;
5072}
5073
5074bool isLCALL(unsigned Opcode) {
5075	switch (Opcode) {
5076	case FARCALL16i:
5077	case FARCALL16m:
5078	case FARCALL32i:
5079	case FARCALL64m:
5080		return true;
5081	}
5082	return false;
5083}
5084
5085bool isPSHUFB(unsigned Opcode) {
5086	switch (Opcode) {
5087	case MMX_PSHUFBrm:
5088	case MMX_PSHUFBrr:
5089	case PSHUFBrm:
5090	case PSHUFBrr:
5091		return true;
5092	}
5093	return false;
5094}
5095
5096bool isCMPSW(unsigned Opcode) {
5097	return Opcode == CMPSW;
5098}
5099
5100bool isPSHUFD(unsigned Opcode) {
5101	switch (Opcode) {
5102	case PSHUFDmi:
5103	case PSHUFDri:
5104		return true;
5105	}
5106	return false;
5107}
5108
5109bool isRDPRU(unsigned Opcode) {
5110	return Opcode == RDPRU;
5111}
5112
5113bool isFRNDINT(unsigned Opcode) {
5114	return Opcode == FRNDINT;
5115}
5116
5117bool isVPACKUSWB(unsigned Opcode) {
5118	switch (Opcode) {
5119	case VPACKUSWBYrm:
5120	case VPACKUSWBYrr:
5121	case VPACKUSWBZ128rm:
5122	case VPACKUSWBZ128rmk:
5123	case VPACKUSWBZ128rmkz:
5124	case VPACKUSWBZ128rr:
5125	case VPACKUSWBZ128rrk:
5126	case VPACKUSWBZ128rrkz:
5127	case VPACKUSWBZ256rm:
5128	case VPACKUSWBZ256rmk:
5129	case VPACKUSWBZ256rmkz:
5130	case VPACKUSWBZ256rr:
5131	case VPACKUSWBZ256rrk:
5132	case VPACKUSWBZ256rrkz:
5133	case VPACKUSWBZrm:
5134	case VPACKUSWBZrmk:
5135	case VPACKUSWBZrmkz:
5136	case VPACKUSWBZrr:
5137	case VPACKUSWBZrrk:
5138	case VPACKUSWBZrrkz:
5139	case VPACKUSWBrm:
5140	case VPACKUSWBrr:
5141		return true;
5142	}
5143	return false;
5144}
5145
5146bool isDIVPD(unsigned Opcode) {
5147	switch (Opcode) {
5148	case DIVPDrm:
5149	case DIVPDrr:
5150		return true;
5151	}
5152	return false;
5153}
5154
5155bool isVAESDEC(unsigned Opcode) {
5156	switch (Opcode) {
5157	case VAESDECYrm:
5158	case VAESDECYrr:
5159	case VAESDECZ128rm:
5160	case VAESDECZ128rr:
5161	case VAESDECZ256rm:
5162	case VAESDECZ256rr:
5163	case VAESDECZrm:
5164	case VAESDECZrr:
5165	case VAESDECrm:
5166	case VAESDECrr:
5167		return true;
5168	}
5169	return false;
5170}
5171
5172bool isPSHUFW(unsigned Opcode) {
5173	switch (Opcode) {
5174	case MMX_PSHUFWmi:
5175	case MMX_PSHUFWri:
5176		return true;
5177	}
5178	return false;
5179}
5180
5181bool isVPDPBUUDS(unsigned Opcode) {
5182	switch (Opcode) {
5183	case VPDPBUUDSYrm:
5184	case VPDPBUUDSYrr:
5185	case VPDPBUUDSrm:
5186	case VPDPBUUDSrr:
5187		return true;
5188	}
5189	return false;
5190}
5191
5192bool isKMOVB(unsigned Opcode) {
5193	switch (Opcode) {
5194	case KMOVBkk:
5195	case KMOVBkm:
5196	case KMOVBkr:
5197	case KMOVBmk:
5198	case KMOVBrk:
5199		return true;
5200	}
5201	return false;
5202}
5203
5204bool isVFMSUB132SD(unsigned Opcode) {
5205	switch (Opcode) {
5206	case VFMSUB132SDZm_Int:
5207	case VFMSUB132SDZm_Intk:
5208	case VFMSUB132SDZm_Intkz:
5209	case VFMSUB132SDZr_Int:
5210	case VFMSUB132SDZr_Intk:
5211	case VFMSUB132SDZr_Intkz:
5212	case VFMSUB132SDZrb_Int:
5213	case VFMSUB132SDZrb_Intk:
5214	case VFMSUB132SDZrb_Intkz:
5215	case VFMSUB132SDm_Int:
5216	case VFMSUB132SDr_Int:
5217		return true;
5218	}
5219	return false;
5220}
5221
5222bool isKMOVD(unsigned Opcode) {
5223	switch (Opcode) {
5224	case KMOVDkk:
5225	case KMOVDkm:
5226	case KMOVDkr:
5227	case KMOVDmk:
5228	case KMOVDrk:
5229		return true;
5230	}
5231	return false;
5232}
5233
5234bool isVCVTTPS2UQQ(unsigned Opcode) {
5235	switch (Opcode) {
5236	case VCVTTPS2UQQZ128rm:
5237	case VCVTTPS2UQQZ128rmb:
5238	case VCVTTPS2UQQZ128rmbk:
5239	case VCVTTPS2UQQZ128rmbkz:
5240	case VCVTTPS2UQQZ128rmk:
5241	case VCVTTPS2UQQZ128rmkz:
5242	case VCVTTPS2UQQZ128rr:
5243	case VCVTTPS2UQQZ128rrk:
5244	case VCVTTPS2UQQZ128rrkz:
5245	case VCVTTPS2UQQZ256rm:
5246	case VCVTTPS2UQQZ256rmb:
5247	case VCVTTPS2UQQZ256rmbk:
5248	case VCVTTPS2UQQZ256rmbkz:
5249	case VCVTTPS2UQQZ256rmk:
5250	case VCVTTPS2UQQZ256rmkz:
5251	case VCVTTPS2UQQZ256rr:
5252	case VCVTTPS2UQQZ256rrk:
5253	case VCVTTPS2UQQZ256rrkz:
5254	case VCVTTPS2UQQZrm:
5255	case VCVTTPS2UQQZrmb:
5256	case VCVTTPS2UQQZrmbk:
5257	case VCVTTPS2UQQZrmbkz:
5258	case VCVTTPS2UQQZrmk:
5259	case VCVTTPS2UQQZrmkz:
5260	case VCVTTPS2UQQZrr:
5261	case VCVTTPS2UQQZrrb:
5262	case VCVTTPS2UQQZrrbk:
5263	case VCVTTPS2UQQZrrbkz:
5264	case VCVTTPS2UQQZrrk:
5265	case VCVTTPS2UQQZrrkz:
5266		return true;
5267	}
5268	return false;
5269}
5270
5271bool isVFMSUB132SH(unsigned Opcode) {
5272	switch (Opcode) {
5273	case VFMSUB132SHZm_Int:
5274	case VFMSUB132SHZm_Intk:
5275	case VFMSUB132SHZm_Intkz:
5276	case VFMSUB132SHZr_Int:
5277	case VFMSUB132SHZr_Intk:
5278	case VFMSUB132SHZr_Intkz:
5279	case VFMSUB132SHZrb_Int:
5280	case VFMSUB132SHZrb_Intk:
5281	case VFMSUB132SHZrb_Intkz:
5282		return true;
5283	}
5284	return false;
5285}
5286
5287bool isDIVPS(unsigned Opcode) {
5288	switch (Opcode) {
5289	case DIVPSrm:
5290	case DIVPSrr:
5291		return true;
5292	}
5293	return false;
5294}
5295
5296bool isVFCMULCSH(unsigned Opcode) {
5297	switch (Opcode) {
5298	case VFCMULCSHZrm:
5299	case VFCMULCSHZrmk:
5300	case VFCMULCSHZrmkz:
5301	case VFCMULCSHZrr:
5302	case VFCMULCSHZrrb:
5303	case VFCMULCSHZrrbk:
5304	case VFCMULCSHZrrbkz:
5305	case VFCMULCSHZrrk:
5306	case VFCMULCSHZrrkz:
5307		return true;
5308	}
5309	return false;
5310}
5311
5312bool isFICOM(unsigned Opcode) {
5313	switch (Opcode) {
5314	case FICOM16m:
5315	case FICOM32m:
5316		return true;
5317	}
5318	return false;
5319}
5320
5321bool isKMOVQ(unsigned Opcode) {
5322	switch (Opcode) {
5323	case KMOVQkk:
5324	case KMOVQkm:
5325	case KMOVQkr:
5326	case KMOVQmk:
5327	case KMOVQrk:
5328		return true;
5329	}
5330	return false;
5331}
5332
5333bool isVFMSUB132SS(unsigned Opcode) {
5334	switch (Opcode) {
5335	case VFMSUB132SSZm_Int:
5336	case VFMSUB132SSZm_Intk:
5337	case VFMSUB132SSZm_Intkz:
5338	case VFMSUB132SSZr_Int:
5339	case VFMSUB132SSZr_Intk:
5340	case VFMSUB132SSZr_Intkz:
5341	case VFMSUB132SSZrb_Int:
5342	case VFMSUB132SSZrb_Intk:
5343	case VFMSUB132SSZrb_Intkz:
5344	case VFMSUB132SSm_Int:
5345	case VFMSUB132SSr_Int:
5346		return true;
5347	}
5348	return false;
5349}
5350
5351bool isENCODEKEY128(unsigned Opcode) {
5352	return Opcode == ENCODEKEY128;
5353}
5354
5355bool isKMOVW(unsigned Opcode) {
5356	switch (Opcode) {
5357	case KMOVWkk:
5358	case KMOVWkm:
5359	case KMOVWkr:
5360	case KMOVWmk:
5361	case KMOVWrk:
5362		return true;
5363	}
5364	return false;
5365}
5366
5367bool isPREFETCHT0(unsigned Opcode) {
5368	return Opcode == PREFETCHT0;
5369}
5370
5371bool isPREFETCHT1(unsigned Opcode) {
5372	return Opcode == PREFETCHT1;
5373}
5374
5375bool isPREFETCHT2(unsigned Opcode) {
5376	return Opcode == PREFETCHT2;
5377}
5378
5379bool isSWAPGS(unsigned Opcode) {
5380	return Opcode == SWAPGS;
5381}
5382
5383bool isVPTESTMD(unsigned Opcode) {
5384	switch (Opcode) {
5385	case VPTESTMDZ128rm:
5386	case VPTESTMDZ128rmb:
5387	case VPTESTMDZ128rmbk:
5388	case VPTESTMDZ128rmk:
5389	case VPTESTMDZ128rr:
5390	case VPTESTMDZ128rrk:
5391	case VPTESTMDZ256rm:
5392	case VPTESTMDZ256rmb:
5393	case VPTESTMDZ256rmbk:
5394	case VPTESTMDZ256rmk:
5395	case VPTESTMDZ256rr:
5396	case VPTESTMDZ256rrk:
5397	case VPTESTMDZrm:
5398	case VPTESTMDZrmb:
5399	case VPTESTMDZrmbk:
5400	case VPTESTMDZrmk:
5401	case VPTESTMDZrr:
5402	case VPTESTMDZrrk:
5403		return true;
5404	}
5405	return false;
5406}
5407
5408bool isVPTESTMB(unsigned Opcode) {
5409	switch (Opcode) {
5410	case VPTESTMBZ128rm:
5411	case VPTESTMBZ128rmk:
5412	case VPTESTMBZ128rr:
5413	case VPTESTMBZ128rrk:
5414	case VPTESTMBZ256rm:
5415	case VPTESTMBZ256rmk:
5416	case VPTESTMBZ256rr:
5417	case VPTESTMBZ256rrk:
5418	case VPTESTMBZrm:
5419	case VPTESTMBZrmk:
5420	case VPTESTMBZrr:
5421	case VPTESTMBZrrk:
5422		return true;
5423	}
5424	return false;
5425}
5426
5427bool isVPHADDUDQ(unsigned Opcode) {
5428	switch (Opcode) {
5429	case VPHADDUDQrm:
5430	case VPHADDUDQrr:
5431		return true;
5432	}
5433	return false;
5434}
5435
5436bool isVPTESTMQ(unsigned Opcode) {
5437	switch (Opcode) {
5438	case VPTESTMQZ128rm:
5439	case VPTESTMQZ128rmb:
5440	case VPTESTMQZ128rmbk:
5441	case VPTESTMQZ128rmk:
5442	case VPTESTMQZ128rr:
5443	case VPTESTMQZ128rrk:
5444	case VPTESTMQZ256rm:
5445	case VPTESTMQZ256rmb:
5446	case VPTESTMQZ256rmbk:
5447	case VPTESTMQZ256rmk:
5448	case VPTESTMQZ256rr:
5449	case VPTESTMQZ256rrk:
5450	case VPTESTMQZrm:
5451	case VPTESTMQZrmb:
5452	case VPTESTMQZrmbk:
5453	case VPTESTMQZrmk:
5454	case VPTESTMQZrr:
5455	case VPTESTMQZrrk:
5456		return true;
5457	}
5458	return false;
5459}
5460
5461bool isXRSTORS(unsigned Opcode) {
5462	return Opcode == XRSTORS;
5463}
5464
5465bool isVPMULDQ(unsigned Opcode) {
5466	switch (Opcode) {
5467	case VPMULDQYrm:
5468	case VPMULDQYrr:
5469	case VPMULDQZ128rm:
5470	case VPMULDQZ128rmb:
5471	case VPMULDQZ128rmbk:
5472	case VPMULDQZ128rmbkz:
5473	case VPMULDQZ128rmk:
5474	case VPMULDQZ128rmkz:
5475	case VPMULDQZ128rr:
5476	case VPMULDQZ128rrk:
5477	case VPMULDQZ128rrkz:
5478	case VPMULDQZ256rm:
5479	case VPMULDQZ256rmb:
5480	case VPMULDQZ256rmbk:
5481	case VPMULDQZ256rmbkz:
5482	case VPMULDQZ256rmk:
5483	case VPMULDQZ256rmkz:
5484	case VPMULDQZ256rr:
5485	case VPMULDQZ256rrk:
5486	case VPMULDQZ256rrkz:
5487	case VPMULDQZrm:
5488	case VPMULDQZrmb:
5489	case VPMULDQZrmbk:
5490	case VPMULDQZrmbkz:
5491	case VPMULDQZrmk:
5492	case VPMULDQZrmkz:
5493	case VPMULDQZrr:
5494	case VPMULDQZrrk:
5495	case VPMULDQZrrkz:
5496	case VPMULDQrm:
5497	case VPMULDQrr:
5498		return true;
5499	}
5500	return false;
5501}
5502
5503bool isUD1(unsigned Opcode) {
5504	switch (Opcode) {
5505	case UD1Lm:
5506	case UD1Lr:
5507	case UD1Qm:
5508	case UD1Qr:
5509	case UD1Wm:
5510	case UD1Wr:
5511		return true;
5512	}
5513	return false;
5514}
5515
5516bool isUD2(unsigned Opcode) {
5517	return Opcode == TRAP;
5518}
5519
5520bool isVPTESTMW(unsigned Opcode) {
5521	switch (Opcode) {
5522	case VPTESTMWZ128rm:
5523	case VPTESTMWZ128rmk:
5524	case VPTESTMWZ128rr:
5525	case VPTESTMWZ128rrk:
5526	case VPTESTMWZ256rm:
5527	case VPTESTMWZ256rmk:
5528	case VPTESTMWZ256rr:
5529	case VPTESTMWZ256rrk:
5530	case VPTESTMWZrm:
5531	case VPTESTMWZrmk:
5532	case VPTESTMWZrr:
5533	case VPTESTMWZrrk:
5534		return true;
5535	}
5536	return false;
5537}
5538
5539bool isSEAMOPS(unsigned Opcode) {
5540	return Opcode == SEAMOPS;
5541}
5542
5543bool isMWAITX(unsigned Opcode) {
5544	return Opcode == MWAITXrrr;
5545}
5546
5547bool isVFMADD132PD(unsigned Opcode) {
5548	switch (Opcode) {
5549	case VFMADD132PDYm:
5550	case VFMADD132PDYr:
5551	case VFMADD132PDZ128m:
5552	case VFMADD132PDZ128mb:
5553	case VFMADD132PDZ128mbk:
5554	case VFMADD132PDZ128mbkz:
5555	case VFMADD132PDZ128mk:
5556	case VFMADD132PDZ128mkz:
5557	case VFMADD132PDZ128r:
5558	case VFMADD132PDZ128rk:
5559	case VFMADD132PDZ128rkz:
5560	case VFMADD132PDZ256m:
5561	case VFMADD132PDZ256mb:
5562	case VFMADD132PDZ256mbk:
5563	case VFMADD132PDZ256mbkz:
5564	case VFMADD132PDZ256mk:
5565	case VFMADD132PDZ256mkz:
5566	case VFMADD132PDZ256r:
5567	case VFMADD132PDZ256rk:
5568	case VFMADD132PDZ256rkz:
5569	case VFMADD132PDZm:
5570	case VFMADD132PDZmb:
5571	case VFMADD132PDZmbk:
5572	case VFMADD132PDZmbkz:
5573	case VFMADD132PDZmk:
5574	case VFMADD132PDZmkz:
5575	case VFMADD132PDZr:
5576	case VFMADD132PDZrb:
5577	case VFMADD132PDZrbk:
5578	case VFMADD132PDZrbkz:
5579	case VFMADD132PDZrk:
5580	case VFMADD132PDZrkz:
5581	case VFMADD132PDm:
5582	case VFMADD132PDr:
5583		return true;
5584	}
5585	return false;
5586}
5587
5588bool isWRMSRNS(unsigned Opcode) {
5589	return Opcode == WRMSRNS;
5590}
5591
5592bool isVMOVNTDQ(unsigned Opcode) {
5593	switch (Opcode) {
5594	case VMOVNTDQYmr:
5595	case VMOVNTDQZ128mr:
5596	case VMOVNTDQZ256mr:
5597	case VMOVNTDQZmr:
5598	case VMOVNTDQmr:
5599		return true;
5600	}
5601	return false;
5602}
5603
5604bool isVFMADD132PH(unsigned Opcode) {
5605	switch (Opcode) {
5606	case VFMADD132PHZ128m:
5607	case VFMADD132PHZ128mb:
5608	case VFMADD132PHZ128mbk:
5609	case VFMADD132PHZ128mbkz:
5610	case VFMADD132PHZ128mk:
5611	case VFMADD132PHZ128mkz:
5612	case VFMADD132PHZ128r:
5613	case VFMADD132PHZ128rk:
5614	case VFMADD132PHZ128rkz:
5615	case VFMADD132PHZ256m:
5616	case VFMADD132PHZ256mb:
5617	case VFMADD132PHZ256mbk:
5618	case VFMADD132PHZ256mbkz:
5619	case VFMADD132PHZ256mk:
5620	case VFMADD132PHZ256mkz:
5621	case VFMADD132PHZ256r:
5622	case VFMADD132PHZ256rk:
5623	case VFMADD132PHZ256rkz:
5624	case VFMADD132PHZm:
5625	case VFMADD132PHZmb:
5626	case VFMADD132PHZmbk:
5627	case VFMADD132PHZmbkz:
5628	case VFMADD132PHZmk:
5629	case VFMADD132PHZmkz:
5630	case VFMADD132PHZr:
5631	case VFMADD132PHZrb:
5632	case VFMADD132PHZrbk:
5633	case VFMADD132PHZrbkz:
5634	case VFMADD132PHZrk:
5635	case VFMADD132PHZrkz:
5636		return true;
5637	}
5638	return false;
5639}
5640
5641bool isPSRLD(unsigned Opcode) {
5642	switch (Opcode) {
5643	case MMX_PSRLDri:
5644	case MMX_PSRLDrm:
5645	case MMX_PSRLDrr:
5646	case PSRLDri:
5647	case PSRLDrm:
5648	case PSRLDrr:
5649		return true;
5650	}
5651	return false;
5652}
5653
5654bool isVBROADCASTI64X2(unsigned Opcode) {
5655	switch (Opcode) {
5656	case VBROADCASTI64X2Z128rm:
5657	case VBROADCASTI64X2Z128rmk:
5658	case VBROADCASTI64X2Z128rmkz:
5659	case VBROADCASTI64X2rm:
5660	case VBROADCASTI64X2rmk:
5661	case VBROADCASTI64X2rmkz:
5662		return true;
5663	}
5664	return false;
5665}
5666
5667bool isVBROADCASTI64X4(unsigned Opcode) {
5668	switch (Opcode) {
5669	case VBROADCASTI64X4rm:
5670	case VBROADCASTI64X4rmk:
5671	case VBROADCASTI64X4rmkz:
5672		return true;
5673	}
5674	return false;
5675}
5676
5677bool isVFMADD132PS(unsigned Opcode) {
5678	switch (Opcode) {
5679	case VFMADD132PSYm:
5680	case VFMADD132PSYr:
5681	case VFMADD132PSZ128m:
5682	case VFMADD132PSZ128mb:
5683	case VFMADD132PSZ128mbk:
5684	case VFMADD132PSZ128mbkz:
5685	case VFMADD132PSZ128mk:
5686	case VFMADD132PSZ128mkz:
5687	case VFMADD132PSZ128r:
5688	case VFMADD132PSZ128rk:
5689	case VFMADD132PSZ128rkz:
5690	case VFMADD132PSZ256m:
5691	case VFMADD132PSZ256mb:
5692	case VFMADD132PSZ256mbk:
5693	case VFMADD132PSZ256mbkz:
5694	case VFMADD132PSZ256mk:
5695	case VFMADD132PSZ256mkz:
5696	case VFMADD132PSZ256r:
5697	case VFMADD132PSZ256rk:
5698	case VFMADD132PSZ256rkz:
5699	case VFMADD132PSZm:
5700	case VFMADD132PSZmb:
5701	case VFMADD132PSZmbk:
5702	case VFMADD132PSZmbkz:
5703	case VFMADD132PSZmk:
5704	case VFMADD132PSZmkz:
5705	case VFMADD132PSZr:
5706	case VFMADD132PSZrb:
5707	case VFMADD132PSZrbk:
5708	case VFMADD132PSZrbkz:
5709	case VFMADD132PSZrk:
5710	case VFMADD132PSZrkz:
5711	case VFMADD132PSm:
5712	case VFMADD132PSr:
5713		return true;
5714	}
5715	return false;
5716}
5717
5718bool isIDIV(unsigned Opcode) {
5719	switch (Opcode) {
5720	case IDIV16m:
5721	case IDIV16r:
5722	case IDIV32m:
5723	case IDIV32r:
5724	case IDIV64m:
5725	case IDIV64r:
5726	case IDIV8m:
5727	case IDIV8r:
5728		return true;
5729	}
5730	return false;
5731}
5732
5733bool isPREFETCHWT1(unsigned Opcode) {
5734	return Opcode == PREFETCHWT1;
5735}
5736
5737bool isVPSRLVD(unsigned Opcode) {
5738	switch (Opcode) {
5739	case VPSRLVDYrm:
5740	case VPSRLVDYrr:
5741	case VPSRLVDZ128rm:
5742	case VPSRLVDZ128rmb:
5743	case VPSRLVDZ128rmbk:
5744	case VPSRLVDZ128rmbkz:
5745	case VPSRLVDZ128rmk:
5746	case VPSRLVDZ128rmkz:
5747	case VPSRLVDZ128rr:
5748	case VPSRLVDZ128rrk:
5749	case VPSRLVDZ128rrkz:
5750	case VPSRLVDZ256rm:
5751	case VPSRLVDZ256rmb:
5752	case VPSRLVDZ256rmbk:
5753	case VPSRLVDZ256rmbkz:
5754	case VPSRLVDZ256rmk:
5755	case VPSRLVDZ256rmkz:
5756	case VPSRLVDZ256rr:
5757	case VPSRLVDZ256rrk:
5758	case VPSRLVDZ256rrkz:
5759	case VPSRLVDZrm:
5760	case VPSRLVDZrmb:
5761	case VPSRLVDZrmbk:
5762	case VPSRLVDZrmbkz:
5763	case VPSRLVDZrmk:
5764	case VPSRLVDZrmkz:
5765	case VPSRLVDZrr:
5766	case VPSRLVDZrrk:
5767	case VPSRLVDZrrkz:
5768	case VPSRLVDrm:
5769	case VPSRLVDrr:
5770		return true;
5771	}
5772	return false;
5773}
5774
5775bool isPSRLQ(unsigned Opcode) {
5776	switch (Opcode) {
5777	case MMX_PSRLQri:
5778	case MMX_PSRLQrm:
5779	case MMX_PSRLQrr:
5780	case PSRLQri:
5781	case PSRLQrm:
5782	case PSRLQrr:
5783		return true;
5784	}
5785	return false;
5786}
5787
5788bool isPSRLW(unsigned Opcode) {
5789	switch (Opcode) {
5790	case MMX_PSRLWri:
5791	case MMX_PSRLWrm:
5792	case MMX_PSRLWrr:
5793	case PSRLWri:
5794	case PSRLWrm:
5795	case PSRLWrr:
5796		return true;
5797	}
5798	return false;
5799}
5800
5801bool isDIVSD(unsigned Opcode) {
5802	switch (Opcode) {
5803	case DIVSDrm_Int:
5804	case DIVSDrr_Int:
5805		return true;
5806	}
5807	return false;
5808}
5809
5810bool isVPMOVDB(unsigned Opcode) {
5811	switch (Opcode) {
5812	case VPMOVDBZ128mr:
5813	case VPMOVDBZ128mrk:
5814	case VPMOVDBZ128rr:
5815	case VPMOVDBZ128rrk:
5816	case VPMOVDBZ128rrkz:
5817	case VPMOVDBZ256mr:
5818	case VPMOVDBZ256mrk:
5819	case VPMOVDBZ256rr:
5820	case VPMOVDBZ256rrk:
5821	case VPMOVDBZ256rrkz:
5822	case VPMOVDBZmr:
5823	case VPMOVDBZmrk:
5824	case VPMOVDBZrr:
5825	case VPMOVDBZrrk:
5826	case VPMOVDBZrrkz:
5827		return true;
5828	}
5829	return false;
5830}
5831
5832bool isVPSRLVQ(unsigned Opcode) {
5833	switch (Opcode) {
5834	case VPSRLVQYrm:
5835	case VPSRLVQYrr:
5836	case VPSRLVQZ128rm:
5837	case VPSRLVQZ128rmb:
5838	case VPSRLVQZ128rmbk:
5839	case VPSRLVQZ128rmbkz:
5840	case VPSRLVQZ128rmk:
5841	case VPSRLVQZ128rmkz:
5842	case VPSRLVQZ128rr:
5843	case VPSRLVQZ128rrk:
5844	case VPSRLVQZ128rrkz:
5845	case VPSRLVQZ256rm:
5846	case VPSRLVQZ256rmb:
5847	case VPSRLVQZ256rmbk:
5848	case VPSRLVQZ256rmbkz:
5849	case VPSRLVQZ256rmk:
5850	case VPSRLVQZ256rmkz:
5851	case VPSRLVQZ256rr:
5852	case VPSRLVQZ256rrk:
5853	case VPSRLVQZ256rrkz:
5854	case VPSRLVQZrm:
5855	case VPSRLVQZrmb:
5856	case VPSRLVQZrmbk:
5857	case VPSRLVQZrmbkz:
5858	case VPSRLVQZrmk:
5859	case VPSRLVQZrmkz:
5860	case VPSRLVQZrr:
5861	case VPSRLVQZrrk:
5862	case VPSRLVQZrrkz:
5863	case VPSRLVQrm:
5864	case VPSRLVQrr:
5865		return true;
5866	}
5867	return false;
5868}
5869
5870bool isVPSRLVW(unsigned Opcode) {
5871	switch (Opcode) {
5872	case VPSRLVWZ128rm:
5873	case VPSRLVWZ128rmk:
5874	case VPSRLVWZ128rmkz:
5875	case VPSRLVWZ128rr:
5876	case VPSRLVWZ128rrk:
5877	case VPSRLVWZ128rrkz:
5878	case VPSRLVWZ256rm:
5879	case VPSRLVWZ256rmk:
5880	case VPSRLVWZ256rmkz:
5881	case VPSRLVWZ256rr:
5882	case VPSRLVWZ256rrk:
5883	case VPSRLVWZ256rrkz:
5884	case VPSRLVWZrm:
5885	case VPSRLVWZrmk:
5886	case VPSRLVWZrmkz:
5887	case VPSRLVWZrr:
5888	case VPSRLVWZrrk:
5889	case VPSRLVWZrrkz:
5890		return true;
5891	}
5892	return false;
5893}
5894
5895bool isDIVSS(unsigned Opcode) {
5896	switch (Opcode) {
5897	case DIVSSrm_Int:
5898	case DIVSSrr_Int:
5899		return true;
5900	}
5901	return false;
5902}
5903
5904bool isMUL(unsigned Opcode) {
5905	switch (Opcode) {
5906	case MUL16m:
5907	case MUL16r:
5908	case MUL32m:
5909	case MUL32r:
5910	case MUL64m:
5911	case MUL64r:
5912	case MUL8m:
5913	case MUL8r:
5914		return true;
5915	}
5916	return false;
5917}
5918
5919bool isVPMOVDW(unsigned Opcode) {
5920	switch (Opcode) {
5921	case VPMOVDWZ128mr:
5922	case VPMOVDWZ128mrk:
5923	case VPMOVDWZ128rr:
5924	case VPMOVDWZ128rrk:
5925	case VPMOVDWZ128rrkz:
5926	case VPMOVDWZ256mr:
5927	case VPMOVDWZ256mrk:
5928	case VPMOVDWZ256rr:
5929	case VPMOVDWZ256rrk:
5930	case VPMOVDWZ256rrkz:
5931	case VPMOVDWZmr:
5932	case VPMOVDWZmrk:
5933	case VPMOVDWZrr:
5934	case VPMOVDWZrrk:
5935	case VPMOVDWZrrkz:
5936		return true;
5937	}
5938	return false;
5939}
5940
5941bool isVCVTTPD2UQQ(unsigned Opcode) {
5942	switch (Opcode) {
5943	case VCVTTPD2UQQZ128rm:
5944	case VCVTTPD2UQQZ128rmb:
5945	case VCVTTPD2UQQZ128rmbk:
5946	case VCVTTPD2UQQZ128rmbkz:
5947	case VCVTTPD2UQQZ128rmk:
5948	case VCVTTPD2UQQZ128rmkz:
5949	case VCVTTPD2UQQZ128rr:
5950	case VCVTTPD2UQQZ128rrk:
5951	case VCVTTPD2UQQZ128rrkz:
5952	case VCVTTPD2UQQZ256rm:
5953	case VCVTTPD2UQQZ256rmb:
5954	case VCVTTPD2UQQZ256rmbk:
5955	case VCVTTPD2UQQZ256rmbkz:
5956	case VCVTTPD2UQQZ256rmk:
5957	case VCVTTPD2UQQZ256rmkz:
5958	case VCVTTPD2UQQZ256rr:
5959	case VCVTTPD2UQQZ256rrk:
5960	case VCVTTPD2UQQZ256rrkz:
5961	case VCVTTPD2UQQZrm:
5962	case VCVTTPD2UQQZrmb:
5963	case VCVTTPD2UQQZrmbk:
5964	case VCVTTPD2UQQZrmbkz:
5965	case VCVTTPD2UQQZrmk:
5966	case VCVTTPD2UQQZrmkz:
5967	case VCVTTPD2UQQZrr:
5968	case VCVTTPD2UQQZrrb:
5969	case VCVTTPD2UQQZrrbk:
5970	case VCVTTPD2UQQZrrbkz:
5971	case VCVTTPD2UQQZrrk:
5972	case VCVTTPD2UQQZrrkz:
5973		return true;
5974	}
5975	return false;
5976}
5977
5978bool isFSINCOS(unsigned Opcode) {
5979	return Opcode == FSINCOS;
5980}
5981
5982bool isVPMADD52LUQ(unsigned Opcode) {
5983	switch (Opcode) {
5984	case VPMADD52LUQYrm:
5985	case VPMADD52LUQYrr:
5986	case VPMADD52LUQZ128m:
5987	case VPMADD52LUQZ128mb:
5988	case VPMADD52LUQZ128mbk:
5989	case VPMADD52LUQZ128mbkz:
5990	case VPMADD52LUQZ128mk:
5991	case VPMADD52LUQZ128mkz:
5992	case VPMADD52LUQZ128r:
5993	case VPMADD52LUQZ128rk:
5994	case VPMADD52LUQZ128rkz:
5995	case VPMADD52LUQZ256m:
5996	case VPMADD52LUQZ256mb:
5997	case VPMADD52LUQZ256mbk:
5998	case VPMADD52LUQZ256mbkz:
5999	case VPMADD52LUQZ256mk:
6000	case VPMADD52LUQZ256mkz:
6001	case VPMADD52LUQZ256r:
6002	case VPMADD52LUQZ256rk:
6003	case VPMADD52LUQZ256rkz:
6004	case VPMADD52LUQZm:
6005	case VPMADD52LUQZmb:
6006	case VPMADD52LUQZmbk:
6007	case VPMADD52LUQZmbkz:
6008	case VPMADD52LUQZmk:
6009	case VPMADD52LUQZmkz:
6010	case VPMADD52LUQZr:
6011	case VPMADD52LUQZrk:
6012	case VPMADD52LUQZrkz:
6013	case VPMADD52LUQrm:
6014	case VPMADD52LUQrr:
6015		return true;
6016	}
6017	return false;
6018}
6019
6020bool isLWPINS(unsigned Opcode) {
6021	switch (Opcode) {
6022	case LWPINS32rmi:
6023	case LWPINS32rri:
6024	case LWPINS64rmi:
6025	case LWPINS64rri:
6026		return true;
6027	}
6028	return false;
6029}
6030
6031bool isMOVDIR64B(unsigned Opcode) {
6032	switch (Opcode) {
6033	case MOVDIR64B16:
6034	case MOVDIR64B32:
6035	case MOVDIR64B64:
6036		return true;
6037	}
6038	return false;
6039}
6040
6041bool isLOOPE(unsigned Opcode) {
6042	return Opcode == LOOPE;
6043}
6044
6045bool isPUSH(unsigned Opcode) {
6046	switch (Opcode) {
6047	case PUSH16i8:
6048	case PUSH16r:
6049	case PUSH16rmm:
6050	case PUSH16rmr:
6051	case PUSH32i8:
6052	case PUSH32r:
6053	case PUSH32rmm:
6054	case PUSH32rmr:
6055	case PUSH64i32:
6056	case PUSH64i8:
6057	case PUSH64r:
6058	case PUSH64rmm:
6059	case PUSH64rmr:
6060	case PUSHCS16:
6061	case PUSHCS32:
6062	case PUSHDS16:
6063	case PUSHDS32:
6064	case PUSHES16:
6065	case PUSHES32:
6066	case PUSHFS16:
6067	case PUSHFS32:
6068	case PUSHFS64:
6069	case PUSHGS16:
6070	case PUSHGS32:
6071	case PUSHGS64:
6072	case PUSHSS16:
6073	case PUSHSS32:
6074	case PUSHi16:
6075	case PUSHi32:
6076		return true;
6077	}
6078	return false;
6079}
6080
6081bool isPSADBW(unsigned Opcode) {
6082	switch (Opcode) {
6083	case MMX_PSADBWrm:
6084	case MMX_PSADBWrr:
6085	case PSADBWrm:
6086	case PSADBWrr:
6087		return true;
6088	}
6089	return false;
6090}
6091
6092bool isFTST(unsigned Opcode) {
6093	return Opcode == TST_F;
6094}
6095
6096bool isSETSSBSY(unsigned Opcode) {
6097	return Opcode == SETSSBSY;
6098}
6099
6100bool isSARX(unsigned Opcode) {
6101	switch (Opcode) {
6102	case SARX32rm:
6103	case SARX32rr:
6104	case SARX64rm:
6105	case SARX64rr:
6106		return true;
6107	}
6108	return false;
6109}
6110
6111bool isVADDSUBPD(unsigned Opcode) {
6112	switch (Opcode) {
6113	case VADDSUBPDYrm:
6114	case VADDSUBPDYrr:
6115	case VADDSUBPDrm:
6116	case VADDSUBPDrr:
6117		return true;
6118	}
6119	return false;
6120}
6121
6122bool isVADDSUBPS(unsigned Opcode) {
6123	switch (Opcode) {
6124	case VADDSUBPSYrm:
6125	case VADDSUBPSYrr:
6126	case VADDSUBPSrm:
6127	case VADDSUBPSrr:
6128		return true;
6129	}
6130	return false;
6131}
6132
6133bool isVMINPD(unsigned Opcode) {
6134	switch (Opcode) {
6135	case VMINPDYrm:
6136	case VMINPDYrr:
6137	case VMINPDZ128rm:
6138	case VMINPDZ128rmb:
6139	case VMINPDZ128rmbk:
6140	case VMINPDZ128rmbkz:
6141	case VMINPDZ128rmk:
6142	case VMINPDZ128rmkz:
6143	case VMINPDZ128rr:
6144	case VMINPDZ128rrk:
6145	case VMINPDZ128rrkz:
6146	case VMINPDZ256rm:
6147	case VMINPDZ256rmb:
6148	case VMINPDZ256rmbk:
6149	case VMINPDZ256rmbkz:
6150	case VMINPDZ256rmk:
6151	case VMINPDZ256rmkz:
6152	case VMINPDZ256rr:
6153	case VMINPDZ256rrk:
6154	case VMINPDZ256rrkz:
6155	case VMINPDZrm:
6156	case VMINPDZrmb:
6157	case VMINPDZrmbk:
6158	case VMINPDZrmbkz:
6159	case VMINPDZrmk:
6160	case VMINPDZrmkz:
6161	case VMINPDZrr:
6162	case VMINPDZrrb:
6163	case VMINPDZrrbk:
6164	case VMINPDZrrbkz:
6165	case VMINPDZrrk:
6166	case VMINPDZrrkz:
6167	case VMINPDrm:
6168	case VMINPDrr:
6169		return true;
6170	}
6171	return false;
6172}
6173
6174bool isCLZERO(unsigned Opcode) {
6175	switch (Opcode) {
6176	case CLZERO32r:
6177	case CLZERO64r:
6178		return true;
6179	}
6180	return false;
6181}
6182
6183bool isVMINPH(unsigned Opcode) {
6184	switch (Opcode) {
6185	case VMINPHZ128rm:
6186	case VMINPHZ128rmb:
6187	case VMINPHZ128rmbk:
6188	case VMINPHZ128rmbkz:
6189	case VMINPHZ128rmk:
6190	case VMINPHZ128rmkz:
6191	case VMINPHZ128rr:
6192	case VMINPHZ128rrk:
6193	case VMINPHZ128rrkz:
6194	case VMINPHZ256rm:
6195	case VMINPHZ256rmb:
6196	case VMINPHZ256rmbk:
6197	case VMINPHZ256rmbkz:
6198	case VMINPHZ256rmk:
6199	case VMINPHZ256rmkz:
6200	case VMINPHZ256rr:
6201	case VMINPHZ256rrk:
6202	case VMINPHZ256rrkz:
6203	case VMINPHZrm:
6204	case VMINPHZrmb:
6205	case VMINPHZrmbk:
6206	case VMINPHZrmbkz:
6207	case VMINPHZrmk:
6208	case VMINPHZrmkz:
6209	case VMINPHZrr:
6210	case VMINPHZrrb:
6211	case VMINPHZrrbk:
6212	case VMINPHZrrbkz:
6213	case VMINPHZrrk:
6214	case VMINPHZrrkz:
6215		return true;
6216	}
6217	return false;
6218}
6219
6220bool isXCRYPTCBC(unsigned Opcode) {
6221	return Opcode == XCRYPTCBC;
6222}
6223
6224bool isFXTRACT(unsigned Opcode) {
6225	return Opcode == FXTRACT;
6226}
6227
6228bool isVMINPS(unsigned Opcode) {
6229	switch (Opcode) {
6230	case VMINPSYrm:
6231	case VMINPSYrr:
6232	case VMINPSZ128rm:
6233	case VMINPSZ128rmb:
6234	case VMINPSZ128rmbk:
6235	case VMINPSZ128rmbkz:
6236	case VMINPSZ128rmk:
6237	case VMINPSZ128rmkz:
6238	case VMINPSZ128rr:
6239	case VMINPSZ128rrk:
6240	case VMINPSZ128rrkz:
6241	case VMINPSZ256rm:
6242	case VMINPSZ256rmb:
6243	case VMINPSZ256rmbk:
6244	case VMINPSZ256rmbkz:
6245	case VMINPSZ256rmk:
6246	case VMINPSZ256rmkz:
6247	case VMINPSZ256rr:
6248	case VMINPSZ256rrk:
6249	case VMINPSZ256rrkz:
6250	case VMINPSZrm:
6251	case VMINPSZrmb:
6252	case VMINPSZrmbk:
6253	case VMINPSZrmbkz:
6254	case VMINPSZrmk:
6255	case VMINPSZrmkz:
6256	case VMINPSZrr:
6257	case VMINPSZrrb:
6258	case VMINPSZrrbk:
6259	case VMINPSZrrbkz:
6260	case VMINPSZrrk:
6261	case VMINPSZrrkz:
6262	case VMINPSrm:
6263	case VMINPSrr:
6264		return true;
6265	}
6266	return false;
6267}
6268
6269bool isVFMADD132SD(unsigned Opcode) {
6270	switch (Opcode) {
6271	case VFMADD132SDZm_Int:
6272	case VFMADD132SDZm_Intk:
6273	case VFMADD132SDZm_Intkz:
6274	case VFMADD132SDZr_Int:
6275	case VFMADD132SDZr_Intk:
6276	case VFMADD132SDZr_Intkz:
6277	case VFMADD132SDZrb_Int:
6278	case VFMADD132SDZrb_Intk:
6279	case VFMADD132SDZrb_Intkz:
6280	case VFMADD132SDm_Int:
6281	case VFMADD132SDr_Int:
6282		return true;
6283	}
6284	return false;
6285}
6286
6287bool isVFMADD132SH(unsigned Opcode) {
6288	switch (Opcode) {
6289	case VFMADD132SHZm_Int:
6290	case VFMADD132SHZm_Intk:
6291	case VFMADD132SHZm_Intkz:
6292	case VFMADD132SHZr_Int:
6293	case VFMADD132SHZr_Intk:
6294	case VFMADD132SHZr_Intkz:
6295	case VFMADD132SHZrb_Int:
6296	case VFMADD132SHZrb_Intk:
6297	case VFMADD132SHZrb_Intkz:
6298		return true;
6299	}
6300	return false;
6301}
6302
6303bool isVPERMI2B(unsigned Opcode) {
6304	switch (Opcode) {
6305	case VPERMI2B128rm:
6306	case VPERMI2B128rmk:
6307	case VPERMI2B128rmkz:
6308	case VPERMI2B128rr:
6309	case VPERMI2B128rrk:
6310	case VPERMI2B128rrkz:
6311	case VPERMI2B256rm:
6312	case VPERMI2B256rmk:
6313	case VPERMI2B256rmkz:
6314	case VPERMI2B256rr:
6315	case VPERMI2B256rrk:
6316	case VPERMI2B256rrkz:
6317	case VPERMI2Brm:
6318	case VPERMI2Brmk:
6319	case VPERMI2Brmkz:
6320	case VPERMI2Brr:
6321	case VPERMI2Brrk:
6322	case VPERMI2Brrkz:
6323		return true;
6324	}
6325	return false;
6326}
6327
6328bool isVPERMI2D(unsigned Opcode) {
6329	switch (Opcode) {
6330	case VPERMI2D128rm:
6331	case VPERMI2D128rmb:
6332	case VPERMI2D128rmbk:
6333	case VPERMI2D128rmbkz:
6334	case VPERMI2D128rmk:
6335	case VPERMI2D128rmkz:
6336	case VPERMI2D128rr:
6337	case VPERMI2D128rrk:
6338	case VPERMI2D128rrkz:
6339	case VPERMI2D256rm:
6340	case VPERMI2D256rmb:
6341	case VPERMI2D256rmbk:
6342	case VPERMI2D256rmbkz:
6343	case VPERMI2D256rmk:
6344	case VPERMI2D256rmkz:
6345	case VPERMI2D256rr:
6346	case VPERMI2D256rrk:
6347	case VPERMI2D256rrkz:
6348	case VPERMI2Drm:
6349	case VPERMI2Drmb:
6350	case VPERMI2Drmbk:
6351	case VPERMI2Drmbkz:
6352	case VPERMI2Drmk:
6353	case VPERMI2Drmkz:
6354	case VPERMI2Drr:
6355	case VPERMI2Drrk:
6356	case VPERMI2Drrkz:
6357		return true;
6358	}
6359	return false;
6360}
6361
6362bool isVFMADD132SS(unsigned Opcode) {
6363	switch (Opcode) {
6364	case VFMADD132SSZm_Int:
6365	case VFMADD132SSZm_Intk:
6366	case VFMADD132SSZm_Intkz:
6367	case VFMADD132SSZr_Int:
6368	case VFMADD132SSZr_Intk:
6369	case VFMADD132SSZr_Intkz:
6370	case VFMADD132SSZrb_Int:
6371	case VFMADD132SSZrb_Intk:
6372	case VFMADD132SSZrb_Intkz:
6373	case VFMADD132SSm_Int:
6374	case VFMADD132SSr_Int:
6375		return true;
6376	}
6377	return false;
6378}
6379
6380bool isVRSQRT28PD(unsigned Opcode) {
6381	switch (Opcode) {
6382	case VRSQRT28PDZm:
6383	case VRSQRT28PDZmb:
6384	case VRSQRT28PDZmbk:
6385	case VRSQRT28PDZmbkz:
6386	case VRSQRT28PDZmk:
6387	case VRSQRT28PDZmkz:
6388	case VRSQRT28PDZr:
6389	case VRSQRT28PDZrb:
6390	case VRSQRT28PDZrbk:
6391	case VRSQRT28PDZrbkz:
6392	case VRSQRT28PDZrk:
6393	case VRSQRT28PDZrkz:
6394		return true;
6395	}
6396	return false;
6397}
6398
6399bool isVPMULHW(unsigned Opcode) {
6400	switch (Opcode) {
6401	case VPMULHWYrm:
6402	case VPMULHWYrr:
6403	case VPMULHWZ128rm:
6404	case VPMULHWZ128rmk:
6405	case VPMULHWZ128rmkz:
6406	case VPMULHWZ128rr:
6407	case VPMULHWZ128rrk:
6408	case VPMULHWZ128rrkz:
6409	case VPMULHWZ256rm:
6410	case VPMULHWZ256rmk:
6411	case VPMULHWZ256rmkz:
6412	case VPMULHWZ256rr:
6413	case VPMULHWZ256rrk:
6414	case VPMULHWZ256rrkz:
6415	case VPMULHWZrm:
6416	case VPMULHWZrmk:
6417	case VPMULHWZrmkz:
6418	case VPMULHWZrr:
6419	case VPMULHWZrrk:
6420	case VPMULHWZrrkz:
6421	case VPMULHWrm:
6422	case VPMULHWrr:
6423		return true;
6424	}
6425	return false;
6426}
6427
6428bool isSIDT(unsigned Opcode) {
6429	return Opcode == SIDT64m;
6430}
6431
6432bool isTDCALL(unsigned Opcode) {
6433	return Opcode == TDCALL;
6434}
6435
6436bool isVPERMI2Q(unsigned Opcode) {
6437	switch (Opcode) {
6438	case VPERMI2Q128rm:
6439	case VPERMI2Q128rmb:
6440	case VPERMI2Q128rmbk:
6441	case VPERMI2Q128rmbkz:
6442	case VPERMI2Q128rmk:
6443	case VPERMI2Q128rmkz:
6444	case VPERMI2Q128rr:
6445	case VPERMI2Q128rrk:
6446	case VPERMI2Q128rrkz:
6447	case VPERMI2Q256rm:
6448	case VPERMI2Q256rmb:
6449	case VPERMI2Q256rmbk:
6450	case VPERMI2Q256rmbkz:
6451	case VPERMI2Q256rmk:
6452	case VPERMI2Q256rmkz:
6453	case VPERMI2Q256rr:
6454	case VPERMI2Q256rrk:
6455	case VPERMI2Q256rrkz:
6456	case VPERMI2Qrm:
6457	case VPERMI2Qrmb:
6458	case VPERMI2Qrmbk:
6459	case VPERMI2Qrmbkz:
6460	case VPERMI2Qrmk:
6461	case VPERMI2Qrmkz:
6462	case VPERMI2Qrr:
6463	case VPERMI2Qrrk:
6464	case VPERMI2Qrrkz:
6465		return true;
6466	}
6467	return false;
6468}
6469
6470bool isVPERMI2W(unsigned Opcode) {
6471	switch (Opcode) {
6472	case VPERMI2W128rm:
6473	case VPERMI2W128rmk:
6474	case VPERMI2W128rmkz:
6475	case VPERMI2W128rr:
6476	case VPERMI2W128rrk:
6477	case VPERMI2W128rrkz:
6478	case VPERMI2W256rm:
6479	case VPERMI2W256rmk:
6480	case VPERMI2W256rmkz:
6481	case VPERMI2W256rr:
6482	case VPERMI2W256rrk:
6483	case VPERMI2W256rrkz:
6484	case VPERMI2Wrm:
6485	case VPERMI2Wrmk:
6486	case VPERMI2Wrmkz:
6487	case VPERMI2Wrr:
6488	case VPERMI2Wrrk:
6489	case VPERMI2Wrrkz:
6490		return true;
6491	}
6492	return false;
6493}
6494
6495bool isVPERM2F128(unsigned Opcode) {
6496	switch (Opcode) {
6497	case VPERM2F128rm:
6498	case VPERM2F128rr:
6499		return true;
6500	}
6501	return false;
6502}
6503
6504bool isVMLAUNCH(unsigned Opcode) {
6505	return Opcode == VMLAUNCH;
6506}
6507
6508bool isFILD(unsigned Opcode) {
6509	switch (Opcode) {
6510	case ILD_F16m:
6511	case ILD_F32m:
6512	case ILD_F64m:
6513		return true;
6514	}
6515	return false;
6516}
6517
6518bool isVRSQRT28PS(unsigned Opcode) {
6519	switch (Opcode) {
6520	case VRSQRT28PSZm:
6521	case VRSQRT28PSZmb:
6522	case VRSQRT28PSZmbk:
6523	case VRSQRT28PSZmbkz:
6524	case VRSQRT28PSZmk:
6525	case VRSQRT28PSZmkz:
6526	case VRSQRT28PSZr:
6527	case VRSQRT28PSZrb:
6528	case VRSQRT28PSZrbk:
6529	case VRSQRT28PSZrbkz:
6530	case VRSQRT28PSZrk:
6531	case VRSQRT28PSZrkz:
6532		return true;
6533	}
6534	return false;
6535}
6536
6537bool isVPBLENDVB(unsigned Opcode) {
6538	switch (Opcode) {
6539	case VPBLENDVBYrm:
6540	case VPBLENDVBYrr:
6541	case VPBLENDVBrm:
6542	case VPBLENDVBrr:
6543		return true;
6544	}
6545	return false;
6546}
6547
6548bool isVPMADDUBSW(unsigned Opcode) {
6549	switch (Opcode) {
6550	case VPMADDUBSWYrm:
6551	case VPMADDUBSWYrr:
6552	case VPMADDUBSWZ128rm:
6553	case VPMADDUBSWZ128rmk:
6554	case VPMADDUBSWZ128rmkz:
6555	case VPMADDUBSWZ128rr:
6556	case VPMADDUBSWZ128rrk:
6557	case VPMADDUBSWZ128rrkz:
6558	case VPMADDUBSWZ256rm:
6559	case VPMADDUBSWZ256rmk:
6560	case VPMADDUBSWZ256rmkz:
6561	case VPMADDUBSWZ256rr:
6562	case VPMADDUBSWZ256rrk:
6563	case VPMADDUBSWZ256rrkz:
6564	case VPMADDUBSWZrm:
6565	case VPMADDUBSWZrmk:
6566	case VPMADDUBSWZrmkz:
6567	case VPMADDUBSWZrr:
6568	case VPMADDUBSWZrrk:
6569	case VPMADDUBSWZrrkz:
6570	case VPMADDUBSWrm:
6571	case VPMADDUBSWrr:
6572		return true;
6573	}
6574	return false;
6575}
6576
6577bool isVSTMXCSR(unsigned Opcode) {
6578	return Opcode == VSTMXCSR;
6579}
6580
6581bool isVCVTTPH2UDQ(unsigned Opcode) {
6582	switch (Opcode) {
6583	case VCVTTPH2UDQZ128rm:
6584	case VCVTTPH2UDQZ128rmb:
6585	case VCVTTPH2UDQZ128rmbk:
6586	case VCVTTPH2UDQZ128rmbkz:
6587	case VCVTTPH2UDQZ128rmk:
6588	case VCVTTPH2UDQZ128rmkz:
6589	case VCVTTPH2UDQZ128rr:
6590	case VCVTTPH2UDQZ128rrk:
6591	case VCVTTPH2UDQZ128rrkz:
6592	case VCVTTPH2UDQZ256rm:
6593	case VCVTTPH2UDQZ256rmb:
6594	case VCVTTPH2UDQZ256rmbk:
6595	case VCVTTPH2UDQZ256rmbkz:
6596	case VCVTTPH2UDQZ256rmk:
6597	case VCVTTPH2UDQZ256rmkz:
6598	case VCVTTPH2UDQZ256rr:
6599	case VCVTTPH2UDQZ256rrk:
6600	case VCVTTPH2UDQZ256rrkz:
6601	case VCVTTPH2UDQZrm:
6602	case VCVTTPH2UDQZrmb:
6603	case VCVTTPH2UDQZrmbk:
6604	case VCVTTPH2UDQZrmbkz:
6605	case VCVTTPH2UDQZrmk:
6606	case VCVTTPH2UDQZrmkz:
6607	case VCVTTPH2UDQZrr:
6608	case VCVTTPH2UDQZrrb:
6609	case VCVTTPH2UDQZrrbk:
6610	case VCVTTPH2UDQZrrbkz:
6611	case VCVTTPH2UDQZrrk:
6612	case VCVTTPH2UDQZrrkz:
6613		return true;
6614	}
6615	return false;
6616}
6617
6618bool isXSHA256(unsigned Opcode) {
6619	return Opcode == XSHA256;
6620}
6621
6622bool isWAIT(unsigned Opcode) {
6623	return Opcode == WAIT;
6624}
6625
6626bool isPACKSSWB(unsigned Opcode) {
6627	switch (Opcode) {
6628	case MMX_PACKSSWBrm:
6629	case MMX_PACKSSWBrr:
6630	case PACKSSWBrm:
6631	case PACKSSWBrr:
6632		return true;
6633	}
6634	return false;
6635}
6636
6637bool isPMULHRSW(unsigned Opcode) {
6638	switch (Opcode) {
6639	case MMX_PMULHRSWrm:
6640	case MMX_PMULHRSWrr:
6641	case PMULHRSWrm:
6642	case PMULHRSWrr:
6643		return true;
6644	}
6645	return false;
6646}
6647
6648bool isMASKMOVQ(unsigned Opcode) {
6649	switch (Opcode) {
6650	case MMX_MASKMOVQ:
6651	case MMX_MASKMOVQ64:
6652		return true;
6653	}
6654	return false;
6655}
6656
6657bool isVMINSD(unsigned Opcode) {
6658	switch (Opcode) {
6659	case VMINSDZrm_Int:
6660	case VMINSDZrm_Intk:
6661	case VMINSDZrm_Intkz:
6662	case VMINSDZrr_Int:
6663	case VMINSDZrr_Intk:
6664	case VMINSDZrr_Intkz:
6665	case VMINSDZrrb_Int:
6666	case VMINSDZrrb_Intk:
6667	case VMINSDZrrb_Intkz:
6668	case VMINSDrm_Int:
6669	case VMINSDrr_Int:
6670		return true;
6671	}
6672	return false;
6673}
6674
6675bool isVMINSH(unsigned Opcode) {
6676	switch (Opcode) {
6677	case VMINSHZrm_Int:
6678	case VMINSHZrm_Intk:
6679	case VMINSHZrm_Intkz:
6680	case VMINSHZrr_Int:
6681	case VMINSHZrr_Intk:
6682	case VMINSHZrr_Intkz:
6683	case VMINSHZrrb_Int:
6684	case VMINSHZrrb_Intk:
6685	case VMINSHZrrb_Intkz:
6686		return true;
6687	}
6688	return false;
6689}
6690
6691bool isRDTSC(unsigned Opcode) {
6692	return Opcode == RDTSC;
6693}
6694
6695bool isVMINSS(unsigned Opcode) {
6696	switch (Opcode) {
6697	case VMINSSZrm_Int:
6698	case VMINSSZrm_Intk:
6699	case VMINSSZrm_Intkz:
6700	case VMINSSZrr_Int:
6701	case VMINSSZrr_Intk:
6702	case VMINSSZrr_Intkz:
6703	case VMINSSZrrb_Int:
6704	case VMINSSZrrb_Intk:
6705	case VMINSSZrrb_Intkz:
6706	case VMINSSrm_Int:
6707	case VMINSSrr_Int:
6708		return true;
6709	}
6710	return false;
6711}
6712
6713bool isVRSQRT28SD(unsigned Opcode) {
6714	switch (Opcode) {
6715	case VRSQRT28SDZm:
6716	case VRSQRT28SDZmk:
6717	case VRSQRT28SDZmkz:
6718	case VRSQRT28SDZr:
6719	case VRSQRT28SDZrb:
6720	case VRSQRT28SDZrbk:
6721	case VRSQRT28SDZrbkz:
6722	case VRSQRT28SDZrk:
6723	case VRSQRT28SDZrkz:
6724		return true;
6725	}
6726	return false;
6727}
6728
6729bool isAAND(unsigned Opcode) {
6730	switch (Opcode) {
6731	case AAND32mr:
6732	case AAND64mr:
6733		return true;
6734	}
6735	return false;
6736}
6737
6738bool isXCRYPTCFB(unsigned Opcode) {
6739	return Opcode == XCRYPTCFB;
6740}
6741
6742bool isVSCALEFPD(unsigned Opcode) {
6743	switch (Opcode) {
6744	case VSCALEFPDZ128rm:
6745	case VSCALEFPDZ128rmb:
6746	case VSCALEFPDZ128rmbk:
6747	case VSCALEFPDZ128rmbkz:
6748	case VSCALEFPDZ128rmk:
6749	case VSCALEFPDZ128rmkz:
6750	case VSCALEFPDZ128rr:
6751	case VSCALEFPDZ128rrk:
6752	case VSCALEFPDZ128rrkz:
6753	case VSCALEFPDZ256rm:
6754	case VSCALEFPDZ256rmb:
6755	case VSCALEFPDZ256rmbk:
6756	case VSCALEFPDZ256rmbkz:
6757	case VSCALEFPDZ256rmk:
6758	case VSCALEFPDZ256rmkz:
6759	case VSCALEFPDZ256rr:
6760	case VSCALEFPDZ256rrk:
6761	case VSCALEFPDZ256rrkz:
6762	case VSCALEFPDZrm:
6763	case VSCALEFPDZrmb:
6764	case VSCALEFPDZrmbk:
6765	case VSCALEFPDZrmbkz:
6766	case VSCALEFPDZrmk:
6767	case VSCALEFPDZrmkz:
6768	case VSCALEFPDZrr:
6769	case VSCALEFPDZrrb:
6770	case VSCALEFPDZrrbk:
6771	case VSCALEFPDZrrbkz:
6772	case VSCALEFPDZrrk:
6773	case VSCALEFPDZrrkz:
6774		return true;
6775	}
6776	return false;
6777}
6778
6779bool isVPBROADCASTB(unsigned Opcode) {
6780	switch (Opcode) {
6781	case VPBROADCASTBYrm:
6782	case VPBROADCASTBYrr:
6783	case VPBROADCASTBZ128rm:
6784	case VPBROADCASTBZ128rmk:
6785	case VPBROADCASTBZ128rmkz:
6786	case VPBROADCASTBZ128rr:
6787	case VPBROADCASTBZ128rrk:
6788	case VPBROADCASTBZ128rrkz:
6789	case VPBROADCASTBZ256rm:
6790	case VPBROADCASTBZ256rmk:
6791	case VPBROADCASTBZ256rmkz:
6792	case VPBROADCASTBZ256rr:
6793	case VPBROADCASTBZ256rrk:
6794	case VPBROADCASTBZ256rrkz:
6795	case VPBROADCASTBZrm:
6796	case VPBROADCASTBZrmk:
6797	case VPBROADCASTBZrmkz:
6798	case VPBROADCASTBZrr:
6799	case VPBROADCASTBZrrk:
6800	case VPBROADCASTBZrrkz:
6801	case VPBROADCASTBrZ128rr:
6802	case VPBROADCASTBrZ128rrk:
6803	case VPBROADCASTBrZ128rrkz:
6804	case VPBROADCASTBrZ256rr:
6805	case VPBROADCASTBrZ256rrk:
6806	case VPBROADCASTBrZ256rrkz:
6807	case VPBROADCASTBrZrr:
6808	case VPBROADCASTBrZrrk:
6809	case VPBROADCASTBrZrrkz:
6810	case VPBROADCASTBrm:
6811	case VPBROADCASTBrr:
6812		return true;
6813	}
6814	return false;
6815}
6816
6817bool isVSCALEFPH(unsigned Opcode) {
6818	switch (Opcode) {
6819	case VSCALEFPHZ128rm:
6820	case VSCALEFPHZ128rmb:
6821	case VSCALEFPHZ128rmbk:
6822	case VSCALEFPHZ128rmbkz:
6823	case VSCALEFPHZ128rmk:
6824	case VSCALEFPHZ128rmkz:
6825	case VSCALEFPHZ128rr:
6826	case VSCALEFPHZ128rrk:
6827	case VSCALEFPHZ128rrkz:
6828	case VSCALEFPHZ256rm:
6829	case VSCALEFPHZ256rmb:
6830	case VSCALEFPHZ256rmbk:
6831	case VSCALEFPHZ256rmbkz:
6832	case VSCALEFPHZ256rmk:
6833	case VSCALEFPHZ256rmkz:
6834	case VSCALEFPHZ256rr:
6835	case VSCALEFPHZ256rrk:
6836	case VSCALEFPHZ256rrkz:
6837	case VSCALEFPHZrm:
6838	case VSCALEFPHZrmb:
6839	case VSCALEFPHZrmbk:
6840	case VSCALEFPHZrmbkz:
6841	case VSCALEFPHZrmk:
6842	case VSCALEFPHZrmkz:
6843	case VSCALEFPHZrr:
6844	case VSCALEFPHZrrb:
6845	case VSCALEFPHZrrbk:
6846	case VSCALEFPHZrrbkz:
6847	case VSCALEFPHZrrk:
6848	case VSCALEFPHZrrkz:
6849		return true;
6850	}
6851	return false;
6852}
6853
6854bool isVPBROADCASTD(unsigned Opcode) {
6855	switch (Opcode) {
6856	case VPBROADCASTDYrm:
6857	case VPBROADCASTDYrr:
6858	case VPBROADCASTDZ128rm:
6859	case VPBROADCASTDZ128rmk:
6860	case VPBROADCASTDZ128rmkz:
6861	case VPBROADCASTDZ128rr:
6862	case VPBROADCASTDZ128rrk:
6863	case VPBROADCASTDZ128rrkz:
6864	case VPBROADCASTDZ256rm:
6865	case VPBROADCASTDZ256rmk:
6866	case VPBROADCASTDZ256rmkz:
6867	case VPBROADCASTDZ256rr:
6868	case VPBROADCASTDZ256rrk:
6869	case VPBROADCASTDZ256rrkz:
6870	case VPBROADCASTDZrm:
6871	case VPBROADCASTDZrmk:
6872	case VPBROADCASTDZrmkz:
6873	case VPBROADCASTDZrr:
6874	case VPBROADCASTDZrrk:
6875	case VPBROADCASTDZrrkz:
6876	case VPBROADCASTDrZ128rr:
6877	case VPBROADCASTDrZ128rrk:
6878	case VPBROADCASTDrZ128rrkz:
6879	case VPBROADCASTDrZ256rr:
6880	case VPBROADCASTDrZ256rrk:
6881	case VPBROADCASTDrZ256rrkz:
6882	case VPBROADCASTDrZrr:
6883	case VPBROADCASTDrZrrk:
6884	case VPBROADCASTDrZrrkz:
6885	case VPBROADCASTDrm:
6886	case VPBROADCASTDrr:
6887		return true;
6888	}
6889	return false;
6890}
6891
6892bool isVRSQRT28SS(unsigned Opcode) {
6893	switch (Opcode) {
6894	case VRSQRT28SSZm:
6895	case VRSQRT28SSZmk:
6896	case VRSQRT28SSZmkz:
6897	case VRSQRT28SSZr:
6898	case VRSQRT28SSZrb:
6899	case VRSQRT28SSZrbk:
6900	case VRSQRT28SSZrbkz:
6901	case VRSQRT28SSZrk:
6902	case VRSQRT28SSZrkz:
6903		return true;
6904	}
6905	return false;
6906}
6907
6908bool isVPMULLD(unsigned Opcode) {
6909	switch (Opcode) {
6910	case VPMULLDYrm:
6911	case VPMULLDYrr:
6912	case VPMULLDZ128rm:
6913	case VPMULLDZ128rmb:
6914	case VPMULLDZ128rmbk:
6915	case VPMULLDZ128rmbkz:
6916	case VPMULLDZ128rmk:
6917	case VPMULLDZ128rmkz:
6918	case VPMULLDZ128rr:
6919	case VPMULLDZ128rrk:
6920	case VPMULLDZ128rrkz:
6921	case VPMULLDZ256rm:
6922	case VPMULLDZ256rmb:
6923	case VPMULLDZ256rmbk:
6924	case VPMULLDZ256rmbkz:
6925	case VPMULLDZ256rmk:
6926	case VPMULLDZ256rmkz:
6927	case VPMULLDZ256rr:
6928	case VPMULLDZ256rrk:
6929	case VPMULLDZ256rrkz:
6930	case VPMULLDZrm:
6931	case VPMULLDZrmb:
6932	case VPMULLDZrmbk:
6933	case VPMULLDZrmbkz:
6934	case VPMULLDZrmk:
6935	case VPMULLDZrmkz:
6936	case VPMULLDZrr:
6937	case VPMULLDZrrk:
6938	case VPMULLDZrrkz:
6939	case VPMULLDrm:
6940	case VPMULLDrr:
6941		return true;
6942	}
6943	return false;
6944}
6945
6946bool isVSCALEFPS(unsigned Opcode) {
6947	switch (Opcode) {
6948	case VSCALEFPSZ128rm:
6949	case VSCALEFPSZ128rmb:
6950	case VSCALEFPSZ128rmbk:
6951	case VSCALEFPSZ128rmbkz:
6952	case VSCALEFPSZ128rmk:
6953	case VSCALEFPSZ128rmkz:
6954	case VSCALEFPSZ128rr:
6955	case VSCALEFPSZ128rrk:
6956	case VSCALEFPSZ128rrkz:
6957	case VSCALEFPSZ256rm:
6958	case VSCALEFPSZ256rmb:
6959	case VSCALEFPSZ256rmbk:
6960	case VSCALEFPSZ256rmbkz:
6961	case VSCALEFPSZ256rmk:
6962	case VSCALEFPSZ256rmkz:
6963	case VSCALEFPSZ256rr:
6964	case VSCALEFPSZ256rrk:
6965	case VSCALEFPSZ256rrkz:
6966	case VSCALEFPSZrm:
6967	case VSCALEFPSZrmb:
6968	case VSCALEFPSZrmbk:
6969	case VSCALEFPSZrmbkz:
6970	case VSCALEFPSZrmk:
6971	case VSCALEFPSZrmkz:
6972	case VSCALEFPSZrr:
6973	case VSCALEFPSZrrb:
6974	case VSCALEFPSZrrbk:
6975	case VSCALEFPSZrrbkz:
6976	case VSCALEFPSZrrk:
6977	case VSCALEFPSZrrkz:
6978		return true;
6979	}
6980	return false;
6981}
6982
6983bool isMOVQ2DQ(unsigned Opcode) {
6984	return Opcode == MMX_MOVQ2DQrr;
6985}
6986
6987bool isVPBROADCASTQ(unsigned Opcode) {
6988	switch (Opcode) {
6989	case VPBROADCASTQYrm:
6990	case VPBROADCASTQYrr:
6991	case VPBROADCASTQZ128rm:
6992	case VPBROADCASTQZ128rmk:
6993	case VPBROADCASTQZ128rmkz:
6994	case VPBROADCASTQZ128rr:
6995	case VPBROADCASTQZ128rrk:
6996	case VPBROADCASTQZ128rrkz:
6997	case VPBROADCASTQZ256rm:
6998	case VPBROADCASTQZ256rmk:
6999	case VPBROADCASTQZ256rmkz:
7000	case VPBROADCASTQZ256rr:
7001	case VPBROADCASTQZ256rrk:
7002	case VPBROADCASTQZ256rrkz:
7003	case VPBROADCASTQZrm:
7004	case VPBROADCASTQZrmk:
7005	case VPBROADCASTQZrmkz:
7006	case VPBROADCASTQZrr:
7007	case VPBROADCASTQZrrk:
7008	case VPBROADCASTQZrrkz:
7009	case VPBROADCASTQrZ128rr:
7010	case VPBROADCASTQrZ128rrk:
7011	case VPBROADCASTQrZ128rrkz:
7012	case VPBROADCASTQrZ256rr:
7013	case VPBROADCASTQrZ256rrk:
7014	case VPBROADCASTQrZ256rrkz:
7015	case VPBROADCASTQrZrr:
7016	case VPBROADCASTQrZrrk:
7017	case VPBROADCASTQrZrrkz:
7018	case VPBROADCASTQrm:
7019	case VPBROADCASTQrr:
7020		return true;
7021	}
7022	return false;
7023}
7024
7025bool isPALIGNR(unsigned Opcode) {
7026	switch (Opcode) {
7027	case MMX_PALIGNRrmi:
7028	case MMX_PALIGNRrri:
7029	case PALIGNRrmi:
7030	case PALIGNRrri:
7031		return true;
7032	}
7033	return false;
7034}
7035
7036bool isPUSHAL(unsigned Opcode) {
7037	return Opcode == PUSHA32;
7038}
7039
7040bool isVPBROADCASTW(unsigned Opcode) {
7041	switch (Opcode) {
7042	case VPBROADCASTWYrm:
7043	case VPBROADCASTWYrr:
7044	case VPBROADCASTWZ128rm:
7045	case VPBROADCASTWZ128rmk:
7046	case VPBROADCASTWZ128rmkz:
7047	case VPBROADCASTWZ128rr:
7048	case VPBROADCASTWZ128rrk:
7049	case VPBROADCASTWZ128rrkz:
7050	case VPBROADCASTWZ256rm:
7051	case VPBROADCASTWZ256rmk:
7052	case VPBROADCASTWZ256rmkz:
7053	case VPBROADCASTWZ256rr:
7054	case VPBROADCASTWZ256rrk:
7055	case VPBROADCASTWZ256rrkz:
7056	case VPBROADCASTWZrm:
7057	case VPBROADCASTWZrmk:
7058	case VPBROADCASTWZrmkz:
7059	case VPBROADCASTWZrr:
7060	case VPBROADCASTWZrrk:
7061	case VPBROADCASTWZrrkz:
7062	case VPBROADCASTWrZ128rr:
7063	case VPBROADCASTWrZ128rrk:
7064	case VPBROADCASTWrZ128rrkz:
7065	case VPBROADCASTWrZ256rr:
7066	case VPBROADCASTWrZ256rrk:
7067	case VPBROADCASTWrZ256rrkz:
7068	case VPBROADCASTWrZrr:
7069	case VPBROADCASTWrZrrk:
7070	case VPBROADCASTWrZrrkz:
7071	case VPBROADCASTWrm:
7072	case VPBROADCASTWrr:
7073		return true;
7074	}
7075	return false;
7076}
7077
7078bool isVPMULLQ(unsigned Opcode) {
7079	switch (Opcode) {
7080	case VPMULLQZ128rm:
7081	case VPMULLQZ128rmb:
7082	case VPMULLQZ128rmbk:
7083	case VPMULLQZ128rmbkz:
7084	case VPMULLQZ128rmk:
7085	case VPMULLQZ128rmkz:
7086	case VPMULLQZ128rr:
7087	case VPMULLQZ128rrk:
7088	case VPMULLQZ128rrkz:
7089	case VPMULLQZ256rm:
7090	case VPMULLQZ256rmb:
7091	case VPMULLQZ256rmbk:
7092	case VPMULLQZ256rmbkz:
7093	case VPMULLQZ256rmk:
7094	case VPMULLQZ256rmkz:
7095	case VPMULLQZ256rr:
7096	case VPMULLQZ256rrk:
7097	case VPMULLQZ256rrkz:
7098	case VPMULLQZrm:
7099	case VPMULLQZrmb:
7100	case VPMULLQZrmbk:
7101	case VPMULLQZrmbkz:
7102	case VPMULLQZrmk:
7103	case VPMULLQZrmkz:
7104	case VPMULLQZrr:
7105	case VPMULLQZrrk:
7106	case VPMULLQZrrkz:
7107		return true;
7108	}
7109	return false;
7110}
7111
7112bool isFINCSTP(unsigned Opcode) {
7113	return Opcode == FINCSTP;
7114}
7115
7116bool isPUSHAW(unsigned Opcode) {
7117	return Opcode == PUSHA16;
7118}
7119
7120bool isVPMULLW(unsigned Opcode) {
7121	switch (Opcode) {
7122	case VPMULLWYrm:
7123	case VPMULLWYrr:
7124	case VPMULLWZ128rm:
7125	case VPMULLWZ128rmk:
7126	case VPMULLWZ128rmkz:
7127	case VPMULLWZ128rr:
7128	case VPMULLWZ128rrk:
7129	case VPMULLWZ128rrkz:
7130	case VPMULLWZ256rm:
7131	case VPMULLWZ256rmk:
7132	case VPMULLWZ256rmkz:
7133	case VPMULLWZ256rr:
7134	case VPMULLWZ256rrk:
7135	case VPMULLWZ256rrkz:
7136	case VPMULLWZrm:
7137	case VPMULLWZrmk:
7138	case VPMULLWZrmkz:
7139	case VPMULLWZrr:
7140	case VPMULLWZrrk:
7141	case VPMULLWZrrkz:
7142	case VPMULLWrm:
7143	case VPMULLWrr:
7144		return true;
7145	}
7146	return false;
7147}
7148
7149bool isPFPNACC(unsigned Opcode) {
7150	switch (Opcode) {
7151	case PFPNACCrm:
7152	case PFPNACCrr:
7153		return true;
7154	}
7155	return false;
7156}
7157
7158bool isTESTUI(unsigned Opcode) {
7159	return Opcode == TESTUI;
7160}
7161
7162bool isVPMOVZXWD(unsigned Opcode) {
7163	switch (Opcode) {
7164	case VPMOVZXWDYrm:
7165	case VPMOVZXWDYrr:
7166	case VPMOVZXWDZ128rm:
7167	case VPMOVZXWDZ128rmk:
7168	case VPMOVZXWDZ128rmkz:
7169	case VPMOVZXWDZ128rr:
7170	case VPMOVZXWDZ128rrk:
7171	case VPMOVZXWDZ128rrkz:
7172	case VPMOVZXWDZ256rm:
7173	case VPMOVZXWDZ256rmk:
7174	case VPMOVZXWDZ256rmkz:
7175	case VPMOVZXWDZ256rr:
7176	case VPMOVZXWDZ256rrk:
7177	case VPMOVZXWDZ256rrkz:
7178	case VPMOVZXWDZrm:
7179	case VPMOVZXWDZrmk:
7180	case VPMOVZXWDZrmkz:
7181	case VPMOVZXWDZrr:
7182	case VPMOVZXWDZrrk:
7183	case VPMOVZXWDZrrkz:
7184	case VPMOVZXWDrm:
7185	case VPMOVZXWDrr:
7186		return true;
7187	}
7188	return false;
7189}
7190
7191bool isVPDPWSSDS(unsigned Opcode) {
7192	switch (Opcode) {
7193	case VPDPWSSDSYrm:
7194	case VPDPWSSDSYrr:
7195	case VPDPWSSDSZ128m:
7196	case VPDPWSSDSZ128mb:
7197	case VPDPWSSDSZ128mbk:
7198	case VPDPWSSDSZ128mbkz:
7199	case VPDPWSSDSZ128mk:
7200	case VPDPWSSDSZ128mkz:
7201	case VPDPWSSDSZ128r:
7202	case VPDPWSSDSZ128rk:
7203	case VPDPWSSDSZ128rkz:
7204	case VPDPWSSDSZ256m:
7205	case VPDPWSSDSZ256mb:
7206	case VPDPWSSDSZ256mbk:
7207	case VPDPWSSDSZ256mbkz:
7208	case VPDPWSSDSZ256mk:
7209	case VPDPWSSDSZ256mkz:
7210	case VPDPWSSDSZ256r:
7211	case VPDPWSSDSZ256rk:
7212	case VPDPWSSDSZ256rkz:
7213	case VPDPWSSDSZm:
7214	case VPDPWSSDSZmb:
7215	case VPDPWSSDSZmbk:
7216	case VPDPWSSDSZmbkz:
7217	case VPDPWSSDSZmk:
7218	case VPDPWSSDSZmkz:
7219	case VPDPWSSDSZr:
7220	case VPDPWSSDSZrk:
7221	case VPDPWSSDSZrkz:
7222	case VPDPWSSDSrm:
7223	case VPDPWSSDSrr:
7224		return true;
7225	}
7226	return false;
7227}
7228
7229bool isINVLPG(unsigned Opcode) {
7230	return Opcode == INVLPG;
7231}
7232
7233bool isJCC(unsigned Opcode) {
7234	switch (Opcode) {
7235	case JCC_1:
7236	case JCC_2:
7237	case JCC_4:
7238		return true;
7239	}
7240	return false;
7241}
7242
7243bool isVPMOVZXWQ(unsigned Opcode) {
7244	switch (Opcode) {
7245	case VPMOVZXWQYrm:
7246	case VPMOVZXWQYrr:
7247	case VPMOVZXWQZ128rm:
7248	case VPMOVZXWQZ128rmk:
7249	case VPMOVZXWQZ128rmkz:
7250	case VPMOVZXWQZ128rr:
7251	case VPMOVZXWQZ128rrk:
7252	case VPMOVZXWQZ128rrkz:
7253	case VPMOVZXWQZ256rm:
7254	case VPMOVZXWQZ256rmk:
7255	case VPMOVZXWQZ256rmkz:
7256	case VPMOVZXWQZ256rr:
7257	case VPMOVZXWQZ256rrk:
7258	case VPMOVZXWQZ256rrkz:
7259	case VPMOVZXWQZrm:
7260	case VPMOVZXWQZrmk:
7261	case VPMOVZXWQZrmkz:
7262	case VPMOVZXWQZrr:
7263	case VPMOVZXWQZrrk:
7264	case VPMOVZXWQZrrkz:
7265	case VPMOVZXWQrm:
7266	case VPMOVZXWQrr:
7267		return true;
7268	}
7269	return false;
7270}
7271
7272bool isBSF(unsigned Opcode) {
7273	switch (Opcode) {
7274	case BSF16rm:
7275	case BSF16rr:
7276	case BSF32rm:
7277	case BSF32rr:
7278	case BSF64rm:
7279	case BSF64rr:
7280		return true;
7281	}
7282	return false;
7283}
7284
7285bool isROUNDPD(unsigned Opcode) {
7286	switch (Opcode) {
7287	case ROUNDPDm:
7288	case ROUNDPDr:
7289		return true;
7290	}
7291	return false;
7292}
7293
7294bool isSAVEPREVSSP(unsigned Opcode) {
7295	return Opcode == SAVEPREVSSP;
7296}
7297
7298bool isVSCATTERDPD(unsigned Opcode) {
7299	switch (Opcode) {
7300	case VSCATTERDPDZ128mr:
7301	case VSCATTERDPDZ256mr:
7302	case VSCATTERDPDZmr:
7303		return true;
7304	}
7305	return false;
7306}
7307
7308bool isBSR(unsigned Opcode) {
7309	switch (Opcode) {
7310	case BSR16rm:
7311	case BSR16rr:
7312	case BSR32rm:
7313	case BSR32rr:
7314	case BSR64rm:
7315	case BSR64rr:
7316		return true;
7317	}
7318	return false;
7319}
7320
7321bool isROUNDPS(unsigned Opcode) {
7322	switch (Opcode) {
7323	case ROUNDPSm:
7324	case ROUNDPSr:
7325		return true;
7326	}
7327	return false;
7328}
7329
7330bool isCVTPI2PD(unsigned Opcode) {
7331	switch (Opcode) {
7332	case MMX_CVTPI2PDrm:
7333	case MMX_CVTPI2PDrr:
7334		return true;
7335	}
7336	return false;
7337}
7338
7339bool isKTESTB(unsigned Opcode) {
7340	return Opcode == KTESTBrr;
7341}
7342
7343bool isKTESTD(unsigned Opcode) {
7344	return Opcode == KTESTDrr;
7345}
7346
7347bool isVSCATTERDPS(unsigned Opcode) {
7348	switch (Opcode) {
7349	case VSCATTERDPSZ128mr:
7350	case VSCATTERDPSZ256mr:
7351	case VSCATTERDPSZmr:
7352		return true;
7353	}
7354	return false;
7355}
7356
7357bool isFLD(unsigned Opcode) {
7358	switch (Opcode) {
7359	case LD_F32m:
7360	case LD_F64m:
7361	case LD_F80m:
7362	case LD_Frr:
7363		return true;
7364	}
7365	return false;
7366}
7367
7368bool isBTC(unsigned Opcode) {
7369	switch (Opcode) {
7370	case BTC16mi8:
7371	case BTC16mr:
7372	case BTC16ri8:
7373	case BTC16rr:
7374	case BTC32mi8:
7375	case BTC32mr:
7376	case BTC32ri8:
7377	case BTC32rr:
7378	case BTC64mi8:
7379	case BTC64mr:
7380	case BTC64ri8:
7381	case BTC64rr:
7382		return true;
7383	}
7384	return false;
7385}
7386
7387bool isVBCSTNEBF162PS(unsigned Opcode) {
7388	switch (Opcode) {
7389	case VBCSTNEBF162PSYrm:
7390	case VBCSTNEBF162PSrm:
7391		return true;
7392	}
7393	return false;
7394}
7395
7396bool isCVTPI2PS(unsigned Opcode) {
7397	switch (Opcode) {
7398	case MMX_CVTPI2PSrm:
7399	case MMX_CVTPI2PSrr:
7400		return true;
7401	}
7402	return false;
7403}
7404
7405bool isKTESTQ(unsigned Opcode) {
7406	return Opcode == KTESTQrr;
7407}
7408
7409bool isVSCALEFSD(unsigned Opcode) {
7410	switch (Opcode) {
7411	case VSCALEFSDZrm:
7412	case VSCALEFSDZrmk:
7413	case VSCALEFSDZrmkz:
7414	case VSCALEFSDZrr:
7415	case VSCALEFSDZrrb_Int:
7416	case VSCALEFSDZrrb_Intk:
7417	case VSCALEFSDZrrb_Intkz:
7418	case VSCALEFSDZrrk:
7419	case VSCALEFSDZrrkz:
7420		return true;
7421	}
7422	return false;
7423}
7424
7425bool isVSCALEFSH(unsigned Opcode) {
7426	switch (Opcode) {
7427	case VSCALEFSHZrm:
7428	case VSCALEFSHZrmk:
7429	case VSCALEFSHZrmkz:
7430	case VSCALEFSHZrr:
7431	case VSCALEFSHZrrb_Int:
7432	case VSCALEFSHZrrb_Intk:
7433	case VSCALEFSHZrrb_Intkz:
7434	case VSCALEFSHZrrk:
7435	case VSCALEFSHZrrkz:
7436		return true;
7437	}
7438	return false;
7439}
7440
7441bool isKTESTW(unsigned Opcode) {
7442	return Opcode == KTESTWrr;
7443}
7444
7445bool isXSTORE(unsigned Opcode) {
7446	return Opcode == XSTORE;
7447}
7448
7449bool isVFMADDSUB132PD(unsigned Opcode) {
7450	switch (Opcode) {
7451	case VFMADDSUB132PDYm:
7452	case VFMADDSUB132PDYr:
7453	case VFMADDSUB132PDZ128m:
7454	case VFMADDSUB132PDZ128mb:
7455	case VFMADDSUB132PDZ128mbk:
7456	case VFMADDSUB132PDZ128mbkz:
7457	case VFMADDSUB132PDZ128mk:
7458	case VFMADDSUB132PDZ128mkz:
7459	case VFMADDSUB132PDZ128r:
7460	case VFMADDSUB132PDZ128rk:
7461	case VFMADDSUB132PDZ128rkz:
7462	case VFMADDSUB132PDZ256m:
7463	case VFMADDSUB132PDZ256mb:
7464	case VFMADDSUB132PDZ256mbk:
7465	case VFMADDSUB132PDZ256mbkz:
7466	case VFMADDSUB132PDZ256mk:
7467	case VFMADDSUB132PDZ256mkz:
7468	case VFMADDSUB132PDZ256r:
7469	case VFMADDSUB132PDZ256rk:
7470	case VFMADDSUB132PDZ256rkz:
7471	case VFMADDSUB132PDZm:
7472	case VFMADDSUB132PDZmb:
7473	case VFMADDSUB132PDZmbk:
7474	case VFMADDSUB132PDZmbkz:
7475	case VFMADDSUB132PDZmk:
7476	case VFMADDSUB132PDZmkz:
7477	case VFMADDSUB132PDZr:
7478	case VFMADDSUB132PDZrb:
7479	case VFMADDSUB132PDZrbk:
7480	case VFMADDSUB132PDZrbkz:
7481	case VFMADDSUB132PDZrk:
7482	case VFMADDSUB132PDZrkz:
7483	case VFMADDSUB132PDm:
7484	case VFMADDSUB132PDr:
7485		return true;
7486	}
7487	return false;
7488}
7489
7490bool isVPSRAVD(unsigned Opcode) {
7491	switch (Opcode) {
7492	case VPSRAVDYrm:
7493	case VPSRAVDYrr:
7494	case VPSRAVDZ128rm:
7495	case VPSRAVDZ128rmb:
7496	case VPSRAVDZ128rmbk:
7497	case VPSRAVDZ128rmbkz:
7498	case VPSRAVDZ128rmk:
7499	case VPSRAVDZ128rmkz:
7500	case VPSRAVDZ128rr:
7501	case VPSRAVDZ128rrk:
7502	case VPSRAVDZ128rrkz:
7503	case VPSRAVDZ256rm:
7504	case VPSRAVDZ256rmb:
7505	case VPSRAVDZ256rmbk:
7506	case VPSRAVDZ256rmbkz:
7507	case VPSRAVDZ256rmk:
7508	case VPSRAVDZ256rmkz:
7509	case VPSRAVDZ256rr:
7510	case VPSRAVDZ256rrk:
7511	case VPSRAVDZ256rrkz:
7512	case VPSRAVDZrm:
7513	case VPSRAVDZrmb:
7514	case VPSRAVDZrmbk:
7515	case VPSRAVDZrmbkz:
7516	case VPSRAVDZrmk:
7517	case VPSRAVDZrmkz:
7518	case VPSRAVDZrr:
7519	case VPSRAVDZrrk:
7520	case VPSRAVDZrrkz:
7521	case VPSRAVDrm:
7522	case VPSRAVDrr:
7523		return true;
7524	}
7525	return false;
7526}
7527
7528bool isBTR(unsigned Opcode) {
7529	switch (Opcode) {
7530	case BTR16mi8:
7531	case BTR16mr:
7532	case BTR16ri8:
7533	case BTR16rr:
7534	case BTR32mi8:
7535	case BTR32mr:
7536	case BTR32ri8:
7537	case BTR32rr:
7538	case BTR64mi8:
7539	case BTR64mr:
7540	case BTR64ri8:
7541	case BTR64rr:
7542		return true;
7543	}
7544	return false;
7545}
7546
7547bool isBTS(unsigned Opcode) {
7548	switch (Opcode) {
7549	case BTS16mi8:
7550	case BTS16mr:
7551	case BTS16ri8:
7552	case BTS16rr:
7553	case BTS32mi8:
7554	case BTS32mr:
7555	case BTS32ri8:
7556	case BTS32rr:
7557	case BTS64mi8:
7558	case BTS64mr:
7559	case BTS64ri8:
7560	case BTS64rr:
7561		return true;
7562	}
7563	return false;
7564}
7565
7566bool isVFMADDSUB132PH(unsigned Opcode) {
7567	switch (Opcode) {
7568	case VFMADDSUB132PHZ128m:
7569	case VFMADDSUB132PHZ128mb:
7570	case VFMADDSUB132PHZ128mbk:
7571	case VFMADDSUB132PHZ128mbkz:
7572	case VFMADDSUB132PHZ128mk:
7573	case VFMADDSUB132PHZ128mkz:
7574	case VFMADDSUB132PHZ128r:
7575	case VFMADDSUB132PHZ128rk:
7576	case VFMADDSUB132PHZ128rkz:
7577	case VFMADDSUB132PHZ256m:
7578	case VFMADDSUB132PHZ256mb:
7579	case VFMADDSUB132PHZ256mbk:
7580	case VFMADDSUB132PHZ256mbkz:
7581	case VFMADDSUB132PHZ256mk:
7582	case VFMADDSUB132PHZ256mkz:
7583	case VFMADDSUB132PHZ256r:
7584	case VFMADDSUB132PHZ256rk:
7585	case VFMADDSUB132PHZ256rkz:
7586	case VFMADDSUB132PHZm:
7587	case VFMADDSUB132PHZmb:
7588	case VFMADDSUB132PHZmbk:
7589	case VFMADDSUB132PHZmbkz:
7590	case VFMADDSUB132PHZmk:
7591	case VFMADDSUB132PHZmkz:
7592	case VFMADDSUB132PHZr:
7593	case VFMADDSUB132PHZrb:
7594	case VFMADDSUB132PHZrbk:
7595	case VFMADDSUB132PHZrbkz:
7596	case VFMADDSUB132PHZrk:
7597	case VFMADDSUB132PHZrkz:
7598		return true;
7599	}
7600	return false;
7601}
7602
7603bool isLGDT(unsigned Opcode) {
7604	return Opcode == LGDT64m;
7605}
7606
7607bool isVSCALEFSS(unsigned Opcode) {
7608	switch (Opcode) {
7609	case VSCALEFSSZrm:
7610	case VSCALEFSSZrmk:
7611	case VSCALEFSSZrmkz:
7612	case VSCALEFSSZrr:
7613	case VSCALEFSSZrrb_Int:
7614	case VSCALEFSSZrrb_Intk:
7615	case VSCALEFSSZrrb_Intkz:
7616	case VSCALEFSSZrrk:
7617	case VSCALEFSSZrrkz:
7618		return true;
7619	}
7620	return false;
7621}
7622
7623bool isVEXTRACTF128(unsigned Opcode) {
7624	switch (Opcode) {
7625	case VEXTRACTF128mr:
7626	case VEXTRACTF128rr:
7627		return true;
7628	}
7629	return false;
7630}
7631
7632bool isPMOVSXBD(unsigned Opcode) {
7633	switch (Opcode) {
7634	case PMOVSXBDrm:
7635	case PMOVSXBDrr:
7636		return true;
7637	}
7638	return false;
7639}
7640
7641bool isKXNORB(unsigned Opcode) {
7642	return Opcode == KXNORBrr;
7643}
7644
7645bool isVFMADDSUB132PS(unsigned Opcode) {
7646	switch (Opcode) {
7647	case VFMADDSUB132PSYm:
7648	case VFMADDSUB132PSYr:
7649	case VFMADDSUB132PSZ128m:
7650	case VFMADDSUB132PSZ128mb:
7651	case VFMADDSUB132PSZ128mbk:
7652	case VFMADDSUB132PSZ128mbkz:
7653	case VFMADDSUB132PSZ128mk:
7654	case VFMADDSUB132PSZ128mkz:
7655	case VFMADDSUB132PSZ128r:
7656	case VFMADDSUB132PSZ128rk:
7657	case VFMADDSUB132PSZ128rkz:
7658	case VFMADDSUB132PSZ256m:
7659	case VFMADDSUB132PSZ256mb:
7660	case VFMADDSUB132PSZ256mbk:
7661	case VFMADDSUB132PSZ256mbkz:
7662	case VFMADDSUB132PSZ256mk:
7663	case VFMADDSUB132PSZ256mkz:
7664	case VFMADDSUB132PSZ256r:
7665	case VFMADDSUB132PSZ256rk:
7666	case VFMADDSUB132PSZ256rkz:
7667	case VFMADDSUB132PSZm:
7668	case VFMADDSUB132PSZmb:
7669	case VFMADDSUB132PSZmbk:
7670	case VFMADDSUB132PSZmbkz:
7671	case VFMADDSUB132PSZmk:
7672	case VFMADDSUB132PSZmkz:
7673	case VFMADDSUB132PSZr:
7674	case VFMADDSUB132PSZrb:
7675	case VFMADDSUB132PSZrbk:
7676	case VFMADDSUB132PSZrbkz:
7677	case VFMADDSUB132PSZrk:
7678	case VFMADDSUB132PSZrkz:
7679	case VFMADDSUB132PSm:
7680	case VFMADDSUB132PSr:
7681		return true;
7682	}
7683	return false;
7684}
7685
7686bool isKXNORD(unsigned Opcode) {
7687	return Opcode == KXNORDrr;
7688}
7689
7690bool isXRSTOR(unsigned Opcode) {
7691	return Opcode == XRSTOR;
7692}
7693
7694bool isVPSRAVQ(unsigned Opcode) {
7695	switch (Opcode) {
7696	case VPSRAVQZ128rm:
7697	case VPSRAVQZ128rmb:
7698	case VPSRAVQZ128rmbk:
7699	case VPSRAVQZ128rmbkz:
7700	case VPSRAVQZ128rmk:
7701	case VPSRAVQZ128rmkz:
7702	case VPSRAVQZ128rr:
7703	case VPSRAVQZ128rrk:
7704	case VPSRAVQZ128rrkz:
7705	case VPSRAVQZ256rm:
7706	case VPSRAVQZ256rmb:
7707	case VPSRAVQZ256rmbk:
7708	case VPSRAVQZ256rmbkz:
7709	case VPSRAVQZ256rmk:
7710	case VPSRAVQZ256rmkz:
7711	case VPSRAVQZ256rr:
7712	case VPSRAVQZ256rrk:
7713	case VPSRAVQZ256rrkz:
7714	case VPSRAVQZrm:
7715	case VPSRAVQZrmb:
7716	case VPSRAVQZrmbk:
7717	case VPSRAVQZrmbkz:
7718	case VPSRAVQZrmk:
7719	case VPSRAVQZrmkz:
7720	case VPSRAVQZrr:
7721	case VPSRAVQZrrk:
7722	case VPSRAVQZrrkz:
7723		return true;
7724	}
7725	return false;
7726}
7727
7728bool isVPSRAVW(unsigned Opcode) {
7729	switch (Opcode) {
7730	case VPSRAVWZ128rm:
7731	case VPSRAVWZ128rmk:
7732	case VPSRAVWZ128rmkz:
7733	case VPSRAVWZ128rr:
7734	case VPSRAVWZ128rrk:
7735	case VPSRAVWZ128rrkz:
7736	case VPSRAVWZ256rm:
7737	case VPSRAVWZ256rmk:
7738	case VPSRAVWZ256rmkz:
7739	case VPSRAVWZ256rr:
7740	case VPSRAVWZ256rrk:
7741	case VPSRAVWZ256rrkz:
7742	case VPSRAVWZrm:
7743	case VPSRAVWZrmk:
7744	case VPSRAVWZrmkz:
7745	case VPSRAVWZrr:
7746	case VPSRAVWZrrk:
7747	case VPSRAVWZrrkz:
7748		return true;
7749	}
7750	return false;
7751}
7752
7753bool isVPDPWSSD(unsigned Opcode) {
7754	switch (Opcode) {
7755	case VPDPWSSDYrm:
7756	case VPDPWSSDYrr:
7757	case VPDPWSSDZ128m:
7758	case VPDPWSSDZ128mb:
7759	case VPDPWSSDZ128mbk:
7760	case VPDPWSSDZ128mbkz:
7761	case VPDPWSSDZ128mk:
7762	case VPDPWSSDZ128mkz:
7763	case VPDPWSSDZ128r:
7764	case VPDPWSSDZ128rk:
7765	case VPDPWSSDZ128rkz:
7766	case VPDPWSSDZ256m:
7767	case VPDPWSSDZ256mb:
7768	case VPDPWSSDZ256mbk:
7769	case VPDPWSSDZ256mbkz:
7770	case VPDPWSSDZ256mk:
7771	case VPDPWSSDZ256mkz:
7772	case VPDPWSSDZ256r:
7773	case VPDPWSSDZ256rk:
7774	case VPDPWSSDZ256rkz:
7775	case VPDPWSSDZm:
7776	case VPDPWSSDZmb:
7777	case VPDPWSSDZmbk:
7778	case VPDPWSSDZmbkz:
7779	case VPDPWSSDZmk:
7780	case VPDPWSSDZmkz:
7781	case VPDPWSSDZr:
7782	case VPDPWSSDZrk:
7783	case VPDPWSSDZrkz:
7784	case VPDPWSSDrm:
7785	case VPDPWSSDrr:
7786		return true;
7787	}
7788	return false;
7789}
7790
7791bool isSQRTPD(unsigned Opcode) {
7792	switch (Opcode) {
7793	case SQRTPDm:
7794	case SQRTPDr:
7795		return true;
7796	}
7797	return false;
7798}
7799
7800bool isVDPPD(unsigned Opcode) {
7801	switch (Opcode) {
7802	case VDPPDrmi:
7803	case VDPPDrri:
7804		return true;
7805	}
7806	return false;
7807}
7808
7809bool isPMOVSXBQ(unsigned Opcode) {
7810	switch (Opcode) {
7811	case PMOVSXBQrm:
7812	case PMOVSXBQrr:
7813		return true;
7814	}
7815	return false;
7816}
7817
7818bool isPMADDWD(unsigned Opcode) {
7819	switch (Opcode) {
7820	case MMX_PMADDWDrm:
7821	case MMX_PMADDWDrr:
7822	case PMADDWDrm:
7823	case PMADDWDrr:
7824		return true;
7825	}
7826	return false;
7827}
7828
7829bool isKXNORQ(unsigned Opcode) {
7830	return Opcode == KXNORQrr;
7831}
7832
7833bool isSTUI(unsigned Opcode) {
7834	return Opcode == STUI;
7835}
7836
7837bool isINSERTQ(unsigned Opcode) {
7838	switch (Opcode) {
7839	case INSERTQ:
7840	case INSERTQI:
7841		return true;
7842	}
7843	return false;
7844}
7845
7846bool isPMOVSXBW(unsigned Opcode) {
7847	switch (Opcode) {
7848	case PMOVSXBWrm:
7849	case PMOVSXBWrr:
7850		return true;
7851	}
7852	return false;
7853}
7854
7855bool isVCVTSI2SD(unsigned Opcode) {
7856	switch (Opcode) {
7857	case VCVTSI2SDZrm_Int:
7858	case VCVTSI2SDZrr_Int:
7859	case VCVTSI2SDrm_Int:
7860	case VCVTSI2SDrr_Int:
7861	case VCVTSI642SDZrm_Int:
7862	case VCVTSI642SDZrr_Int:
7863	case VCVTSI642SDZrrb_Int:
7864	case VCVTSI642SDrm_Int:
7865	case VCVTSI642SDrr_Int:
7866		return true;
7867	}
7868	return false;
7869}
7870
7871bool isKXNORW(unsigned Opcode) {
7872	return Opcode == KXNORWrr;
7873}
7874
7875bool isVSCATTERPF0DPD(unsigned Opcode) {
7876	return Opcode == VSCATTERPF0DPDm;
7877}
7878
7879bool isVCVTSI2SH(unsigned Opcode) {
7880	switch (Opcode) {
7881	case VCVTSI2SHZrm_Int:
7882	case VCVTSI2SHZrr_Int:
7883	case VCVTSI2SHZrrb_Int:
7884	case VCVTSI642SHZrm_Int:
7885	case VCVTSI642SHZrr_Int:
7886	case VCVTSI642SHZrrb_Int:
7887		return true;
7888	}
7889	return false;
7890}
7891
7892bool isSQRTPS(unsigned Opcode) {
7893	switch (Opcode) {
7894	case SQRTPSm:
7895	case SQRTPSr:
7896		return true;
7897	}
7898	return false;
7899}
7900
7901bool isVDPPS(unsigned Opcode) {
7902	switch (Opcode) {
7903	case VDPPSYrmi:
7904	case VDPPSYrri:
7905	case VDPPSrmi:
7906	case VDPPSrri:
7907		return true;
7908	}
7909	return false;
7910}
7911
7912bool isPSUBSB(unsigned Opcode) {
7913	switch (Opcode) {
7914	case MMX_PSUBSBrm:
7915	case MMX_PSUBSBrr:
7916	case PSUBSBrm:
7917	case PSUBSBrr:
7918		return true;
7919	}
7920	return false;
7921}
7922
7923bool isVPSHRDVD(unsigned Opcode) {
7924	switch (Opcode) {
7925	case VPSHRDVDZ128m:
7926	case VPSHRDVDZ128mb:
7927	case VPSHRDVDZ128mbk:
7928	case VPSHRDVDZ128mbkz:
7929	case VPSHRDVDZ128mk:
7930	case VPSHRDVDZ128mkz:
7931	case VPSHRDVDZ128r:
7932	case VPSHRDVDZ128rk:
7933	case VPSHRDVDZ128rkz:
7934	case VPSHRDVDZ256m:
7935	case VPSHRDVDZ256mb:
7936	case VPSHRDVDZ256mbk:
7937	case VPSHRDVDZ256mbkz:
7938	case VPSHRDVDZ256mk:
7939	case VPSHRDVDZ256mkz:
7940	case VPSHRDVDZ256r:
7941	case VPSHRDVDZ256rk:
7942	case VPSHRDVDZ256rkz:
7943	case VPSHRDVDZm:
7944	case VPSHRDVDZmb:
7945	case VPSHRDVDZmbk:
7946	case VPSHRDVDZmbkz:
7947	case VPSHRDVDZmk:
7948	case VPSHRDVDZmkz:
7949	case VPSHRDVDZr:
7950	case VPSHRDVDZrk:
7951	case VPSHRDVDZrkz:
7952		return true;
7953	}
7954	return false;
7955}
7956
7957bool isFIST(unsigned Opcode) {
7958	switch (Opcode) {
7959	case IST_F16m:
7960	case IST_F32m:
7961		return true;
7962	}
7963	return false;
7964}
7965
7966bool isVCVTSI2SS(unsigned Opcode) {
7967	switch (Opcode) {
7968	case VCVTSI2SSZrm_Int:
7969	case VCVTSI2SSZrr_Int:
7970	case VCVTSI2SSZrrb_Int:
7971	case VCVTSI2SSrm_Int:
7972	case VCVTSI2SSrr_Int:
7973	case VCVTSI642SSZrm_Int:
7974	case VCVTSI642SSZrr_Int:
7975	case VCVTSI642SSZrrb_Int:
7976	case VCVTSI642SSrm_Int:
7977	case VCVTSI642SSrr_Int:
7978		return true;
7979	}
7980	return false;
7981}
7982
7983bool isVSCATTERPF0DPS(unsigned Opcode) {
7984	return Opcode == VSCATTERPF0DPSm;
7985}
7986
7987bool isVMOVNTPD(unsigned Opcode) {
7988	switch (Opcode) {
7989	case VMOVNTPDYmr:
7990	case VMOVNTPDZ128mr:
7991	case VMOVNTPDZ256mr:
7992	case VMOVNTPDZmr:
7993	case VMOVNTPDmr:
7994		return true;
7995	}
7996	return false;
7997}
7998
7999bool isROUNDSD(unsigned Opcode) {
8000	switch (Opcode) {
8001	case ROUNDSDm_Int:
8002	case ROUNDSDr_Int:
8003		return true;
8004	}
8005	return false;
8006}
8007
8008bool isVPSHRDVQ(unsigned Opcode) {
8009	switch (Opcode) {
8010	case VPSHRDVQZ128m:
8011	case VPSHRDVQZ128mb:
8012	case VPSHRDVQZ128mbk:
8013	case VPSHRDVQZ128mbkz:
8014	case VPSHRDVQZ128mk:
8015	case VPSHRDVQZ128mkz:
8016	case VPSHRDVQZ128r:
8017	case VPSHRDVQZ128rk:
8018	case VPSHRDVQZ128rkz:
8019	case VPSHRDVQZ256m:
8020	case VPSHRDVQZ256mb:
8021	case VPSHRDVQZ256mbk:
8022	case VPSHRDVQZ256mbkz:
8023	case VPSHRDVQZ256mk:
8024	case VPSHRDVQZ256mkz:
8025	case VPSHRDVQZ256r:
8026	case VPSHRDVQZ256rk:
8027	case VPSHRDVQZ256rkz:
8028	case VPSHRDVQZm:
8029	case VPSHRDVQZmb:
8030	case VPSHRDVQZmbk:
8031	case VPSHRDVQZmbkz:
8032	case VPSHRDVQZmk:
8033	case VPSHRDVQZmkz:
8034	case VPSHRDVQZr:
8035	case VPSHRDVQZrk:
8036	case VPSHRDVQZrkz:
8037		return true;
8038	}
8039	return false;
8040}
8041
8042bool isPSIGNB(unsigned Opcode) {
8043	switch (Opcode) {
8044	case MMX_PSIGNBrm:
8045	case MMX_PSIGNBrr:
8046	case PSIGNBrm:
8047	case PSIGNBrr:
8048		return true;
8049	}
8050	return false;
8051}
8052
8053bool isJECXZ(unsigned Opcode) {
8054	return Opcode == JECXZ;
8055}
8056
8057bool isPSIGND(unsigned Opcode) {
8058	switch (Opcode) {
8059	case MMX_PSIGNDrm:
8060	case MMX_PSIGNDrr:
8061	case PSIGNDrm:
8062	case PSIGNDrr:
8063		return true;
8064	}
8065	return false;
8066}
8067
8068bool isPSUBSW(unsigned Opcode) {
8069	switch (Opcode) {
8070	case MMX_PSUBSWrm:
8071	case MMX_PSUBSWrr:
8072	case PSUBSWrm:
8073	case PSUBSWrr:
8074		return true;
8075	}
8076	return false;
8077}
8078
8079bool isMOVDQ2Q(unsigned Opcode) {
8080	return Opcode == MMX_MOVDQ2Qrr;
8081}
8082
8083bool isPUSHFD(unsigned Opcode) {
8084	return Opcode == PUSHF32;
8085}
8086
8087bool isVMOVNTPS(unsigned Opcode) {
8088	switch (Opcode) {
8089	case VMOVNTPSYmr:
8090	case VMOVNTPSZ128mr:
8091	case VMOVNTPSZ256mr:
8092	case VMOVNTPSZmr:
8093	case VMOVNTPSmr:
8094		return true;
8095	}
8096	return false;
8097}
8098
8099bool isROUNDSS(unsigned Opcode) {
8100	switch (Opcode) {
8101	case ROUNDSSm_Int:
8102	case ROUNDSSr_Int:
8103		return true;
8104	}
8105	return false;
8106}
8107
8108bool isVAESDECLAST(unsigned Opcode) {
8109	switch (Opcode) {
8110	case VAESDECLASTYrm:
8111	case VAESDECLASTYrr:
8112	case VAESDECLASTZ128rm:
8113	case VAESDECLASTZ128rr:
8114	case VAESDECLASTZ256rm:
8115	case VAESDECLASTZ256rr:
8116	case VAESDECLASTZrm:
8117	case VAESDECLASTZrr:
8118	case VAESDECLASTrm:
8119	case VAESDECLASTrr:
8120		return true;
8121	}
8122	return false;
8123}
8124
8125bool isPAVGB(unsigned Opcode) {
8126	switch (Opcode) {
8127	case MMX_PAVGBrm:
8128	case MMX_PAVGBrr:
8129	case PAVGBrm:
8130	case PAVGBrr:
8131		return true;
8132	}
8133	return false;
8134}
8135
8136bool isVPSUBB(unsigned Opcode) {
8137	switch (Opcode) {
8138	case VPSUBBYrm:
8139	case VPSUBBYrr:
8140	case VPSUBBZ128rm:
8141	case VPSUBBZ128rmk:
8142	case VPSUBBZ128rmkz:
8143	case VPSUBBZ128rr:
8144	case VPSUBBZ128rrk:
8145	case VPSUBBZ128rrkz:
8146	case VPSUBBZ256rm:
8147	case VPSUBBZ256rmk:
8148	case VPSUBBZ256rmkz:
8149	case VPSUBBZ256rr:
8150	case VPSUBBZ256rrk:
8151	case VPSUBBZ256rrkz:
8152	case VPSUBBZrm:
8153	case VPSUBBZrmk:
8154	case VPSUBBZrmkz:
8155	case VPSUBBZrr:
8156	case VPSUBBZrrk:
8157	case VPSUBBZrrkz:
8158	case VPSUBBrm:
8159	case VPSUBBrr:
8160		return true;
8161	}
8162	return false;
8163}
8164
8165bool isVPSHRDVW(unsigned Opcode) {
8166	switch (Opcode) {
8167	case VPSHRDVWZ128m:
8168	case VPSHRDVWZ128mk:
8169	case VPSHRDVWZ128mkz:
8170	case VPSHRDVWZ128r:
8171	case VPSHRDVWZ128rk:
8172	case VPSHRDVWZ128rkz:
8173	case VPSHRDVWZ256m:
8174	case VPSHRDVWZ256mk:
8175	case VPSHRDVWZ256mkz:
8176	case VPSHRDVWZ256r:
8177	case VPSHRDVWZ256rk:
8178	case VPSHRDVWZ256rkz:
8179	case VPSHRDVWZm:
8180	case VPSHRDVWZmk:
8181	case VPSHRDVWZmkz:
8182	case VPSHRDVWZr:
8183	case VPSHRDVWZrk:
8184	case VPSHRDVWZrkz:
8185		return true;
8186	}
8187	return false;
8188}
8189
8190bool isVPSUBD(unsigned Opcode) {
8191	switch (Opcode) {
8192	case VPSUBDYrm:
8193	case VPSUBDYrr:
8194	case VPSUBDZ128rm:
8195	case VPSUBDZ128rmb:
8196	case VPSUBDZ128rmbk:
8197	case VPSUBDZ128rmbkz:
8198	case VPSUBDZ128rmk:
8199	case VPSUBDZ128rmkz:
8200	case VPSUBDZ128rr:
8201	case VPSUBDZ128rrk:
8202	case VPSUBDZ128rrkz:
8203	case VPSUBDZ256rm:
8204	case VPSUBDZ256rmb:
8205	case VPSUBDZ256rmbk:
8206	case VPSUBDZ256rmbkz:
8207	case VPSUBDZ256rmk:
8208	case VPSUBDZ256rmkz:
8209	case VPSUBDZ256rr:
8210	case VPSUBDZ256rrk:
8211	case VPSUBDZ256rrkz:
8212	case VPSUBDZrm:
8213	case VPSUBDZrmb:
8214	case VPSUBDZrmbk:
8215	case VPSUBDZrmbkz:
8216	case VPSUBDZrmk:
8217	case VPSUBDZrmkz:
8218	case VPSUBDZrr:
8219	case VPSUBDZrrk:
8220	case VPSUBDZrrkz:
8221	case VPSUBDrm:
8222	case VPSUBDrr:
8223		return true;
8224	}
8225	return false;
8226}
8227
8228bool isPUSHFQ(unsigned Opcode) {
8229	return Opcode == PUSHF64;
8230}
8231
8232bool isPSIGNW(unsigned Opcode) {
8233	switch (Opcode) {
8234	case MMX_PSIGNWrm:
8235	case MMX_PSIGNWrr:
8236	case PSIGNWrm:
8237	case PSIGNWrr:
8238		return true;
8239	}
8240	return false;
8241}
8242
8243bool isVBROADCASTSD(unsigned Opcode) {
8244	switch (Opcode) {
8245	case VBROADCASTSDYrm:
8246	case VBROADCASTSDYrr:
8247	case VBROADCASTSDZ256rm:
8248	case VBROADCASTSDZ256rmk:
8249	case VBROADCASTSDZ256rmkz:
8250	case VBROADCASTSDZ256rr:
8251	case VBROADCASTSDZ256rrk:
8252	case VBROADCASTSDZ256rrkz:
8253	case VBROADCASTSDZrm:
8254	case VBROADCASTSDZrmk:
8255	case VBROADCASTSDZrmkz:
8256	case VBROADCASTSDZrr:
8257	case VBROADCASTSDZrrk:
8258	case VBROADCASTSDZrrkz:
8259		return true;
8260	}
8261	return false;
8262}
8263
8264bool isVPSUBQ(unsigned Opcode) {
8265	switch (Opcode) {
8266	case VPSUBQYrm:
8267	case VPSUBQYrr:
8268	case VPSUBQZ128rm:
8269	case VPSUBQZ128rmb:
8270	case VPSUBQZ128rmbk:
8271	case VPSUBQZ128rmbkz:
8272	case VPSUBQZ128rmk:
8273	case VPSUBQZ128rmkz:
8274	case VPSUBQZ128rr:
8275	case VPSUBQZ128rrk:
8276	case VPSUBQZ128rrkz:
8277	case VPSUBQZ256rm:
8278	case VPSUBQZ256rmb:
8279	case VPSUBQZ256rmbk:
8280	case VPSUBQZ256rmbkz:
8281	case VPSUBQZ256rmk:
8282	case VPSUBQZ256rmkz:
8283	case VPSUBQZ256rr:
8284	case VPSUBQZ256rrk:
8285	case VPSUBQZ256rrkz:
8286	case VPSUBQZrm:
8287	case VPSUBQZrmb:
8288	case VPSUBQZrmbk:
8289	case VPSUBQZrmbkz:
8290	case VPSUBQZrmk:
8291	case VPSUBQZrmkz:
8292	case VPSUBQZrr:
8293	case VPSUBQZrrk:
8294	case VPSUBQZrrkz:
8295	case VPSUBQrm:
8296	case VPSUBQrr:
8297		return true;
8298	}
8299	return false;
8300}
8301
8302bool isPMOVSXDQ(unsigned Opcode) {
8303	switch (Opcode) {
8304	case PMOVSXDQrm:
8305	case PMOVSXDQrr:
8306		return true;
8307	}
8308	return false;
8309}
8310
8311bool isPAVGW(unsigned Opcode) {
8312	switch (Opcode) {
8313	case MMX_PAVGWrm:
8314	case MMX_PAVGWrr:
8315	case PAVGWrm:
8316	case PAVGWrr:
8317		return true;
8318	}
8319	return false;
8320}
8321
8322bool isVFMSUBADD132PD(unsigned Opcode) {
8323	switch (Opcode) {
8324	case VFMSUBADD132PDYm:
8325	case VFMSUBADD132PDYr:
8326	case VFMSUBADD132PDZ128m:
8327	case VFMSUBADD132PDZ128mb:
8328	case VFMSUBADD132PDZ128mbk:
8329	case VFMSUBADD132PDZ128mbkz:
8330	case VFMSUBADD132PDZ128mk:
8331	case VFMSUBADD132PDZ128mkz:
8332	case VFMSUBADD132PDZ128r:
8333	case VFMSUBADD132PDZ128rk:
8334	case VFMSUBADD132PDZ128rkz:
8335	case VFMSUBADD132PDZ256m:
8336	case VFMSUBADD132PDZ256mb:
8337	case VFMSUBADD132PDZ256mbk:
8338	case VFMSUBADD132PDZ256mbkz:
8339	case VFMSUBADD132PDZ256mk:
8340	case VFMSUBADD132PDZ256mkz:
8341	case VFMSUBADD132PDZ256r:
8342	case VFMSUBADD132PDZ256rk:
8343	case VFMSUBADD132PDZ256rkz:
8344	case VFMSUBADD132PDZm:
8345	case VFMSUBADD132PDZmb:
8346	case VFMSUBADD132PDZmbk:
8347	case VFMSUBADD132PDZmbkz:
8348	case VFMSUBADD132PDZmk:
8349	case VFMSUBADD132PDZmkz:
8350	case VFMSUBADD132PDZr:
8351	case VFMSUBADD132PDZrb:
8352	case VFMSUBADD132PDZrbk:
8353	case VFMSUBADD132PDZrbkz:
8354	case VFMSUBADD132PDZrk:
8355	case VFMSUBADD132PDZrkz:
8356	case VFMSUBADD132PDm:
8357	case VFMSUBADD132PDr:
8358		return true;
8359	}
8360	return false;
8361}
8362
8363bool isVPSUBW(unsigned Opcode) {
8364	switch (Opcode) {
8365	case VPSUBWYrm:
8366	case VPSUBWYrr:
8367	case VPSUBWZ128rm:
8368	case VPSUBWZ128rmk:
8369	case VPSUBWZ128rmkz:
8370	case VPSUBWZ128rr:
8371	case VPSUBWZ128rrk:
8372	case VPSUBWZ128rrkz:
8373	case VPSUBWZ256rm:
8374	case VPSUBWZ256rmk:
8375	case VPSUBWZ256rmkz:
8376	case VPSUBWZ256rr:
8377	case VPSUBWZ256rrk:
8378	case VPSUBWZ256rrkz:
8379	case VPSUBWZrm:
8380	case VPSUBWZrmk:
8381	case VPSUBWZrmkz:
8382	case VPSUBWZrr:
8383	case VPSUBWZrrk:
8384	case VPSUBWZrrkz:
8385	case VPSUBWrm:
8386	case VPSUBWrr:
8387		return true;
8388	}
8389	return false;
8390}
8391
8392bool isVCVTPS2PHX(unsigned Opcode) {
8393	switch (Opcode) {
8394	case VCVTPS2PHXZ128rm:
8395	case VCVTPS2PHXZ128rmb:
8396	case VCVTPS2PHXZ128rmbk:
8397	case VCVTPS2PHXZ128rmbkz:
8398	case VCVTPS2PHXZ128rmk:
8399	case VCVTPS2PHXZ128rmkz:
8400	case VCVTPS2PHXZ128rr:
8401	case VCVTPS2PHXZ128rrk:
8402	case VCVTPS2PHXZ128rrkz:
8403	case VCVTPS2PHXZ256rm:
8404	case VCVTPS2PHXZ256rmb:
8405	case VCVTPS2PHXZ256rmbk:
8406	case VCVTPS2PHXZ256rmbkz:
8407	case VCVTPS2PHXZ256rmk:
8408	case VCVTPS2PHXZ256rmkz:
8409	case VCVTPS2PHXZ256rr:
8410	case VCVTPS2PHXZ256rrk:
8411	case VCVTPS2PHXZ256rrkz:
8412	case VCVTPS2PHXZrm:
8413	case VCVTPS2PHXZrmb:
8414	case VCVTPS2PHXZrmbk:
8415	case VCVTPS2PHXZrmbkz:
8416	case VCVTPS2PHXZrmk:
8417	case VCVTPS2PHXZrmkz:
8418	case VCVTPS2PHXZrr:
8419	case VCVTPS2PHXZrrb:
8420	case VCVTPS2PHXZrrbk:
8421	case VCVTPS2PHXZrrbkz:
8422	case VCVTPS2PHXZrrk:
8423	case VCVTPS2PHXZrrkz:
8424		return true;
8425	}
8426	return false;
8427}
8428
8429bool isMOVHLPS(unsigned Opcode) {
8430	return Opcode == MOVHLPSrr;
8431}
8432
8433bool isVFMSUBADD132PH(unsigned Opcode) {
8434	switch (Opcode) {
8435	case VFMSUBADD132PHZ128m:
8436	case VFMSUBADD132PHZ128mb:
8437	case VFMSUBADD132PHZ128mbk:
8438	case VFMSUBADD132PHZ128mbkz:
8439	case VFMSUBADD132PHZ128mk:
8440	case VFMSUBADD132PHZ128mkz:
8441	case VFMSUBADD132PHZ128r:
8442	case VFMSUBADD132PHZ128rk:
8443	case VFMSUBADD132PHZ128rkz:
8444	case VFMSUBADD132PHZ256m:
8445	case VFMSUBADD132PHZ256mb:
8446	case VFMSUBADD132PHZ256mbk:
8447	case VFMSUBADD132PHZ256mbkz:
8448	case VFMSUBADD132PHZ256mk:
8449	case VFMSUBADD132PHZ256mkz:
8450	case VFMSUBADD132PHZ256r:
8451	case VFMSUBADD132PHZ256rk:
8452	case VFMSUBADD132PHZ256rkz:
8453	case VFMSUBADD132PHZm:
8454	case VFMSUBADD132PHZmb:
8455	case VFMSUBADD132PHZmbk:
8456	case VFMSUBADD132PHZmbkz:
8457	case VFMSUBADD132PHZmk:
8458	case VFMSUBADD132PHZmkz:
8459	case VFMSUBADD132PHZr:
8460	case VFMSUBADD132PHZrb:
8461	case VFMSUBADD132PHZrbk:
8462	case VFMSUBADD132PHZrbkz:
8463	case VFMSUBADD132PHZrk:
8464	case VFMSUBADD132PHZrkz:
8465		return true;
8466	}
8467	return false;
8468}
8469
8470bool isVSHUFF64X2(unsigned Opcode) {
8471	switch (Opcode) {
8472	case VSHUFF64X2Z256rmbi:
8473	case VSHUFF64X2Z256rmbik:
8474	case VSHUFF64X2Z256rmbikz:
8475	case VSHUFF64X2Z256rmi:
8476	case VSHUFF64X2Z256rmik:
8477	case VSHUFF64X2Z256rmikz:
8478	case VSHUFF64X2Z256rri:
8479	case VSHUFF64X2Z256rrik:
8480	case VSHUFF64X2Z256rrikz:
8481	case VSHUFF64X2Zrmbi:
8482	case VSHUFF64X2Zrmbik:
8483	case VSHUFF64X2Zrmbikz:
8484	case VSHUFF64X2Zrmi:
8485	case VSHUFF64X2Zrmik:
8486	case VSHUFF64X2Zrmikz:
8487	case VSHUFF64X2Zrri:
8488	case VSHUFF64X2Zrrik:
8489	case VSHUFF64X2Zrrikz:
8490		return true;
8491	}
8492	return false;
8493}
8494
8495bool isVBROADCASTSS(unsigned Opcode) {
8496	switch (Opcode) {
8497	case VBROADCASTSSYrm:
8498	case VBROADCASTSSYrr:
8499	case VBROADCASTSSZ128rm:
8500	case VBROADCASTSSZ128rmk:
8501	case VBROADCASTSSZ128rmkz:
8502	case VBROADCASTSSZ128rr:
8503	case VBROADCASTSSZ128rrk:
8504	case VBROADCASTSSZ128rrkz:
8505	case VBROADCASTSSZ256rm:
8506	case VBROADCASTSSZ256rmk:
8507	case VBROADCASTSSZ256rmkz:
8508	case VBROADCASTSSZ256rr:
8509	case VBROADCASTSSZ256rrk:
8510	case VBROADCASTSSZ256rrkz:
8511	case VBROADCASTSSZrm:
8512	case VBROADCASTSSZrmk:
8513	case VBROADCASTSSZrmkz:
8514	case VBROADCASTSSZrr:
8515	case VBROADCASTSSZrrk:
8516	case VBROADCASTSSZrrkz:
8517	case VBROADCASTSSrm:
8518	case VBROADCASTSSrr:
8519		return true;
8520	}
8521	return false;
8522}
8523
8524bool isVFMSUBADD132PS(unsigned Opcode) {
8525	switch (Opcode) {
8526	case VFMSUBADD132PSYm:
8527	case VFMSUBADD132PSYr:
8528	case VFMSUBADD132PSZ128m:
8529	case VFMSUBADD132PSZ128mb:
8530	case VFMSUBADD132PSZ128mbk:
8531	case VFMSUBADD132PSZ128mbkz:
8532	case VFMSUBADD132PSZ128mk:
8533	case VFMSUBADD132PSZ128mkz:
8534	case VFMSUBADD132PSZ128r:
8535	case VFMSUBADD132PSZ128rk:
8536	case VFMSUBADD132PSZ128rkz:
8537	case VFMSUBADD132PSZ256m:
8538	case VFMSUBADD132PSZ256mb:
8539	case VFMSUBADD132PSZ256mbk:
8540	case VFMSUBADD132PSZ256mbkz:
8541	case VFMSUBADD132PSZ256mk:
8542	case VFMSUBADD132PSZ256mkz:
8543	case VFMSUBADD132PSZ256r:
8544	case VFMSUBADD132PSZ256rk:
8545	case VFMSUBADD132PSZ256rkz:
8546	case VFMSUBADD132PSZm:
8547	case VFMSUBADD132PSZmb:
8548	case VFMSUBADD132PSZmbk:
8549	case VFMSUBADD132PSZmbkz:
8550	case VFMSUBADD132PSZmk:
8551	case VFMSUBADD132PSZmkz:
8552	case VFMSUBADD132PSZr:
8553	case VFMSUBADD132PSZrb:
8554	case VFMSUBADD132PSZrbk:
8555	case VFMSUBADD132PSZrbkz:
8556	case VFMSUBADD132PSZrk:
8557	case VFMSUBADD132PSZrkz:
8558	case VFMSUBADD132PSm:
8559	case VFMSUBADD132PSr:
8560		return true;
8561	}
8562	return false;
8563}
8564
8565bool isMAXPD(unsigned Opcode) {
8566	switch (Opcode) {
8567	case MAXPDrm:
8568	case MAXPDrr:
8569		return true;
8570	}
8571	return false;
8572}
8573
8574bool isSQRTSD(unsigned Opcode) {
8575	switch (Opcode) {
8576	case SQRTSDm_Int:
8577	case SQRTSDr_Int:
8578		return true;
8579	}
8580	return false;
8581}
8582
8583bool isCVTPD2DQ(unsigned Opcode) {
8584	switch (Opcode) {
8585	case CVTPD2DQrm:
8586	case CVTPD2DQrr:
8587		return true;
8588	}
8589	return false;
8590}
8591
8592bool isMAXPS(unsigned Opcode) {
8593	switch (Opcode) {
8594	case MAXPSrm:
8595	case MAXPSrr:
8596		return true;
8597	}
8598	return false;
8599}
8600
8601bool isVPMOVQB(unsigned Opcode) {
8602	switch (Opcode) {
8603	case VPMOVQBZ128mr:
8604	case VPMOVQBZ128mrk:
8605	case VPMOVQBZ128rr:
8606	case VPMOVQBZ128rrk:
8607	case VPMOVQBZ128rrkz:
8608	case VPMOVQBZ256mr:
8609	case VPMOVQBZ256mrk:
8610	case VPMOVQBZ256rr:
8611	case VPMOVQBZ256rrk:
8612	case VPMOVQBZ256rrkz:
8613	case VPMOVQBZmr:
8614	case VPMOVQBZmrk:
8615	case VPMOVQBZrr:
8616	case VPMOVQBZrrk:
8617	case VPMOVQBZrrkz:
8618		return true;
8619	}
8620	return false;
8621}
8622
8623bool isINVPCID(unsigned Opcode) {
8624	switch (Opcode) {
8625	case INVPCID32:
8626	case INVPCID64:
8627		return true;
8628	}
8629	return false;
8630}
8631
8632bool isVCVTPS2DQ(unsigned Opcode) {
8633	switch (Opcode) {
8634	case VCVTPS2DQYrm:
8635	case VCVTPS2DQYrr:
8636	case VCVTPS2DQZ128rm:
8637	case VCVTPS2DQZ128rmb:
8638	case VCVTPS2DQZ128rmbk:
8639	case VCVTPS2DQZ128rmbkz:
8640	case VCVTPS2DQZ128rmk:
8641	case VCVTPS2DQZ128rmkz:
8642	case VCVTPS2DQZ128rr:
8643	case VCVTPS2DQZ128rrk:
8644	case VCVTPS2DQZ128rrkz:
8645	case VCVTPS2DQZ256rm:
8646	case VCVTPS2DQZ256rmb:
8647	case VCVTPS2DQZ256rmbk:
8648	case VCVTPS2DQZ256rmbkz:
8649	case VCVTPS2DQZ256rmk:
8650	case VCVTPS2DQZ256rmkz:
8651	case VCVTPS2DQZ256rr:
8652	case VCVTPS2DQZ256rrk:
8653	case VCVTPS2DQZ256rrkz:
8654	case VCVTPS2DQZrm:
8655	case VCVTPS2DQZrmb:
8656	case VCVTPS2DQZrmbk:
8657	case VCVTPS2DQZrmbkz:
8658	case VCVTPS2DQZrmk:
8659	case VCVTPS2DQZrmkz:
8660	case VCVTPS2DQZrr:
8661	case VCVTPS2DQZrrb:
8662	case VCVTPS2DQZrrbk:
8663	case VCVTPS2DQZrrbkz:
8664	case VCVTPS2DQZrrk:
8665	case VCVTPS2DQZrrkz:
8666	case VCVTPS2DQrm:
8667	case VCVTPS2DQrr:
8668		return true;
8669	}
8670	return false;
8671}
8672
8673bool isSQRTSS(unsigned Opcode) {
8674	switch (Opcode) {
8675	case SQRTSSm_Int:
8676	case SQRTSSr_Int:
8677		return true;
8678	}
8679	return false;
8680}
8681
8682bool isVADDPD(unsigned Opcode) {
8683	switch (Opcode) {
8684	case VADDPDYrm:
8685	case VADDPDYrr:
8686	case VADDPDZ128rm:
8687	case VADDPDZ128rmb:
8688	case VADDPDZ128rmbk:
8689	case VADDPDZ128rmbkz:
8690	case VADDPDZ128rmk:
8691	case VADDPDZ128rmkz:
8692	case VADDPDZ128rr:
8693	case VADDPDZ128rrk:
8694	case VADDPDZ128rrkz:
8695	case VADDPDZ256rm:
8696	case VADDPDZ256rmb:
8697	case VADDPDZ256rmbk:
8698	case VADDPDZ256rmbkz:
8699	case VADDPDZ256rmk:
8700	case VADDPDZ256rmkz:
8701	case VADDPDZ256rr:
8702	case VADDPDZ256rrk:
8703	case VADDPDZ256rrkz:
8704	case VADDPDZrm:
8705	case VADDPDZrmb:
8706	case VADDPDZrmbk:
8707	case VADDPDZrmbkz:
8708	case VADDPDZrmk:
8709	case VADDPDZrmkz:
8710	case VADDPDZrr:
8711	case VADDPDZrrb:
8712	case VADDPDZrrbk:
8713	case VADDPDZrrbkz:
8714	case VADDPDZrrk:
8715	case VADDPDZrrkz:
8716	case VADDPDrm:
8717	case VADDPDrr:
8718		return true;
8719	}
8720	return false;
8721}
8722
8723bool isLODSB(unsigned Opcode) {
8724	return Opcode == LODSB;
8725}
8726
8727bool isLODSD(unsigned Opcode) {
8728	return Opcode == LODSL;
8729}
8730
8731bool isV4FNMADDPS(unsigned Opcode) {
8732	switch (Opcode) {
8733	case V4FNMADDPSrm:
8734	case V4FNMADDPSrmk:
8735	case V4FNMADDPSrmkz:
8736		return true;
8737	}
8738	return false;
8739}
8740
8741bool isIRETD(unsigned Opcode) {
8742	return Opcode == IRET32;
8743}
8744
8745bool isVADDPH(unsigned Opcode) {
8746	switch (Opcode) {
8747	case VADDPHZ128rm:
8748	case VADDPHZ128rmb:
8749	case VADDPHZ128rmbk:
8750	case VADDPHZ128rmbkz:
8751	case VADDPHZ128rmk:
8752	case VADDPHZ128rmkz:
8753	case VADDPHZ128rr:
8754	case VADDPHZ128rrk:
8755	case VADDPHZ128rrkz:
8756	case VADDPHZ256rm:
8757	case VADDPHZ256rmb:
8758	case VADDPHZ256rmbk:
8759	case VADDPHZ256rmbkz:
8760	case VADDPHZ256rmk:
8761	case VADDPHZ256rmkz:
8762	case VADDPHZ256rr:
8763	case VADDPHZ256rrk:
8764	case VADDPHZ256rrkz:
8765	case VADDPHZrm:
8766	case VADDPHZrmb:
8767	case VADDPHZrmbk:
8768	case VADDPHZrmbkz:
8769	case VADDPHZrmk:
8770	case VADDPHZrmkz:
8771	case VADDPHZrr:
8772	case VADDPHZrrb:
8773	case VADDPHZrrbk:
8774	case VADDPHZrrbkz:
8775	case VADDPHZrrk:
8776	case VADDPHZrrkz:
8777		return true;
8778	}
8779	return false;
8780}
8781
8782bool isVHADDPD(unsigned Opcode) {
8783	switch (Opcode) {
8784	case VHADDPDYrm:
8785	case VHADDPDYrr:
8786	case VHADDPDrm:
8787	case VHADDPDrr:
8788		return true;
8789	}
8790	return false;
8791}
8792
8793bool isVPMOVQD(unsigned Opcode) {
8794	switch (Opcode) {
8795	case VPMOVQDZ128mr:
8796	case VPMOVQDZ128mrk:
8797	case VPMOVQDZ128rr:
8798	case VPMOVQDZ128rrk:
8799	case VPMOVQDZ128rrkz:
8800	case VPMOVQDZ256mr:
8801	case VPMOVQDZ256mrk:
8802	case VPMOVQDZ256rr:
8803	case VPMOVQDZ256rrk:
8804	case VPMOVQDZ256rrkz:
8805	case VPMOVQDZmr:
8806	case VPMOVQDZmrk:
8807	case VPMOVQDZrr:
8808	case VPMOVQDZrrk:
8809	case VPMOVQDZrrkz:
8810		return true;
8811	}
8812	return false;
8813}
8814
8815bool isVPSUBUSB(unsigned Opcode) {
8816	switch (Opcode) {
8817	case VPSUBUSBYrm:
8818	case VPSUBUSBYrr:
8819	case VPSUBUSBZ128rm:
8820	case VPSUBUSBZ128rmk:
8821	case VPSUBUSBZ128rmkz:
8822	case VPSUBUSBZ128rr:
8823	case VPSUBUSBZ128rrk:
8824	case VPSUBUSBZ128rrkz:
8825	case VPSUBUSBZ256rm:
8826	case VPSUBUSBZ256rmk:
8827	case VPSUBUSBZ256rmkz:
8828	case VPSUBUSBZ256rr:
8829	case VPSUBUSBZ256rrk:
8830	case VPSUBUSBZ256rrkz:
8831	case VPSUBUSBZrm:
8832	case VPSUBUSBZrmk:
8833	case VPSUBUSBZrmkz:
8834	case VPSUBUSBZrr:
8835	case VPSUBUSBZrrk:
8836	case VPSUBUSBZrrkz:
8837	case VPSUBUSBrm:
8838	case VPSUBUSBrr:
8839		return true;
8840	}
8841	return false;
8842}
8843
8844bool isVPMOVQW(unsigned Opcode) {
8845	switch (Opcode) {
8846	case VPMOVQWZ128mr:
8847	case VPMOVQWZ128mrk:
8848	case VPMOVQWZ128rr:
8849	case VPMOVQWZ128rrk:
8850	case VPMOVQWZ128rrkz:
8851	case VPMOVQWZ256mr:
8852	case VPMOVQWZ256mrk:
8853	case VPMOVQWZ256rr:
8854	case VPMOVQWZ256rrk:
8855	case VPMOVQWZ256rrkz:
8856	case VPMOVQWZmr:
8857	case VPMOVQWZmrk:
8858	case VPMOVQWZrr:
8859	case VPMOVQWZrrk:
8860	case VPMOVQWZrrkz:
8861		return true;
8862	}
8863	return false;
8864}
8865
8866bool isVADDPS(unsigned Opcode) {
8867	switch (Opcode) {
8868	case VADDPSYrm:
8869	case VADDPSYrr:
8870	case VADDPSZ128rm:
8871	case VADDPSZ128rmb:
8872	case VADDPSZ128rmbk:
8873	case VADDPSZ128rmbkz:
8874	case VADDPSZ128rmk:
8875	case VADDPSZ128rmkz:
8876	case VADDPSZ128rr:
8877	case VADDPSZ128rrk:
8878	case VADDPSZ128rrkz:
8879	case VADDPSZ256rm:
8880	case VADDPSZ256rmb:
8881	case VADDPSZ256rmbk:
8882	case VADDPSZ256rmbkz:
8883	case VADDPSZ256rmk:
8884	case VADDPSZ256rmkz:
8885	case VADDPSZ256rr:
8886	case VADDPSZ256rrk:
8887	case VADDPSZ256rrkz:
8888	case VADDPSZrm:
8889	case VADDPSZrmb:
8890	case VADDPSZrmbk:
8891	case VADDPSZrmbkz:
8892	case VADDPSZrmk:
8893	case VADDPSZrmkz:
8894	case VADDPSZrr:
8895	case VADDPSZrrb:
8896	case VADDPSZrrbk:
8897	case VADDPSZrrbkz:
8898	case VADDPSZrrk:
8899	case VADDPSZrrkz:
8900	case VADDPSrm:
8901	case VADDPSrr:
8902		return true;
8903	}
8904	return false;
8905}
8906
8907bool isLODSQ(unsigned Opcode) {
8908	return Opcode == LODSQ;
8909}
8910
8911bool isFIDIVR(unsigned Opcode) {
8912	switch (Opcode) {
8913	case DIVR_FI16m:
8914	case DIVR_FI32m:
8915		return true;
8916	}
8917	return false;
8918}
8919
8920bool isIRETQ(unsigned Opcode) {
8921	return Opcode == IRET64;
8922}
8923
8924bool isLODSW(unsigned Opcode) {
8925	return Opcode == LODSW;
8926}
8927
8928bool isVHADDPS(unsigned Opcode) {
8929	switch (Opcode) {
8930	case VHADDPSYrm:
8931	case VHADDPSYrr:
8932	case VHADDPSrm:
8933	case VHADDPSrr:
8934		return true;
8935	}
8936	return false;
8937}
8938
8939bool isCVTTPS2DQ(unsigned Opcode) {
8940	switch (Opcode) {
8941	case CVTTPS2DQrm:
8942	case CVTTPS2DQrr:
8943		return true;
8944	}
8945	return false;
8946}
8947
8948bool isVPORD(unsigned Opcode) {
8949	switch (Opcode) {
8950	case VPORDZ128rm:
8951	case VPORDZ128rmb:
8952	case VPORDZ128rmbk:
8953	case VPORDZ128rmbkz:
8954	case VPORDZ128rmk:
8955	case VPORDZ128rmkz:
8956	case VPORDZ128rr:
8957	case VPORDZ128rrk:
8958	case VPORDZ128rrkz:
8959	case VPORDZ256rm:
8960	case VPORDZ256rmb:
8961	case VPORDZ256rmbk:
8962	case VPORDZ256rmbkz:
8963	case VPORDZ256rmk:
8964	case VPORDZ256rmkz:
8965	case VPORDZ256rr:
8966	case VPORDZ256rrk:
8967	case VPORDZ256rrkz:
8968	case VPORDZrm:
8969	case VPORDZrmb:
8970	case VPORDZrmbk:
8971	case VPORDZrmbkz:
8972	case VPORDZrmk:
8973	case VPORDZrmkz:
8974	case VPORDZrr:
8975	case VPORDZrrk:
8976	case VPORDZrrkz:
8977		return true;
8978	}
8979	return false;
8980}
8981
8982bool isVP2INTERSECTD(unsigned Opcode) {
8983	switch (Opcode) {
8984	case VP2INTERSECTDZ128rm:
8985	case VP2INTERSECTDZ128rmb:
8986	case VP2INTERSECTDZ128rr:
8987	case VP2INTERSECTDZ256rm:
8988	case VP2INTERSECTDZ256rmb:
8989	case VP2INTERSECTDZ256rr:
8990	case VP2INTERSECTDZrm:
8991	case VP2INTERSECTDZrmb:
8992	case VP2INTERSECTDZrr:
8993		return true;
8994	}
8995	return false;
8996}
8997
8998bool isVPSUBUSW(unsigned Opcode) {
8999	switch (Opcode) {
9000	case VPSUBUSWYrm:
9001	case VPSUBUSWYrr:
9002	case VPSUBUSWZ128rm:
9003	case VPSUBUSWZ128rmk:
9004	case VPSUBUSWZ128rmkz:
9005	case VPSUBUSWZ128rr:
9006	case VPSUBUSWZ128rrk:
9007	case VPSUBUSWZ128rrkz:
9008	case VPSUBUSWZ256rm:
9009	case VPSUBUSWZ256rmk:
9010	case VPSUBUSWZ256rmkz:
9011	case VPSUBUSWZ256rr:
9012	case VPSUBUSWZ256rrk:
9013	case VPSUBUSWZ256rrkz:
9014	case VPSUBUSWZrm:
9015	case VPSUBUSWZrmk:
9016	case VPSUBUSWZrmkz:
9017	case VPSUBUSWZrr:
9018	case VPSUBUSWZrrk:
9019	case VPSUBUSWZrrkz:
9020	case VPSUBUSWrm:
9021	case VPSUBUSWrr:
9022		return true;
9023	}
9024	return false;
9025}
9026
9027bool isVPERMILPD(unsigned Opcode) {
9028	switch (Opcode) {
9029	case VPERMILPDYmi:
9030	case VPERMILPDYri:
9031	case VPERMILPDYrm:
9032	case VPERMILPDYrr:
9033	case VPERMILPDZ128mbi:
9034	case VPERMILPDZ128mbik:
9035	case VPERMILPDZ128mbikz:
9036	case VPERMILPDZ128mi:
9037	case VPERMILPDZ128mik:
9038	case VPERMILPDZ128mikz:
9039	case VPERMILPDZ128ri:
9040	case VPERMILPDZ128rik:
9041	case VPERMILPDZ128rikz:
9042	case VPERMILPDZ128rm:
9043	case VPERMILPDZ128rmb:
9044	case VPERMILPDZ128rmbk:
9045	case VPERMILPDZ128rmbkz:
9046	case VPERMILPDZ128rmk:
9047	case VPERMILPDZ128rmkz:
9048	case VPERMILPDZ128rr:
9049	case VPERMILPDZ128rrk:
9050	case VPERMILPDZ128rrkz:
9051	case VPERMILPDZ256mbi:
9052	case VPERMILPDZ256mbik:
9053	case VPERMILPDZ256mbikz:
9054	case VPERMILPDZ256mi:
9055	case VPERMILPDZ256mik:
9056	case VPERMILPDZ256mikz:
9057	case VPERMILPDZ256ri:
9058	case VPERMILPDZ256rik:
9059	case VPERMILPDZ256rikz:
9060	case VPERMILPDZ256rm:
9061	case VPERMILPDZ256rmb:
9062	case VPERMILPDZ256rmbk:
9063	case VPERMILPDZ256rmbkz:
9064	case VPERMILPDZ256rmk:
9065	case VPERMILPDZ256rmkz:
9066	case VPERMILPDZ256rr:
9067	case VPERMILPDZ256rrk:
9068	case VPERMILPDZ256rrkz:
9069	case VPERMILPDZmbi:
9070	case VPERMILPDZmbik:
9071	case VPERMILPDZmbikz:
9072	case VPERMILPDZmi:
9073	case VPERMILPDZmik:
9074	case VPERMILPDZmikz:
9075	case VPERMILPDZri:
9076	case VPERMILPDZrik:
9077	case VPERMILPDZrikz:
9078	case VPERMILPDZrm:
9079	case VPERMILPDZrmb:
9080	case VPERMILPDZrmbk:
9081	case VPERMILPDZrmbkz:
9082	case VPERMILPDZrmk:
9083	case VPERMILPDZrmkz:
9084	case VPERMILPDZrr:
9085	case VPERMILPDZrrk:
9086	case VPERMILPDZrrkz:
9087	case VPERMILPDmi:
9088	case VPERMILPDri:
9089	case VPERMILPDrm:
9090	case VPERMILPDrr:
9091		return true;
9092	}
9093	return false;
9094}
9095
9096bool isVPSHLDD(unsigned Opcode) {
9097	switch (Opcode) {
9098	case VPSHLDDZ128rmbi:
9099	case VPSHLDDZ128rmbik:
9100	case VPSHLDDZ128rmbikz:
9101	case VPSHLDDZ128rmi:
9102	case VPSHLDDZ128rmik:
9103	case VPSHLDDZ128rmikz:
9104	case VPSHLDDZ128rri:
9105	case VPSHLDDZ128rrik:
9106	case VPSHLDDZ128rrikz:
9107	case VPSHLDDZ256rmbi:
9108	case VPSHLDDZ256rmbik:
9109	case VPSHLDDZ256rmbikz:
9110	case VPSHLDDZ256rmi:
9111	case VPSHLDDZ256rmik:
9112	case VPSHLDDZ256rmikz:
9113	case VPSHLDDZ256rri:
9114	case VPSHLDDZ256rrik:
9115	case VPSHLDDZ256rrikz:
9116	case VPSHLDDZrmbi:
9117	case VPSHLDDZrmbik:
9118	case VPSHLDDZrmbikz:
9119	case VPSHLDDZrmi:
9120	case VPSHLDDZrmik:
9121	case VPSHLDDZrmikz:
9122	case VPSHLDDZrri:
9123	case VPSHLDDZrrik:
9124	case VPSHLDDZrrikz:
9125		return true;
9126	}
9127	return false;
9128}
9129
9130bool isMOVD(unsigned Opcode) {
9131	switch (Opcode) {
9132	case MMX_MOVD64grr:
9133	case MMX_MOVD64mr:
9134	case MMX_MOVD64rm:
9135	case MMX_MOVD64rr:
9136	case MOVDI2PDIrm:
9137	case MOVDI2PDIrr:
9138	case MOVPDI2DImr:
9139	case MOVPDI2DIrr:
9140		return true;
9141	}
9142	return false;
9143}
9144
9145bool isVPORQ(unsigned Opcode) {
9146	switch (Opcode) {
9147	case VPORQZ128rm:
9148	case VPORQZ128rmb:
9149	case VPORQZ128rmbk:
9150	case VPORQZ128rmbkz:
9151	case VPORQZ128rmk:
9152	case VPORQZ128rmkz:
9153	case VPORQZ128rr:
9154	case VPORQZ128rrk:
9155	case VPORQZ128rrkz:
9156	case VPORQZ256rm:
9157	case VPORQZ256rmb:
9158	case VPORQZ256rmbk:
9159	case VPORQZ256rmbkz:
9160	case VPORQZ256rmk:
9161	case VPORQZ256rmkz:
9162	case VPORQZ256rr:
9163	case VPORQZ256rrk:
9164	case VPORQZ256rrkz:
9165	case VPORQZrm:
9166	case VPORQZrmb:
9167	case VPORQZrmbk:
9168	case VPORQZrmbkz:
9169	case VPORQZrmk:
9170	case VPORQZrmkz:
9171	case VPORQZrr:
9172	case VPORQZrrk:
9173	case VPORQZrrkz:
9174		return true;
9175	}
9176	return false;
9177}
9178
9179bool isVP2INTERSECTQ(unsigned Opcode) {
9180	switch (Opcode) {
9181	case VP2INTERSECTQZ128rm:
9182	case VP2INTERSECTQZ128rmb:
9183	case VP2INTERSECTQZ128rr:
9184	case VP2INTERSECTQZ256rm:
9185	case VP2INTERSECTQZ256rmb:
9186	case VP2INTERSECTQZ256rr:
9187	case VP2INTERSECTQZrm:
9188	case VP2INTERSECTQZrmb:
9189	case VP2INTERSECTQZrr:
9190		return true;
9191	}
9192	return false;
9193}
9194
9195bool isCRC32(unsigned Opcode) {
9196	switch (Opcode) {
9197	case CRC32r32m16:
9198	case CRC32r32m32:
9199	case CRC32r32m8:
9200	case CRC32r32r16:
9201	case CRC32r32r32:
9202	case CRC32r32r8:
9203	case CRC32r64m64:
9204	case CRC32r64m8:
9205	case CRC32r64r64:
9206	case CRC32r64r8:
9207		return true;
9208	}
9209	return false;
9210}
9211
9212bool isVPERMILPS(unsigned Opcode) {
9213	switch (Opcode) {
9214	case VPERMILPSYmi:
9215	case VPERMILPSYri:
9216	case VPERMILPSYrm:
9217	case VPERMILPSYrr:
9218	case VPERMILPSZ128mbi:
9219	case VPERMILPSZ128mbik:
9220	case VPERMILPSZ128mbikz:
9221	case VPERMILPSZ128mi:
9222	case VPERMILPSZ128mik:
9223	case VPERMILPSZ128mikz:
9224	case VPERMILPSZ128ri:
9225	case VPERMILPSZ128rik:
9226	case VPERMILPSZ128rikz:
9227	case VPERMILPSZ128rm:
9228	case VPERMILPSZ128rmb:
9229	case VPERMILPSZ128rmbk:
9230	case VPERMILPSZ128rmbkz:
9231	case VPERMILPSZ128rmk:
9232	case VPERMILPSZ128rmkz:
9233	case VPERMILPSZ128rr:
9234	case VPERMILPSZ128rrk:
9235	case VPERMILPSZ128rrkz:
9236	case VPERMILPSZ256mbi:
9237	case VPERMILPSZ256mbik:
9238	case VPERMILPSZ256mbikz:
9239	case VPERMILPSZ256mi:
9240	case VPERMILPSZ256mik:
9241	case VPERMILPSZ256mikz:
9242	case VPERMILPSZ256ri:
9243	case VPERMILPSZ256rik:
9244	case VPERMILPSZ256rikz:
9245	case VPERMILPSZ256rm:
9246	case VPERMILPSZ256rmb:
9247	case VPERMILPSZ256rmbk:
9248	case VPERMILPSZ256rmbkz:
9249	case VPERMILPSZ256rmk:
9250	case VPERMILPSZ256rmkz:
9251	case VPERMILPSZ256rr:
9252	case VPERMILPSZ256rrk:
9253	case VPERMILPSZ256rrkz:
9254	case VPERMILPSZmbi:
9255	case VPERMILPSZmbik:
9256	case VPERMILPSZmbikz:
9257	case VPERMILPSZmi:
9258	case VPERMILPSZmik:
9259	case VPERMILPSZmikz:
9260	case VPERMILPSZri:
9261	case VPERMILPSZrik:
9262	case VPERMILPSZrikz:
9263	case VPERMILPSZrm:
9264	case VPERMILPSZrmb:
9265	case VPERMILPSZrmbk:
9266	case VPERMILPSZrmbkz:
9267	case VPERMILPSZrmk:
9268	case VPERMILPSZrmkz:
9269	case VPERMILPSZrr:
9270	case VPERMILPSZrrk:
9271	case VPERMILPSZrrkz:
9272	case VPERMILPSmi:
9273	case VPERMILPSri:
9274	case VPERMILPSrm:
9275	case VPERMILPSrr:
9276		return true;
9277	}
9278	return false;
9279}
9280
9281bool isMOVQ(unsigned Opcode) {
9282	switch (Opcode) {
9283	case MMX_MOVD64from64mr:
9284	case MMX_MOVD64from64rr:
9285	case MMX_MOVD64to64rm:
9286	case MMX_MOVD64to64rr:
9287	case MMX_MOVQ64mr:
9288	case MMX_MOVQ64rm:
9289	case MMX_MOVQ64rr:
9290	case MMX_MOVQ64rr_REV:
9291	case MOV64toPQIrm:
9292	case MOV64toPQIrr:
9293	case MOVPQI2QImr:
9294	case MOVPQI2QIrr:
9295	case MOVPQIto64mr:
9296	case MOVPQIto64rr:
9297	case MOVQI2PQIrm:
9298	case MOVZPQILo2PQIrr:
9299		return true;
9300	}
9301	return false;
9302}
9303
9304bool isVPSHLDQ(unsigned Opcode) {
9305	switch (Opcode) {
9306	case VPSHLDQZ128rmbi:
9307	case VPSHLDQZ128rmbik:
9308	case VPSHLDQZ128rmbikz:
9309	case VPSHLDQZ128rmi:
9310	case VPSHLDQZ128rmik:
9311	case VPSHLDQZ128rmikz:
9312	case VPSHLDQZ128rri:
9313	case VPSHLDQZ128rrik:
9314	case VPSHLDQZ128rrikz:
9315	case VPSHLDQZ256rmbi:
9316	case VPSHLDQZ256rmbik:
9317	case VPSHLDQZ256rmbikz:
9318	case VPSHLDQZ256rmi:
9319	case VPSHLDQZ256rmik:
9320	case VPSHLDQZ256rmikz:
9321	case VPSHLDQZ256rri:
9322	case VPSHLDQZ256rrik:
9323	case VPSHLDQZ256rrikz:
9324	case VPSHLDQZrmbi:
9325	case VPSHLDQZrmbik:
9326	case VPSHLDQZrmbikz:
9327	case VPSHLDQZrmi:
9328	case VPSHLDQZrmik:
9329	case VPSHLDQZrmikz:
9330	case VPSHLDQZrri:
9331	case VPSHLDQZrrik:
9332	case VPSHLDQZrrikz:
9333		return true;
9334	}
9335	return false;
9336}
9337
9338bool isVPMASKMOVD(unsigned Opcode) {
9339	switch (Opcode) {
9340	case VPMASKMOVDYmr:
9341	case VPMASKMOVDYrm:
9342	case VPMASKMOVDmr:
9343	case VPMASKMOVDrm:
9344		return true;
9345	}
9346	return false;
9347}
9348
9349bool isVPSHLDW(unsigned Opcode) {
9350	switch (Opcode) {
9351	case VPSHLDWZ128rmi:
9352	case VPSHLDWZ128rmik:
9353	case VPSHLDWZ128rmikz:
9354	case VPSHLDWZ128rri:
9355	case VPSHLDWZ128rrik:
9356	case VPSHLDWZ128rrikz:
9357	case VPSHLDWZ256rmi:
9358	case VPSHLDWZ256rmik:
9359	case VPSHLDWZ256rmikz:
9360	case VPSHLDWZ256rri:
9361	case VPSHLDWZ256rrik:
9362	case VPSHLDWZ256rrikz:
9363	case VPSHLDWZrmi:
9364	case VPSHLDWZrmik:
9365	case VPSHLDWZrmikz:
9366	case VPSHLDWZrri:
9367	case VPSHLDWZrrik:
9368	case VPSHLDWZrrikz:
9369		return true;
9370	}
9371	return false;
9372}
9373
9374bool isSLWPCB(unsigned Opcode) {
9375	switch (Opcode) {
9376	case SLWPCB:
9377	case SLWPCB64:
9378		return true;
9379	}
9380	return false;
9381}
9382
9383bool isVORPD(unsigned Opcode) {
9384	switch (Opcode) {
9385	case VORPDYrm:
9386	case VORPDYrr:
9387	case VORPDZ128rm:
9388	case VORPDZ128rmb:
9389	case VORPDZ128rmbk:
9390	case VORPDZ128rmbkz:
9391	case VORPDZ128rmk:
9392	case VORPDZ128rmkz:
9393	case VORPDZ128rr:
9394	case VORPDZ128rrk:
9395	case VORPDZ128rrkz:
9396	case VORPDZ256rm:
9397	case VORPDZ256rmb:
9398	case VORPDZ256rmbk:
9399	case VORPDZ256rmbkz:
9400	case VORPDZ256rmk:
9401	case VORPDZ256rmkz:
9402	case VORPDZ256rr:
9403	case VORPDZ256rrk:
9404	case VORPDZ256rrkz:
9405	case VORPDZrm:
9406	case VORPDZrmb:
9407	case VORPDZrmbk:
9408	case VORPDZrmbkz:
9409	case VORPDZrmk:
9410	case VORPDZrmkz:
9411	case VORPDZrr:
9412	case VORPDZrrk:
9413	case VORPDZrrkz:
9414	case VORPDrm:
9415	case VORPDrr:
9416		return true;
9417	}
9418	return false;
9419}
9420
9421bool isPCMPGTB(unsigned Opcode) {
9422	switch (Opcode) {
9423	case MMX_PCMPGTBrm:
9424	case MMX_PCMPGTBrr:
9425	case PCMPGTBrm:
9426	case PCMPGTBrr:
9427		return true;
9428	}
9429	return false;
9430}
9431
9432bool isPCMPGTD(unsigned Opcode) {
9433	switch (Opcode) {
9434	case MMX_PCMPGTDrm:
9435	case MMX_PCMPGTDrr:
9436	case PCMPGTDrm:
9437	case PCMPGTDrr:
9438		return true;
9439	}
9440	return false;
9441}
9442
9443bool isVPMASKMOVQ(unsigned Opcode) {
9444	switch (Opcode) {
9445	case VPMASKMOVQYmr:
9446	case VPMASKMOVQYrm:
9447	case VPMASKMOVQmr:
9448	case VPMASKMOVQrm:
9449		return true;
9450	}
9451	return false;
9452}
9453
9454bool isPFRSQIT1(unsigned Opcode) {
9455	switch (Opcode) {
9456	case PFRSQIT1rm:
9457	case PFRSQIT1rr:
9458		return true;
9459	}
9460	return false;
9461}
9462
9463bool isVORPS(unsigned Opcode) {
9464	switch (Opcode) {
9465	case VORPSYrm:
9466	case VORPSYrr:
9467	case VORPSZ128rm:
9468	case VORPSZ128rmb:
9469	case VORPSZ128rmbk:
9470	case VORPSZ128rmbkz:
9471	case VORPSZ128rmk:
9472	case VORPSZ128rmkz:
9473	case VORPSZ128rr:
9474	case VORPSZ128rrk:
9475	case VORPSZ128rrkz:
9476	case VORPSZ256rm:
9477	case VORPSZ256rmb:
9478	case VORPSZ256rmbk:
9479	case VORPSZ256rmbkz:
9480	case VORPSZ256rmk:
9481	case VORPSZ256rmkz:
9482	case VORPSZ256rr:
9483	case VORPSZ256rrk:
9484	case VORPSZ256rrkz:
9485	case VORPSZrm:
9486	case VORPSZrmb:
9487	case VORPSZrmbk:
9488	case VORPSZrmbkz:
9489	case VORPSZrmk:
9490	case VORPSZrmkz:
9491	case VORPSZrr:
9492	case VORPSZrrk:
9493	case VORPSZrrkz:
9494	case VORPSrm:
9495	case VORPSrr:
9496		return true;
9497	}
9498	return false;
9499}
9500
9501bool isPCMPGTQ(unsigned Opcode) {
9502	switch (Opcode) {
9503	case PCMPGTQrm:
9504	case PCMPGTQrr:
9505		return true;
9506	}
9507	return false;
9508}
9509
9510bool isBLCIC(unsigned Opcode) {
9511	switch (Opcode) {
9512	case BLCIC32rm:
9513	case BLCIC32rr:
9514	case BLCIC64rm:
9515	case BLCIC64rr:
9516		return true;
9517	}
9518	return false;
9519}
9520
9521bool isMAXSD(unsigned Opcode) {
9522	switch (Opcode) {
9523	case MAXSDrm_Int:
9524	case MAXSDrr_Int:
9525		return true;
9526	}
9527	return false;
9528}
9529
9530bool isPCMPGTW(unsigned Opcode) {
9531	switch (Opcode) {
9532	case MMX_PCMPGTWrm:
9533	case MMX_PCMPGTWrr:
9534	case PCMPGTWrm:
9535	case PCMPGTWrr:
9536		return true;
9537	}
9538	return false;
9539}
9540
9541bool isVBCSTNESH2PS(unsigned Opcode) {
9542	switch (Opcode) {
9543	case VBCSTNESH2PSYrm:
9544	case VBCSTNESH2PSrm:
9545		return true;
9546	}
9547	return false;
9548}
9549
9550bool isMOVLHPS(unsigned Opcode) {
9551	return Opcode == MOVLHPSrr;
9552}
9553
9554bool isXSAVEC(unsigned Opcode) {
9555	return Opcode == XSAVEC;
9556}
9557
9558bool isMAXSS(unsigned Opcode) {
9559	switch (Opcode) {
9560	case MAXSSrm_Int:
9561	case MAXSSrr_Int:
9562		return true;
9563	}
9564	return false;
9565}
9566
9567bool isFST(unsigned Opcode) {
9568	switch (Opcode) {
9569	case ST_F32m:
9570	case ST_F64m:
9571	case ST_Frr:
9572		return true;
9573	}
9574	return false;
9575}
9576
9577bool isVCVTSS2USI(unsigned Opcode) {
9578	switch (Opcode) {
9579	case VCVTSS2USI64Zrm_Int:
9580	case VCVTSS2USI64Zrr_Int:
9581	case VCVTSS2USI64Zrrb_Int:
9582	case VCVTSS2USIZrm_Int:
9583	case VCVTSS2USIZrr_Int:
9584	case VCVTSS2USIZrrb_Int:
9585		return true;
9586	}
9587	return false;
9588}
9589
9590bool isVADDSD(unsigned Opcode) {
9591	switch (Opcode) {
9592	case VADDSDZrm_Int:
9593	case VADDSDZrm_Intk:
9594	case VADDSDZrm_Intkz:
9595	case VADDSDZrr_Int:
9596	case VADDSDZrr_Intk:
9597	case VADDSDZrr_Intkz:
9598	case VADDSDZrrb_Int:
9599	case VADDSDZrrb_Intk:
9600	case VADDSDZrrb_Intkz:
9601	case VADDSDrm_Int:
9602	case VADDSDrr_Int:
9603		return true;
9604	}
9605	return false;
9606}
9607
9608bool isVRNDSCALEPD(unsigned Opcode) {
9609	switch (Opcode) {
9610	case VRNDSCALEPDZ128rmbi:
9611	case VRNDSCALEPDZ128rmbik:
9612	case VRNDSCALEPDZ128rmbikz:
9613	case VRNDSCALEPDZ128rmi:
9614	case VRNDSCALEPDZ128rmik:
9615	case VRNDSCALEPDZ128rmikz:
9616	case VRNDSCALEPDZ128rri:
9617	case VRNDSCALEPDZ128rrik:
9618	case VRNDSCALEPDZ128rrikz:
9619	case VRNDSCALEPDZ256rmbi:
9620	case VRNDSCALEPDZ256rmbik:
9621	case VRNDSCALEPDZ256rmbikz:
9622	case VRNDSCALEPDZ256rmi:
9623	case VRNDSCALEPDZ256rmik:
9624	case VRNDSCALEPDZ256rmikz:
9625	case VRNDSCALEPDZ256rri:
9626	case VRNDSCALEPDZ256rrik:
9627	case VRNDSCALEPDZ256rrikz:
9628	case VRNDSCALEPDZrmbi:
9629	case VRNDSCALEPDZrmbik:
9630	case VRNDSCALEPDZrmbikz:
9631	case VRNDSCALEPDZrmi:
9632	case VRNDSCALEPDZrmik:
9633	case VRNDSCALEPDZrmikz:
9634	case VRNDSCALEPDZrri:
9635	case VRNDSCALEPDZrrib:
9636	case VRNDSCALEPDZrribk:
9637	case VRNDSCALEPDZrribkz:
9638	case VRNDSCALEPDZrrik:
9639	case VRNDSCALEPDZrrikz:
9640		return true;
9641	}
9642	return false;
9643}
9644
9645bool isVCVTTPH2UQQ(unsigned Opcode) {
9646	switch (Opcode) {
9647	case VCVTTPH2UQQZ128rm:
9648	case VCVTTPH2UQQZ128rmb:
9649	case VCVTTPH2UQQZ128rmbk:
9650	case VCVTTPH2UQQZ128rmbkz:
9651	case VCVTTPH2UQQZ128rmk:
9652	case VCVTTPH2UQQZ128rmkz:
9653	case VCVTTPH2UQQZ128rr:
9654	case VCVTTPH2UQQZ128rrk:
9655	case VCVTTPH2UQQZ128rrkz:
9656	case VCVTTPH2UQQZ256rm:
9657	case VCVTTPH2UQQZ256rmb:
9658	case VCVTTPH2UQQZ256rmbk:
9659	case VCVTTPH2UQQZ256rmbkz:
9660	case VCVTTPH2UQQZ256rmk:
9661	case VCVTTPH2UQQZ256rmkz:
9662	case VCVTTPH2UQQZ256rr:
9663	case VCVTTPH2UQQZ256rrk:
9664	case VCVTTPH2UQQZ256rrkz:
9665	case VCVTTPH2UQQZrm:
9666	case VCVTTPH2UQQZrmb:
9667	case VCVTTPH2UQQZrmbk:
9668	case VCVTTPH2UQQZrmbkz:
9669	case VCVTTPH2UQQZrmk:
9670	case VCVTTPH2UQQZrmkz:
9671	case VCVTTPH2UQQZrr:
9672	case VCVTTPH2UQQZrrb:
9673	case VCVTTPH2UQQZrrbk:
9674	case VCVTTPH2UQQZrrbkz:
9675	case VCVTTPH2UQQZrrk:
9676	case VCVTTPH2UQQZrrkz:
9677		return true;
9678	}
9679	return false;
9680}
9681
9682bool isV4FNMADDSS(unsigned Opcode) {
9683	switch (Opcode) {
9684	case V4FNMADDSSrm:
9685	case V4FNMADDSSrmk:
9686	case V4FNMADDSSrmkz:
9687		return true;
9688	}
9689	return false;
9690}
9691
9692bool isVADDSH(unsigned Opcode) {
9693	switch (Opcode) {
9694	case VADDSHZrm_Int:
9695	case VADDSHZrm_Intk:
9696	case VADDSHZrm_Intkz:
9697	case VADDSHZrr_Int:
9698	case VADDSHZrr_Intk:
9699	case VADDSHZrr_Intkz:
9700	case VADDSHZrrb_Int:
9701	case VADDSHZrrb_Intk:
9702	case VADDSHZrrb_Intkz:
9703		return true;
9704	}
9705	return false;
9706}
9707
9708bool isVRNDSCALEPH(unsigned Opcode) {
9709	switch (Opcode) {
9710	case VRNDSCALEPHZ128rmbi:
9711	case VRNDSCALEPHZ128rmbik:
9712	case VRNDSCALEPHZ128rmbikz:
9713	case VRNDSCALEPHZ128rmi:
9714	case VRNDSCALEPHZ128rmik:
9715	case VRNDSCALEPHZ128rmikz:
9716	case VRNDSCALEPHZ128rri:
9717	case VRNDSCALEPHZ128rrik:
9718	case VRNDSCALEPHZ128rrikz:
9719	case VRNDSCALEPHZ256rmbi:
9720	case VRNDSCALEPHZ256rmbik:
9721	case VRNDSCALEPHZ256rmbikz:
9722	case VRNDSCALEPHZ256rmi:
9723	case VRNDSCALEPHZ256rmik:
9724	case VRNDSCALEPHZ256rmikz:
9725	case VRNDSCALEPHZ256rri:
9726	case VRNDSCALEPHZ256rrik:
9727	case VRNDSCALEPHZ256rrikz:
9728	case VRNDSCALEPHZrmbi:
9729	case VRNDSCALEPHZrmbik:
9730	case VRNDSCALEPHZrmbikz:
9731	case VRNDSCALEPHZrmi:
9732	case VRNDSCALEPHZrmik:
9733	case VRNDSCALEPHZrmikz:
9734	case VRNDSCALEPHZrri:
9735	case VRNDSCALEPHZrrib:
9736	case VRNDSCALEPHZrribk:
9737	case VRNDSCALEPHZrribkz:
9738	case VRNDSCALEPHZrrik:
9739	case VRNDSCALEPHZrrikz:
9740		return true;
9741	}
9742	return false;
9743}
9744
9745bool isXSAVES(unsigned Opcode) {
9746	return Opcode == XSAVES;
9747}
9748
9749bool isXRESLDTRK(unsigned Opcode) {
9750	return Opcode == XRESLDTRK;
9751}
9752
9753bool isVADDSS(unsigned Opcode) {
9754	switch (Opcode) {
9755	case VADDSSZrm_Int:
9756	case VADDSSZrm_Intk:
9757	case VADDSSZrm_Intkz:
9758	case VADDSSZrr_Int:
9759	case VADDSSZrr_Intk:
9760	case VADDSSZrr_Intkz:
9761	case VADDSSZrrb_Int:
9762	case VADDSSZrrb_Intk:
9763	case VADDSSZrrb_Intkz:
9764	case VADDSSrm_Int:
9765	case VADDSSrr_Int:
9766		return true;
9767	}
9768	return false;
9769}
9770
9771bool isVRNDSCALEPS(unsigned Opcode) {
9772	switch (Opcode) {
9773	case VRNDSCALEPSZ128rmbi:
9774	case VRNDSCALEPSZ128rmbik:
9775	case VRNDSCALEPSZ128rmbikz:
9776	case VRNDSCALEPSZ128rmi:
9777	case VRNDSCALEPSZ128rmik:
9778	case VRNDSCALEPSZ128rmikz:
9779	case VRNDSCALEPSZ128rri:
9780	case VRNDSCALEPSZ128rrik:
9781	case VRNDSCALEPSZ128rrikz:
9782	case VRNDSCALEPSZ256rmbi:
9783	case VRNDSCALEPSZ256rmbik:
9784	case VRNDSCALEPSZ256rmbikz:
9785	case VRNDSCALEPSZ256rmi:
9786	case VRNDSCALEPSZ256rmik:
9787	case VRNDSCALEPSZ256rmikz:
9788	case VRNDSCALEPSZ256rri:
9789	case VRNDSCALEPSZ256rrik:
9790	case VRNDSCALEPSZ256rrikz:
9791	case VRNDSCALEPSZrmbi:
9792	case VRNDSCALEPSZrmbik:
9793	case VRNDSCALEPSZrmbikz:
9794	case VRNDSCALEPSZrmi:
9795	case VRNDSCALEPSZrmik:
9796	case VRNDSCALEPSZrmikz:
9797	case VRNDSCALEPSZrri:
9798	case VRNDSCALEPSZrrib:
9799	case VRNDSCALEPSZrribk:
9800	case VRNDSCALEPSZrribkz:
9801	case VRNDSCALEPSZrrik:
9802	case VRNDSCALEPSZrrikz:
9803		return true;
9804	}
9805	return false;
9806}
9807
9808bool isVPHADDUWD(unsigned Opcode) {
9809	switch (Opcode) {
9810	case VPHADDUWDrm:
9811	case VPHADDUWDrr:
9812		return true;
9813	}
9814	return false;
9815}
9816
9817bool isRDSSPD(unsigned Opcode) {
9818	return Opcode == RDSSPD;
9819}
9820
9821bool isVPHADDUWQ(unsigned Opcode) {
9822	switch (Opcode) {
9823	case VPHADDUWQrm:
9824	case VPHADDUWQrr:
9825		return true;
9826	}
9827	return false;
9828}
9829
9830bool isVMOVDDUP(unsigned Opcode) {
9831	switch (Opcode) {
9832	case VMOVDDUPYrm:
9833	case VMOVDDUPYrr:
9834	case VMOVDDUPZ128rm:
9835	case VMOVDDUPZ128rmk:
9836	case VMOVDDUPZ128rmkz:
9837	case VMOVDDUPZ128rr:
9838	case VMOVDDUPZ128rrk:
9839	case VMOVDDUPZ128rrkz:
9840	case VMOVDDUPZ256rm:
9841	case VMOVDDUPZ256rmk:
9842	case VMOVDDUPZ256rmkz:
9843	case VMOVDDUPZ256rr:
9844	case VMOVDDUPZ256rrk:
9845	case VMOVDDUPZ256rrkz:
9846	case VMOVDDUPZrm:
9847	case VMOVDDUPZrmk:
9848	case VMOVDDUPZrmkz:
9849	case VMOVDDUPZrr:
9850	case VMOVDDUPZrrk:
9851	case VMOVDDUPZrrkz:
9852	case VMOVDDUPrm:
9853	case VMOVDDUPrr:
9854		return true;
9855	}
9856	return false;
9857}
9858
9859bool isINSERTPS(unsigned Opcode) {
9860	switch (Opcode) {
9861	case INSERTPSrm:
9862	case INSERTPSrr:
9863		return true;
9864	}
9865	return false;
9866}
9867
9868bool isNEG(unsigned Opcode) {
9869	switch (Opcode) {
9870	case NEG16m:
9871	case NEG16r:
9872	case NEG32m:
9873	case NEG32r:
9874	case NEG64m:
9875	case NEG64r:
9876	case NEG8m:
9877	case NEG8r:
9878		return true;
9879	}
9880	return false;
9881}
9882
9883bool isMOVUPD(unsigned Opcode) {
9884	switch (Opcode) {
9885	case MOVUPDmr:
9886	case MOVUPDrm:
9887	case MOVUPDrr:
9888	case MOVUPDrr_REV:
9889		return true;
9890	}
9891	return false;
9892}
9893
9894bool isRDSSPQ(unsigned Opcode) {
9895	return Opcode == RDSSPQ;
9896}
9897
9898bool isVFRCZPD(unsigned Opcode) {
9899	switch (Opcode) {
9900	case VFRCZPDYrm:
9901	case VFRCZPDYrr:
9902	case VFRCZPDrm:
9903	case VFRCZPDrr:
9904		return true;
9905	}
9906	return false;
9907}
9908
9909bool isPHMINPOSUW(unsigned Opcode) {
9910	switch (Opcode) {
9911	case PHMINPOSUWrm:
9912	case PHMINPOSUWrr:
9913		return true;
9914	}
9915	return false;
9916}
9917
9918bool isVBROADCASTI32X2(unsigned Opcode) {
9919	switch (Opcode) {
9920	case VBROADCASTI32X2Z128rm:
9921	case VBROADCASTI32X2Z128rmk:
9922	case VBROADCASTI32X2Z128rmkz:
9923	case VBROADCASTI32X2Z128rr:
9924	case VBROADCASTI32X2Z128rrk:
9925	case VBROADCASTI32X2Z128rrkz:
9926	case VBROADCASTI32X2Z256rm:
9927	case VBROADCASTI32X2Z256rmk:
9928	case VBROADCASTI32X2Z256rmkz:
9929	case VBROADCASTI32X2Z256rr:
9930	case VBROADCASTI32X2Z256rrk:
9931	case VBROADCASTI32X2Z256rrkz:
9932	case VBROADCASTI32X2Zrm:
9933	case VBROADCASTI32X2Zrmk:
9934	case VBROADCASTI32X2Zrmkz:
9935	case VBROADCASTI32X2Zrr:
9936	case VBROADCASTI32X2Zrrk:
9937	case VBROADCASTI32X2Zrrkz:
9938		return true;
9939	}
9940	return false;
9941}
9942
9943bool isVBROADCASTI32X4(unsigned Opcode) {
9944	switch (Opcode) {
9945	case VBROADCASTI32X4Z256rm:
9946	case VBROADCASTI32X4Z256rmk:
9947	case VBROADCASTI32X4Z256rmkz:
9948	case VBROADCASTI32X4rm:
9949	case VBROADCASTI32X4rmk:
9950	case VBROADCASTI32X4rmkz:
9951		return true;
9952	}
9953	return false;
9954}
9955
9956bool isJMP(unsigned Opcode) {
9957	switch (Opcode) {
9958	case FARJMP32m:
9959	case JMP16m:
9960	case JMP16r:
9961	case JMP32m:
9962	case JMP32r:
9963	case JMP64m:
9964	case JMP64r:
9965	case JMP_1:
9966	case JMP_2:
9967	case JMP_4:
9968		return true;
9969	}
9970	return false;
9971}
9972
9973bool isVBROADCASTI32X8(unsigned Opcode) {
9974	switch (Opcode) {
9975	case VBROADCASTI32X8rm:
9976	case VBROADCASTI32X8rmk:
9977	case VBROADCASTI32X8rmkz:
9978		return true;
9979	}
9980	return false;
9981}
9982
9983bool isMOVUPS(unsigned Opcode) {
9984	switch (Opcode) {
9985	case MOVUPSmr:
9986	case MOVUPSrm:
9987	case MOVUPSrr:
9988	case MOVUPSrr_REV:
9989		return true;
9990	}
9991	return false;
9992}
9993
9994bool isVPANDND(unsigned Opcode) {
9995	switch (Opcode) {
9996	case VPANDNDZ128rm:
9997	case VPANDNDZ128rmb:
9998	case VPANDNDZ128rmbk:
9999	case VPANDNDZ128rmbkz:
10000	case VPANDNDZ128rmk:
10001	case VPANDNDZ128rmkz:
10002	case VPANDNDZ128rr:
10003	case VPANDNDZ128rrk:
10004	case VPANDNDZ128rrkz:
10005	case VPANDNDZ256rm:
10006	case VPANDNDZ256rmb:
10007	case VPANDNDZ256rmbk:
10008	case VPANDNDZ256rmbkz:
10009	case VPANDNDZ256rmk:
10010	case VPANDNDZ256rmkz:
10011	case VPANDNDZ256rr:
10012	case VPANDNDZ256rrk:
10013	case VPANDNDZ256rrkz:
10014	case VPANDNDZrm:
10015	case VPANDNDZrmb:
10016	case VPANDNDZrmbk:
10017	case VPANDNDZrmbkz:
10018	case VPANDNDZrmk:
10019	case VPANDNDZrmkz:
10020	case VPANDNDZrr:
10021	case VPANDNDZrrk:
10022	case VPANDNDZrrkz:
10023		return true;
10024	}
10025	return false;
10026}
10027
10028bool isVCVTNE2PS2BF16(unsigned Opcode) {
10029	switch (Opcode) {
10030	case VCVTNE2PS2BF16Z128rm:
10031	case VCVTNE2PS2BF16Z128rmb:
10032	case VCVTNE2PS2BF16Z128rmbk:
10033	case VCVTNE2PS2BF16Z128rmbkz:
10034	case VCVTNE2PS2BF16Z128rmk:
10035	case VCVTNE2PS2BF16Z128rmkz:
10036	case VCVTNE2PS2BF16Z128rr:
10037	case VCVTNE2PS2BF16Z128rrk:
10038	case VCVTNE2PS2BF16Z128rrkz:
10039	case VCVTNE2PS2BF16Z256rm:
10040	case VCVTNE2PS2BF16Z256rmb:
10041	case VCVTNE2PS2BF16Z256rmbk:
10042	case VCVTNE2PS2BF16Z256rmbkz:
10043	case VCVTNE2PS2BF16Z256rmk:
10044	case VCVTNE2PS2BF16Z256rmkz:
10045	case VCVTNE2PS2BF16Z256rr:
10046	case VCVTNE2PS2BF16Z256rrk:
10047	case VCVTNE2PS2BF16Z256rrkz:
10048	case VCVTNE2PS2BF16Zrm:
10049	case VCVTNE2PS2BF16Zrmb:
10050	case VCVTNE2PS2BF16Zrmbk:
10051	case VCVTNE2PS2BF16Zrmbkz:
10052	case VCVTNE2PS2BF16Zrmk:
10053	case VCVTNE2PS2BF16Zrmkz:
10054	case VCVTNE2PS2BF16Zrr:
10055	case VCVTNE2PS2BF16Zrrk:
10056	case VCVTNE2PS2BF16Zrrkz:
10057		return true;
10058	}
10059	return false;
10060}
10061
10062bool isVPROLVD(unsigned Opcode) {
10063	switch (Opcode) {
10064	case VPROLVDZ128rm:
10065	case VPROLVDZ128rmb:
10066	case VPROLVDZ128rmbk:
10067	case VPROLVDZ128rmbkz:
10068	case VPROLVDZ128rmk:
10069	case VPROLVDZ128rmkz:
10070	case VPROLVDZ128rr:
10071	case VPROLVDZ128rrk:
10072	case VPROLVDZ128rrkz:
10073	case VPROLVDZ256rm:
10074	case VPROLVDZ256rmb:
10075	case VPROLVDZ256rmbk:
10076	case VPROLVDZ256rmbkz:
10077	case VPROLVDZ256rmk:
10078	case VPROLVDZ256rmkz:
10079	case VPROLVDZ256rr:
10080	case VPROLVDZ256rrk:
10081	case VPROLVDZ256rrkz:
10082	case VPROLVDZrm:
10083	case VPROLVDZrmb:
10084	case VPROLVDZrmbk:
10085	case VPROLVDZrmbkz:
10086	case VPROLVDZrmk:
10087	case VPROLVDZrmkz:
10088	case VPROLVDZrr:
10089	case VPROLVDZrrk:
10090	case VPROLVDZrrkz:
10091		return true;
10092	}
10093	return false;
10094}
10095
10096bool isVFRCZPS(unsigned Opcode) {
10097	switch (Opcode) {
10098	case VFRCZPSYrm:
10099	case VFRCZPSYrr:
10100	case VFRCZPSrm:
10101	case VFRCZPSrr:
10102		return true;
10103	}
10104	return false;
10105}
10106
10107bool isJRCXZ(unsigned Opcode) {
10108	return Opcode == JRCXZ;
10109}
10110
10111bool isFNSTCW(unsigned Opcode) {
10112	return Opcode == FNSTCW16m;
10113}
10114
10115bool isFFREEP(unsigned Opcode) {
10116	return Opcode == FFREEP;
10117}
10118
10119bool isVPANDNQ(unsigned Opcode) {
10120	switch (Opcode) {
10121	case VPANDNQZ128rm:
10122	case VPANDNQZ128rmb:
10123	case VPANDNQZ128rmbk:
10124	case VPANDNQZ128rmbkz:
10125	case VPANDNQZ128rmk:
10126	case VPANDNQZ128rmkz:
10127	case VPANDNQZ128rr:
10128	case VPANDNQZ128rrk:
10129	case VPANDNQZ128rrkz:
10130	case VPANDNQZ256rm:
10131	case VPANDNQZ256rmb:
10132	case VPANDNQZ256rmbk:
10133	case VPANDNQZ256rmbkz:
10134	case VPANDNQZ256rmk:
10135	case VPANDNQZ256rmkz:
10136	case VPANDNQZ256rr:
10137	case VPANDNQZ256rrk:
10138	case VPANDNQZ256rrkz:
10139	case VPANDNQZrm:
10140	case VPANDNQZrmb:
10141	case VPANDNQZrmbk:
10142	case VPANDNQZrmbkz:
10143	case VPANDNQZrmk:
10144	case VPANDNQZrmkz:
10145	case VPANDNQZrr:
10146	case VPANDNQZrrk:
10147	case VPANDNQZrrkz:
10148		return true;
10149	}
10150	return false;
10151}
10152
10153bool isVPROLVQ(unsigned Opcode) {
10154	switch (Opcode) {
10155	case VPROLVQZ128rm:
10156	case VPROLVQZ128rmb:
10157	case VPROLVQZ128rmbk:
10158	case VPROLVQZ128rmbkz:
10159	case VPROLVQZ128rmk:
10160	case VPROLVQZ128rmkz:
10161	case VPROLVQZ128rr:
10162	case VPROLVQZ128rrk:
10163	case VPROLVQZ128rrkz:
10164	case VPROLVQZ256rm:
10165	case VPROLVQZ256rmb:
10166	case VPROLVQZ256rmbk:
10167	case VPROLVQZ256rmbkz:
10168	case VPROLVQZ256rmk:
10169	case VPROLVQZ256rmkz:
10170	case VPROLVQZ256rr:
10171	case VPROLVQZ256rrk:
10172	case VPROLVQZ256rrkz:
10173	case VPROLVQZrm:
10174	case VPROLVQZrmb:
10175	case VPROLVQZrmbk:
10176	case VPROLVQZrmbkz:
10177	case VPROLVQZrmk:
10178	case VPROLVQZrmkz:
10179	case VPROLVQZrr:
10180	case VPROLVQZrrk:
10181	case VPROLVQZrrkz:
10182		return true;
10183	}
10184	return false;
10185}
10186
10187bool isAESDECWIDE128KL(unsigned Opcode) {
10188	return Opcode == AESDECWIDE128KL;
10189}
10190
10191bool isSTTILECFG(unsigned Opcode) {
10192	return Opcode == STTILECFG;
10193}
10194
10195bool isVPMOVWB(unsigned Opcode) {
10196	switch (Opcode) {
10197	case VPMOVWBZ128mr:
10198	case VPMOVWBZ128mrk:
10199	case VPMOVWBZ128rr:
10200	case VPMOVWBZ128rrk:
10201	case VPMOVWBZ128rrkz:
10202	case VPMOVWBZ256mr:
10203	case VPMOVWBZ256mrk:
10204	case VPMOVWBZ256rr:
10205	case VPMOVWBZ256rrk:
10206	case VPMOVWBZ256rrkz:
10207	case VPMOVWBZmr:
10208	case VPMOVWBZmrk:
10209	case VPMOVWBZrr:
10210	case VPMOVWBZrrk:
10211	case VPMOVWBZrrkz:
10212		return true;
10213	}
10214	return false;
10215}
10216
10217bool isVRNDSCALESD(unsigned Opcode) {
10218	switch (Opcode) {
10219	case VRNDSCALESDZm_Int:
10220	case VRNDSCALESDZm_Intk:
10221	case VRNDSCALESDZm_Intkz:
10222	case VRNDSCALESDZr_Int:
10223	case VRNDSCALESDZr_Intk:
10224	case VRNDSCALESDZr_Intkz:
10225	case VRNDSCALESDZrb_Int:
10226	case VRNDSCALESDZrb_Intk:
10227	case VRNDSCALESDZrb_Intkz:
10228		return true;
10229	}
10230	return false;
10231}
10232
10233bool isVGATHERPF0QPD(unsigned Opcode) {
10234	return Opcode == VGATHERPF0QPDm;
10235}
10236
10237bool isVPHSUBD(unsigned Opcode) {
10238	switch (Opcode) {
10239	case VPHSUBDYrm:
10240	case VPHSUBDYrr:
10241	case VPHSUBDrm:
10242	case VPHSUBDrr:
10243		return true;
10244	}
10245	return false;
10246}
10247
10248bool isVCVTSD2USI(unsigned Opcode) {
10249	switch (Opcode) {
10250	case VCVTSD2USI64Zrm_Int:
10251	case VCVTSD2USI64Zrr_Int:
10252	case VCVTSD2USI64Zrrb_Int:
10253	case VCVTSD2USIZrm_Int:
10254	case VCVTSD2USIZrr_Int:
10255	case VCVTSD2USIZrrb_Int:
10256		return true;
10257	}
10258	return false;
10259}
10260
10261bool isWRGSBASE(unsigned Opcode) {
10262	switch (Opcode) {
10263	case WRGSBASE:
10264	case WRGSBASE64:
10265		return true;
10266	}
10267	return false;
10268}
10269
10270bool isVRNDSCALESH(unsigned Opcode) {
10271	switch (Opcode) {
10272	case VRNDSCALESHZm_Int:
10273	case VRNDSCALESHZm_Intk:
10274	case VRNDSCALESHZm_Intkz:
10275	case VRNDSCALESHZr_Int:
10276	case VRNDSCALESHZr_Intk:
10277	case VRNDSCALESHZr_Intkz:
10278	case VRNDSCALESHZrb_Int:
10279	case VRNDSCALESHZrb_Intk:
10280	case VRNDSCALESHZrb_Intkz:
10281		return true;
10282	}
10283	return false;
10284}
10285
10286bool isAESENC256KL(unsigned Opcode) {
10287	return Opcode == AESENC256KL;
10288}
10289
10290bool isVRNDSCALESS(unsigned Opcode) {
10291	switch (Opcode) {
10292	case VRNDSCALESSZm_Int:
10293	case VRNDSCALESSZm_Intk:
10294	case VRNDSCALESSZm_Intkz:
10295	case VRNDSCALESSZr_Int:
10296	case VRNDSCALESSZr_Intk:
10297	case VRNDSCALESSZr_Intkz:
10298	case VRNDSCALESSZrb_Int:
10299	case VRNDSCALESSZrb_Intk:
10300	case VRNDSCALESSZrb_Intkz:
10301		return true;
10302	}
10303	return false;
10304}
10305
10306bool isVGATHERPF0QPS(unsigned Opcode) {
10307	return Opcode == VGATHERPF0QPSm;
10308}
10309
10310bool isVPHSUBW(unsigned Opcode) {
10311	switch (Opcode) {
10312	case VPHSUBWYrm:
10313	case VPHSUBWYrr:
10314	case VPHSUBWrm:
10315	case VPHSUBWrr:
10316		return true;
10317	}
10318	return false;
10319}
10320
10321bool isSHA1NEXTE(unsigned Opcode) {
10322	switch (Opcode) {
10323	case SHA1NEXTErm:
10324	case SHA1NEXTErr:
10325		return true;
10326	}
10327	return false;
10328}
10329
10330bool isXCRYPTCTR(unsigned Opcode) {
10331	return Opcode == XCRYPTCTR;
10332}
10333
10334bool isFMUL(unsigned Opcode) {
10335	switch (Opcode) {
10336	case MUL_F32m:
10337	case MUL_F64m:
10338	case MUL_FST0r:
10339	case MUL_FrST0:
10340		return true;
10341	}
10342	return false;
10343}
10344
10345bool isFBLD(unsigned Opcode) {
10346	return Opcode == FBLDm;
10347}
10348
10349bool isVMXON(unsigned Opcode) {
10350	return Opcode == VMXON;
10351}
10352
10353bool isPUNPCKHQDQ(unsigned Opcode) {
10354	switch (Opcode) {
10355	case PUNPCKHQDQrm:
10356	case PUNPCKHQDQrr:
10357		return true;
10358	}
10359	return false;
10360}
10361
10362bool isVFRCZSD(unsigned Opcode) {
10363	switch (Opcode) {
10364	case VFRCZSDrm:
10365	case VFRCZSDrr:
10366		return true;
10367	}
10368	return false;
10369}
10370
10371bool isVFRCZSS(unsigned Opcode) {
10372	switch (Opcode) {
10373	case VFRCZSSrm:
10374	case VFRCZSSrr:
10375		return true;
10376	}
10377	return false;
10378}
10379
10380bool isRMPUPDATE(unsigned Opcode) {
10381	return Opcode == RMPUPDATE;
10382}
10383
10384bool isVFNMADDPD(unsigned Opcode) {
10385	switch (Opcode) {
10386	case VFNMADDPD4Ymr:
10387	case VFNMADDPD4Yrm:
10388	case VFNMADDPD4Yrr:
10389	case VFNMADDPD4Yrr_REV:
10390	case VFNMADDPD4mr:
10391	case VFNMADDPD4rm:
10392	case VFNMADDPD4rr:
10393	case VFNMADDPD4rr_REV:
10394		return true;
10395	}
10396	return false;
10397}
10398
10399bool isVCOMISD(unsigned Opcode) {
10400	switch (Opcode) {
10401	case VCOMISDZrm:
10402	case VCOMISDZrr:
10403	case VCOMISDZrrb:
10404	case VCOMISDrm:
10405	case VCOMISDrr:
10406		return true;
10407	}
10408	return false;
10409}
10410
10411bool isVCOMISH(unsigned Opcode) {
10412	switch (Opcode) {
10413	case VCOMISHZrm:
10414	case VCOMISHZrr:
10415	case VCOMISHZrrb:
10416		return true;
10417	}
10418	return false;
10419}
10420
10421bool isAXOR(unsigned Opcode) {
10422	switch (Opcode) {
10423	case AXOR32mr:
10424	case AXOR64mr:
10425		return true;
10426	}
10427	return false;
10428}
10429
10430bool isVFNMADDPS(unsigned Opcode) {
10431	switch (Opcode) {
10432	case VFNMADDPS4Ymr:
10433	case VFNMADDPS4Yrm:
10434	case VFNMADDPS4Yrr:
10435	case VFNMADDPS4Yrr_REV:
10436	case VFNMADDPS4mr:
10437	case VFNMADDPS4rm:
10438	case VFNMADDPS4rr:
10439	case VFNMADDPS4rr_REV:
10440		return true;
10441	}
10442	return false;
10443}
10444
10445bool isVCOMISS(unsigned Opcode) {
10446	switch (Opcode) {
10447	case VCOMISSZrm:
10448	case VCOMISSZrr:
10449	case VCOMISSZrrb:
10450	case VCOMISSrm:
10451	case VCOMISSrr:
10452		return true;
10453	}
10454	return false;
10455}
10456
10457bool isPHADDD(unsigned Opcode) {
10458	switch (Opcode) {
10459	case MMX_PHADDDrm:
10460	case MMX_PHADDDrr:
10461	case PHADDDrm:
10462	case PHADDDrr:
10463		return true;
10464	}
10465	return false;
10466}
10467
10468bool isVPMULHUW(unsigned Opcode) {
10469	switch (Opcode) {
10470	case VPMULHUWYrm:
10471	case VPMULHUWYrr:
10472	case VPMULHUWZ128rm:
10473	case VPMULHUWZ128rmk:
10474	case VPMULHUWZ128rmkz:
10475	case VPMULHUWZ128rr:
10476	case VPMULHUWZ128rrk:
10477	case VPMULHUWZ128rrkz:
10478	case VPMULHUWZ256rm:
10479	case VPMULHUWZ256rmk:
10480	case VPMULHUWZ256rmkz:
10481	case VPMULHUWZ256rr:
10482	case VPMULHUWZ256rrk:
10483	case VPMULHUWZ256rrkz:
10484	case VPMULHUWZrm:
10485	case VPMULHUWZrmk:
10486	case VPMULHUWZrmkz:
10487	case VPMULHUWZrr:
10488	case VPMULHUWZrrk:
10489	case VPMULHUWZrrkz:
10490	case VPMULHUWrm:
10491	case VPMULHUWrr:
10492		return true;
10493	}
10494	return false;
10495}
10496
10497bool isVFNMSUB132PD(unsigned Opcode) {
10498	switch (Opcode) {
10499	case VFNMSUB132PDYm:
10500	case VFNMSUB132PDYr:
10501	case VFNMSUB132PDZ128m:
10502	case VFNMSUB132PDZ128mb:
10503	case VFNMSUB132PDZ128mbk:
10504	case VFNMSUB132PDZ128mbkz:
10505	case VFNMSUB132PDZ128mk:
10506	case VFNMSUB132PDZ128mkz:
10507	case VFNMSUB132PDZ128r:
10508	case VFNMSUB132PDZ128rk:
10509	case VFNMSUB132PDZ128rkz:
10510	case VFNMSUB132PDZ256m:
10511	case VFNMSUB132PDZ256mb:
10512	case VFNMSUB132PDZ256mbk:
10513	case VFNMSUB132PDZ256mbkz:
10514	case VFNMSUB132PDZ256mk:
10515	case VFNMSUB132PDZ256mkz:
10516	case VFNMSUB132PDZ256r:
10517	case VFNMSUB132PDZ256rk:
10518	case VFNMSUB132PDZ256rkz:
10519	case VFNMSUB132PDZm:
10520	case VFNMSUB132PDZmb:
10521	case VFNMSUB132PDZmbk:
10522	case VFNMSUB132PDZmbkz:
10523	case VFNMSUB132PDZmk:
10524	case VFNMSUB132PDZmkz:
10525	case VFNMSUB132PDZr:
10526	case VFNMSUB132PDZrb:
10527	case VFNMSUB132PDZrbk:
10528	case VFNMSUB132PDZrbkz:
10529	case VFNMSUB132PDZrk:
10530	case VFNMSUB132PDZrkz:
10531	case VFNMSUB132PDm:
10532	case VFNMSUB132PDr:
10533		return true;
10534	}
10535	return false;
10536}
10537
10538bool isPMOVMSKB(unsigned Opcode) {
10539	switch (Opcode) {
10540	case MMX_PMOVMSKBrr:
10541	case PMOVMSKBrr:
10542		return true;
10543	}
10544	return false;
10545}
10546
10547bool isVFNMSUB132PH(unsigned Opcode) {
10548	switch (Opcode) {
10549	case VFNMSUB132PHZ128m:
10550	case VFNMSUB132PHZ128mb:
10551	case VFNMSUB132PHZ128mbk:
10552	case VFNMSUB132PHZ128mbkz:
10553	case VFNMSUB132PHZ128mk:
10554	case VFNMSUB132PHZ128mkz:
10555	case VFNMSUB132PHZ128r:
10556	case VFNMSUB132PHZ128rk:
10557	case VFNMSUB132PHZ128rkz:
10558	case VFNMSUB132PHZ256m:
10559	case VFNMSUB132PHZ256mb:
10560	case VFNMSUB132PHZ256mbk:
10561	case VFNMSUB132PHZ256mbkz:
10562	case VFNMSUB132PHZ256mk:
10563	case VFNMSUB132PHZ256mkz:
10564	case VFNMSUB132PHZ256r:
10565	case VFNMSUB132PHZ256rk:
10566	case VFNMSUB132PHZ256rkz:
10567	case VFNMSUB132PHZm:
10568	case VFNMSUB132PHZmb:
10569	case VFNMSUB132PHZmbk:
10570	case VFNMSUB132PHZmbkz:
10571	case VFNMSUB132PHZmk:
10572	case VFNMSUB132PHZmkz:
10573	case VFNMSUB132PHZr:
10574	case VFNMSUB132PHZrb:
10575	case VFNMSUB132PHZrbk:
10576	case VFNMSUB132PHZrbkz:
10577	case VFNMSUB132PHZrk:
10578	case VFNMSUB132PHZrkz:
10579		return true;
10580	}
10581	return false;
10582}
10583
10584bool isPHADDW(unsigned Opcode) {
10585	switch (Opcode) {
10586	case MMX_PHADDWrm:
10587	case MMX_PHADDWrr:
10588	case PHADDWrm:
10589	case PHADDWrr:
10590		return true;
10591	}
10592	return false;
10593}
10594
10595bool isVFNMSUB132PS(unsigned Opcode) {
10596	switch (Opcode) {
10597	case VFNMSUB132PSYm:
10598	case VFNMSUB132PSYr:
10599	case VFNMSUB132PSZ128m:
10600	case VFNMSUB132PSZ128mb:
10601	case VFNMSUB132PSZ128mbk:
10602	case VFNMSUB132PSZ128mbkz:
10603	case VFNMSUB132PSZ128mk:
10604	case VFNMSUB132PSZ128mkz:
10605	case VFNMSUB132PSZ128r:
10606	case VFNMSUB132PSZ128rk:
10607	case VFNMSUB132PSZ128rkz:
10608	case VFNMSUB132PSZ256m:
10609	case VFNMSUB132PSZ256mb:
10610	case VFNMSUB132PSZ256mbk:
10611	case VFNMSUB132PSZ256mbkz:
10612	case VFNMSUB132PSZ256mk:
10613	case VFNMSUB132PSZ256mkz:
10614	case VFNMSUB132PSZ256r:
10615	case VFNMSUB132PSZ256rk:
10616	case VFNMSUB132PSZ256rkz:
10617	case VFNMSUB132PSZm:
10618	case VFNMSUB132PSZmb:
10619	case VFNMSUB132PSZmbk:
10620	case VFNMSUB132PSZmbkz:
10621	case VFNMSUB132PSZmk:
10622	case VFNMSUB132PSZmkz:
10623	case VFNMSUB132PSZr:
10624	case VFNMSUB132PSZrb:
10625	case VFNMSUB132PSZrbk:
10626	case VFNMSUB132PSZrbkz:
10627	case VFNMSUB132PSZrk:
10628	case VFNMSUB132PSZrkz:
10629	case VFNMSUB132PSm:
10630	case VFNMSUB132PSr:
10631		return true;
10632	}
10633	return false;
10634}
10635
10636bool isVMOVDQA(unsigned Opcode) {
10637	switch (Opcode) {
10638	case VMOVDQAYmr:
10639	case VMOVDQAYrm:
10640	case VMOVDQAYrr:
10641	case VMOVDQAYrr_REV:
10642	case VMOVDQAmr:
10643	case VMOVDQArm:
10644	case VMOVDQArr:
10645	case VMOVDQArr_REV:
10646		return true;
10647	}
10648	return false;
10649}
10650
10651bool isSENDUIPI(unsigned Opcode) {
10652	return Opcode == SENDUIPI;
10653}
10654
10655bool isVCVTTPS2DQ(unsigned Opcode) {
10656	switch (Opcode) {
10657	case VCVTTPS2DQYrm:
10658	case VCVTTPS2DQYrr:
10659	case VCVTTPS2DQZ128rm:
10660	case VCVTTPS2DQZ128rmb:
10661	case VCVTTPS2DQZ128rmbk:
10662	case VCVTTPS2DQZ128rmbkz:
10663	case VCVTTPS2DQZ128rmk:
10664	case VCVTTPS2DQZ128rmkz:
10665	case VCVTTPS2DQZ128rr:
10666	case VCVTTPS2DQZ128rrk:
10667	case VCVTTPS2DQZ128rrkz:
10668	case VCVTTPS2DQZ256rm:
10669	case VCVTTPS2DQZ256rmb:
10670	case VCVTTPS2DQZ256rmbk:
10671	case VCVTTPS2DQZ256rmbkz:
10672	case VCVTTPS2DQZ256rmk:
10673	case VCVTTPS2DQZ256rmkz:
10674	case VCVTTPS2DQZ256rr:
10675	case VCVTTPS2DQZ256rrk:
10676	case VCVTTPS2DQZ256rrkz:
10677	case VCVTTPS2DQZrm:
10678	case VCVTTPS2DQZrmb:
10679	case VCVTTPS2DQZrmbk:
10680	case VCVTTPS2DQZrmbkz:
10681	case VCVTTPS2DQZrmk:
10682	case VCVTTPS2DQZrmkz:
10683	case VCVTTPS2DQZrr:
10684	case VCVTTPS2DQZrrb:
10685	case VCVTTPS2DQZrrbk:
10686	case VCVTTPS2DQZrrbkz:
10687	case VCVTTPS2DQZrrk:
10688	case VCVTTPS2DQZrrkz:
10689	case VCVTTPS2DQrm:
10690	case VCVTTPS2DQrr:
10691		return true;
10692	}
10693	return false;
10694}
10695
10696bool isRCPPS(unsigned Opcode) {
10697	switch (Opcode) {
10698	case RCPPSm:
10699	case RCPPSr:
10700		return true;
10701	}
10702	return false;
10703}
10704
10705bool isRDMSR(unsigned Opcode) {
10706	return Opcode == RDMSR;
10707}
10708
10709bool isVCVTQQ2PD(unsigned Opcode) {
10710	switch (Opcode) {
10711	case VCVTQQ2PDZ128rm:
10712	case VCVTQQ2PDZ128rmb:
10713	case VCVTQQ2PDZ128rmbk:
10714	case VCVTQQ2PDZ128rmbkz:
10715	case VCVTQQ2PDZ128rmk:
10716	case VCVTQQ2PDZ128rmkz:
10717	case VCVTQQ2PDZ128rr:
10718	case VCVTQQ2PDZ128rrk:
10719	case VCVTQQ2PDZ128rrkz:
10720	case VCVTQQ2PDZ256rm:
10721	case VCVTQQ2PDZ256rmb:
10722	case VCVTQQ2PDZ256rmbk:
10723	case VCVTQQ2PDZ256rmbkz:
10724	case VCVTQQ2PDZ256rmk:
10725	case VCVTQQ2PDZ256rmkz:
10726	case VCVTQQ2PDZ256rr:
10727	case VCVTQQ2PDZ256rrk:
10728	case VCVTQQ2PDZ256rrkz:
10729	case VCVTQQ2PDZrm:
10730	case VCVTQQ2PDZrmb:
10731	case VCVTQQ2PDZrmbk:
10732	case VCVTQQ2PDZrmbkz:
10733	case VCVTQQ2PDZrmk:
10734	case VCVTQQ2PDZrmkz:
10735	case VCVTQQ2PDZrr:
10736	case VCVTQQ2PDZrrb:
10737	case VCVTQQ2PDZrrbk:
10738	case VCVTQQ2PDZrrbkz:
10739	case VCVTQQ2PDZrrk:
10740	case VCVTQQ2PDZrrkz:
10741		return true;
10742	}
10743	return false;
10744}
10745
10746bool isVRSQRT14PD(unsigned Opcode) {
10747	switch (Opcode) {
10748	case VRSQRT14PDZ128m:
10749	case VRSQRT14PDZ128mb:
10750	case VRSQRT14PDZ128mbk:
10751	case VRSQRT14PDZ128mbkz:
10752	case VRSQRT14PDZ128mk:
10753	case VRSQRT14PDZ128mkz:
10754	case VRSQRT14PDZ128r:
10755	case VRSQRT14PDZ128rk:
10756	case VRSQRT14PDZ128rkz:
10757	case VRSQRT14PDZ256m:
10758	case VRSQRT14PDZ256mb:
10759	case VRSQRT14PDZ256mbk:
10760	case VRSQRT14PDZ256mbkz:
10761	case VRSQRT14PDZ256mk:
10762	case VRSQRT14PDZ256mkz:
10763	case VRSQRT14PDZ256r:
10764	case VRSQRT14PDZ256rk:
10765	case VRSQRT14PDZ256rkz:
10766	case VRSQRT14PDZm:
10767	case VRSQRT14PDZmb:
10768	case VRSQRT14PDZmbk:
10769	case VRSQRT14PDZmbkz:
10770	case VRSQRT14PDZmk:
10771	case VRSQRT14PDZmkz:
10772	case VRSQRT14PDZr:
10773	case VRSQRT14PDZrk:
10774	case VRSQRT14PDZrkz:
10775		return true;
10776	}
10777	return false;
10778}
10779
10780bool isXORPD(unsigned Opcode) {
10781	switch (Opcode) {
10782	case XORPDrm:
10783	case XORPDrr:
10784		return true;
10785	}
10786	return false;
10787}
10788
10789bool isVCVTQQ2PH(unsigned Opcode) {
10790	switch (Opcode) {
10791	case VCVTQQ2PHZ128rm:
10792	case VCVTQQ2PHZ128rmb:
10793	case VCVTQQ2PHZ128rmbk:
10794	case VCVTQQ2PHZ128rmbkz:
10795	case VCVTQQ2PHZ128rmk:
10796	case VCVTQQ2PHZ128rmkz:
10797	case VCVTQQ2PHZ128rr:
10798	case VCVTQQ2PHZ128rrk:
10799	case VCVTQQ2PHZ128rrkz:
10800	case VCVTQQ2PHZ256rm:
10801	case VCVTQQ2PHZ256rmb:
10802	case VCVTQQ2PHZ256rmbk:
10803	case VCVTQQ2PHZ256rmbkz:
10804	case VCVTQQ2PHZ256rmk:
10805	case VCVTQQ2PHZ256rmkz:
10806	case VCVTQQ2PHZ256rr:
10807	case VCVTQQ2PHZ256rrk:
10808	case VCVTQQ2PHZ256rrkz:
10809	case VCVTQQ2PHZrm:
10810	case VCVTQQ2PHZrmb:
10811	case VCVTQQ2PHZrmbk:
10812	case VCVTQQ2PHZrmbkz:
10813	case VCVTQQ2PHZrmk:
10814	case VCVTQQ2PHZrmkz:
10815	case VCVTQQ2PHZrr:
10816	case VCVTQQ2PHZrrb:
10817	case VCVTQQ2PHZrrbk:
10818	case VCVTQQ2PHZrrbkz:
10819	case VCVTQQ2PHZrrk:
10820	case VCVTQQ2PHZrrkz:
10821		return true;
10822	}
10823	return false;
10824}
10825
10826bool isVMOVDQU(unsigned Opcode) {
10827	switch (Opcode) {
10828	case VMOVDQUYmr:
10829	case VMOVDQUYrm:
10830	case VMOVDQUYrr:
10831	case VMOVDQUYrr_REV:
10832	case VMOVDQUmr:
10833	case VMOVDQUrm:
10834	case VMOVDQUrr:
10835	case VMOVDQUrr_REV:
10836		return true;
10837	}
10838	return false;
10839}
10840
10841bool isBLENDPD(unsigned Opcode) {
10842	switch (Opcode) {
10843	case BLENDPDrmi:
10844	case BLENDPDrri:
10845		return true;
10846	}
10847	return false;
10848}
10849
10850bool isVCVTQQ2PS(unsigned Opcode) {
10851	switch (Opcode) {
10852	case VCVTQQ2PSZ128rm:
10853	case VCVTQQ2PSZ128rmb:
10854	case VCVTQQ2PSZ128rmbk:
10855	case VCVTQQ2PSZ128rmbkz:
10856	case VCVTQQ2PSZ128rmk:
10857	case VCVTQQ2PSZ128rmkz:
10858	case VCVTQQ2PSZ128rr:
10859	case VCVTQQ2PSZ128rrk:
10860	case VCVTQQ2PSZ128rrkz:
10861	case VCVTQQ2PSZ256rm:
10862	case VCVTQQ2PSZ256rmb:
10863	case VCVTQQ2PSZ256rmbk:
10864	case VCVTQQ2PSZ256rmbkz:
10865	case VCVTQQ2PSZ256rmk:
10866	case VCVTQQ2PSZ256rmkz:
10867	case VCVTQQ2PSZ256rr:
10868	case VCVTQQ2PSZ256rrk:
10869	case VCVTQQ2PSZ256rrkz:
10870	case VCVTQQ2PSZrm:
10871	case VCVTQQ2PSZrmb:
10872	case VCVTQQ2PSZrmbk:
10873	case VCVTQQ2PSZrmbkz:
10874	case VCVTQQ2PSZrmk:
10875	case VCVTQQ2PSZrmkz:
10876	case VCVTQQ2PSZrr:
10877	case VCVTQQ2PSZrrb:
10878	case VCVTQQ2PSZrrbk:
10879	case VCVTQQ2PSZrrbkz:
10880	case VCVTQQ2PSZrrk:
10881	case VCVTQQ2PSZrrkz:
10882		return true;
10883	}
10884	return false;
10885}
10886
10887bool isVRSQRT14PS(unsigned Opcode) {
10888	switch (Opcode) {
10889	case VRSQRT14PSZ128m:
10890	case VRSQRT14PSZ128mb:
10891	case VRSQRT14PSZ128mbk:
10892	case VRSQRT14PSZ128mbkz:
10893	case VRSQRT14PSZ128mk:
10894	case VRSQRT14PSZ128mkz:
10895	case VRSQRT14PSZ128r:
10896	case VRSQRT14PSZ128rk:
10897	case VRSQRT14PSZ128rkz:
10898	case VRSQRT14PSZ256m:
10899	case VRSQRT14PSZ256mb:
10900	case VRSQRT14PSZ256mbk:
10901	case VRSQRT14PSZ256mbkz:
10902	case VRSQRT14PSZ256mk:
10903	case VRSQRT14PSZ256mkz:
10904	case VRSQRT14PSZ256r:
10905	case VRSQRT14PSZ256rk:
10906	case VRSQRT14PSZ256rkz:
10907	case VRSQRT14PSZm:
10908	case VRSQRT14PSZmb:
10909	case VRSQRT14PSZmbk:
10910	case VRSQRT14PSZmbkz:
10911	case VRSQRT14PSZmk:
10912	case VRSQRT14PSZmkz:
10913	case VRSQRT14PSZr:
10914	case VRSQRT14PSZrk:
10915	case VRSQRT14PSZrkz:
10916		return true;
10917	}
10918	return false;
10919}
10920
10921bool isXORPS(unsigned Opcode) {
10922	switch (Opcode) {
10923	case XORPSrm:
10924	case XORPSrr:
10925		return true;
10926	}
10927	return false;
10928}
10929
10930bool isRCL(unsigned Opcode) {
10931	switch (Opcode) {
10932	case RCL16m1:
10933	case RCL16mCL:
10934	case RCL16mi:
10935	case RCL16r1:
10936	case RCL16rCL:
10937	case RCL16ri:
10938	case RCL32m1:
10939	case RCL32mCL:
10940	case RCL32mi:
10941	case RCL32r1:
10942	case RCL32rCL:
10943	case RCL32ri:
10944	case RCL64m1:
10945	case RCL64mCL:
10946	case RCL64mi:
10947	case RCL64r1:
10948	case RCL64rCL:
10949	case RCL64ri:
10950	case RCL8m1:
10951	case RCL8mCL:
10952	case RCL8mi:
10953	case RCL8r1:
10954	case RCL8rCL:
10955	case RCL8ri:
10956		return true;
10957	}
10958	return false;
10959}
10960
10961bool isRCR(unsigned Opcode) {
10962	switch (Opcode) {
10963	case RCR16m1:
10964	case RCR16mCL:
10965	case RCR16mi:
10966	case RCR16r1:
10967	case RCR16rCL:
10968	case RCR16ri:
10969	case RCR32m1:
10970	case RCR32mCL:
10971	case RCR32mi:
10972	case RCR32r1:
10973	case RCR32rCL:
10974	case RCR32ri:
10975	case RCR64m1:
10976	case RCR64mCL:
10977	case RCR64mi:
10978	case RCR64r1:
10979	case RCR64rCL:
10980	case RCR64ri:
10981	case RCR8m1:
10982	case RCR8mCL:
10983	case RCR8mi:
10984	case RCR8r1:
10985	case RCR8rCL:
10986	case RCR8ri:
10987		return true;
10988	}
10989	return false;
10990}
10991
10992bool isBLENDPS(unsigned Opcode) {
10993	switch (Opcode) {
10994	case BLENDPSrmi:
10995	case BLENDPSrri:
10996		return true;
10997	}
10998	return false;
10999}
11000
11001bool isVPEXPANDB(unsigned Opcode) {
11002	switch (Opcode) {
11003	case VPEXPANDBZ128rm:
11004	case VPEXPANDBZ128rmk:
11005	case VPEXPANDBZ128rmkz:
11006	case VPEXPANDBZ128rr:
11007	case VPEXPANDBZ128rrk:
11008	case VPEXPANDBZ128rrkz:
11009	case VPEXPANDBZ256rm:
11010	case VPEXPANDBZ256rmk:
11011	case VPEXPANDBZ256rmkz:
11012	case VPEXPANDBZ256rr:
11013	case VPEXPANDBZ256rrk:
11014	case VPEXPANDBZ256rrkz:
11015	case VPEXPANDBZrm:
11016	case VPEXPANDBZrmk:
11017	case VPEXPANDBZrmkz:
11018	case VPEXPANDBZrr:
11019	case VPEXPANDBZrrk:
11020	case VPEXPANDBZrrkz:
11021		return true;
11022	}
11023	return false;
11024}
11025
11026bool isVEXPANDPD(unsigned Opcode) {
11027	switch (Opcode) {
11028	case VEXPANDPDZ128rm:
11029	case VEXPANDPDZ128rmk:
11030	case VEXPANDPDZ128rmkz:
11031	case VEXPANDPDZ128rr:
11032	case VEXPANDPDZ128rrk:
11033	case VEXPANDPDZ128rrkz:
11034	case VEXPANDPDZ256rm:
11035	case VEXPANDPDZ256rmk:
11036	case VEXPANDPDZ256rmkz:
11037	case VEXPANDPDZ256rr:
11038	case VEXPANDPDZ256rrk:
11039	case VEXPANDPDZ256rrkz:
11040	case VEXPANDPDZrm:
11041	case VEXPANDPDZrmk:
11042	case VEXPANDPDZrmkz:
11043	case VEXPANDPDZrr:
11044	case VEXPANDPDZrrk:
11045	case VEXPANDPDZrrkz:
11046		return true;
11047	}
11048	return false;
11049}
11050
11051bool isVPEXPANDD(unsigned Opcode) {
11052	switch (Opcode) {
11053	case VPEXPANDDZ128rm:
11054	case VPEXPANDDZ128rmk:
11055	case VPEXPANDDZ128rmkz:
11056	case VPEXPANDDZ128rr:
11057	case VPEXPANDDZ128rrk:
11058	case VPEXPANDDZ128rrkz:
11059	case VPEXPANDDZ256rm:
11060	case VPEXPANDDZ256rmk:
11061	case VPEXPANDDZ256rmkz:
11062	case VPEXPANDDZ256rr:
11063	case VPEXPANDDZ256rrk:
11064	case VPEXPANDDZ256rrkz:
11065	case VPEXPANDDZrm:
11066	case VPEXPANDDZrmk:
11067	case VPEXPANDDZrmkz:
11068	case VPEXPANDDZrr:
11069	case VPEXPANDDZrrk:
11070	case VPEXPANDDZrrkz:
11071		return true;
11072	}
11073	return false;
11074}
11075
11076bool isBLSMSK(unsigned Opcode) {
11077	switch (Opcode) {
11078	case BLSMSK32rm:
11079	case BLSMSK32rr:
11080	case BLSMSK64rm:
11081	case BLSMSK64rr:
11082		return true;
11083	}
11084	return false;
11085}
11086
11087bool isXSUSLDTRK(unsigned Opcode) {
11088	return Opcode == XSUSLDTRK;
11089}
11090
11091bool isGF2P8MULB(unsigned Opcode) {
11092	switch (Opcode) {
11093	case GF2P8MULBrm:
11094	case GF2P8MULBrr:
11095		return true;
11096	}
11097	return false;
11098}
11099
11100bool isSIDTD(unsigned Opcode) {
11101	return Opcode == SIDT32m;
11102}
11103
11104bool isVEXPANDPS(unsigned Opcode) {
11105	switch (Opcode) {
11106	case VEXPANDPSZ128rm:
11107	case VEXPANDPSZ128rmk:
11108	case VEXPANDPSZ128rmkz:
11109	case VEXPANDPSZ128rr:
11110	case VEXPANDPSZ128rrk:
11111	case VEXPANDPSZ128rrkz:
11112	case VEXPANDPSZ256rm:
11113	case VEXPANDPSZ256rmk:
11114	case VEXPANDPSZ256rmkz:
11115	case VEXPANDPSZ256rr:
11116	case VEXPANDPSZ256rrk:
11117	case VEXPANDPSZ256rrkz:
11118	case VEXPANDPSZrm:
11119	case VEXPANDPSZrmk:
11120	case VEXPANDPSZrmkz:
11121	case VEXPANDPSZrr:
11122	case VEXPANDPSZrrk:
11123	case VEXPANDPSZrrkz:
11124		return true;
11125	}
11126	return false;
11127}
11128
11129bool isVFNMADDSD(unsigned Opcode) {
11130	switch (Opcode) {
11131	case VFNMADDSD4mr:
11132	case VFNMADDSD4rm:
11133	case VFNMADDSD4rr:
11134	case VFNMADDSD4rr_REV:
11135		return true;
11136	}
11137	return false;
11138}
11139
11140bool isCBW(unsigned Opcode) {
11141	return Opcode == CBW;
11142}
11143
11144bool isVPEXPANDW(unsigned Opcode) {
11145	switch (Opcode) {
11146	case VPEXPANDWZ128rm:
11147	case VPEXPANDWZ128rmk:
11148	case VPEXPANDWZ128rmkz:
11149	case VPEXPANDWZ128rr:
11150	case VPEXPANDWZ128rrk:
11151	case VPEXPANDWZ128rrkz:
11152	case VPEXPANDWZ256rm:
11153	case VPEXPANDWZ256rmk:
11154	case VPEXPANDWZ256rmkz:
11155	case VPEXPANDWZ256rr:
11156	case VPEXPANDWZ256rrk:
11157	case VPEXPANDWZ256rrkz:
11158	case VPEXPANDWZrm:
11159	case VPEXPANDWZrmk:
11160	case VPEXPANDWZrmkz:
11161	case VPEXPANDWZrr:
11162	case VPEXPANDWZrrk:
11163	case VPEXPANDWZrrkz:
11164		return true;
11165	}
11166	return false;
11167}
11168
11169bool isVPEXPANDQ(unsigned Opcode) {
11170	switch (Opcode) {
11171	case VPEXPANDQZ128rm:
11172	case VPEXPANDQZ128rmk:
11173	case VPEXPANDQZ128rmkz:
11174	case VPEXPANDQZ128rr:
11175	case VPEXPANDQZ128rrk:
11176	case VPEXPANDQZ128rrkz:
11177	case VPEXPANDQZ256rm:
11178	case VPEXPANDQZ256rmk:
11179	case VPEXPANDQZ256rmkz:
11180	case VPEXPANDQZ256rr:
11181	case VPEXPANDQZ256rrk:
11182	case VPEXPANDQZ256rrkz:
11183	case VPEXPANDQZrm:
11184	case VPEXPANDQZrmk:
11185	case VPEXPANDQZrmkz:
11186	case VPEXPANDQZrr:
11187	case VPEXPANDQZrrk:
11188	case VPEXPANDQZrrkz:
11189		return true;
11190	}
11191	return false;
11192}
11193
11194bool isFXRSTOR64(unsigned Opcode) {
11195	return Opcode == FXRSTOR64;
11196}
11197
11198bool isVFNMADDSS(unsigned Opcode) {
11199	switch (Opcode) {
11200	case VFNMADDSS4mr:
11201	case VFNMADDSS4rm:
11202	case VFNMADDSS4rr:
11203	case VFNMADDSS4rr_REV:
11204		return true;
11205	}
11206	return false;
11207}
11208
11209bool isSIDTW(unsigned Opcode) {
11210	return Opcode == SIDT16m;
11211}
11212
11213bool isCVTPD2PI(unsigned Opcode) {
11214	switch (Opcode) {
11215	case MMX_CVTPD2PIrm:
11216	case MMX_CVTPD2PIrr:
11217		return true;
11218	}
11219	return false;
11220}
11221
11222bool isVCVTPS2PD(unsigned Opcode) {
11223	switch (Opcode) {
11224	case VCVTPS2PDYrm:
11225	case VCVTPS2PDYrr:
11226	case VCVTPS2PDZ128rm:
11227	case VCVTPS2PDZ128rmb:
11228	case VCVTPS2PDZ128rmbk:
11229	case VCVTPS2PDZ128rmbkz:
11230	case VCVTPS2PDZ128rmk:
11231	case VCVTPS2PDZ128rmkz:
11232	case VCVTPS2PDZ128rr:
11233	case VCVTPS2PDZ128rrk:
11234	case VCVTPS2PDZ128rrkz:
11235	case VCVTPS2PDZ256rm:
11236	case VCVTPS2PDZ256rmb:
11237	case VCVTPS2PDZ256rmbk:
11238	case VCVTPS2PDZ256rmbkz:
11239	case VCVTPS2PDZ256rmk:
11240	case VCVTPS2PDZ256rmkz:
11241	case VCVTPS2PDZ256rr:
11242	case VCVTPS2PDZ256rrk:
11243	case VCVTPS2PDZ256rrkz:
11244	case VCVTPS2PDZrm:
11245	case VCVTPS2PDZrmb:
11246	case VCVTPS2PDZrmbk:
11247	case VCVTPS2PDZrmbkz:
11248	case VCVTPS2PDZrmk:
11249	case VCVTPS2PDZrmkz:
11250	case VCVTPS2PDZrr:
11251	case VCVTPS2PDZrrb:
11252	case VCVTPS2PDZrrbk:
11253	case VCVTPS2PDZrrbkz:
11254	case VCVTPS2PDZrrk:
11255	case VCVTPS2PDZrrkz:
11256	case VCVTPS2PDrm:
11257	case VCVTPS2PDrr:
11258		return true;
11259	}
11260	return false;
11261}
11262
11263bool isVFNMSUB132SD(unsigned Opcode) {
11264	switch (Opcode) {
11265	case VFNMSUB132SDZm_Int:
11266	case VFNMSUB132SDZm_Intk:
11267	case VFNMSUB132SDZm_Intkz:
11268	case VFNMSUB132SDZr_Int:
11269	case VFNMSUB132SDZr_Intk:
11270	case VFNMSUB132SDZr_Intkz:
11271	case VFNMSUB132SDZrb_Int:
11272	case VFNMSUB132SDZrb_Intk:
11273	case VFNMSUB132SDZrb_Intkz:
11274	case VFNMSUB132SDm_Int:
11275	case VFNMSUB132SDr_Int:
11276		return true;
11277	}
11278	return false;
11279}
11280
11281bool isVCVTPS2PH(unsigned Opcode) {
11282	switch (Opcode) {
11283	case VCVTPS2PHYmr:
11284	case VCVTPS2PHYrr:
11285	case VCVTPS2PHZ128mr:
11286	case VCVTPS2PHZ128mrk:
11287	case VCVTPS2PHZ128rr:
11288	case VCVTPS2PHZ128rrk:
11289	case VCVTPS2PHZ128rrkz:
11290	case VCVTPS2PHZ256mr:
11291	case VCVTPS2PHZ256mrk:
11292	case VCVTPS2PHZ256rr:
11293	case VCVTPS2PHZ256rrk:
11294	case VCVTPS2PHZ256rrkz:
11295	case VCVTPS2PHZmr:
11296	case VCVTPS2PHZmrk:
11297	case VCVTPS2PHZrr:
11298	case VCVTPS2PHZrrb:
11299	case VCVTPS2PHZrrbk:
11300	case VCVTPS2PHZrrbkz:
11301	case VCVTPS2PHZrrk:
11302	case VCVTPS2PHZrrkz:
11303	case VCVTPS2PHmr:
11304	case VCVTPS2PHrr:
11305		return true;
11306	}
11307	return false;
11308}
11309
11310bool isFIDIV(unsigned Opcode) {
11311	switch (Opcode) {
11312	case DIV_FI16m:
11313	case DIV_FI32m:
11314		return true;
11315	}
11316	return false;
11317}
11318
11319bool isVFNMSUB132SH(unsigned Opcode) {
11320	switch (Opcode) {
11321	case VFNMSUB132SHZm_Int:
11322	case VFNMSUB132SHZm_Intk:
11323	case VFNMSUB132SHZm_Intkz:
11324	case VFNMSUB132SHZr_Int:
11325	case VFNMSUB132SHZr_Intk:
11326	case VFNMSUB132SHZr_Intkz:
11327	case VFNMSUB132SHZrb_Int:
11328	case VFNMSUB132SHZrb_Intk:
11329	case VFNMSUB132SHZrb_Intkz:
11330		return true;
11331	}
11332	return false;
11333}
11334
11335bool isCVTPD2PS(unsigned Opcode) {
11336	switch (Opcode) {
11337	case CVTPD2PSrm:
11338	case CVTPD2PSrr:
11339		return true;
11340	}
11341	return false;
11342}
11343
11344bool isINVEPT(unsigned Opcode) {
11345	switch (Opcode) {
11346	case INVEPT32:
11347	case INVEPT64:
11348		return true;
11349	}
11350	return false;
11351}
11352
11353bool isVPERMI2PD(unsigned Opcode) {
11354	switch (Opcode) {
11355	case VPERMI2PD128rm:
11356	case VPERMI2PD128rmb:
11357	case VPERMI2PD128rmbk:
11358	case VPERMI2PD128rmbkz:
11359	case VPERMI2PD128rmk:
11360	case VPERMI2PD128rmkz:
11361	case VPERMI2PD128rr:
11362	case VPERMI2PD128rrk:
11363	case VPERMI2PD128rrkz:
11364	case VPERMI2PD256rm:
11365	case VPERMI2PD256rmb:
11366	case VPERMI2PD256rmbk:
11367	case VPERMI2PD256rmbkz:
11368	case VPERMI2PD256rmk:
11369	case VPERMI2PD256rmkz:
11370	case VPERMI2PD256rr:
11371	case VPERMI2PD256rrk:
11372	case VPERMI2PD256rrkz:
11373	case VPERMI2PDrm:
11374	case VPERMI2PDrmb:
11375	case VPERMI2PDrmbk:
11376	case VPERMI2PDrmbkz:
11377	case VPERMI2PDrmk:
11378	case VPERMI2PDrmkz:
11379	case VPERMI2PDrr:
11380	case VPERMI2PDrrk:
11381	case VPERMI2PDrrkz:
11382		return true;
11383	}
11384	return false;
11385}
11386
11387bool isVFMSUB213PD(unsigned Opcode) {
11388	switch (Opcode) {
11389	case VFMSUB213PDYm:
11390	case VFMSUB213PDYr:
11391	case VFMSUB213PDZ128m:
11392	case VFMSUB213PDZ128mb:
11393	case VFMSUB213PDZ128mbk:
11394	case VFMSUB213PDZ128mbkz:
11395	case VFMSUB213PDZ128mk:
11396	case VFMSUB213PDZ128mkz:
11397	case VFMSUB213PDZ128r:
11398	case VFMSUB213PDZ128rk:
11399	case VFMSUB213PDZ128rkz:
11400	case VFMSUB213PDZ256m:
11401	case VFMSUB213PDZ256mb:
11402	case VFMSUB213PDZ256mbk:
11403	case VFMSUB213PDZ256mbkz:
11404	case VFMSUB213PDZ256mk:
11405	case VFMSUB213PDZ256mkz:
11406	case VFMSUB213PDZ256r:
11407	case VFMSUB213PDZ256rk:
11408	case VFMSUB213PDZ256rkz:
11409	case VFMSUB213PDZm:
11410	case VFMSUB213PDZmb:
11411	case VFMSUB213PDZmbk:
11412	case VFMSUB213PDZmbkz:
11413	case VFMSUB213PDZmk:
11414	case VFMSUB213PDZmkz:
11415	case VFMSUB213PDZr:
11416	case VFMSUB213PDZrb:
11417	case VFMSUB213PDZrbk:
11418	case VFMSUB213PDZrbkz:
11419	case VFMSUB213PDZrk:
11420	case VFMSUB213PDZrkz:
11421	case VFMSUB213PDm:
11422	case VFMSUB213PDr:
11423		return true;
11424	}
11425	return false;
11426}
11427
11428bool isVFNMSUB132SS(unsigned Opcode) {
11429	switch (Opcode) {
11430	case VFNMSUB132SSZm_Int:
11431	case VFNMSUB132SSZm_Intk:
11432	case VFNMSUB132SSZm_Intkz:
11433	case VFNMSUB132SSZr_Int:
11434	case VFNMSUB132SSZr_Intk:
11435	case VFNMSUB132SSZr_Intkz:
11436	case VFNMSUB132SSZrb_Int:
11437	case VFNMSUB132SSZrb_Intk:
11438	case VFNMSUB132SSZrb_Intkz:
11439	case VFNMSUB132SSm_Int:
11440	case VFNMSUB132SSr_Int:
11441		return true;
11442	}
11443	return false;
11444}
11445
11446bool isINVVPID(unsigned Opcode) {
11447	switch (Opcode) {
11448	case INVVPID32:
11449	case INVVPID64:
11450		return true;
11451	}
11452	return false;
11453}
11454
11455bool isVFMSUB213PH(unsigned Opcode) {
11456	switch (Opcode) {
11457	case VFMSUB213PHZ128m:
11458	case VFMSUB213PHZ128mb:
11459	case VFMSUB213PHZ128mbk:
11460	case VFMSUB213PHZ128mbkz:
11461	case VFMSUB213PHZ128mk:
11462	case VFMSUB213PHZ128mkz:
11463	case VFMSUB213PHZ128r:
11464	case VFMSUB213PHZ128rk:
11465	case VFMSUB213PHZ128rkz:
11466	case VFMSUB213PHZ256m:
11467	case VFMSUB213PHZ256mb:
11468	case VFMSUB213PHZ256mbk:
11469	case VFMSUB213PHZ256mbkz:
11470	case VFMSUB213PHZ256mk:
11471	case VFMSUB213PHZ256mkz:
11472	case VFMSUB213PHZ256r:
11473	case VFMSUB213PHZ256rk:
11474	case VFMSUB213PHZ256rkz:
11475	case VFMSUB213PHZm:
11476	case VFMSUB213PHZmb:
11477	case VFMSUB213PHZmbk:
11478	case VFMSUB213PHZmbkz:
11479	case VFMSUB213PHZmk:
11480	case VFMSUB213PHZmkz:
11481	case VFMSUB213PHZr:
11482	case VFMSUB213PHZrb:
11483	case VFMSUB213PHZrbk:
11484	case VFMSUB213PHZrbkz:
11485	case VFMSUB213PHZrk:
11486	case VFMSUB213PHZrkz:
11487		return true;
11488	}
11489	return false;
11490}
11491
11492bool isVPCOMB(unsigned Opcode) {
11493	switch (Opcode) {
11494	case VPCOMBmi:
11495	case VPCOMBri:
11496		return true;
11497	}
11498	return false;
11499}
11500
11501bool isVPERMI2PS(unsigned Opcode) {
11502	switch (Opcode) {
11503	case VPERMI2PS128rm:
11504	case VPERMI2PS128rmb:
11505	case VPERMI2PS128rmbk:
11506	case VPERMI2PS128rmbkz:
11507	case VPERMI2PS128rmk:
11508	case VPERMI2PS128rmkz:
11509	case VPERMI2PS128rr:
11510	case VPERMI2PS128rrk:
11511	case VPERMI2PS128rrkz:
11512	case VPERMI2PS256rm:
11513	case VPERMI2PS256rmb:
11514	case VPERMI2PS256rmbk:
11515	case VPERMI2PS256rmbkz:
11516	case VPERMI2PS256rmk:
11517	case VPERMI2PS256rmkz:
11518	case VPERMI2PS256rr:
11519	case VPERMI2PS256rrk:
11520	case VPERMI2PS256rrkz:
11521	case VPERMI2PSrm:
11522	case VPERMI2PSrmb:
11523	case VPERMI2PSrmbk:
11524	case VPERMI2PSrmbkz:
11525	case VPERMI2PSrmk:
11526	case VPERMI2PSrmkz:
11527	case VPERMI2PSrr:
11528	case VPERMI2PSrrk:
11529	case VPERMI2PSrrkz:
11530		return true;
11531	}
11532	return false;
11533}
11534
11535bool isVPCOMD(unsigned Opcode) {
11536	switch (Opcode) {
11537	case VPCOMDmi:
11538	case VPCOMDri:
11539		return true;
11540	}
11541	return false;
11542}
11543
11544bool isSMSW(unsigned Opcode) {
11545	switch (Opcode) {
11546	case SMSW16m:
11547	case SMSW16r:
11548	case SMSW32r:
11549	case SMSW64r:
11550		return true;
11551	}
11552	return false;
11553}
11554
11555bool isRCPSS(unsigned Opcode) {
11556	switch (Opcode) {
11557	case RCPSSm_Int:
11558	case RCPSSr_Int:
11559		return true;
11560	}
11561	return false;
11562}
11563
11564bool isRET(unsigned Opcode) {
11565	switch (Opcode) {
11566	case RET16:
11567	case RET32:
11568	case RET64:
11569	case RETI16:
11570	case RETI32:
11571	case RETI64:
11572		return true;
11573	}
11574	return false;
11575}
11576
11577bool isVFMSUB213PS(unsigned Opcode) {
11578	switch (Opcode) {
11579	case VFMSUB213PSYm:
11580	case VFMSUB213PSYr:
11581	case VFMSUB213PSZ128m:
11582	case VFMSUB213PSZ128mb:
11583	case VFMSUB213PSZ128mbk:
11584	case VFMSUB213PSZ128mbkz:
11585	case VFMSUB213PSZ128mk:
11586	case VFMSUB213PSZ128mkz:
11587	case VFMSUB213PSZ128r:
11588	case VFMSUB213PSZ128rk:
11589	case VFMSUB213PSZ128rkz:
11590	case VFMSUB213PSZ256m:
11591	case VFMSUB213PSZ256mb:
11592	case VFMSUB213PSZ256mbk:
11593	case VFMSUB213PSZ256mbkz:
11594	case VFMSUB213PSZ256mk:
11595	case VFMSUB213PSZ256mkz:
11596	case VFMSUB213PSZ256r:
11597	case VFMSUB213PSZ256rk:
11598	case VFMSUB213PSZ256rkz:
11599	case VFMSUB213PSZm:
11600	case VFMSUB213PSZmb:
11601	case VFMSUB213PSZmbk:
11602	case VFMSUB213PSZmbkz:
11603	case VFMSUB213PSZmk:
11604	case VFMSUB213PSZmkz:
11605	case VFMSUB213PSZr:
11606	case VFMSUB213PSZrb:
11607	case VFMSUB213PSZrbk:
11608	case VFMSUB213PSZrbkz:
11609	case VFMSUB213PSZrk:
11610	case VFMSUB213PSZrkz:
11611	case VFMSUB213PSm:
11612	case VFMSUB213PSr:
11613		return true;
11614	}
11615	return false;
11616}
11617
11618bool isVRSQRT14SD(unsigned Opcode) {
11619	switch (Opcode) {
11620	case VRSQRT14SDZrm:
11621	case VRSQRT14SDZrmk:
11622	case VRSQRT14SDZrmkz:
11623	case VRSQRT14SDZrr:
11624	case VRSQRT14SDZrrk:
11625	case VRSQRT14SDZrrkz:
11626		return true;
11627	}
11628	return false;
11629}
11630
11631bool isCVTTPS2PI(unsigned Opcode) {
11632	switch (Opcode) {
11633	case MMX_CVTTPS2PIrm:
11634	case MMX_CVTTPS2PIrr:
11635		return true;
11636	}
11637	return false;
11638}
11639
11640bool isVMCLEAR(unsigned Opcode) {
11641	return Opcode == VMCLEARm;
11642}
11643
11644bool isVPCOMQ(unsigned Opcode) {
11645	switch (Opcode) {
11646	case VPCOMQmi:
11647	case VPCOMQri:
11648		return true;
11649	}
11650	return false;
11651}
11652
11653bool isCDQ(unsigned Opcode) {
11654	return Opcode == CDQ;
11655}
11656
11657bool isFLDL2E(unsigned Opcode) {
11658	return Opcode == FLDL2E;
11659}
11660
11661bool isVCVTPS2QQ(unsigned Opcode) {
11662	switch (Opcode) {
11663	case VCVTPS2QQZ128rm:
11664	case VCVTPS2QQZ128rmb:
11665	case VCVTPS2QQZ128rmbk:
11666	case VCVTPS2QQZ128rmbkz:
11667	case VCVTPS2QQZ128rmk:
11668	case VCVTPS2QQZ128rmkz:
11669	case VCVTPS2QQZ128rr:
11670	case VCVTPS2QQZ128rrk:
11671	case VCVTPS2QQZ128rrkz:
11672	case VCVTPS2QQZ256rm:
11673	case VCVTPS2QQZ256rmb:
11674	case VCVTPS2QQZ256rmbk:
11675	case VCVTPS2QQZ256rmbkz:
11676	case VCVTPS2QQZ256rmk:
11677	case VCVTPS2QQZ256rmkz:
11678	case VCVTPS2QQZ256rr:
11679	case VCVTPS2QQZ256rrk:
11680	case VCVTPS2QQZ256rrkz:
11681	case VCVTPS2QQZrm:
11682	case VCVTPS2QQZrmb:
11683	case VCVTPS2QQZrmbk:
11684	case VCVTPS2QQZrmbkz:
11685	case VCVTPS2QQZrmk:
11686	case VCVTPS2QQZrmkz:
11687	case VCVTPS2QQZrr:
11688	case VCVTPS2QQZrrb:
11689	case VCVTPS2QQZrrbk:
11690	case VCVTPS2QQZrrbkz:
11691	case VCVTPS2QQZrrk:
11692	case VCVTPS2QQZrrkz:
11693		return true;
11694	}
11695	return false;
11696}
11697
11698bool isVPCOMW(unsigned Opcode) {
11699	switch (Opcode) {
11700	case VPCOMWmi:
11701	case VPCOMWri:
11702		return true;
11703	}
11704	return false;
11705}
11706
11707bool isVRSQRT14SS(unsigned Opcode) {
11708	switch (Opcode) {
11709	case VRSQRT14SSZrm:
11710	case VRSQRT14SSZrmk:
11711	case VRSQRT14SSZrmkz:
11712	case VRSQRT14SSZrr:
11713	case VRSQRT14SSZrrk:
11714	case VRSQRT14SSZrrkz:
11715		return true;
11716	}
11717	return false;
11718}
11719
11720bool isVP4DPWSSDS(unsigned Opcode) {
11721	switch (Opcode) {
11722	case VP4DPWSSDSrm:
11723	case VP4DPWSSDSrmk:
11724	case VP4DPWSSDSrmkz:
11725		return true;
11726	}
11727	return false;
11728}
11729
11730bool isVPSLLDQ(unsigned Opcode) {
11731	switch (Opcode) {
11732	case VPSLLDQYri:
11733	case VPSLLDQZ128mi:
11734	case VPSLLDQZ128ri:
11735	case VPSLLDQZ256mi:
11736	case VPSLLDQZ256ri:
11737	case VPSLLDQZmi:
11738	case VPSLLDQZri:
11739	case VPSLLDQri:
11740		return true;
11741	}
11742	return false;
11743}
11744
11745bool isVCVTSD2SH(unsigned Opcode) {
11746	switch (Opcode) {
11747	case VCVTSD2SHZrm_Int:
11748	case VCVTSD2SHZrm_Intk:
11749	case VCVTSD2SHZrm_Intkz:
11750	case VCVTSD2SHZrr_Int:
11751	case VCVTSD2SHZrr_Intk:
11752	case VCVTSD2SHZrr_Intkz:
11753	case VCVTSD2SHZrrb_Int:
11754	case VCVTSD2SHZrrb_Intk:
11755	case VCVTSD2SHZrrb_Intkz:
11756		return true;
11757	}
11758	return false;
11759}
11760
11761bool isFLDL2T(unsigned Opcode) {
11762	return Opcode == FLDL2T;
11763}
11764
11765bool isVEXP2PD(unsigned Opcode) {
11766	switch (Opcode) {
11767	case VEXP2PDZm:
11768	case VEXP2PDZmb:
11769	case VEXP2PDZmbk:
11770	case VEXP2PDZmbkz:
11771	case VEXP2PDZmk:
11772	case VEXP2PDZmkz:
11773	case VEXP2PDZr:
11774	case VEXP2PDZrb:
11775	case VEXP2PDZrbk:
11776	case VEXP2PDZrbkz:
11777	case VEXP2PDZrk:
11778	case VEXP2PDZrkz:
11779		return true;
11780	}
11781	return false;
11782}
11783
11784bool isVFNMADD132PD(unsigned Opcode) {
11785	switch (Opcode) {
11786	case VFNMADD132PDYm:
11787	case VFNMADD132PDYr:
11788	case VFNMADD132PDZ128m:
11789	case VFNMADD132PDZ128mb:
11790	case VFNMADD132PDZ128mbk:
11791	case VFNMADD132PDZ128mbkz:
11792	case VFNMADD132PDZ128mk:
11793	case VFNMADD132PDZ128mkz:
11794	case VFNMADD132PDZ128r:
11795	case VFNMADD132PDZ128rk:
11796	case VFNMADD132PDZ128rkz:
11797	case VFNMADD132PDZ256m:
11798	case VFNMADD132PDZ256mb:
11799	case VFNMADD132PDZ256mbk:
11800	case VFNMADD132PDZ256mbkz:
11801	case VFNMADD132PDZ256mk:
11802	case VFNMADD132PDZ256mkz:
11803	case VFNMADD132PDZ256r:
11804	case VFNMADD132PDZ256rk:
11805	case VFNMADD132PDZ256rkz:
11806	case VFNMADD132PDZm:
11807	case VFNMADD132PDZmb:
11808	case VFNMADD132PDZmbk:
11809	case VFNMADD132PDZmbkz:
11810	case VFNMADD132PDZmk:
11811	case VFNMADD132PDZmkz:
11812	case VFNMADD132PDZr:
11813	case VFNMADD132PDZrb:
11814	case VFNMADD132PDZrbk:
11815	case VFNMADD132PDZrbkz:
11816	case VFNMADD132PDZrk:
11817	case VFNMADD132PDZrkz:
11818	case VFNMADD132PDm:
11819	case VFNMADD132PDr:
11820		return true;
11821	}
11822	return false;
11823}
11824
11825bool isVCVTSD2SI(unsigned Opcode) {
11826	switch (Opcode) {
11827	case VCVTSD2SI64Zrm_Int:
11828	case VCVTSD2SI64Zrr_Int:
11829	case VCVTSD2SI64Zrrb_Int:
11830	case VCVTSD2SI64rm_Int:
11831	case VCVTSD2SI64rr_Int:
11832	case VCVTSD2SIZrm_Int:
11833	case VCVTSD2SIZrr_Int:
11834	case VCVTSD2SIZrrb_Int:
11835	case VCVTSD2SIrm_Int:
11836	case VCVTSD2SIrr_Int:
11837		return true;
11838	}
11839	return false;
11840}
11841
11842bool isVPOPCNTB(unsigned Opcode) {
11843	switch (Opcode) {
11844	case VPOPCNTBZ128rm:
11845	case VPOPCNTBZ128rmk:
11846	case VPOPCNTBZ128rmkz:
11847	case VPOPCNTBZ128rr:
11848	case VPOPCNTBZ128rrk:
11849	case VPOPCNTBZ128rrkz:
11850	case VPOPCNTBZ256rm:
11851	case VPOPCNTBZ256rmk:
11852	case VPOPCNTBZ256rmkz:
11853	case VPOPCNTBZ256rr:
11854	case VPOPCNTBZ256rrk:
11855	case VPOPCNTBZ256rrkz:
11856	case VPOPCNTBZrm:
11857	case VPOPCNTBZrmk:
11858	case VPOPCNTBZrmkz:
11859	case VPOPCNTBZrr:
11860	case VPOPCNTBZrrk:
11861	case VPOPCNTBZrrkz:
11862		return true;
11863	}
11864	return false;
11865}
11866
11867bool isVFNMADD132PH(unsigned Opcode) {
11868	switch (Opcode) {
11869	case VFNMADD132PHZ128m:
11870	case VFNMADD132PHZ128mb:
11871	case VFNMADD132PHZ128mbk:
11872	case VFNMADD132PHZ128mbkz:
11873	case VFNMADD132PHZ128mk:
11874	case VFNMADD132PHZ128mkz:
11875	case VFNMADD132PHZ128r:
11876	case VFNMADD132PHZ128rk:
11877	case VFNMADD132PHZ128rkz:
11878	case VFNMADD132PHZ256m:
11879	case VFNMADD132PHZ256mb:
11880	case VFNMADD132PHZ256mbk:
11881	case VFNMADD132PHZ256mbkz:
11882	case VFNMADD132PHZ256mk:
11883	case VFNMADD132PHZ256mkz:
11884	case VFNMADD132PHZ256r:
11885	case VFNMADD132PHZ256rk:
11886	case VFNMADD132PHZ256rkz:
11887	case VFNMADD132PHZm:
11888	case VFNMADD132PHZmb:
11889	case VFNMADD132PHZmbk:
11890	case VFNMADD132PHZmbkz:
11891	case VFNMADD132PHZmk:
11892	case VFNMADD132PHZmkz:
11893	case VFNMADD132PHZr:
11894	case VFNMADD132PHZrb:
11895	case VFNMADD132PHZrbk:
11896	case VFNMADD132PHZrbkz:
11897	case VFNMADD132PHZrk:
11898	case VFNMADD132PHZrkz:
11899		return true;
11900	}
11901	return false;
11902}
11903
11904bool isVINSERTI128(unsigned Opcode) {
11905	switch (Opcode) {
11906	case VINSERTI128rm:
11907	case VINSERTI128rr:
11908		return true;
11909	}
11910	return false;
11911}
11912
11913bool isVPOPCNTD(unsigned Opcode) {
11914	switch (Opcode) {
11915	case VPOPCNTDZ128rm:
11916	case VPOPCNTDZ128rmb:
11917	case VPOPCNTDZ128rmbk:
11918	case VPOPCNTDZ128rmbkz:
11919	case VPOPCNTDZ128rmk:
11920	case VPOPCNTDZ128rmkz:
11921	case VPOPCNTDZ128rr:
11922	case VPOPCNTDZ128rrk:
11923	case VPOPCNTDZ128rrkz:
11924	case VPOPCNTDZ256rm:
11925	case VPOPCNTDZ256rmb:
11926	case VPOPCNTDZ256rmbk:
11927	case VPOPCNTDZ256rmbkz:
11928	case VPOPCNTDZ256rmk:
11929	case VPOPCNTDZ256rmkz:
11930	case VPOPCNTDZ256rr:
11931	case VPOPCNTDZ256rrk:
11932	case VPOPCNTDZ256rrkz:
11933	case VPOPCNTDZrm:
11934	case VPOPCNTDZrmb:
11935	case VPOPCNTDZrmbk:
11936	case VPOPCNTDZrmbkz:
11937	case VPOPCNTDZrmk:
11938	case VPOPCNTDZrmkz:
11939	case VPOPCNTDZrr:
11940	case VPOPCNTDZrrk:
11941	case VPOPCNTDZrrkz:
11942		return true;
11943	}
11944	return false;
11945}
11946
11947bool isSETCC(unsigned Opcode) {
11948	switch (Opcode) {
11949	case SETCCm:
11950	case SETCCr:
11951		return true;
11952	}
11953	return false;
11954}
11955
11956bool isVCVTSD2SS(unsigned Opcode) {
11957	switch (Opcode) {
11958	case VCVTSD2SSZrm_Int:
11959	case VCVTSD2SSZrm_Intk:
11960	case VCVTSD2SSZrm_Intkz:
11961	case VCVTSD2SSZrr_Int:
11962	case VCVTSD2SSZrr_Intk:
11963	case VCVTSD2SSZrr_Intkz:
11964	case VCVTSD2SSZrrb_Int:
11965	case VCVTSD2SSZrrb_Intk:
11966	case VCVTSD2SSZrrb_Intkz:
11967	case VCVTSD2SSrm_Int:
11968	case VCVTSD2SSrr_Int:
11969		return true;
11970	}
11971	return false;
11972}
11973
11974bool isVEXP2PS(unsigned Opcode) {
11975	switch (Opcode) {
11976	case VEXP2PSZm:
11977	case VEXP2PSZmb:
11978	case VEXP2PSZmbk:
11979	case VEXP2PSZmbkz:
11980	case VEXP2PSZmk:
11981	case VEXP2PSZmkz:
11982	case VEXP2PSZr:
11983	case VEXP2PSZrb:
11984	case VEXP2PSZrbk:
11985	case VEXP2PSZrbkz:
11986	case VEXP2PSZrk:
11987	case VEXP2PSZrkz:
11988		return true;
11989	}
11990	return false;
11991}
11992
11993bool isVFNMADD132PS(unsigned Opcode) {
11994	switch (Opcode) {
11995	case VFNMADD132PSYm:
11996	case VFNMADD132PSYr:
11997	case VFNMADD132PSZ128m:
11998	case VFNMADD132PSZ128mb:
11999	case VFNMADD132PSZ128mbk:
12000	case VFNMADD132PSZ128mbkz:
12001	case VFNMADD132PSZ128mk:
12002	case VFNMADD132PSZ128mkz:
12003	case VFNMADD132PSZ128r:
12004	case VFNMADD132PSZ128rk:
12005	case VFNMADD132PSZ128rkz:
12006	case VFNMADD132PSZ256m:
12007	case VFNMADD132PSZ256mb:
12008	case VFNMADD132PSZ256mbk:
12009	case VFNMADD132PSZ256mbkz:
12010	case VFNMADD132PSZ256mk:
12011	case VFNMADD132PSZ256mkz:
12012	case VFNMADD132PSZ256r:
12013	case VFNMADD132PSZ256rk:
12014	case VFNMADD132PSZ256rkz:
12015	case VFNMADD132PSZm:
12016	case VFNMADD132PSZmb:
12017	case VFNMADD132PSZmbk:
12018	case VFNMADD132PSZmbkz:
12019	case VFNMADD132PSZmk:
12020	case VFNMADD132PSZmkz:
12021	case VFNMADD132PSZr:
12022	case VFNMADD132PSZrb:
12023	case VFNMADD132PSZrbk:
12024	case VFNMADD132PSZrbkz:
12025	case VFNMADD132PSZrk:
12026	case VFNMADD132PSZrkz:
12027	case VFNMADD132PSm:
12028	case VFNMADD132PSr:
12029		return true;
12030	}
12031	return false;
12032}
12033
12034bool isMOVDIRI(unsigned Opcode) {
12035	switch (Opcode) {
12036	case MOVDIRI32:
12037	case MOVDIRI64:
12038		return true;
12039	}
12040	return false;
12041}
12042
12043bool isVPOPCNTQ(unsigned Opcode) {
12044	switch (Opcode) {
12045	case VPOPCNTQZ128rm:
12046	case VPOPCNTQZ128rmb:
12047	case VPOPCNTQZ128rmbk:
12048	case VPOPCNTQZ128rmbkz:
12049	case VPOPCNTQZ128rmk:
12050	case VPOPCNTQZ128rmkz:
12051	case VPOPCNTQZ128rr:
12052	case VPOPCNTQZ128rrk:
12053	case VPOPCNTQZ128rrkz:
12054	case VPOPCNTQZ256rm:
12055	case VPOPCNTQZ256rmb:
12056	case VPOPCNTQZ256rmbk:
12057	case VPOPCNTQZ256rmbkz:
12058	case VPOPCNTQZ256rmk:
12059	case VPOPCNTQZ256rmkz:
12060	case VPOPCNTQZ256rr:
12061	case VPOPCNTQZ256rrk:
12062	case VPOPCNTQZ256rrkz:
12063	case VPOPCNTQZrm:
12064	case VPOPCNTQZrmb:
12065	case VPOPCNTQZrmbk:
12066	case VPOPCNTQZrmbkz:
12067	case VPOPCNTQZrmk:
12068	case VPOPCNTQZrmkz:
12069	case VPOPCNTQZrr:
12070	case VPOPCNTQZrrk:
12071	case VPOPCNTQZrrkz:
12072		return true;
12073	}
12074	return false;
12075}
12076
12077bool isVFMSUB231PD(unsigned Opcode) {
12078	switch (Opcode) {
12079	case VFMSUB231PDYm:
12080	case VFMSUB231PDYr:
12081	case VFMSUB231PDZ128m:
12082	case VFMSUB231PDZ128mb:
12083	case VFMSUB231PDZ128mbk:
12084	case VFMSUB231PDZ128mbkz:
12085	case VFMSUB231PDZ128mk:
12086	case VFMSUB231PDZ128mkz:
12087	case VFMSUB231PDZ128r:
12088	case VFMSUB231PDZ128rk:
12089	case VFMSUB231PDZ128rkz:
12090	case VFMSUB231PDZ256m:
12091	case VFMSUB231PDZ256mb:
12092	case VFMSUB231PDZ256mbk:
12093	case VFMSUB231PDZ256mbkz:
12094	case VFMSUB231PDZ256mk:
12095	case VFMSUB231PDZ256mkz:
12096	case VFMSUB231PDZ256r:
12097	case VFMSUB231PDZ256rk:
12098	case VFMSUB231PDZ256rkz:
12099	case VFMSUB231PDZm:
12100	case VFMSUB231PDZmb:
12101	case VFMSUB231PDZmbk:
12102	case VFMSUB231PDZmbkz:
12103	case VFMSUB231PDZmk:
12104	case VFMSUB231PDZmkz:
12105	case VFMSUB231PDZr:
12106	case VFMSUB231PDZrb:
12107	case VFMSUB231PDZrbk:
12108	case VFMSUB231PDZrbkz:
12109	case VFMSUB231PDZrk:
12110	case VFMSUB231PDZrkz:
12111	case VFMSUB231PDm:
12112	case VFMSUB231PDr:
12113		return true;
12114	}
12115	return false;
12116}
12117
12118bool isVFMSUB231PH(unsigned Opcode) {
12119	switch (Opcode) {
12120	case VFMSUB231PHZ128m:
12121	case VFMSUB231PHZ128mb:
12122	case VFMSUB231PHZ128mbk:
12123	case VFMSUB231PHZ128mbkz:
12124	case VFMSUB231PHZ128mk:
12125	case VFMSUB231PHZ128mkz:
12126	case VFMSUB231PHZ128r:
12127	case VFMSUB231PHZ128rk:
12128	case VFMSUB231PHZ128rkz:
12129	case VFMSUB231PHZ256m:
12130	case VFMSUB231PHZ256mb:
12131	case VFMSUB231PHZ256mbk:
12132	case VFMSUB231PHZ256mbkz:
12133	case VFMSUB231PHZ256mk:
12134	case VFMSUB231PHZ256mkz:
12135	case VFMSUB231PHZ256r:
12136	case VFMSUB231PHZ256rk:
12137	case VFMSUB231PHZ256rkz:
12138	case VFMSUB231PHZm:
12139	case VFMSUB231PHZmb:
12140	case VFMSUB231PHZmbk:
12141	case VFMSUB231PHZmbkz:
12142	case VFMSUB231PHZmk:
12143	case VFMSUB231PHZmkz:
12144	case VFMSUB231PHZr:
12145	case VFMSUB231PHZrb:
12146	case VFMSUB231PHZrbk:
12147	case VFMSUB231PHZrbkz:
12148	case VFMSUB231PHZrk:
12149	case VFMSUB231PHZrkz:
12150		return true;
12151	}
12152	return false;
12153}
12154
12155bool isFCMOVBE(unsigned Opcode) {
12156	return Opcode == CMOVBE_F;
12157}
12158
12159bool isVPOPCNTW(unsigned Opcode) {
12160	switch (Opcode) {
12161	case VPOPCNTWZ128rm:
12162	case VPOPCNTWZ128rmk:
12163	case VPOPCNTWZ128rmkz:
12164	case VPOPCNTWZ128rr:
12165	case VPOPCNTWZ128rrk:
12166	case VPOPCNTWZ128rrkz:
12167	case VPOPCNTWZ256rm:
12168	case VPOPCNTWZ256rmk:
12169	case VPOPCNTWZ256rmkz:
12170	case VPOPCNTWZ256rr:
12171	case VPOPCNTWZ256rrk:
12172	case VPOPCNTWZ256rrkz:
12173	case VPOPCNTWZrm:
12174	case VPOPCNTWZrmk:
12175	case VPOPCNTWZrmkz:
12176	case VPOPCNTWZrr:
12177	case VPOPCNTWZrrk:
12178	case VPOPCNTWZrrkz:
12179		return true;
12180	}
12181	return false;
12182}
12183
12184bool isCVTTSD2SI(unsigned Opcode) {
12185	switch (Opcode) {
12186	case CVTTSD2SI64rm_Int:
12187	case CVTTSD2SI64rr_Int:
12188	case CVTTSD2SIrm_Int:
12189	case CVTTSD2SIrr_Int:
12190		return true;
12191	}
12192	return false;
12193}
12194
12195bool isVFMSUB231PS(unsigned Opcode) {
12196	switch (Opcode) {
12197	case VFMSUB231PSYm:
12198	case VFMSUB231PSYr:
12199	case VFMSUB231PSZ128m:
12200	case VFMSUB231PSZ128mb:
12201	case VFMSUB231PSZ128mbk:
12202	case VFMSUB231PSZ128mbkz:
12203	case VFMSUB231PSZ128mk:
12204	case VFMSUB231PSZ128mkz:
12205	case VFMSUB231PSZ128r:
12206	case VFMSUB231PSZ128rk:
12207	case VFMSUB231PSZ128rkz:
12208	case VFMSUB231PSZ256m:
12209	case VFMSUB231PSZ256mb:
12210	case VFMSUB231PSZ256mbk:
12211	case VFMSUB231PSZ256mbkz:
12212	case VFMSUB231PSZ256mk:
12213	case VFMSUB231PSZ256mkz:
12214	case VFMSUB231PSZ256r:
12215	case VFMSUB231PSZ256rk:
12216	case VFMSUB231PSZ256rkz:
12217	case VFMSUB231PSZm:
12218	case VFMSUB231PSZmb:
12219	case VFMSUB231PSZmbk:
12220	case VFMSUB231PSZmbkz:
12221	case VFMSUB231PSZmk:
12222	case VFMSUB231PSZmkz:
12223	case VFMSUB231PSZr:
12224	case VFMSUB231PSZrb:
12225	case VFMSUB231PSZrbk:
12226	case VFMSUB231PSZrbkz:
12227	case VFMSUB231PSZrk:
12228	case VFMSUB231PSZrkz:
12229	case VFMSUB231PSm:
12230	case VFMSUB231PSr:
12231		return true;
12232	}
12233	return false;
12234}
12235
12236bool isNOP(unsigned Opcode) {
12237	switch (Opcode) {
12238	case NOOP:
12239	case NOOPL:
12240	case NOOPLr:
12241	case NOOPQ:
12242	case NOOPQr:
12243	case NOOPW:
12244	case NOOPWr:
12245		return true;
12246	}
12247	return false;
12248}
12249
12250bool isNOT(unsigned Opcode) {
12251	switch (Opcode) {
12252	case NOT16m:
12253	case NOT16r:
12254	case NOT32m:
12255	case NOT32r:
12256	case NOT64m:
12257	case NOT64r:
12258	case NOT8m:
12259	case NOT8r:
12260		return true;
12261	}
12262	return false;
12263}
12264
12265bool isTPAUSE(unsigned Opcode) {
12266	return Opcode == TPAUSE;
12267}
12268
12269bool isVCVTNEPS2BF16(unsigned Opcode) {
12270	switch (Opcode) {
12271	case VCVTNEPS2BF16Yrm:
12272	case VCVTNEPS2BF16Yrr:
12273	case VCVTNEPS2BF16Z128rm:
12274	case VCVTNEPS2BF16Z128rmb:
12275	case VCVTNEPS2BF16Z128rmbk:
12276	case VCVTNEPS2BF16Z128rmbkz:
12277	case VCVTNEPS2BF16Z128rmk:
12278	case VCVTNEPS2BF16Z128rmkz:
12279	case VCVTNEPS2BF16Z128rr:
12280	case VCVTNEPS2BF16Z128rrk:
12281	case VCVTNEPS2BF16Z128rrkz:
12282	case VCVTNEPS2BF16Z256rm:
12283	case VCVTNEPS2BF16Z256rmb:
12284	case VCVTNEPS2BF16Z256rmbk:
12285	case VCVTNEPS2BF16Z256rmbkz:
12286	case VCVTNEPS2BF16Z256rmk:
12287	case VCVTNEPS2BF16Z256rmkz:
12288	case VCVTNEPS2BF16Z256rr:
12289	case VCVTNEPS2BF16Z256rrk:
12290	case VCVTNEPS2BF16Z256rrkz:
12291	case VCVTNEPS2BF16Zrm:
12292	case VCVTNEPS2BF16Zrmb:
12293	case VCVTNEPS2BF16Zrmbk:
12294	case VCVTNEPS2BF16Zrmbkz:
12295	case VCVTNEPS2BF16Zrmk:
12296	case VCVTNEPS2BF16Zrmkz:
12297	case VCVTNEPS2BF16Zrr:
12298	case VCVTNEPS2BF16Zrrk:
12299	case VCVTNEPS2BF16Zrrkz:
12300	case VCVTNEPS2BF16rm:
12301	case VCVTNEPS2BF16rr:
12302		return true;
12303	}
12304	return false;
12305}
12306
12307bool isVFMSUB213SD(unsigned Opcode) {
12308	switch (Opcode) {
12309	case VFMSUB213SDZm_Int:
12310	case VFMSUB213SDZm_Intk:
12311	case VFMSUB213SDZm_Intkz:
12312	case VFMSUB213SDZr_Int:
12313	case VFMSUB213SDZr_Intk:
12314	case VFMSUB213SDZr_Intkz:
12315	case VFMSUB213SDZrb_Int:
12316	case VFMSUB213SDZrb_Intk:
12317	case VFMSUB213SDZrb_Intkz:
12318	case VFMSUB213SDm_Int:
12319	case VFMSUB213SDr_Int:
12320		return true;
12321	}
12322	return false;
12323}
12324
12325bool isVFMSUB213SH(unsigned Opcode) {
12326	switch (Opcode) {
12327	case VFMSUB213SHZm_Int:
12328	case VFMSUB213SHZm_Intk:
12329	case VFMSUB213SHZm_Intkz:
12330	case VFMSUB213SHZr_Int:
12331	case VFMSUB213SHZr_Intk:
12332	case VFMSUB213SHZr_Intkz:
12333	case VFMSUB213SHZrb_Int:
12334	case VFMSUB213SHZrb_Intk:
12335	case VFMSUB213SHZrb_Intkz:
12336		return true;
12337	}
12338	return false;
12339}
12340
12341bool isVFMADDCPH(unsigned Opcode) {
12342	switch (Opcode) {
12343	case VFMADDCPHZ128m:
12344	case VFMADDCPHZ128mb:
12345	case VFMADDCPHZ128mbk:
12346	case VFMADDCPHZ128mbkz:
12347	case VFMADDCPHZ128mk:
12348	case VFMADDCPHZ128mkz:
12349	case VFMADDCPHZ128r:
12350	case VFMADDCPHZ128rk:
12351	case VFMADDCPHZ128rkz:
12352	case VFMADDCPHZ256m:
12353	case VFMADDCPHZ256mb:
12354	case VFMADDCPHZ256mbk:
12355	case VFMADDCPHZ256mbkz:
12356	case VFMADDCPHZ256mk:
12357	case VFMADDCPHZ256mkz:
12358	case VFMADDCPHZ256r:
12359	case VFMADDCPHZ256rk:
12360	case VFMADDCPHZ256rkz:
12361	case VFMADDCPHZm:
12362	case VFMADDCPHZmb:
12363	case VFMADDCPHZmbk:
12364	case VFMADDCPHZmbkz:
12365	case VFMADDCPHZmk:
12366	case VFMADDCPHZmkz:
12367	case VFMADDCPHZr:
12368	case VFMADDCPHZrb:
12369	case VFMADDCPHZrbk:
12370	case VFMADDCPHZrbkz:
12371	case VFMADDCPHZrk:
12372	case VFMADDCPHZrkz:
12373		return true;
12374	}
12375	return false;
12376}
12377
12378bool isVEXTRACTI64X2(unsigned Opcode) {
12379	switch (Opcode) {
12380	case VEXTRACTI64x2Z256mr:
12381	case VEXTRACTI64x2Z256mrk:
12382	case VEXTRACTI64x2Z256rr:
12383	case VEXTRACTI64x2Z256rrk:
12384	case VEXTRACTI64x2Z256rrkz:
12385	case VEXTRACTI64x2Zmr:
12386	case VEXTRACTI64x2Zmrk:
12387	case VEXTRACTI64x2Zrr:
12388	case VEXTRACTI64x2Zrrk:
12389	case VEXTRACTI64x2Zrrkz:
12390		return true;
12391	}
12392	return false;
12393}
12394
12395bool isVFMSUB213SS(unsigned Opcode) {
12396	switch (Opcode) {
12397	case VFMSUB213SSZm_Int:
12398	case VFMSUB213SSZm_Intk:
12399	case VFMSUB213SSZm_Intkz:
12400	case VFMSUB213SSZr_Int:
12401	case VFMSUB213SSZr_Intk:
12402	case VFMSUB213SSZr_Intkz:
12403	case VFMSUB213SSZrb_Int:
12404	case VFMSUB213SSZrb_Intk:
12405	case VFMSUB213SSZrb_Intkz:
12406	case VFMSUB213SSm_Int:
12407	case VFMSUB213SSr_Int:
12408		return true;
12409	}
12410	return false;
12411}
12412
12413bool isVEXTRACTI64X4(unsigned Opcode) {
12414	switch (Opcode) {
12415	case VEXTRACTI64x4Zmr:
12416	case VEXTRACTI64x4Zmrk:
12417	case VEXTRACTI64x4Zrr:
12418	case VEXTRACTI64x4Zrrk:
12419	case VEXTRACTI64x4Zrrkz:
12420		return true;
12421	}
12422	return false;
12423}
12424
12425bool isXSAVEC64(unsigned Opcode) {
12426	return Opcode == XSAVEC64;
12427}
12428
12429bool isBLCFILL(unsigned Opcode) {
12430	switch (Opcode) {
12431	case BLCFILL32rm:
12432	case BLCFILL32rr:
12433	case BLCFILL64rm:
12434	case BLCFILL64rr:
12435		return true;
12436	}
12437	return false;
12438}
12439
12440bool isXBEGIN(unsigned Opcode) {
12441	switch (Opcode) {
12442	case XBEGIN_2:
12443	case XBEGIN_4:
12444		return true;
12445	}
12446	return false;
12447}
12448
12449bool isXCRYPTOFB(unsigned Opcode) {
12450	return Opcode == XCRYPTOFB;
12451}
12452
12453bool isFUCOMI(unsigned Opcode) {
12454	return Opcode == UCOM_FIr;
12455}
12456
12457bool isVMOVHPD(unsigned Opcode) {
12458	switch (Opcode) {
12459	case VMOVHPDZ128mr:
12460	case VMOVHPDZ128rm:
12461	case VMOVHPDmr:
12462	case VMOVHPDrm:
12463		return true;
12464	}
12465	return false;
12466}
12467
12468bool isMASKMOVDQU(unsigned Opcode) {
12469	switch (Opcode) {
12470	case MASKMOVDQU:
12471	case MASKMOVDQU64:
12472		return true;
12473	}
12474	return false;
12475}
12476
12477bool isFUCOMP(unsigned Opcode) {
12478	return Opcode == UCOM_FPr;
12479}
12480
12481bool isVFNMADD132SD(unsigned Opcode) {
12482	switch (Opcode) {
12483	case VFNMADD132SDZm_Int:
12484	case VFNMADD132SDZm_Intk:
12485	case VFNMADD132SDZm_Intkz:
12486	case VFNMADD132SDZr_Int:
12487	case VFNMADD132SDZr_Intk:
12488	case VFNMADD132SDZr_Intkz:
12489	case VFNMADD132SDZrb_Int:
12490	case VFNMADD132SDZrb_Intk:
12491	case VFNMADD132SDZrb_Intkz:
12492	case VFNMADD132SDm_Int:
12493	case VFNMADD132SDr_Int:
12494		return true;
12495	}
12496	return false;
12497}
12498
12499bool isMFENCE(unsigned Opcode) {
12500	return Opcode == MFENCE;
12501}
12502
12503bool isVFNMADD132SH(unsigned Opcode) {
12504	switch (Opcode) {
12505	case VFNMADD132SHZm_Int:
12506	case VFNMADD132SHZm_Intk:
12507	case VFNMADD132SHZm_Intkz:
12508	case VFNMADD132SHZr_Int:
12509	case VFNMADD132SHZr_Intk:
12510	case VFNMADD132SHZr_Intkz:
12511	case VFNMADD132SHZrb_Int:
12512	case VFNMADD132SHZrb_Intk:
12513	case VFNMADD132SHZrb_Intkz:
12514		return true;
12515	}
12516	return false;
12517}
12518
12519bool isVMOVHPS(unsigned Opcode) {
12520	switch (Opcode) {
12521	case VMOVHPSZ128mr:
12522	case VMOVHPSZ128rm:
12523	case VMOVHPSmr:
12524	case VMOVHPSrm:
12525		return true;
12526	}
12527	return false;
12528}
12529
12530bool isVPBROADCASTMW2D(unsigned Opcode) {
12531	switch (Opcode) {
12532	case VPBROADCASTMW2DZ128rr:
12533	case VPBROADCASTMW2DZ256rr:
12534	case VPBROADCASTMW2DZrr:
12535		return true;
12536	}
12537	return false;
12538}
12539
12540bool isVFMADD213PD(unsigned Opcode) {
12541	switch (Opcode) {
12542	case VFMADD213PDYm:
12543	case VFMADD213PDYr:
12544	case VFMADD213PDZ128m:
12545	case VFMADD213PDZ128mb:
12546	case VFMADD213PDZ128mbk:
12547	case VFMADD213PDZ128mbkz:
12548	case VFMADD213PDZ128mk:
12549	case VFMADD213PDZ128mkz:
12550	case VFMADD213PDZ128r:
12551	case VFMADD213PDZ128rk:
12552	case VFMADD213PDZ128rkz:
12553	case VFMADD213PDZ256m:
12554	case VFMADD213PDZ256mb:
12555	case VFMADD213PDZ256mbk:
12556	case VFMADD213PDZ256mbkz:
12557	case VFMADD213PDZ256mk:
12558	case VFMADD213PDZ256mkz:
12559	case VFMADD213PDZ256r:
12560	case VFMADD213PDZ256rk:
12561	case VFMADD213PDZ256rkz:
12562	case VFMADD213PDZm:
12563	case VFMADD213PDZmb:
12564	case VFMADD213PDZmbk:
12565	case VFMADD213PDZmbkz:
12566	case VFMADD213PDZmk:
12567	case VFMADD213PDZmkz:
12568	case VFMADD213PDZr:
12569	case VFMADD213PDZrb:
12570	case VFMADD213PDZrbk:
12571	case VFMADD213PDZrbkz:
12572	case VFMADD213PDZrk:
12573	case VFMADD213PDZrkz:
12574	case VFMADD213PDm:
12575	case VFMADD213PDr:
12576		return true;
12577	}
12578	return false;
12579}
12580
12581bool isVFNMADD132SS(unsigned Opcode) {
12582	switch (Opcode) {
12583	case VFNMADD132SSZm_Int:
12584	case VFNMADD132SSZm_Intk:
12585	case VFNMADD132SSZm_Intkz:
12586	case VFNMADD132SSZr_Int:
12587	case VFNMADD132SSZr_Intk:
12588	case VFNMADD132SSZr_Intkz:
12589	case VFNMADD132SSZrb_Int:
12590	case VFNMADD132SSZrb_Intk:
12591	case VFNMADD132SSZrb_Intkz:
12592	case VFNMADD132SSm_Int:
12593	case VFNMADD132SSr_Int:
12594		return true;
12595	}
12596	return false;
12597}
12598
12599bool isVFMADD213PH(unsigned Opcode) {
12600	switch (Opcode) {
12601	case VFMADD213PHZ128m:
12602	case VFMADD213PHZ128mb:
12603	case VFMADD213PHZ128mbk:
12604	case VFMADD213PHZ128mbkz:
12605	case VFMADD213PHZ128mk:
12606	case VFMADD213PHZ128mkz:
12607	case VFMADD213PHZ128r:
12608	case VFMADD213PHZ128rk:
12609	case VFMADD213PHZ128rkz:
12610	case VFMADD213PHZ256m:
12611	case VFMADD213PHZ256mb:
12612	case VFMADD213PHZ256mbk:
12613	case VFMADD213PHZ256mbkz:
12614	case VFMADD213PHZ256mk:
12615	case VFMADD213PHZ256mkz:
12616	case VFMADD213PHZ256r:
12617	case VFMADD213PHZ256rk:
12618	case VFMADD213PHZ256rkz:
12619	case VFMADD213PHZm:
12620	case VFMADD213PHZmb:
12621	case VFMADD213PHZmbk:
12622	case VFMADD213PHZmbkz:
12623	case VFMADD213PHZmk:
12624	case VFMADD213PHZmkz:
12625	case VFMADD213PHZr:
12626	case VFMADD213PHZrb:
12627	case VFMADD213PHZrbk:
12628	case VFMADD213PHZrbkz:
12629	case VFMADD213PHZrk:
12630	case VFMADD213PHZrkz:
12631		return true;
12632	}
12633	return false;
12634}
12635
12636bool isVFMSUB231SD(unsigned Opcode) {
12637	switch (Opcode) {
12638	case VFMSUB231SDZm_Int:
12639	case VFMSUB231SDZm_Intk:
12640	case VFMSUB231SDZm_Intkz:
12641	case VFMSUB231SDZr_Int:
12642	case VFMSUB231SDZr_Intk:
12643	case VFMSUB231SDZr_Intkz:
12644	case VFMSUB231SDZrb_Int:
12645	case VFMSUB231SDZrb_Intk:
12646	case VFMSUB231SDZrb_Intkz:
12647	case VFMSUB231SDm_Int:
12648	case VFMSUB231SDr_Int:
12649		return true;
12650	}
12651	return false;
12652}
12653
12654bool isVPMULTISHIFTQB(unsigned Opcode) {
12655	switch (Opcode) {
12656	case VPMULTISHIFTQBZ128rm:
12657	case VPMULTISHIFTQBZ128rmb:
12658	case VPMULTISHIFTQBZ128rmbk:
12659	case VPMULTISHIFTQBZ128rmbkz:
12660	case VPMULTISHIFTQBZ128rmk:
12661	case VPMULTISHIFTQBZ128rmkz:
12662	case VPMULTISHIFTQBZ128rr:
12663	case VPMULTISHIFTQBZ128rrk:
12664	case VPMULTISHIFTQBZ128rrkz:
12665	case VPMULTISHIFTQBZ256rm:
12666	case VPMULTISHIFTQBZ256rmb:
12667	case VPMULTISHIFTQBZ256rmbk:
12668	case VPMULTISHIFTQBZ256rmbkz:
12669	case VPMULTISHIFTQBZ256rmk:
12670	case VPMULTISHIFTQBZ256rmkz:
12671	case VPMULTISHIFTQBZ256rr:
12672	case VPMULTISHIFTQBZ256rrk:
12673	case VPMULTISHIFTQBZ256rrkz:
12674	case VPMULTISHIFTQBZrm:
12675	case VPMULTISHIFTQBZrmb:
12676	case VPMULTISHIFTQBZrmbk:
12677	case VPMULTISHIFTQBZrmbkz:
12678	case VPMULTISHIFTQBZrmk:
12679	case VPMULTISHIFTQBZrmkz:
12680	case VPMULTISHIFTQBZrr:
12681	case VPMULTISHIFTQBZrrk:
12682	case VPMULTISHIFTQBZrrkz:
12683		return true;
12684	}
12685	return false;
12686}
12687
12688bool isFNSAVE(unsigned Opcode) {
12689	return Opcode == FSAVEm;
12690}
12691
12692bool isVFMSUB231SH(unsigned Opcode) {
12693	switch (Opcode) {
12694	case VFMSUB231SHZm_Int:
12695	case VFMSUB231SHZm_Intk:
12696	case VFMSUB231SHZm_Intkz:
12697	case VFMSUB231SHZr_Int:
12698	case VFMSUB231SHZr_Intk:
12699	case VFMSUB231SHZr_Intkz:
12700	case VFMSUB231SHZrb_Int:
12701	case VFMSUB231SHZrb_Intk:
12702	case VFMSUB231SHZrb_Intkz:
12703		return true;
12704	}
12705	return false;
12706}
12707
12708bool isVSHUFF32X4(unsigned Opcode) {
12709	switch (Opcode) {
12710	case VSHUFF32X4Z256rmbi:
12711	case VSHUFF32X4Z256rmbik:
12712	case VSHUFF32X4Z256rmbikz:
12713	case VSHUFF32X4Z256rmi:
12714	case VSHUFF32X4Z256rmik:
12715	case VSHUFF32X4Z256rmikz:
12716	case VSHUFF32X4Z256rri:
12717	case VSHUFF32X4Z256rrik:
12718	case VSHUFF32X4Z256rrikz:
12719	case VSHUFF32X4Zrmbi:
12720	case VSHUFF32X4Zrmbik:
12721	case VSHUFF32X4Zrmbikz:
12722	case VSHUFF32X4Zrmi:
12723	case VSHUFF32X4Zrmik:
12724	case VSHUFF32X4Zrmikz:
12725	case VSHUFF32X4Zrri:
12726	case VSHUFF32X4Zrrik:
12727	case VSHUFF32X4Zrrikz:
12728		return true;
12729	}
12730	return false;
12731}
12732
12733bool isPMOVSXWD(unsigned Opcode) {
12734	switch (Opcode) {
12735	case PMOVSXWDrm:
12736	case PMOVSXWDrr:
12737		return true;
12738	}
12739	return false;
12740}
12741
12742bool isVFMADD213PS(unsigned Opcode) {
12743	switch (Opcode) {
12744	case VFMADD213PSYm:
12745	case VFMADD213PSYr:
12746	case VFMADD213PSZ128m:
12747	case VFMADD213PSZ128mb:
12748	case VFMADD213PSZ128mbk:
12749	case VFMADD213PSZ128mbkz:
12750	case VFMADD213PSZ128mk:
12751	case VFMADD213PSZ128mkz:
12752	case VFMADD213PSZ128r:
12753	case VFMADD213PSZ128rk:
12754	case VFMADD213PSZ128rkz:
12755	case VFMADD213PSZ256m:
12756	case VFMADD213PSZ256mb:
12757	case VFMADD213PSZ256mbk:
12758	case VFMADD213PSZ256mbkz:
12759	case VFMADD213PSZ256mk:
12760	case VFMADD213PSZ256mkz:
12761	case VFMADD213PSZ256r:
12762	case VFMADD213PSZ256rk:
12763	case VFMADD213PSZ256rkz:
12764	case VFMADD213PSZm:
12765	case VFMADD213PSZmb:
12766	case VFMADD213PSZmbk:
12767	case VFMADD213PSZmbkz:
12768	case VFMADD213PSZmk:
12769	case VFMADD213PSZmkz:
12770	case VFMADD213PSZr:
12771	case VFMADD213PSZrb:
12772	case VFMADD213PSZrbk:
12773	case VFMADD213PSZrbkz:
12774	case VFMADD213PSZrk:
12775	case VFMADD213PSZrkz:
12776	case VFMADD213PSm:
12777	case VFMADD213PSr:
12778		return true;
12779	}
12780	return false;
12781}
12782
12783bool isVFMSUB231SS(unsigned Opcode) {
12784	switch (Opcode) {
12785	case VFMSUB231SSZm_Int:
12786	case VFMSUB231SSZm_Intk:
12787	case VFMSUB231SSZm_Intkz:
12788	case VFMSUB231SSZr_Int:
12789	case VFMSUB231SSZr_Intk:
12790	case VFMSUB231SSZr_Intkz:
12791	case VFMSUB231SSZrb_Int:
12792	case VFMSUB231SSZrb_Intk:
12793	case VFMSUB231SSZrb_Intkz:
12794	case VFMSUB231SSm_Int:
12795	case VFMSUB231SSr_Int:
12796		return true;
12797	}
12798	return false;
12799}
12800
12801bool isVPCOMPRESSB(unsigned Opcode) {
12802	switch (Opcode) {
12803	case VPCOMPRESSBZ128mr:
12804	case VPCOMPRESSBZ128mrk:
12805	case VPCOMPRESSBZ128rr:
12806	case VPCOMPRESSBZ128rrk:
12807	case VPCOMPRESSBZ128rrkz:
12808	case VPCOMPRESSBZ256mr:
12809	case VPCOMPRESSBZ256mrk:
12810	case VPCOMPRESSBZ256rr:
12811	case VPCOMPRESSBZ256rrk:
12812	case VPCOMPRESSBZ256rrkz:
12813	case VPCOMPRESSBZmr:
12814	case VPCOMPRESSBZmrk:
12815	case VPCOMPRESSBZrr:
12816	case VPCOMPRESSBZrrk:
12817	case VPCOMPRESSBZrrkz:
12818		return true;
12819	}
12820	return false;
12821}
12822
12823bool isPMOVSXWQ(unsigned Opcode) {
12824	switch (Opcode) {
12825	case PMOVSXWQrm:
12826	case PMOVSXWQrr:
12827		return true;
12828	}
12829	return false;
12830}
12831
12832bool isVPCOMPRESSD(unsigned Opcode) {
12833	switch (Opcode) {
12834	case VPCOMPRESSDZ128mr:
12835	case VPCOMPRESSDZ128mrk:
12836	case VPCOMPRESSDZ128rr:
12837	case VPCOMPRESSDZ128rrk:
12838	case VPCOMPRESSDZ128rrkz:
12839	case VPCOMPRESSDZ256mr:
12840	case VPCOMPRESSDZ256mrk:
12841	case VPCOMPRESSDZ256rr:
12842	case VPCOMPRESSDZ256rrk:
12843	case VPCOMPRESSDZ256rrkz:
12844	case VPCOMPRESSDZmr:
12845	case VPCOMPRESSDZmrk:
12846	case VPCOMPRESSDZrr:
12847	case VPCOMPRESSDZrrk:
12848	case VPCOMPRESSDZrrkz:
12849		return true;
12850	}
12851	return false;
12852}
12853
12854bool isVPABSB(unsigned Opcode) {
12855	switch (Opcode) {
12856	case VPABSBYrm:
12857	case VPABSBYrr:
12858	case VPABSBZ128rm:
12859	case VPABSBZ128rmk:
12860	case VPABSBZ128rmkz:
12861	case VPABSBZ128rr:
12862	case VPABSBZ128rrk:
12863	case VPABSBZ128rrkz:
12864	case VPABSBZ256rm:
12865	case VPABSBZ256rmk:
12866	case VPABSBZ256rmkz:
12867	case VPABSBZ256rr:
12868	case VPABSBZ256rrk:
12869	case VPABSBZ256rrkz:
12870	case VPABSBZrm:
12871	case VPABSBZrmk:
12872	case VPABSBZrmkz:
12873	case VPABSBZrr:
12874	case VPABSBZrrk:
12875	case VPABSBZrrkz:
12876	case VPABSBrm:
12877	case VPABSBrr:
12878		return true;
12879	}
12880	return false;
12881}
12882
12883bool isVMOVNTDQA(unsigned Opcode) {
12884	switch (Opcode) {
12885	case VMOVNTDQAYrm:
12886	case VMOVNTDQAZ128rm:
12887	case VMOVNTDQAZ256rm:
12888	case VMOVNTDQAZrm:
12889	case VMOVNTDQArm:
12890		return true;
12891	}
12892	return false;
12893}
12894
12895bool isVPABSD(unsigned Opcode) {
12896	switch (Opcode) {
12897	case VPABSDYrm:
12898	case VPABSDYrr:
12899	case VPABSDZ128rm:
12900	case VPABSDZ128rmb:
12901	case VPABSDZ128rmbk:
12902	case VPABSDZ128rmbkz:
12903	case VPABSDZ128rmk:
12904	case VPABSDZ128rmkz:
12905	case VPABSDZ128rr:
12906	case VPABSDZ128rrk:
12907	case VPABSDZ128rrkz:
12908	case VPABSDZ256rm:
12909	case VPABSDZ256rmb:
12910	case VPABSDZ256rmbk:
12911	case VPABSDZ256rmbkz:
12912	case VPABSDZ256rmk:
12913	case VPABSDZ256rmkz:
12914	case VPABSDZ256rr:
12915	case VPABSDZ256rrk:
12916	case VPABSDZ256rrkz:
12917	case VPABSDZrm:
12918	case VPABSDZrmb:
12919	case VPABSDZrmbk:
12920	case VPABSDZrmbkz:
12921	case VPABSDZrmk:
12922	case VPABSDZrmkz:
12923	case VPABSDZrr:
12924	case VPABSDZrrk:
12925	case VPABSDZrrkz:
12926	case VPABSDrm:
12927	case VPABSDrr:
12928		return true;
12929	}
12930	return false;
12931}
12932
12933bool isVPCOMPRESSQ(unsigned Opcode) {
12934	switch (Opcode) {
12935	case VPCOMPRESSQZ128mr:
12936	case VPCOMPRESSQZ128mrk:
12937	case VPCOMPRESSQZ128rr:
12938	case VPCOMPRESSQZ128rrk:
12939	case VPCOMPRESSQZ128rrkz:
12940	case VPCOMPRESSQZ256mr:
12941	case VPCOMPRESSQZ256mrk:
12942	case VPCOMPRESSQZ256rr:
12943	case VPCOMPRESSQZ256rrk:
12944	case VPCOMPRESSQZ256rrkz:
12945	case VPCOMPRESSQZmr:
12946	case VPCOMPRESSQZmrk:
12947	case VPCOMPRESSQZrr:
12948	case VPCOMPRESSQZrrk:
12949	case VPCOMPRESSQZrrkz:
12950		return true;
12951	}
12952	return false;
12953}
12954
12955bool isVINSERTI64X2(unsigned Opcode) {
12956	switch (Opcode) {
12957	case VINSERTI64x2Z256rm:
12958	case VINSERTI64x2Z256rmk:
12959	case VINSERTI64x2Z256rmkz:
12960	case VINSERTI64x2Z256rr:
12961	case VINSERTI64x2Z256rrk:
12962	case VINSERTI64x2Z256rrkz:
12963	case VINSERTI64x2Zrm:
12964	case VINSERTI64x2Zrmk:
12965	case VINSERTI64x2Zrmkz:
12966	case VINSERTI64x2Zrr:
12967	case VINSERTI64x2Zrrk:
12968	case VINSERTI64x2Zrrkz:
12969		return true;
12970	}
12971	return false;
12972}
12973
12974bool isVPCOMPRESSW(unsigned Opcode) {
12975	switch (Opcode) {
12976	case VPCOMPRESSWZ128mr:
12977	case VPCOMPRESSWZ128mrk:
12978	case VPCOMPRESSWZ128rr:
12979	case VPCOMPRESSWZ128rrk:
12980	case VPCOMPRESSWZ128rrkz:
12981	case VPCOMPRESSWZ256mr:
12982	case VPCOMPRESSWZ256mrk:
12983	case VPCOMPRESSWZ256rr:
12984	case VPCOMPRESSWZ256rrk:
12985	case VPCOMPRESSWZ256rrkz:
12986	case VPCOMPRESSWZmr:
12987	case VPCOMPRESSWZmrk:
12988	case VPCOMPRESSWZrr:
12989	case VPCOMPRESSWZrrk:
12990	case VPCOMPRESSWZrrkz:
12991		return true;
12992	}
12993	return false;
12994}
12995
12996bool isVINSERTI64X4(unsigned Opcode) {
12997	switch (Opcode) {
12998	case VINSERTI64x4Zrm:
12999	case VINSERTI64x4Zrmk:
13000	case VINSERTI64x4Zrmkz:
13001	case VINSERTI64x4Zrr:
13002	case VINSERTI64x4Zrrk:
13003	case VINSERTI64x4Zrrkz:
13004		return true;
13005	}
13006	return false;
13007}
13008
13009bool isVPABSQ(unsigned Opcode) {
13010	switch (Opcode) {
13011	case VPABSQZ128rm:
13012	case VPABSQZ128rmb:
13013	case VPABSQZ128rmbk:
13014	case VPABSQZ128rmbkz:
13015	case VPABSQZ128rmk:
13016	case VPABSQZ128rmkz:
13017	case VPABSQZ128rr:
13018	case VPABSQZ128rrk:
13019	case VPABSQZ128rrkz:
13020	case VPABSQZ256rm:
13021	case VPABSQZ256rmb:
13022	case VPABSQZ256rmbk:
13023	case VPABSQZ256rmbkz:
13024	case VPABSQZ256rmk:
13025	case VPABSQZ256rmkz:
13026	case VPABSQZ256rr:
13027	case VPABSQZ256rrk:
13028	case VPABSQZ256rrkz:
13029	case VPABSQZrm:
13030	case VPABSQZrmb:
13031	case VPABSQZrmbk:
13032	case VPABSQZrmbkz:
13033	case VPABSQZrmk:
13034	case VPABSQZrmkz:
13035	case VPABSQZrr:
13036	case VPABSQZrrk:
13037	case VPABSQZrrkz:
13038		return true;
13039	}
13040	return false;
13041}
13042
13043bool isVFMADDCSH(unsigned Opcode) {
13044	switch (Opcode) {
13045	case VFMADDCSHZm:
13046	case VFMADDCSHZmk:
13047	case VFMADDCSHZmkz:
13048	case VFMADDCSHZr:
13049	case VFMADDCSHZrb:
13050	case VFMADDCSHZrbk:
13051	case VFMADDCSHZrbkz:
13052	case VFMADDCSHZrk:
13053	case VFMADDCSHZrkz:
13054		return true;
13055	}
13056	return false;
13057}
13058
13059bool isVPABSW(unsigned Opcode) {
13060	switch (Opcode) {
13061	case VPABSWYrm:
13062	case VPABSWYrr:
13063	case VPABSWZ128rm:
13064	case VPABSWZ128rmk:
13065	case VPABSWZ128rmkz:
13066	case VPABSWZ128rr:
13067	case VPABSWZ128rrk:
13068	case VPABSWZ128rrkz:
13069	case VPABSWZ256rm:
13070	case VPABSWZ256rmk:
13071	case VPABSWZ256rmkz:
13072	case VPABSWZ256rr:
13073	case VPABSWZ256rrk:
13074	case VPABSWZ256rrkz:
13075	case VPABSWZrm:
13076	case VPABSWZrmk:
13077	case VPABSWZrmkz:
13078	case VPABSWZrr:
13079	case VPABSWZrrk:
13080	case VPABSWZrrkz:
13081	case VPABSWrm:
13082	case VPABSWrr:
13083		return true;
13084	}
13085	return false;
13086}
13087
13088bool isPVALIDATE(unsigned Opcode) {
13089	switch (Opcode) {
13090	case PVALIDATE32:
13091	case PVALIDATE64:
13092		return true;
13093	}
13094	return false;
13095}
13096
13097bool isVFMADD231PD(unsigned Opcode) {
13098	switch (Opcode) {
13099	case VFMADD231PDYm:
13100	case VFMADD231PDYr:
13101	case VFMADD231PDZ128m:
13102	case VFMADD231PDZ128mb:
13103	case VFMADD231PDZ128mbk:
13104	case VFMADD231PDZ128mbkz:
13105	case VFMADD231PDZ128mk:
13106	case VFMADD231PDZ128mkz:
13107	case VFMADD231PDZ128r:
13108	case VFMADD231PDZ128rk:
13109	case VFMADD231PDZ128rkz:
13110	case VFMADD231PDZ256m:
13111	case VFMADD231PDZ256mb:
13112	case VFMADD231PDZ256mbk:
13113	case VFMADD231PDZ256mbkz:
13114	case VFMADD231PDZ256mk:
13115	case VFMADD231PDZ256mkz:
13116	case VFMADD231PDZ256r:
13117	case VFMADD231PDZ256rk:
13118	case VFMADD231PDZ256rkz:
13119	case VFMADD231PDZm:
13120	case VFMADD231PDZmb:
13121	case VFMADD231PDZmbk:
13122	case VFMADD231PDZmbkz:
13123	case VFMADD231PDZmk:
13124	case VFMADD231PDZmkz:
13125	case VFMADD231PDZr:
13126	case VFMADD231PDZrb:
13127	case VFMADD231PDZrbk:
13128	case VFMADD231PDZrbkz:
13129	case VFMADD231PDZrk:
13130	case VFMADD231PDZrkz:
13131	case VFMADD231PDm:
13132	case VFMADD231PDr:
13133		return true;
13134	}
13135	return false;
13136}
13137
13138bool isVFMADD231PH(unsigned Opcode) {
13139	switch (Opcode) {
13140	case VFMADD231PHZ128m:
13141	case VFMADD231PHZ128mb:
13142	case VFMADD231PHZ128mbk:
13143	case VFMADD231PHZ128mbkz:
13144	case VFMADD231PHZ128mk:
13145	case VFMADD231PHZ128mkz:
13146	case VFMADD231PHZ128r:
13147	case VFMADD231PHZ128rk:
13148	case VFMADD231PHZ128rkz:
13149	case VFMADD231PHZ256m:
13150	case VFMADD231PHZ256mb:
13151	case VFMADD231PHZ256mbk:
13152	case VFMADD231PHZ256mbkz:
13153	case VFMADD231PHZ256mk:
13154	case VFMADD231PHZ256mkz:
13155	case VFMADD231PHZ256r:
13156	case VFMADD231PHZ256rk:
13157	case VFMADD231PHZ256rkz:
13158	case VFMADD231PHZm:
13159	case VFMADD231PHZmb:
13160	case VFMADD231PHZmbk:
13161	case VFMADD231PHZmbkz:
13162	case VFMADD231PHZmk:
13163	case VFMADD231PHZmkz:
13164	case VFMADD231PHZr:
13165	case VFMADD231PHZrb:
13166	case VFMADD231PHZrbk:
13167	case VFMADD231PHZrbkz:
13168	case VFMADD231PHZrk:
13169	case VFMADD231PHZrkz:
13170		return true;
13171	}
13172	return false;
13173}
13174
13175bool isPUNPCKLQDQ(unsigned Opcode) {
13176	switch (Opcode) {
13177	case PUNPCKLQDQrm:
13178	case PUNPCKLQDQrr:
13179		return true;
13180	}
13181	return false;
13182}
13183
13184bool isVCVTNEEPH2PS(unsigned Opcode) {
13185	switch (Opcode) {
13186	case VCVTNEEPH2PSYrm:
13187	case VCVTNEEPH2PSrm:
13188		return true;
13189	}
13190	return false;
13191}
13192
13193bool isVFMADD231PS(unsigned Opcode) {
13194	switch (Opcode) {
13195	case VFMADD231PSYm:
13196	case VFMADD231PSYr:
13197	case VFMADD231PSZ128m:
13198	case VFMADD231PSZ128mb:
13199	case VFMADD231PSZ128mbk:
13200	case VFMADD231PSZ128mbkz:
13201	case VFMADD231PSZ128mk:
13202	case VFMADD231PSZ128mkz:
13203	case VFMADD231PSZ128r:
13204	case VFMADD231PSZ128rk:
13205	case VFMADD231PSZ128rkz:
13206	case VFMADD231PSZ256m:
13207	case VFMADD231PSZ256mb:
13208	case VFMADD231PSZ256mbk:
13209	case VFMADD231PSZ256mbkz:
13210	case VFMADD231PSZ256mk:
13211	case VFMADD231PSZ256mkz:
13212	case VFMADD231PSZ256r:
13213	case VFMADD231PSZ256rk:
13214	case VFMADD231PSZ256rkz:
13215	case VFMADD231PSZm:
13216	case VFMADD231PSZmb:
13217	case VFMADD231PSZmbk:
13218	case VFMADD231PSZmbkz:
13219	case VFMADD231PSZmk:
13220	case VFMADD231PSZmkz:
13221	case VFMADD231PSZr:
13222	case VFMADD231PSZrb:
13223	case VFMADD231PSZrbk:
13224	case VFMADD231PSZrbkz:
13225	case VFMADD231PSZrk:
13226	case VFMADD231PSZrkz:
13227	case VFMADD231PSm:
13228	case VFMADD231PSr:
13229		return true;
13230	}
13231	return false;
13232}
13233
13234bool isAESENCWIDE256KL(unsigned Opcode) {
13235	return Opcode == AESENCWIDE256KL;
13236}
13237
13238bool isVGF2P8MULB(unsigned Opcode) {
13239	switch (Opcode) {
13240	case VGF2P8MULBYrm:
13241	case VGF2P8MULBYrr:
13242	case VGF2P8MULBZ128rm:
13243	case VGF2P8MULBZ128rmk:
13244	case VGF2P8MULBZ128rmkz:
13245	case VGF2P8MULBZ128rr:
13246	case VGF2P8MULBZ128rrk:
13247	case VGF2P8MULBZ128rrkz:
13248	case VGF2P8MULBZ256rm:
13249	case VGF2P8MULBZ256rmk:
13250	case VGF2P8MULBZ256rmkz:
13251	case VGF2P8MULBZ256rr:
13252	case VGF2P8MULBZ256rrk:
13253	case VGF2P8MULBZ256rrkz:
13254	case VGF2P8MULBZrm:
13255	case VGF2P8MULBZrmk:
13256	case VGF2P8MULBZrmkz:
13257	case VGF2P8MULBZrr:
13258	case VGF2P8MULBZrrk:
13259	case VGF2P8MULBZrrkz:
13260	case VGF2P8MULBrm:
13261	case VGF2P8MULBrr:
13262		return true;
13263	}
13264	return false;
13265}
13266
13267bool isWRSSD(unsigned Opcode) {
13268	return Opcode == WRSSD;
13269}
13270
13271bool isMOVSHDUP(unsigned Opcode) {
13272	switch (Opcode) {
13273	case MOVSHDUPrm:
13274	case MOVSHDUPrr:
13275		return true;
13276	}
13277	return false;
13278}
13279
13280bool isTZMSK(unsigned Opcode) {
13281	switch (Opcode) {
13282	case TZMSK32rm:
13283	case TZMSK32rr:
13284	case TZMSK64rm:
13285	case TZMSK64rr:
13286		return true;
13287	}
13288	return false;
13289}
13290
13291bool isFPATAN(unsigned Opcode) {
13292	return Opcode == FPATAN;
13293}
13294
13295bool isFUCOM(unsigned Opcode) {
13296	return Opcode == UCOM_Fr;
13297}
13298
13299bool isVFMADD213SD(unsigned Opcode) {
13300	switch (Opcode) {
13301	case VFMADD213SDZm_Int:
13302	case VFMADD213SDZm_Intk:
13303	case VFMADD213SDZm_Intkz:
13304	case VFMADD213SDZr_Int:
13305	case VFMADD213SDZr_Intk:
13306	case VFMADD213SDZr_Intkz:
13307	case VFMADD213SDZrb_Int:
13308	case VFMADD213SDZrb_Intk:
13309	case VFMADD213SDZrb_Intkz:
13310	case VFMADD213SDm_Int:
13311	case VFMADD213SDr_Int:
13312		return true;
13313	}
13314	return false;
13315}
13316
13317bool isWRSSQ(unsigned Opcode) {
13318	return Opcode == WRSSQ;
13319}
13320
13321bool isVFMADD213SH(unsigned Opcode) {
13322	switch (Opcode) {
13323	case VFMADD213SHZm_Int:
13324	case VFMADD213SHZm_Intk:
13325	case VFMADD213SHZm_Intkz:
13326	case VFMADD213SHZr_Int:
13327	case VFMADD213SHZr_Intk:
13328	case VFMADD213SHZr_Intkz:
13329	case VFMADD213SHZrb_Int:
13330	case VFMADD213SHZrb_Intk:
13331	case VFMADD213SHZrb_Intkz:
13332		return true;
13333	}
13334	return false;
13335}
13336
13337bool isVPTESTNMB(unsigned Opcode) {
13338	switch (Opcode) {
13339	case VPTESTNMBZ128rm:
13340	case VPTESTNMBZ128rmk:
13341	case VPTESTNMBZ128rr:
13342	case VPTESTNMBZ128rrk:
13343	case VPTESTNMBZ256rm:
13344	case VPTESTNMBZ256rmk:
13345	case VPTESTNMBZ256rr:
13346	case VPTESTNMBZ256rrk:
13347	case VPTESTNMBZrm:
13348	case VPTESTNMBZrmk:
13349	case VPTESTNMBZrr:
13350	case VPTESTNMBZrrk:
13351		return true;
13352	}
13353	return false;
13354}
13355
13356bool isVPTESTNMD(unsigned Opcode) {
13357	switch (Opcode) {
13358	case VPTESTNMDZ128rm:
13359	case VPTESTNMDZ128rmb:
13360	case VPTESTNMDZ128rmbk:
13361	case VPTESTNMDZ128rmk:
13362	case VPTESTNMDZ128rr:
13363	case VPTESTNMDZ128rrk:
13364	case VPTESTNMDZ256rm:
13365	case VPTESTNMDZ256rmb:
13366	case VPTESTNMDZ256rmbk:
13367	case VPTESTNMDZ256rmk:
13368	case VPTESTNMDZ256rr:
13369	case VPTESTNMDZ256rrk:
13370	case VPTESTNMDZrm:
13371	case VPTESTNMDZrmb:
13372	case VPTESTNMDZrmbk:
13373	case VPTESTNMDZrmk:
13374	case VPTESTNMDZrr:
13375	case VPTESTNMDZrrk:
13376		return true;
13377	}
13378	return false;
13379}
13380
13381bool isPMULUDQ(unsigned Opcode) {
13382	switch (Opcode) {
13383	case MMX_PMULUDQrm:
13384	case MMX_PMULUDQrr:
13385	case PMULUDQrm:
13386	case PMULUDQrr:
13387		return true;
13388	}
13389	return false;
13390}
13391
13392bool isHRESET(unsigned Opcode) {
13393	return Opcode == HRESET;
13394}
13395
13396bool isPMAXSB(unsigned Opcode) {
13397	switch (Opcode) {
13398	case PMAXSBrm:
13399	case PMAXSBrr:
13400		return true;
13401	}
13402	return false;
13403}
13404
13405bool isPMAXSD(unsigned Opcode) {
13406	switch (Opcode) {
13407	case PMAXSDrm:
13408	case PMAXSDrr:
13409		return true;
13410	}
13411	return false;
13412}
13413
13414bool isVFMADD213SS(unsigned Opcode) {
13415	switch (Opcode) {
13416	case VFMADD213SSZm_Int:
13417	case VFMADD213SSZm_Intk:
13418	case VFMADD213SSZm_Intkz:
13419	case VFMADD213SSZr_Int:
13420	case VFMADD213SSZr_Intk:
13421	case VFMADD213SSZr_Intkz:
13422	case VFMADD213SSZrb_Int:
13423	case VFMADD213SSZrb_Intk:
13424	case VFMADD213SSZrb_Intkz:
13425	case VFMADD213SSm_Int:
13426	case VFMADD213SSr_Int:
13427		return true;
13428	}
13429	return false;
13430}
13431
13432bool isCLC(unsigned Opcode) {
13433	return Opcode == CLC;
13434}
13435
13436bool isCLD(unsigned Opcode) {
13437	return Opcode == CLD;
13438}
13439
13440bool isENCODEKEY256(unsigned Opcode) {
13441	return Opcode == ENCODEKEY256;
13442}
13443
13444bool isVPTESTNMQ(unsigned Opcode) {
13445	switch (Opcode) {
13446	case VPTESTNMQZ128rm:
13447	case VPTESTNMQZ128rmb:
13448	case VPTESTNMQZ128rmbk:
13449	case VPTESTNMQZ128rmk:
13450	case VPTESTNMQZ128rr:
13451	case VPTESTNMQZ128rrk:
13452	case VPTESTNMQZ256rm:
13453	case VPTESTNMQZ256rmb:
13454	case VPTESTNMQZ256rmbk:
13455	case VPTESTNMQZ256rmk:
13456	case VPTESTNMQZ256rr:
13457	case VPTESTNMQZ256rrk:
13458	case VPTESTNMQZrm:
13459	case VPTESTNMQZrmb:
13460	case VPTESTNMQZrmbk:
13461	case VPTESTNMQZrmk:
13462	case VPTESTNMQZrr:
13463	case VPTESTNMQZrrk:
13464		return true;
13465	}
13466	return false;
13467}
13468
13469bool isVGATHERQPD(unsigned Opcode) {
13470	switch (Opcode) {
13471	case VGATHERQPDYrm:
13472	case VGATHERQPDZ128rm:
13473	case VGATHERQPDZ256rm:
13474	case VGATHERQPDZrm:
13475	case VGATHERQPDrm:
13476		return true;
13477	}
13478	return false;
13479}
13480
13481bool isBOUND(unsigned Opcode) {
13482	switch (Opcode) {
13483	case BOUNDS16rm:
13484	case BOUNDS32rm:
13485		return true;
13486	}
13487	return false;
13488}
13489
13490bool isCLI(unsigned Opcode) {
13491	return Opcode == CLI;
13492}
13493
13494bool isVPTESTNMW(unsigned Opcode) {
13495	switch (Opcode) {
13496	case VPTESTNMWZ128rm:
13497	case VPTESTNMWZ128rmk:
13498	case VPTESTNMWZ128rr:
13499	case VPTESTNMWZ128rrk:
13500	case VPTESTNMWZ256rm:
13501	case VPTESTNMWZ256rmk:
13502	case VPTESTNMWZ256rr:
13503	case VPTESTNMWZ256rrk:
13504	case VPTESTNMWZrm:
13505	case VPTESTNMWZrmk:
13506	case VPTESTNMWZrr:
13507	case VPTESTNMWZrrk:
13508		return true;
13509	}
13510	return false;
13511}
13512
13513bool isPREFETCHIT0(unsigned Opcode) {
13514	return Opcode == PREFETCHIT0;
13515}
13516
13517bool isPREFETCHIT1(unsigned Opcode) {
13518	return Opcode == PREFETCHIT1;
13519}
13520
13521bool isPMAXSW(unsigned Opcode) {
13522	switch (Opcode) {
13523	case MMX_PMAXSWrm:
13524	case MMX_PMAXSWrr:
13525	case PMAXSWrm:
13526	case PMAXSWrr:
13527		return true;
13528	}
13529	return false;
13530}
13531
13532bool isPFSUB(unsigned Opcode) {
13533	switch (Opcode) {
13534	case PFSUBrm:
13535	case PFSUBrr:
13536		return true;
13537	}
13538	return false;
13539}
13540
13541bool isVCVTDQ2PH(unsigned Opcode) {
13542	switch (Opcode) {
13543	case VCVTDQ2PHZ128rm:
13544	case VCVTDQ2PHZ128rmb:
13545	case VCVTDQ2PHZ128rmbk:
13546	case VCVTDQ2PHZ128rmbkz:
13547	case VCVTDQ2PHZ128rmk:
13548	case VCVTDQ2PHZ128rmkz:
13549	case VCVTDQ2PHZ128rr:
13550	case VCVTDQ2PHZ128rrk:
13551	case VCVTDQ2PHZ128rrkz:
13552	case VCVTDQ2PHZ256rm:
13553	case VCVTDQ2PHZ256rmb:
13554	case VCVTDQ2PHZ256rmbk:
13555	case VCVTDQ2PHZ256rmbkz:
13556	case VCVTDQ2PHZ256rmk:
13557	case VCVTDQ2PHZ256rmkz:
13558	case VCVTDQ2PHZ256rr:
13559	case VCVTDQ2PHZ256rrk:
13560	case VCVTDQ2PHZ256rrkz:
13561	case VCVTDQ2PHZrm:
13562	case VCVTDQ2PHZrmb:
13563	case VCVTDQ2PHZrmbk:
13564	case VCVTDQ2PHZrmbkz:
13565	case VCVTDQ2PHZrmk:
13566	case VCVTDQ2PHZrmkz:
13567	case VCVTDQ2PHZrr:
13568	case VCVTDQ2PHZrrb:
13569	case VCVTDQ2PHZrrbk:
13570	case VCVTDQ2PHZrrbkz:
13571	case VCVTDQ2PHZrrk:
13572	case VCVTDQ2PHZrrkz:
13573		return true;
13574	}
13575	return false;
13576}
13577
13578bool isVPALIGNR(unsigned Opcode) {
13579	switch (Opcode) {
13580	case VPALIGNRYrmi:
13581	case VPALIGNRYrri:
13582	case VPALIGNRZ128rmi:
13583	case VPALIGNRZ128rmik:
13584	case VPALIGNRZ128rmikz:
13585	case VPALIGNRZ128rri:
13586	case VPALIGNRZ128rrik:
13587	case VPALIGNRZ128rrikz:
13588	case VPALIGNRZ256rmi:
13589	case VPALIGNRZ256rmik:
13590	case VPALIGNRZ256rmikz:
13591	case VPALIGNRZ256rri:
13592	case VPALIGNRZ256rrik:
13593	case VPALIGNRZ256rrikz:
13594	case VPALIGNRZrmi:
13595	case VPALIGNRZrmik:
13596	case VPALIGNRZrmikz:
13597	case VPALIGNRZrri:
13598	case VPALIGNRZrrik:
13599	case VPALIGNRZrrikz:
13600	case VPALIGNRrmi:
13601	case VPALIGNRrri:
13602		return true;
13603	}
13604	return false;
13605}
13606
13607bool isVCVTDQ2PD(unsigned Opcode) {
13608	switch (Opcode) {
13609	case VCVTDQ2PDYrm:
13610	case VCVTDQ2PDYrr:
13611	case VCVTDQ2PDZ128rm:
13612	case VCVTDQ2PDZ128rmb:
13613	case VCVTDQ2PDZ128rmbk:
13614	case VCVTDQ2PDZ128rmbkz:
13615	case VCVTDQ2PDZ128rmk:
13616	case VCVTDQ2PDZ128rmkz:
13617	case VCVTDQ2PDZ128rr:
13618	case VCVTDQ2PDZ128rrk:
13619	case VCVTDQ2PDZ128rrkz:
13620	case VCVTDQ2PDZ256rm:
13621	case VCVTDQ2PDZ256rmb:
13622	case VCVTDQ2PDZ256rmbk:
13623	case VCVTDQ2PDZ256rmbkz:
13624	case VCVTDQ2PDZ256rmk:
13625	case VCVTDQ2PDZ256rmkz:
13626	case VCVTDQ2PDZ256rr:
13627	case VCVTDQ2PDZ256rrk:
13628	case VCVTDQ2PDZ256rrkz:
13629	case VCVTDQ2PDZrm:
13630	case VCVTDQ2PDZrmb:
13631	case VCVTDQ2PDZrmbk:
13632	case VCVTDQ2PDZrmbkz:
13633	case VCVTDQ2PDZrmk:
13634	case VCVTDQ2PDZrmkz:
13635	case VCVTDQ2PDZrr:
13636	case VCVTDQ2PDZrrk:
13637	case VCVTDQ2PDZrrkz:
13638	case VCVTDQ2PDrm:
13639	case VCVTDQ2PDrr:
13640		return true;
13641	}
13642	return false;
13643}
13644
13645bool isFNSTSW(unsigned Opcode) {
13646	switch (Opcode) {
13647	case FNSTSW16r:
13648	case FNSTSWm:
13649		return true;
13650	}
13651	return false;
13652}
13653
13654bool isFISTP(unsigned Opcode) {
13655	switch (Opcode) {
13656	case IST_FP16m:
13657	case IST_FP32m:
13658	case IST_FP64m:
13659		return true;
13660	}
13661	return false;
13662}
13663
13664bool isVFMADDPD(unsigned Opcode) {
13665	switch (Opcode) {
13666	case VFMADDPD4Ymr:
13667	case VFMADDPD4Yrm:
13668	case VFMADDPD4Yrr:
13669	case VFMADDPD4Yrr_REV:
13670	case VFMADDPD4mr:
13671	case VFMADDPD4rm:
13672	case VFMADDPD4rr:
13673	case VFMADDPD4rr_REV:
13674		return true;
13675	}
13676	return false;
13677}
13678
13679bool isVGATHERQPS(unsigned Opcode) {
13680	switch (Opcode) {
13681	case VGATHERQPSYrm:
13682	case VGATHERQPSZ128rm:
13683	case VGATHERQPSZ256rm:
13684	case VGATHERQPSZrm:
13685	case VGATHERQPSrm:
13686		return true;
13687	}
13688	return false;
13689}
13690
13691bool isPBLENDW(unsigned Opcode) {
13692	switch (Opcode) {
13693	case PBLENDWrmi:
13694	case PBLENDWrri:
13695		return true;
13696	}
13697	return false;
13698}
13699
13700bool isVCVTDQ2PS(unsigned Opcode) {
13701	switch (Opcode) {
13702	case VCVTDQ2PSYrm:
13703	case VCVTDQ2PSYrr:
13704	case VCVTDQ2PSZ128rm:
13705	case VCVTDQ2PSZ128rmb:
13706	case VCVTDQ2PSZ128rmbk:
13707	case VCVTDQ2PSZ128rmbkz:
13708	case VCVTDQ2PSZ128rmk:
13709	case VCVTDQ2PSZ128rmkz:
13710	case VCVTDQ2PSZ128rr:
13711	case VCVTDQ2PSZ128rrk:
13712	case VCVTDQ2PSZ128rrkz:
13713	case VCVTDQ2PSZ256rm:
13714	case VCVTDQ2PSZ256rmb:
13715	case VCVTDQ2PSZ256rmbk:
13716	case VCVTDQ2PSZ256rmbkz:
13717	case VCVTDQ2PSZ256rmk:
13718	case VCVTDQ2PSZ256rmkz:
13719	case VCVTDQ2PSZ256rr:
13720	case VCVTDQ2PSZ256rrk:
13721	case VCVTDQ2PSZ256rrkz:
13722	case VCVTDQ2PSZrm:
13723	case VCVTDQ2PSZrmb:
13724	case VCVTDQ2PSZrmbk:
13725	case VCVTDQ2PSZrmbkz:
13726	case VCVTDQ2PSZrmk:
13727	case VCVTDQ2PSZrmkz:
13728	case VCVTDQ2PSZrr:
13729	case VCVTDQ2PSZrrb:
13730	case VCVTDQ2PSZrrbk:
13731	case VCVTDQ2PSZrrbkz:
13732	case VCVTDQ2PSZrrk:
13733	case VCVTDQ2PSZrrkz:
13734	case VCVTDQ2PSrm:
13735	case VCVTDQ2PSrr:
13736		return true;
13737	}
13738	return false;
13739}
13740
13741bool isPREFETCH(unsigned Opcode) {
13742	return Opcode == PREFETCH;
13743}
13744
13745bool isSKINIT(unsigned Opcode) {
13746	return Opcode == SKINIT;
13747}
13748
13749bool isCMC(unsigned Opcode) {
13750	return Opcode == CMC;
13751}
13752
13753bool isVFMADDPS(unsigned Opcode) {
13754	switch (Opcode) {
13755	case VFMADDPS4Ymr:
13756	case VFMADDPS4Yrm:
13757	case VFMADDPS4Yrr:
13758	case VFMADDPS4Yrr_REV:
13759	case VFMADDPS4mr:
13760	case VFMADDPS4rm:
13761	case VFMADDPS4rr:
13762	case VFMADDPS4rr_REV:
13763		return true;
13764	}
13765	return false;
13766}
13767
13768bool isVPACKSSDW(unsigned Opcode) {
13769	switch (Opcode) {
13770	case VPACKSSDWYrm:
13771	case VPACKSSDWYrr:
13772	case VPACKSSDWZ128rm:
13773	case VPACKSSDWZ128rmb:
13774	case VPACKSSDWZ128rmbk:
13775	case VPACKSSDWZ128rmbkz:
13776	case VPACKSSDWZ128rmk:
13777	case VPACKSSDWZ128rmkz:
13778	case VPACKSSDWZ128rr:
13779	case VPACKSSDWZ128rrk:
13780	case VPACKSSDWZ128rrkz:
13781	case VPACKSSDWZ256rm:
13782	case VPACKSSDWZ256rmb:
13783	case VPACKSSDWZ256rmbk:
13784	case VPACKSSDWZ256rmbkz:
13785	case VPACKSSDWZ256rmk:
13786	case VPACKSSDWZ256rmkz:
13787	case VPACKSSDWZ256rr:
13788	case VPACKSSDWZ256rrk:
13789	case VPACKSSDWZ256rrkz:
13790	case VPACKSSDWZrm:
13791	case VPACKSSDWZrmb:
13792	case VPACKSSDWZrmbk:
13793	case VPACKSSDWZrmbkz:
13794	case VPACKSSDWZrmk:
13795	case VPACKSSDWZrmkz:
13796	case VPACKSSDWZrr:
13797	case VPACKSSDWZrrk:
13798	case VPACKSSDWZrrkz:
13799	case VPACKSSDWrm:
13800	case VPACKSSDWrr:
13801		return true;
13802	}
13803	return false;
13804}
13805
13806bool isFISUB(unsigned Opcode) {
13807	switch (Opcode) {
13808	case SUB_FI16m:
13809	case SUB_FI32m:
13810		return true;
13811	}
13812	return false;
13813}
13814
13815bool isPADDB(unsigned Opcode) {
13816	switch (Opcode) {
13817	case MMX_PADDBrm:
13818	case MMX_PADDBrr:
13819	case PADDBrm:
13820	case PADDBrr:
13821		return true;
13822	}
13823	return false;
13824}
13825
13826bool isPOPAL(unsigned Opcode) {
13827	return Opcode == POPA32;
13828}
13829
13830bool isPADDD(unsigned Opcode) {
13831	switch (Opcode) {
13832	case MMX_PADDDrm:
13833	case MMX_PADDDrr:
13834	case PADDDrm:
13835	case PADDDrr:
13836		return true;
13837	}
13838	return false;
13839}
13840
13841bool isVFMADD231SD(unsigned Opcode) {
13842	switch (Opcode) {
13843	case VFMADD231SDZm_Int:
13844	case VFMADD231SDZm_Intk:
13845	case VFMADD231SDZm_Intkz:
13846	case VFMADD231SDZr_Int:
13847	case VFMADD231SDZr_Intk:
13848	case VFMADD231SDZr_Intkz:
13849	case VFMADD231SDZrb_Int:
13850	case VFMADD231SDZrb_Intk:
13851	case VFMADD231SDZrb_Intkz:
13852	case VFMADD231SDm_Int:
13853	case VFMADD231SDr_Int:
13854		return true;
13855	}
13856	return false;
13857}
13858
13859bool isCMP(unsigned Opcode) {
13860	switch (Opcode) {
13861	case CMP16i16:
13862	case CMP16mi:
13863	case CMP16mi8:
13864	case CMP16mr:
13865	case CMP16ri:
13866	case CMP16ri8:
13867	case CMP16rm:
13868	case CMP16rr:
13869	case CMP16rr_REV:
13870	case CMP32i32:
13871	case CMP32mi:
13872	case CMP32mi8:
13873	case CMP32mr:
13874	case CMP32ri:
13875	case CMP32ri8:
13876	case CMP32rm:
13877	case CMP32rr:
13878	case CMP32rr_REV:
13879	case CMP64i32:
13880	case CMP64mi32:
13881	case CMP64mi8:
13882	case CMP64mr:
13883	case CMP64ri32:
13884	case CMP64ri8:
13885	case CMP64rm:
13886	case CMP64rr:
13887	case CMP64rr_REV:
13888	case CMP8i8:
13889	case CMP8mi:
13890	case CMP8mi8:
13891	case CMP8mr:
13892	case CMP8ri:
13893	case CMP8ri8:
13894	case CMP8rm:
13895	case CMP8rr:
13896	case CMP8rr_REV:
13897		return true;
13898	}
13899	return false;
13900}
13901
13902bool isKANDB(unsigned Opcode) {
13903	return Opcode == KANDBrr;
13904}
13905
13906bool isKANDD(unsigned Opcode) {
13907	return Opcode == KANDDrr;
13908}
13909
13910bool isVFMADD231SH(unsigned Opcode) {
13911	switch (Opcode) {
13912	case VFMADD231SHZm_Int:
13913	case VFMADD231SHZm_Intk:
13914	case VFMADD231SHZm_Intkz:
13915	case VFMADD231SHZr_Int:
13916	case VFMADD231SHZr_Intk:
13917	case VFMADD231SHZr_Intkz:
13918	case VFMADD231SHZrb_Int:
13919	case VFMADD231SHZrb_Intk:
13920	case VFMADD231SHZrb_Intkz:
13921		return true;
13922	}
13923	return false;
13924}
13925
13926bool isVCVTSH2USI(unsigned Opcode) {
13927	switch (Opcode) {
13928	case VCVTSH2USI64Zrm_Int:
13929	case VCVTSH2USI64Zrr_Int:
13930	case VCVTSH2USI64Zrrb_Int:
13931	case VCVTSH2USIZrm_Int:
13932	case VCVTSH2USIZrr_Int:
13933	case VCVTSH2USIZrrb_Int:
13934		return true;
13935	}
13936	return false;
13937}
13938
13939bool isPCONFIG(unsigned Opcode) {
13940	return Opcode == PCONFIG;
13941}
13942
13943bool isPOPAW(unsigned Opcode) {
13944	return Opcode == POPA16;
13945}
13946
13947bool isPADDQ(unsigned Opcode) {
13948	switch (Opcode) {
13949	case MMX_PADDQrm:
13950	case MMX_PADDQrr:
13951	case PADDQrm:
13952	case PADDQrr:
13953		return true;
13954	}
13955	return false;
13956}
13957
13958bool isPMAXUB(unsigned Opcode) {
13959	switch (Opcode) {
13960	case MMX_PMAXUBrm:
13961	case MMX_PMAXUBrr:
13962	case PMAXUBrm:
13963	case PMAXUBrr:
13964		return true;
13965	}
13966	return false;
13967}
13968
13969bool isROL(unsigned Opcode) {
13970	switch (Opcode) {
13971	case ROL16m1:
13972	case ROL16mCL:
13973	case ROL16mi:
13974	case ROL16r1:
13975	case ROL16rCL:
13976	case ROL16ri:
13977	case ROL32m1:
13978	case ROL32mCL:
13979	case ROL32mi:
13980	case ROL32r1:
13981	case ROL32rCL:
13982	case ROL32ri:
13983	case ROL64m1:
13984	case ROL64mCL:
13985	case ROL64mi:
13986	case ROL64r1:
13987	case ROL64rCL:
13988	case ROL64ri:
13989	case ROL8m1:
13990	case ROL8mCL:
13991	case ROL8mi:
13992	case ROL8r1:
13993	case ROL8rCL:
13994	case ROL8ri:
13995		return true;
13996	}
13997	return false;
13998}
13999
14000bool isKANDQ(unsigned Opcode) {
14001	return Opcode == KANDQrr;
14002}
14003
14004bool isPADDW(unsigned Opcode) {
14005	switch (Opcode) {
14006	case MMX_PADDWrm:
14007	case MMX_PADDWrr:
14008	case PADDWrm:
14009	case PADDWrr:
14010		return true;
14011	}
14012	return false;
14013}
14014
14015bool isVCVTTPS2QQ(unsigned Opcode) {
14016	switch (Opcode) {
14017	case VCVTTPS2QQZ128rm:
14018	case VCVTTPS2QQZ128rmb:
14019	case VCVTTPS2QQZ128rmbk:
14020	case VCVTTPS2QQZ128rmbkz:
14021	case VCVTTPS2QQZ128rmk:
14022	case VCVTTPS2QQZ128rmkz:
14023	case VCVTTPS2QQZ128rr:
14024	case VCVTTPS2QQZ128rrk:
14025	case VCVTTPS2QQZ128rrkz:
14026	case VCVTTPS2QQZ256rm:
14027	case VCVTTPS2QQZ256rmb:
14028	case VCVTTPS2QQZ256rmbk:
14029	case VCVTTPS2QQZ256rmbkz:
14030	case VCVTTPS2QQZ256rmk:
14031	case VCVTTPS2QQZ256rmkz:
14032	case VCVTTPS2QQZ256rr:
14033	case VCVTTPS2QQZ256rrk:
14034	case VCVTTPS2QQZ256rrkz:
14035	case VCVTTPS2QQZrm:
14036	case VCVTTPS2QQZrmb:
14037	case VCVTTPS2QQZrmbk:
14038	case VCVTTPS2QQZrmbkz:
14039	case VCVTTPS2QQZrmk:
14040	case VCVTTPS2QQZrmkz:
14041	case VCVTTPS2QQZrr:
14042	case VCVTTPS2QQZrrb:
14043	case VCVTTPS2QQZrrbk:
14044	case VCVTTPS2QQZrrbkz:
14045	case VCVTTPS2QQZrrk:
14046	case VCVTTPS2QQZrrkz:
14047		return true;
14048	}
14049	return false;
14050}
14051
14052bool isPMAXUD(unsigned Opcode) {
14053	switch (Opcode) {
14054	case PMAXUDrm:
14055	case PMAXUDrr:
14056		return true;
14057	}
14058	return false;
14059}
14060
14061bool isROR(unsigned Opcode) {
14062	switch (Opcode) {
14063	case ROR16m1:
14064	case ROR16mCL:
14065	case ROR16mi:
14066	case ROR16r1:
14067	case ROR16rCL:
14068	case ROR16ri:
14069	case ROR32m1:
14070	case ROR32mCL:
14071	case ROR32mi:
14072	case ROR32r1:
14073	case ROR32rCL:
14074	case ROR32ri:
14075	case ROR64m1:
14076	case ROR64mCL:
14077	case ROR64mi:
14078	case ROR64r1:
14079	case ROR64rCL:
14080	case ROR64ri:
14081	case ROR8m1:
14082	case ROR8mCL:
14083	case ROR8mi:
14084	case ROR8r1:
14085	case ROR8rCL:
14086	case ROR8ri:
14087		return true;
14088	}
14089	return false;
14090}
14091
14092bool isVFMADD231SS(unsigned Opcode) {
14093	switch (Opcode) {
14094	case VFMADD231SSZm_Int:
14095	case VFMADD231SSZm_Intk:
14096	case VFMADD231SSZm_Intkz:
14097	case VFMADD231SSZr_Int:
14098	case VFMADD231SSZr_Intk:
14099	case VFMADD231SSZr_Intkz:
14100	case VFMADD231SSZrb_Int:
14101	case VFMADD231SSZrb_Intk:
14102	case VFMADD231SSZrb_Intkz:
14103	case VFMADD231SSm_Int:
14104	case VFMADD231SSr_Int:
14105		return true;
14106	}
14107	return false;
14108}
14109
14110bool isKANDW(unsigned Opcode) {
14111	return Opcode == KANDWrr;
14112}
14113
14114bool isVPSRAD(unsigned Opcode) {
14115	switch (Opcode) {
14116	case VPSRADYri:
14117	case VPSRADYrm:
14118	case VPSRADYrr:
14119	case VPSRADZ128mbi:
14120	case VPSRADZ128mbik:
14121	case VPSRADZ128mbikz:
14122	case VPSRADZ128mi:
14123	case VPSRADZ128mik:
14124	case VPSRADZ128mikz:
14125	case VPSRADZ128ri:
14126	case VPSRADZ128rik:
14127	case VPSRADZ128rikz:
14128	case VPSRADZ128rm:
14129	case VPSRADZ128rmk:
14130	case VPSRADZ128rmkz:
14131	case VPSRADZ128rr:
14132	case VPSRADZ128rrk:
14133	case VPSRADZ128rrkz:
14134	case VPSRADZ256mbi:
14135	case VPSRADZ256mbik:
14136	case VPSRADZ256mbikz:
14137	case VPSRADZ256mi:
14138	case VPSRADZ256mik:
14139	case VPSRADZ256mikz:
14140	case VPSRADZ256ri:
14141	case VPSRADZ256rik:
14142	case VPSRADZ256rikz:
14143	case VPSRADZ256rm:
14144	case VPSRADZ256rmk:
14145	case VPSRADZ256rmkz:
14146	case VPSRADZ256rr:
14147	case VPSRADZ256rrk:
14148	case VPSRADZ256rrkz:
14149	case VPSRADZmbi:
14150	case VPSRADZmbik:
14151	case VPSRADZmbikz:
14152	case VPSRADZmi:
14153	case VPSRADZmik:
14154	case VPSRADZmikz:
14155	case VPSRADZri:
14156	case VPSRADZrik:
14157	case VPSRADZrikz:
14158	case VPSRADZrm:
14159	case VPSRADZrmk:
14160	case VPSRADZrmkz:
14161	case VPSRADZrr:
14162	case VPSRADZrrk:
14163	case VPSRADZrrkz:
14164	case VPSRADri:
14165	case VPSRADrm:
14166	case VPSRADrr:
14167		return true;
14168	}
14169	return false;
14170}
14171
14172bool isVROUNDPD(unsigned Opcode) {
14173	switch (Opcode) {
14174	case VROUNDPDYm:
14175	case VROUNDPDYr:
14176	case VROUNDPDm:
14177	case VROUNDPDr:
14178		return true;
14179	}
14180	return false;
14181}
14182
14183bool isMOVBE(unsigned Opcode) {
14184	switch (Opcode) {
14185	case MOVBE16mr:
14186	case MOVBE16rm:
14187	case MOVBE32mr:
14188	case MOVBE32rm:
14189	case MOVBE64mr:
14190	case MOVBE64rm:
14191		return true;
14192	}
14193	return false;
14194}
14195
14196bool isLOOP(unsigned Opcode) {
14197	return Opcode == LOOP;
14198}
14199
14200bool isVCVTTSD2SI(unsigned Opcode) {
14201	switch (Opcode) {
14202	case VCVTTSD2SI64Zrm_Int:
14203	case VCVTTSD2SI64Zrr_Int:
14204	case VCVTTSD2SI64Zrrb_Int:
14205	case VCVTTSD2SI64rm_Int:
14206	case VCVTTSD2SI64rr_Int:
14207	case VCVTTSD2SIZrm_Int:
14208	case VCVTTSD2SIZrr_Int:
14209	case VCVTTSD2SIZrrb_Int:
14210	case VCVTTSD2SIrm_Int:
14211	case VCVTTSD2SIrr_Int:
14212		return true;
14213	}
14214	return false;
14215}
14216
14217bool isVPSRAQ(unsigned Opcode) {
14218	switch (Opcode) {
14219	case VPSRAQZ128mbi:
14220	case VPSRAQZ128mbik:
14221	case VPSRAQZ128mbikz:
14222	case VPSRAQZ128mi:
14223	case VPSRAQZ128mik:
14224	case VPSRAQZ128mikz:
14225	case VPSRAQZ128ri:
14226	case VPSRAQZ128rik:
14227	case VPSRAQZ128rikz:
14228	case VPSRAQZ128rm:
14229	case VPSRAQZ128rmk:
14230	case VPSRAQZ128rmkz:
14231	case VPSRAQZ128rr:
14232	case VPSRAQZ128rrk:
14233	case VPSRAQZ128rrkz:
14234	case VPSRAQZ256mbi:
14235	case VPSRAQZ256mbik:
14236	case VPSRAQZ256mbikz:
14237	case VPSRAQZ256mi:
14238	case VPSRAQZ256mik:
14239	case VPSRAQZ256mikz:
14240	case VPSRAQZ256ri:
14241	case VPSRAQZ256rik:
14242	case VPSRAQZ256rikz:
14243	case VPSRAQZ256rm:
14244	case VPSRAQZ256rmk:
14245	case VPSRAQZ256rmkz:
14246	case VPSRAQZ256rr:
14247	case VPSRAQZ256rrk:
14248	case VPSRAQZ256rrkz:
14249	case VPSRAQZmbi:
14250	case VPSRAQZmbik:
14251	case VPSRAQZmbikz:
14252	case VPSRAQZmi:
14253	case VPSRAQZmik:
14254	case VPSRAQZmikz:
14255	case VPSRAQZri:
14256	case VPSRAQZrik:
14257	case VPSRAQZrikz:
14258	case VPSRAQZrm:
14259	case VPSRAQZrmk:
14260	case VPSRAQZrmkz:
14261	case VPSRAQZrr:
14262	case VPSRAQZrrk:
14263	case VPSRAQZrrkz:
14264		return true;
14265	}
14266	return false;
14267}
14268
14269bool isVROUNDPS(unsigned Opcode) {
14270	switch (Opcode) {
14271	case VROUNDPSYm:
14272	case VROUNDPSYr:
14273	case VROUNDPSm:
14274	case VROUNDPSr:
14275		return true;
14276	}
14277	return false;
14278}
14279
14280bool isPMAXUW(unsigned Opcode) {
14281	switch (Opcode) {
14282	case PMAXUWrm:
14283	case PMAXUWrr:
14284		return true;
14285	}
14286	return false;
14287}
14288
14289bool isVPSRAW(unsigned Opcode) {
14290	switch (Opcode) {
14291	case VPSRAWYri:
14292	case VPSRAWYrm:
14293	case VPSRAWYrr:
14294	case VPSRAWZ128mi:
14295	case VPSRAWZ128mik:
14296	case VPSRAWZ128mikz:
14297	case VPSRAWZ128ri:
14298	case VPSRAWZ128rik:
14299	case VPSRAWZ128rikz:
14300	case VPSRAWZ128rm:
14301	case VPSRAWZ128rmk:
14302	case VPSRAWZ128rmkz:
14303	case VPSRAWZ128rr:
14304	case VPSRAWZ128rrk:
14305	case VPSRAWZ128rrkz:
14306	case VPSRAWZ256mi:
14307	case VPSRAWZ256mik:
14308	case VPSRAWZ256mikz:
14309	case VPSRAWZ256ri:
14310	case VPSRAWZ256rik:
14311	case VPSRAWZ256rikz:
14312	case VPSRAWZ256rm:
14313	case VPSRAWZ256rmk:
14314	case VPSRAWZ256rmkz:
14315	case VPSRAWZ256rr:
14316	case VPSRAWZ256rrk:
14317	case VPSRAWZ256rrkz:
14318	case VPSRAWZmi:
14319	case VPSRAWZmik:
14320	case VPSRAWZmikz:
14321	case VPSRAWZri:
14322	case VPSRAWZrik:
14323	case VPSRAWZrikz:
14324	case VPSRAWZrm:
14325	case VPSRAWZrmk:
14326	case VPSRAWZrmkz:
14327	case VPSRAWZrr:
14328	case VPSRAWZrrk:
14329	case VPSRAWZrrkz:
14330	case VPSRAWri:
14331	case VPSRAWrm:
14332	case VPSRAWrr:
14333		return true;
14334	}
14335	return false;
14336}
14337
14338bool isVPOR(unsigned Opcode) {
14339	switch (Opcode) {
14340	case VPORYrm:
14341	case VPORYrr:
14342	case VPORrm:
14343	case VPORrr:
14344		return true;
14345	}
14346	return false;
14347}
14348
14349bool isVPEXTRB(unsigned Opcode) {
14350	switch (Opcode) {
14351	case VPEXTRBZmr:
14352	case VPEXTRBZrr:
14353	case VPEXTRBmr:
14354	case VPEXTRBrr:
14355		return true;
14356	}
14357	return false;
14358}
14359
14360bool isVPEXTRD(unsigned Opcode) {
14361	switch (Opcode) {
14362	case VPEXTRDZmr:
14363	case VPEXTRDZrr:
14364	case VPEXTRDmr:
14365	case VPEXTRDrr:
14366		return true;
14367	}
14368	return false;
14369}
14370
14371bool isXGETBV(unsigned Opcode) {
14372	return Opcode == XGETBV;
14373}
14374
14375bool isVSUBPD(unsigned Opcode) {
14376	switch (Opcode) {
14377	case VSUBPDYrm:
14378	case VSUBPDYrr:
14379	case VSUBPDZ128rm:
14380	case VSUBPDZ128rmb:
14381	case VSUBPDZ128rmbk:
14382	case VSUBPDZ128rmbkz:
14383	case VSUBPDZ128rmk:
14384	case VSUBPDZ128rmkz:
14385	case VSUBPDZ128rr:
14386	case VSUBPDZ128rrk:
14387	case VSUBPDZ128rrkz:
14388	case VSUBPDZ256rm:
14389	case VSUBPDZ256rmb:
14390	case VSUBPDZ256rmbk:
14391	case VSUBPDZ256rmbkz:
14392	case VSUBPDZ256rmk:
14393	case VSUBPDZ256rmkz:
14394	case VSUBPDZ256rr:
14395	case VSUBPDZ256rrk:
14396	case VSUBPDZ256rrkz:
14397	case VSUBPDZrm:
14398	case VSUBPDZrmb:
14399	case VSUBPDZrmbk:
14400	case VSUBPDZrmbkz:
14401	case VSUBPDZrmk:
14402	case VSUBPDZrmkz:
14403	case VSUBPDZrr:
14404	case VSUBPDZrrb:
14405	case VSUBPDZrrbk:
14406	case VSUBPDZrrbkz:
14407	case VSUBPDZrrk:
14408	case VSUBPDZrrkz:
14409	case VSUBPDrm:
14410	case VSUBPDrr:
14411		return true;
14412	}
14413	return false;
14414}
14415
14416bool isENCLS(unsigned Opcode) {
14417	return Opcode == ENCLS;
14418}
14419
14420bool isENCLU(unsigned Opcode) {
14421	return Opcode == ENCLU;
14422}
14423
14424bool isENCLV(unsigned Opcode) {
14425	return Opcode == ENCLV;
14426}
14427
14428bool isVSUBPH(unsigned Opcode) {
14429	switch (Opcode) {
14430	case VSUBPHZ128rm:
14431	case VSUBPHZ128rmb:
14432	case VSUBPHZ128rmbk:
14433	case VSUBPHZ128rmbkz:
14434	case VSUBPHZ128rmk:
14435	case VSUBPHZ128rmkz:
14436	case VSUBPHZ128rr:
14437	case VSUBPHZ128rrk:
14438	case VSUBPHZ128rrkz:
14439	case VSUBPHZ256rm:
14440	case VSUBPHZ256rmb:
14441	case VSUBPHZ256rmbk:
14442	case VSUBPHZ256rmbkz:
14443	case VSUBPHZ256rmk:
14444	case VSUBPHZ256rmkz:
14445	case VSUBPHZ256rr:
14446	case VSUBPHZ256rrk:
14447	case VSUBPHZ256rrkz:
14448	case VSUBPHZrm:
14449	case VSUBPHZrmb:
14450	case VSUBPHZrmbk:
14451	case VSUBPHZrmbkz:
14452	case VSUBPHZrmk:
14453	case VSUBPHZrmkz:
14454	case VSUBPHZrr:
14455	case VSUBPHZrrb:
14456	case VSUBPHZrrbk:
14457	case VSUBPHZrrbkz:
14458	case VSUBPHZrrk:
14459	case VSUBPHZrrkz:
14460		return true;
14461	}
14462	return false;
14463}
14464
14465bool isVPEXTRQ(unsigned Opcode) {
14466	switch (Opcode) {
14467	case VPEXTRQZmr:
14468	case VPEXTRQZrr:
14469	case VPEXTRQmr:
14470	case VPEXTRQrr:
14471		return true;
14472	}
14473	return false;
14474}
14475
14476bool isVHSUBPD(unsigned Opcode) {
14477	switch (Opcode) {
14478	case VHSUBPDYrm:
14479	case VHSUBPDYrr:
14480	case VHSUBPDrm:
14481	case VHSUBPDrr:
14482		return true;
14483	}
14484	return false;
14485}
14486
14487bool isVPEXTRW(unsigned Opcode) {
14488	switch (Opcode) {
14489	case VPEXTRWZmr:
14490	case VPEXTRWZrr:
14491	case VPEXTRWZrr_REV:
14492	case VPEXTRWmr:
14493	case VPEXTRWrr:
14494	case VPEXTRWrr_REV:
14495		return true;
14496	}
14497	return false;
14498}
14499
14500bool isVSUBPS(unsigned Opcode) {
14501	switch (Opcode) {
14502	case VSUBPSYrm:
14503	case VSUBPSYrr:
14504	case VSUBPSZ128rm:
14505	case VSUBPSZ128rmb:
14506	case VSUBPSZ128rmbk:
14507	case VSUBPSZ128rmbkz:
14508	case VSUBPSZ128rmk:
14509	case VSUBPSZ128rmkz:
14510	case VSUBPSZ128rr:
14511	case VSUBPSZ128rrk:
14512	case VSUBPSZ128rrkz:
14513	case VSUBPSZ256rm:
14514	case VSUBPSZ256rmb:
14515	case VSUBPSZ256rmbk:
14516	case VSUBPSZ256rmbkz:
14517	case VSUBPSZ256rmk:
14518	case VSUBPSZ256rmkz:
14519	case VSUBPSZ256rr:
14520	case VSUBPSZ256rrk:
14521	case VSUBPSZ256rrkz:
14522	case VSUBPSZrm:
14523	case VSUBPSZrmb:
14524	case VSUBPSZrmbk:
14525	case VSUBPSZrmbkz:
14526	case VSUBPSZrmk:
14527	case VSUBPSZrmkz:
14528	case VSUBPSZrr:
14529	case VSUBPSZrrb:
14530	case VSUBPSZrrbk:
14531	case VSUBPSZrrbkz:
14532	case VSUBPSZrrk:
14533	case VSUBPSZrrkz:
14534	case VSUBPSrm:
14535	case VSUBPSrr:
14536		return true;
14537	}
14538	return false;
14539}
14540
14541bool isVGF2P8AFFINEINVQB(unsigned Opcode) {
14542	switch (Opcode) {
14543	case VGF2P8AFFINEINVQBYrmi:
14544	case VGF2P8AFFINEINVQBYrri:
14545	case VGF2P8AFFINEINVQBZ128rmbi:
14546	case VGF2P8AFFINEINVQBZ128rmbik:
14547	case VGF2P8AFFINEINVQBZ128rmbikz:
14548	case VGF2P8AFFINEINVQBZ128rmi:
14549	case VGF2P8AFFINEINVQBZ128rmik:
14550	case VGF2P8AFFINEINVQBZ128rmikz:
14551	case VGF2P8AFFINEINVQBZ128rri:
14552	case VGF2P8AFFINEINVQBZ128rrik:
14553	case VGF2P8AFFINEINVQBZ128rrikz:
14554	case VGF2P8AFFINEINVQBZ256rmbi:
14555	case VGF2P8AFFINEINVQBZ256rmbik:
14556	case VGF2P8AFFINEINVQBZ256rmbikz:
14557	case VGF2P8AFFINEINVQBZ256rmi:
14558	case VGF2P8AFFINEINVQBZ256rmik:
14559	case VGF2P8AFFINEINVQBZ256rmikz:
14560	case VGF2P8AFFINEINVQBZ256rri:
14561	case VGF2P8AFFINEINVQBZ256rrik:
14562	case VGF2P8AFFINEINVQBZ256rrikz:
14563	case VGF2P8AFFINEINVQBZrmbi:
14564	case VGF2P8AFFINEINVQBZrmbik:
14565	case VGF2P8AFFINEINVQBZrmbikz:
14566	case VGF2P8AFFINEINVQBZrmi:
14567	case VGF2P8AFFINEINVQBZrmik:
14568	case VGF2P8AFFINEINVQBZrmikz:
14569	case VGF2P8AFFINEINVQBZrri:
14570	case VGF2P8AFFINEINVQBZrrik:
14571	case VGF2P8AFFINEINVQBZrrikz:
14572	case VGF2P8AFFINEINVQBrmi:
14573	case VGF2P8AFFINEINVQBrri:
14574		return true;
14575	}
14576	return false;
14577}
14578
14579bool isVMOVLPD(unsigned Opcode) {
14580	switch (Opcode) {
14581	case VMOVLPDZ128mr:
14582	case VMOVLPDZ128rm:
14583	case VMOVLPDmr:
14584	case VMOVLPDrm:
14585		return true;
14586	}
14587	return false;
14588}
14589
14590bool isVFMADDSD(unsigned Opcode) {
14591	switch (Opcode) {
14592	case VFMADDSD4mr:
14593	case VFMADDSD4rm:
14594	case VFMADDSD4rr:
14595	case VFMADDSD4rr_REV:
14596		return true;
14597	}
14598	return false;
14599}
14600
14601bool isVHSUBPS(unsigned Opcode) {
14602	switch (Opcode) {
14603	case VHSUBPSYrm:
14604	case VHSUBPSYrr:
14605	case VHSUBPSrm:
14606	case VHSUBPSrr:
14607		return true;
14608	}
14609	return false;
14610}
14611
14612bool isPSRLDQ(unsigned Opcode) {
14613	return Opcode == PSRLDQri;
14614}
14615
14616bool isVMOVLPS(unsigned Opcode) {
14617	switch (Opcode) {
14618	case VMOVLPSZ128mr:
14619	case VMOVLPSZ128rm:
14620	case VMOVLPSmr:
14621	case VMOVLPSrm:
14622		return true;
14623	}
14624	return false;
14625}
14626
14627bool isVFMADDSS(unsigned Opcode) {
14628	switch (Opcode) {
14629	case VFMADDSS4mr:
14630	case VFMADDSS4rm:
14631	case VFMADDSS4rr:
14632	case VFMADDSS4rr_REV:
14633		return true;
14634	}
14635	return false;
14636}
14637
14638bool isVRCP28PD(unsigned Opcode) {
14639	switch (Opcode) {
14640	case VRCP28PDZm:
14641	case VRCP28PDZmb:
14642	case VRCP28PDZmbk:
14643	case VRCP28PDZmbkz:
14644	case VRCP28PDZmk:
14645	case VRCP28PDZmkz:
14646	case VRCP28PDZr:
14647	case VRCP28PDZrb:
14648	case VRCP28PDZrbk:
14649	case VRCP28PDZrbkz:
14650	case VRCP28PDZrk:
14651	case VRCP28PDZrkz:
14652		return true;
14653	}
14654	return false;
14655}
14656
14657bool isFPREM(unsigned Opcode) {
14658	return Opcode == FPREM;
14659}
14660
14661bool isVPMADDWD(unsigned Opcode) {
14662	switch (Opcode) {
14663	case VPMADDWDYrm:
14664	case VPMADDWDYrr:
14665	case VPMADDWDZ128rm:
14666	case VPMADDWDZ128rmk:
14667	case VPMADDWDZ128rmkz:
14668	case VPMADDWDZ128rr:
14669	case VPMADDWDZ128rrk:
14670	case VPMADDWDZ128rrkz:
14671	case VPMADDWDZ256rm:
14672	case VPMADDWDZ256rmk:
14673	case VPMADDWDZ256rmkz:
14674	case VPMADDWDZ256rr:
14675	case VPMADDWDZ256rrk:
14676	case VPMADDWDZ256rrkz:
14677	case VPMADDWDZrm:
14678	case VPMADDWDZrmk:
14679	case VPMADDWDZrmkz:
14680	case VPMADDWDZrr:
14681	case VPMADDWDZrrk:
14682	case VPMADDWDZrrkz:
14683	case VPMADDWDrm:
14684	case VPMADDWDrr:
14685		return true;
14686	}
14687	return false;
14688}
14689
14690bool isVCVTSH2SD(unsigned Opcode) {
14691	switch (Opcode) {
14692	case VCVTSH2SDZrm_Int:
14693	case VCVTSH2SDZrm_Intk:
14694	case VCVTSH2SDZrm_Intkz:
14695	case VCVTSH2SDZrr_Int:
14696	case VCVTSH2SDZrr_Intk:
14697	case VCVTSH2SDZrr_Intkz:
14698	case VCVTSH2SDZrrb_Int:
14699	case VCVTSH2SDZrrb_Intk:
14700	case VCVTSH2SDZrrb_Intkz:
14701		return true;
14702	}
14703	return false;
14704}
14705
14706bool isSERIALIZE(unsigned Opcode) {
14707	return Opcode == SERIALIZE;
14708}
14709
14710bool isV4FMADDPS(unsigned Opcode) {
14711	switch (Opcode) {
14712	case V4FMADDPSrm:
14713	case V4FMADDPSrmk:
14714	case V4FMADDPSrmkz:
14715		return true;
14716	}
14717	return false;
14718}
14719
14720bool isVRCP28PS(unsigned Opcode) {
14721	switch (Opcode) {
14722	case VRCP28PSZm:
14723	case VRCP28PSZmb:
14724	case VRCP28PSZmbk:
14725	case VRCP28PSZmbkz:
14726	case VRCP28PSZmk:
14727	case VRCP28PSZmkz:
14728	case VRCP28PSZr:
14729	case VRCP28PSZrb:
14730	case VRCP28PSZrbk:
14731	case VRCP28PSZrbkz:
14732	case VRCP28PSZrk:
14733	case VRCP28PSZrkz:
14734		return true;
14735	}
14736	return false;
14737}
14738
14739bool isVCVTSH2SI(unsigned Opcode) {
14740	switch (Opcode) {
14741	case VCVTSH2SI64Zrm_Int:
14742	case VCVTSH2SI64Zrr_Int:
14743	case VCVTSH2SI64Zrrb_Int:
14744	case VCVTSH2SIZrm_Int:
14745	case VCVTSH2SIZrr_Int:
14746	case VCVTSH2SIZrrb_Int:
14747		return true;
14748	}
14749	return false;
14750}
14751
14752bool isRETF(unsigned Opcode) {
14753	switch (Opcode) {
14754	case LRET16:
14755	case LRET32:
14756	case LRETI16:
14757	case LRETI32:
14758		return true;
14759	}
14760	return false;
14761}
14762
14763bool isVROUNDSD(unsigned Opcode) {
14764	switch (Opcode) {
14765	case VROUNDSDm_Int:
14766	case VROUNDSDr_Int:
14767		return true;
14768	}
14769	return false;
14770}
14771
14772bool isVCVTSH2SS(unsigned Opcode) {
14773	switch (Opcode) {
14774	case VCVTSH2SSZrm_Int:
14775	case VCVTSH2SSZrm_Intk:
14776	case VCVTSH2SSZrm_Intkz:
14777	case VCVTSH2SSZrr_Int:
14778	case VCVTSH2SSZrr_Intk:
14779	case VCVTSH2SSZrr_Intkz:
14780	case VCVTSH2SSZrrb_Int:
14781	case VCVTSH2SSZrrb_Intk:
14782	case VCVTSH2SSZrrb_Intkz:
14783		return true;
14784	}
14785	return false;
14786}
14787
14788bool isVSCATTERPF1QPD(unsigned Opcode) {
14789	return Opcode == VSCATTERPF1QPDm;
14790}
14791
14792bool isVPCONFLICTD(unsigned Opcode) {
14793	switch (Opcode) {
14794	case VPCONFLICTDZ128rm:
14795	case VPCONFLICTDZ128rmb:
14796	case VPCONFLICTDZ128rmbk:
14797	case VPCONFLICTDZ128rmbkz:
14798	case VPCONFLICTDZ128rmk:
14799	case VPCONFLICTDZ128rmkz:
14800	case VPCONFLICTDZ128rr:
14801	case VPCONFLICTDZ128rrk:
14802	case VPCONFLICTDZ128rrkz:
14803	case VPCONFLICTDZ256rm:
14804	case VPCONFLICTDZ256rmb:
14805	case VPCONFLICTDZ256rmbk:
14806	case VPCONFLICTDZ256rmbkz:
14807	case VPCONFLICTDZ256rmk:
14808	case VPCONFLICTDZ256rmkz:
14809	case VPCONFLICTDZ256rr:
14810	case VPCONFLICTDZ256rrk:
14811	case VPCONFLICTDZ256rrkz:
14812	case VPCONFLICTDZrm:
14813	case VPCONFLICTDZrmb:
14814	case VPCONFLICTDZrmbk:
14815	case VPCONFLICTDZrmbkz:
14816	case VPCONFLICTDZrmk:
14817	case VPCONFLICTDZrmkz:
14818	case VPCONFLICTDZrr:
14819	case VPCONFLICTDZrrk:
14820	case VPCONFLICTDZrrkz:
14821		return true;
14822	}
14823	return false;
14824}
14825
14826bool isMOVNTI(unsigned Opcode) {
14827	switch (Opcode) {
14828	case MOVNTI_64mr:
14829	case MOVNTImr:
14830		return true;
14831	}
14832	return false;
14833}
14834
14835bool isCQO(unsigned Opcode) {
14836	return Opcode == CQO;
14837}
14838
14839bool isVROUNDSS(unsigned Opcode) {
14840	switch (Opcode) {
14841	case VROUNDSSm_Int:
14842	case VROUNDSSr_Int:
14843		return true;
14844	}
14845	return false;
14846}
14847
14848bool isMOVNTQ(unsigned Opcode) {
14849	return Opcode == MMX_MOVNTQmr;
14850}
14851
14852bool isVAESENC(unsigned Opcode) {
14853	switch (Opcode) {
14854	case VAESENCYrm:
14855	case VAESENCYrr:
14856	case VAESENCZ128rm:
14857	case VAESENCZ128rr:
14858	case VAESENCZ256rm:
14859	case VAESENCZ256rr:
14860	case VAESENCZrm:
14861	case VAESENCZrr:
14862	case VAESENCrm:
14863	case VAESENCrr:
14864		return true;
14865	}
14866	return false;
14867}
14868
14869bool isVSCATTERPF1QPS(unsigned Opcode) {
14870	return Opcode == VSCATTERPF1QPSm;
14871}
14872
14873bool isVPCONFLICTQ(unsigned Opcode) {
14874	switch (Opcode) {
14875	case VPCONFLICTQZ128rm:
14876	case VPCONFLICTQZ128rmb:
14877	case VPCONFLICTQZ128rmbk:
14878	case VPCONFLICTQZ128rmbkz:
14879	case VPCONFLICTQZ128rmk:
14880	case VPCONFLICTQZ128rmkz:
14881	case VPCONFLICTQZ128rr:
14882	case VPCONFLICTQZ128rrk:
14883	case VPCONFLICTQZ128rrkz:
14884	case VPCONFLICTQZ256rm:
14885	case VPCONFLICTQZ256rmb:
14886	case VPCONFLICTQZ256rmbk:
14887	case VPCONFLICTQZ256rmbkz:
14888	case VPCONFLICTQZ256rmk:
14889	case VPCONFLICTQZ256rmkz:
14890	case VPCONFLICTQZ256rr:
14891	case VPCONFLICTQZ256rrk:
14892	case VPCONFLICTQZ256rrkz:
14893	case VPCONFLICTQZrm:
14894	case VPCONFLICTQZrmb:
14895	case VPCONFLICTQZrmbk:
14896	case VPCONFLICTQZrmbkz:
14897	case VPCONFLICTQZrmk:
14898	case VPCONFLICTQZrmkz:
14899	case VPCONFLICTQZrr:
14900	case VPCONFLICTQZrrk:
14901	case VPCONFLICTQZrrkz:
14902		return true;
14903	}
14904	return false;
14905}
14906
14907bool isFCMOVNB(unsigned Opcode) {
14908	return Opcode == CMOVNB_F;
14909}
14910
14911bool isLZCNT(unsigned Opcode) {
14912	switch (Opcode) {
14913	case LZCNT16rm:
14914	case LZCNT16rr:
14915	case LZCNT32rm:
14916	case LZCNT32rr:
14917	case LZCNT64rm:
14918	case LZCNT64rr:
14919		return true;
14920	}
14921	return false;
14922}
14923
14924bool isFCMOVNE(unsigned Opcode) {
14925	return Opcode == CMOVNE_F;
14926}
14927
14928bool isRSM(unsigned Opcode) {
14929	return Opcode == RSM;
14930}
14931
14932bool isPOPCNT(unsigned Opcode) {
14933	switch (Opcode) {
14934	case POPCNT16rm:
14935	case POPCNT16rr:
14936	case POPCNT32rm:
14937	case POPCNT32rr:
14938	case POPCNT64rm:
14939	case POPCNT64rr:
14940		return true;
14941	}
14942	return false;
14943}
14944
14945bool isVSUBSD(unsigned Opcode) {
14946	switch (Opcode) {
14947	case VSUBSDZrm_Int:
14948	case VSUBSDZrm_Intk:
14949	case VSUBSDZrm_Intkz:
14950	case VSUBSDZrr_Int:
14951	case VSUBSDZrr_Intk:
14952	case VSUBSDZrr_Intkz:
14953	case VSUBSDZrrb_Int:
14954	case VSUBSDZrrb_Intk:
14955	case VSUBSDZrrb_Intkz:
14956	case VSUBSDrm_Int:
14957	case VSUBSDrr_Int:
14958		return true;
14959	}
14960	return false;
14961}
14962
14963bool isPOPFD(unsigned Opcode) {
14964	return Opcode == POPF32;
14965}
14966
14967bool isVSUBSH(unsigned Opcode) {
14968	switch (Opcode) {
14969	case VSUBSHZrm_Int:
14970	case VSUBSHZrm_Intk:
14971	case VSUBSHZrm_Intkz:
14972	case VSUBSHZrr_Int:
14973	case VSUBSHZrr_Intk:
14974	case VSUBSHZrr_Intkz:
14975	case VSUBSHZrrb_Int:
14976	case VSUBSHZrrb_Intk:
14977	case VSUBSHZrrb_Intkz:
14978		return true;
14979	}
14980	return false;
14981}
14982
14983bool isVPANDD(unsigned Opcode) {
14984	switch (Opcode) {
14985	case VPANDDZ128rm:
14986	case VPANDDZ128rmb:
14987	case VPANDDZ128rmbk:
14988	case VPANDDZ128rmbkz:
14989	case VPANDDZ128rmk:
14990	case VPANDDZ128rmkz:
14991	case VPANDDZ128rr:
14992	case VPANDDZ128rrk:
14993	case VPANDDZ128rrkz:
14994	case VPANDDZ256rm:
14995	case VPANDDZ256rmb:
14996	case VPANDDZ256rmbk:
14997	case VPANDDZ256rmbkz:
14998	case VPANDDZ256rmk:
14999	case VPANDDZ256rmkz:
15000	case VPANDDZ256rr:
15001	case VPANDDZ256rrk:
15002	case VPANDDZ256rrkz:
15003	case VPANDDZrm:
15004	case VPANDDZrmb:
15005	case VPANDDZrmbk:
15006	case VPANDDZrmbkz:
15007	case VPANDDZrmk:
15008	case VPANDDZrmkz:
15009	case VPANDDZrr:
15010	case VPANDDZrrk:
15011	case VPANDDZrrkz:
15012		return true;
15013	}
15014	return false;
15015}
15016
15017bool isFCMOVNU(unsigned Opcode) {
15018	return Opcode == CMOVNP_F;
15019}
15020
15021bool isVMOVHLPS(unsigned Opcode) {
15022	switch (Opcode) {
15023	case VMOVHLPSZrr:
15024	case VMOVHLPSrr:
15025		return true;
15026	}
15027	return false;
15028}
15029
15030bool isPOPFQ(unsigned Opcode) {
15031	return Opcode == POPF64;
15032}
15033
15034bool isVPANDN(unsigned Opcode) {
15035	switch (Opcode) {
15036	case VPANDNYrm:
15037	case VPANDNYrr:
15038	case VPANDNrm:
15039	case VPANDNrr:
15040		return true;
15041	}
15042	return false;
15043}
15044
15045bool isVFMADDSUB213PD(unsigned Opcode) {
15046	switch (Opcode) {
15047	case VFMADDSUB213PDYm:
15048	case VFMADDSUB213PDYr:
15049	case VFMADDSUB213PDZ128m:
15050	case VFMADDSUB213PDZ128mb:
15051	case VFMADDSUB213PDZ128mbk:
15052	case VFMADDSUB213PDZ128mbkz:
15053	case VFMADDSUB213PDZ128mk:
15054	case VFMADDSUB213PDZ128mkz:
15055	case VFMADDSUB213PDZ128r:
15056	case VFMADDSUB213PDZ128rk:
15057	case VFMADDSUB213PDZ128rkz:
15058	case VFMADDSUB213PDZ256m:
15059	case VFMADDSUB213PDZ256mb:
15060	case VFMADDSUB213PDZ256mbk:
15061	case VFMADDSUB213PDZ256mbkz:
15062	case VFMADDSUB213PDZ256mk:
15063	case VFMADDSUB213PDZ256mkz:
15064	case VFMADDSUB213PDZ256r:
15065	case VFMADDSUB213PDZ256rk:
15066	case VFMADDSUB213PDZ256rkz:
15067	case VFMADDSUB213PDZm:
15068	case VFMADDSUB213PDZmb:
15069	case VFMADDSUB213PDZmbk:
15070	case VFMADDSUB213PDZmbkz:
15071	case VFMADDSUB213PDZmk:
15072	case VFMADDSUB213PDZmkz:
15073	case VFMADDSUB213PDZr:
15074	case VFMADDSUB213PDZrb:
15075	case VFMADDSUB213PDZrbk:
15076	case VFMADDSUB213PDZrbkz:
15077	case VFMADDSUB213PDZrk:
15078	case VFMADDSUB213PDZrkz:
15079	case VFMADDSUB213PDm:
15080	case VFMADDSUB213PDr:
15081		return true;
15082	}
15083	return false;
15084}
15085
15086bool isVCMPPD(unsigned Opcode) {
15087	switch (Opcode) {
15088	case VCMPPDYrmi:
15089	case VCMPPDYrri:
15090	case VCMPPDZ128rmbi:
15091	case VCMPPDZ128rmbik:
15092	case VCMPPDZ128rmi:
15093	case VCMPPDZ128rmik:
15094	case VCMPPDZ128rri:
15095	case VCMPPDZ128rrik:
15096	case VCMPPDZ256rmbi:
15097	case VCMPPDZ256rmbik:
15098	case VCMPPDZ256rmi:
15099	case VCMPPDZ256rmik:
15100	case VCMPPDZ256rri:
15101	case VCMPPDZ256rrik:
15102	case VCMPPDZrmbi:
15103	case VCMPPDZrmbik:
15104	case VCMPPDZrmi:
15105	case VCMPPDZrmik:
15106	case VCMPPDZrri:
15107	case VCMPPDZrrib:
15108	case VCMPPDZrribk:
15109	case VCMPPDZrrik:
15110	case VCMPPDrmi:
15111	case VCMPPDrri:
15112		return true;
15113	}
15114	return false;
15115}
15116
15117bool isVFMADDSUB213PH(unsigned Opcode) {
15118	switch (Opcode) {
15119	case VFMADDSUB213PHZ128m:
15120	case VFMADDSUB213PHZ128mb:
15121	case VFMADDSUB213PHZ128mbk:
15122	case VFMADDSUB213PHZ128mbkz:
15123	case VFMADDSUB213PHZ128mk:
15124	case VFMADDSUB213PHZ128mkz:
15125	case VFMADDSUB213PHZ128r:
15126	case VFMADDSUB213PHZ128rk:
15127	case VFMADDSUB213PHZ128rkz:
15128	case VFMADDSUB213PHZ256m:
15129	case VFMADDSUB213PHZ256mb:
15130	case VFMADDSUB213PHZ256mbk:
15131	case VFMADDSUB213PHZ256mbkz:
15132	case VFMADDSUB213PHZ256mk:
15133	case VFMADDSUB213PHZ256mkz:
15134	case VFMADDSUB213PHZ256r:
15135	case VFMADDSUB213PHZ256rk:
15136	case VFMADDSUB213PHZ256rkz:
15137	case VFMADDSUB213PHZm:
15138	case VFMADDSUB213PHZmb:
15139	case VFMADDSUB213PHZmbk:
15140	case VFMADDSUB213PHZmbkz:
15141	case VFMADDSUB213PHZmk:
15142	case VFMADDSUB213PHZmkz:
15143	case VFMADDSUB213PHZr:
15144	case VFMADDSUB213PHZrb:
15145	case VFMADDSUB213PHZrbk:
15146	case VFMADDSUB213PHZrbkz:
15147	case VFMADDSUB213PHZrk:
15148	case VFMADDSUB213PHZrkz:
15149		return true;
15150	}
15151	return false;
15152}
15153
15154bool isVSUBSS(unsigned Opcode) {
15155	switch (Opcode) {
15156	case VSUBSSZrm_Int:
15157	case VSUBSSZrm_Intk:
15158	case VSUBSSZrm_Intkz:
15159	case VSUBSSZrr_Int:
15160	case VSUBSSZrr_Intk:
15161	case VSUBSSZrr_Intkz:
15162	case VSUBSSZrrb_Int:
15163	case VSUBSSZrrb_Intk:
15164	case VSUBSSZrrb_Intkz:
15165	case VSUBSSrm_Int:
15166	case VSUBSSrr_Int:
15167		return true;
15168	}
15169	return false;
15170}
15171
15172bool isVPANDQ(unsigned Opcode) {
15173	switch (Opcode) {
15174	case VPANDQZ128rm:
15175	case VPANDQZ128rmb:
15176	case VPANDQZ128rmbk:
15177	case VPANDQZ128rmbkz:
15178	case VPANDQZ128rmk:
15179	case VPANDQZ128rmkz:
15180	case VPANDQZ128rr:
15181	case VPANDQZ128rrk:
15182	case VPANDQZ128rrkz:
15183	case VPANDQZ256rm:
15184	case VPANDQZ256rmb:
15185	case VPANDQZ256rmbk:
15186	case VPANDQZ256rmbkz:
15187	case VPANDQZ256rmk:
15188	case VPANDQZ256rmkz:
15189	case VPANDQZ256rr:
15190	case VPANDQZ256rrk:
15191	case VPANDQZ256rrkz:
15192	case VPANDQZrm:
15193	case VPANDQZrmb:
15194	case VPANDQZrmbk:
15195	case VPANDQZrmbkz:
15196	case VPANDQZrmk:
15197	case VPANDQZrmkz:
15198	case VPANDQZrr:
15199	case VPANDQZrrk:
15200	case VPANDQZrrkz:
15201		return true;
15202	}
15203	return false;
15204}
15205
15206bool isVCMPPH(unsigned Opcode) {
15207	switch (Opcode) {
15208	case VCMPPHZ128rmbi:
15209	case VCMPPHZ128rmbik:
15210	case VCMPPHZ128rmi:
15211	case VCMPPHZ128rmik:
15212	case VCMPPHZ128rri:
15213	case VCMPPHZ128rrik:
15214	case VCMPPHZ256rmbi:
15215	case VCMPPHZ256rmbik:
15216	case VCMPPHZ256rmi:
15217	case VCMPPHZ256rmik:
15218	case VCMPPHZ256rri:
15219	case VCMPPHZ256rrik:
15220	case VCMPPHZrmbi:
15221	case VCMPPHZrmbik:
15222	case VCMPPHZrmi:
15223	case VCMPPHZrmik:
15224	case VCMPPHZrri:
15225	case VCMPPHZrrib:
15226	case VCMPPHZrribk:
15227	case VCMPPHZrrik:
15228		return true;
15229	}
15230	return false;
15231}
15232
15233bool isVP4DPWSSD(unsigned Opcode) {
15234	switch (Opcode) {
15235	case VP4DPWSSDrm:
15236	case VP4DPWSSDrmk:
15237	case VP4DPWSSDrmkz:
15238		return true;
15239	}
15240	return false;
15241}
15242
15243bool isENDBR32(unsigned Opcode) {
15244	return Opcode == ENDBR32;
15245}
15246
15247bool isEMMS(unsigned Opcode) {
15248	return Opcode == MMX_EMMS;
15249}
15250
15251bool isXCHG(unsigned Opcode) {
15252	switch (Opcode) {
15253	case XCHG16ar:
15254	case XCHG16rm:
15255	case XCHG16rr:
15256	case XCHG32ar:
15257	case XCHG32rm:
15258	case XCHG32rr:
15259	case XCHG64ar:
15260	case XCHG64rm:
15261	case XCHG64rr:
15262	case XCHG8rm:
15263	case XCHG8rr:
15264		return true;
15265	}
15266	return false;
15267}
15268
15269bool isVFMADDSUB213PS(unsigned Opcode) {
15270	switch (Opcode) {
15271	case VFMADDSUB213PSYm:
15272	case VFMADDSUB213PSYr:
15273	case VFMADDSUB213PSZ128m:
15274	case VFMADDSUB213PSZ128mb:
15275	case VFMADDSUB213PSZ128mbk:
15276	case VFMADDSUB213PSZ128mbkz:
15277	case VFMADDSUB213PSZ128mk:
15278	case VFMADDSUB213PSZ128mkz:
15279	case VFMADDSUB213PSZ128r:
15280	case VFMADDSUB213PSZ128rk:
15281	case VFMADDSUB213PSZ128rkz:
15282	case VFMADDSUB213PSZ256m:
15283	case VFMADDSUB213PSZ256mb:
15284	case VFMADDSUB213PSZ256mbk:
15285	case VFMADDSUB213PSZ256mbkz:
15286	case VFMADDSUB213PSZ256mk:
15287	case VFMADDSUB213PSZ256mkz:
15288	case VFMADDSUB213PSZ256r:
15289	case VFMADDSUB213PSZ256rk:
15290	case VFMADDSUB213PSZ256rkz:
15291	case VFMADDSUB213PSZm:
15292	case VFMADDSUB213PSZmb:
15293	case VFMADDSUB213PSZmbk:
15294	case VFMADDSUB213PSZmbkz:
15295	case VFMADDSUB213PSZmk:
15296	case VFMADDSUB213PSZmkz:
15297	case VFMADDSUB213PSZr:
15298	case VFMADDSUB213PSZrb:
15299	case VFMADDSUB213PSZrbk:
15300	case VFMADDSUB213PSZrbkz:
15301	case VFMADDSUB213PSZrk:
15302	case VFMADDSUB213PSZrkz:
15303	case VFMADDSUB213PSm:
15304	case VFMADDSUB213PSr:
15305		return true;
15306	}
15307	return false;
15308}
15309
15310bool isTDPBUSD(unsigned Opcode) {
15311	return Opcode == TDPBUSD;
15312}
15313
15314bool isRDSEED(unsigned Opcode) {
15315	switch (Opcode) {
15316	case RDSEED16r:
15317	case RDSEED32r:
15318	case RDSEED64r:
15319		return true;
15320	}
15321	return false;
15322}
15323
15324bool isVCMPPS(unsigned Opcode) {
15325	switch (Opcode) {
15326	case VCMPPSYrmi:
15327	case VCMPPSYrri:
15328	case VCMPPSZ128rmbi:
15329	case VCMPPSZ128rmbik:
15330	case VCMPPSZ128rmi:
15331	case VCMPPSZ128rmik:
15332	case VCMPPSZ128rri:
15333	case VCMPPSZ128rrik:
15334	case VCMPPSZ256rmbi:
15335	case VCMPPSZ256rmbik:
15336	case VCMPPSZ256rmi:
15337	case VCMPPSZ256rmik:
15338	case VCMPPSZ256rri:
15339	case VCMPPSZ256rrik:
15340	case VCMPPSZrmbi:
15341	case VCMPPSZrmbik:
15342	case VCMPPSZrmi:
15343	case VCMPPSZrmik:
15344	case VCMPPSZrri:
15345	case VCMPPSZrrib:
15346	case VCMPPSZrribk:
15347	case VCMPPSZrrik:
15348	case VCMPPSrmi:
15349	case VCMPPSrri:
15350		return true;
15351	}
15352	return false;
15353}
15354
15355bool isVRCP28SD(unsigned Opcode) {
15356	switch (Opcode) {
15357	case VRCP28SDZm:
15358	case VRCP28SDZmk:
15359	case VRCP28SDZmkz:
15360	case VRCP28SDZr:
15361	case VRCP28SDZrb:
15362	case VRCP28SDZrbk:
15363	case VRCP28SDZrbkz:
15364	case VRCP28SDZrk:
15365	case VRCP28SDZrkz:
15366		return true;
15367	}
15368	return false;
15369}
15370
15371bool isRDMSRLIST(unsigned Opcode) {
15372	return Opcode == RDMSRLIST;
15373}
15374
15375bool isVRCP28SS(unsigned Opcode) {
15376	switch (Opcode) {
15377	case VRCP28SSZm:
15378	case VRCP28SSZmk:
15379	case VRCP28SSZmkz:
15380	case VRCP28SSZr:
15381	case VRCP28SSZrb:
15382	case VRCP28SSZrbk:
15383	case VRCP28SSZrbkz:
15384	case VRCP28SSZrk:
15385	case VRCP28SSZrkz:
15386		return true;
15387	}
15388	return false;
15389}
15390
15391bool isV4FMADDSS(unsigned Opcode) {
15392	switch (Opcode) {
15393	case V4FMADDSSrm:
15394	case V4FMADDSSrmk:
15395	case V4FMADDSSrmkz:
15396		return true;
15397	}
15398	return false;
15399}
15400
15401bool isAESKEYGENASSIST(unsigned Opcode) {
15402	switch (Opcode) {
15403	case AESKEYGENASSIST128rm:
15404	case AESKEYGENASSIST128rr:
15405		return true;
15406	}
15407	return false;
15408}
15409
15410bool isFUCOMPI(unsigned Opcode) {
15411	return Opcode == UCOM_FIPr;
15412}
15413
15414bool isTDPBF16PS(unsigned Opcode) {
15415	return Opcode == TDPBF16PS;
15416}
15417
15418bool isFUCOMPP(unsigned Opcode) {
15419	return Opcode == UCOM_FPPr;
15420}
15421
15422bool isVFMADDSUB231PD(unsigned Opcode) {
15423	switch (Opcode) {
15424	case VFMADDSUB231PDYm:
15425	case VFMADDSUB231PDYr:
15426	case VFMADDSUB231PDZ128m:
15427	case VFMADDSUB231PDZ128mb:
15428	case VFMADDSUB231PDZ128mbk:
15429	case VFMADDSUB231PDZ128mbkz:
15430	case VFMADDSUB231PDZ128mk:
15431	case VFMADDSUB231PDZ128mkz:
15432	case VFMADDSUB231PDZ128r:
15433	case VFMADDSUB231PDZ128rk:
15434	case VFMADDSUB231PDZ128rkz:
15435	case VFMADDSUB231PDZ256m:
15436	case VFMADDSUB231PDZ256mb:
15437	case VFMADDSUB231PDZ256mbk:
15438	case VFMADDSUB231PDZ256mbkz:
15439	case VFMADDSUB231PDZ256mk:
15440	case VFMADDSUB231PDZ256mkz:
15441	case VFMADDSUB231PDZ256r:
15442	case VFMADDSUB231PDZ256rk:
15443	case VFMADDSUB231PDZ256rkz:
15444	case VFMADDSUB231PDZm:
15445	case VFMADDSUB231PDZmb:
15446	case VFMADDSUB231PDZmbk:
15447	case VFMADDSUB231PDZmbkz:
15448	case VFMADDSUB231PDZmk:
15449	case VFMADDSUB231PDZmkz:
15450	case VFMADDSUB231PDZr:
15451	case VFMADDSUB231PDZrb:
15452	case VFMADDSUB231PDZrbk:
15453	case VFMADDSUB231PDZrbkz:
15454	case VFMADDSUB231PDZrk:
15455	case VFMADDSUB231PDZrkz:
15456	case VFMADDSUB231PDm:
15457	case VFMADDSUB231PDr:
15458		return true;
15459	}
15460	return false;
15461}
15462
15463bool isVCVTPH2PSX(unsigned Opcode) {
15464	switch (Opcode) {
15465	case VCVTPH2PSXZ128rm:
15466	case VCVTPH2PSXZ128rmb:
15467	case VCVTPH2PSXZ128rmbk:
15468	case VCVTPH2PSXZ128rmbkz:
15469	case VCVTPH2PSXZ128rmk:
15470	case VCVTPH2PSXZ128rmkz:
15471	case VCVTPH2PSXZ128rr:
15472	case VCVTPH2PSXZ128rrk:
15473	case VCVTPH2PSXZ128rrkz:
15474	case VCVTPH2PSXZ256rm:
15475	case VCVTPH2PSXZ256rmb:
15476	case VCVTPH2PSXZ256rmbk:
15477	case VCVTPH2PSXZ256rmbkz:
15478	case VCVTPH2PSXZ256rmk:
15479	case VCVTPH2PSXZ256rmkz:
15480	case VCVTPH2PSXZ256rr:
15481	case VCVTPH2PSXZ256rrk:
15482	case VCVTPH2PSXZ256rrkz:
15483	case VCVTPH2PSXZrm:
15484	case VCVTPH2PSXZrmb:
15485	case VCVTPH2PSXZrmbk:
15486	case VCVTPH2PSXZrmbkz:
15487	case VCVTPH2PSXZrmk:
15488	case VCVTPH2PSXZrmkz:
15489	case VCVTPH2PSXZrr:
15490	case VCVTPH2PSXZrrb:
15491	case VCVTPH2PSXZrrbk:
15492	case VCVTPH2PSXZrrbkz:
15493	case VCVTPH2PSXZrrk:
15494	case VCVTPH2PSXZrrkz:
15495		return true;
15496	}
15497	return false;
15498}
15499
15500bool isVFMADDSUB231PH(unsigned Opcode) {
15501	switch (Opcode) {
15502	case VFMADDSUB231PHZ128m:
15503	case VFMADDSUB231PHZ128mb:
15504	case VFMADDSUB231PHZ128mbk:
15505	case VFMADDSUB231PHZ128mbkz:
15506	case VFMADDSUB231PHZ128mk:
15507	case VFMADDSUB231PHZ128mkz:
15508	case VFMADDSUB231PHZ128r:
15509	case VFMADDSUB231PHZ128rk:
15510	case VFMADDSUB231PHZ128rkz:
15511	case VFMADDSUB231PHZ256m:
15512	case VFMADDSUB231PHZ256mb:
15513	case VFMADDSUB231PHZ256mbk:
15514	case VFMADDSUB231PHZ256mbkz:
15515	case VFMADDSUB231PHZ256mk:
15516	case VFMADDSUB231PHZ256mkz:
15517	case VFMADDSUB231PHZ256r:
15518	case VFMADDSUB231PHZ256rk:
15519	case VFMADDSUB231PHZ256rkz:
15520	case VFMADDSUB231PHZm:
15521	case VFMADDSUB231PHZmb:
15522	case VFMADDSUB231PHZmbk:
15523	case VFMADDSUB231PHZmbkz:
15524	case VFMADDSUB231PHZmk:
15525	case VFMADDSUB231PHZmkz:
15526	case VFMADDSUB231PHZr:
15527	case VFMADDSUB231PHZrb:
15528	case VFMADDSUB231PHZrbk:
15529	case VFMADDSUB231PHZrbkz:
15530	case VFMADDSUB231PHZrk:
15531	case VFMADDSUB231PHZrkz:
15532		return true;
15533	}
15534	return false;
15535}
15536
15537bool isBLENDVPD(unsigned Opcode) {
15538	switch (Opcode) {
15539	case BLENDVPDrm0:
15540	case BLENDVPDrr0:
15541		return true;
15542	}
15543	return false;
15544}
15545
15546bool isPSWAPD(unsigned Opcode) {
15547	switch (Opcode) {
15548	case PSWAPDrm:
15549	case PSWAPDrr:
15550		return true;
15551	}
15552	return false;
15553}
15554
15555bool isVMSAVE(unsigned Opcode) {
15556	switch (Opcode) {
15557	case VMSAVE32:
15558	case VMSAVE64:
15559		return true;
15560	}
15561	return false;
15562}
15563
15564bool isVFMADDSUB231PS(unsigned Opcode) {
15565	switch (Opcode) {
15566	case VFMADDSUB231PSYm:
15567	case VFMADDSUB231PSYr:
15568	case VFMADDSUB231PSZ128m:
15569	case VFMADDSUB231PSZ128mb:
15570	case VFMADDSUB231PSZ128mbk:
15571	case VFMADDSUB231PSZ128mbkz:
15572	case VFMADDSUB231PSZ128mk:
15573	case VFMADDSUB231PSZ128mkz:
15574	case VFMADDSUB231PSZ128r:
15575	case VFMADDSUB231PSZ128rk:
15576	case VFMADDSUB231PSZ128rkz:
15577	case VFMADDSUB231PSZ256m:
15578	case VFMADDSUB231PSZ256mb:
15579	case VFMADDSUB231PSZ256mbk:
15580	case VFMADDSUB231PSZ256mbkz:
15581	case VFMADDSUB231PSZ256mk:
15582	case VFMADDSUB231PSZ256mkz:
15583	case VFMADDSUB231PSZ256r:
15584	case VFMADDSUB231PSZ256rk:
15585	case VFMADDSUB231PSZ256rkz:
15586	case VFMADDSUB231PSZm:
15587	case VFMADDSUB231PSZmb:
15588	case VFMADDSUB231PSZmbk:
15589	case VFMADDSUB231PSZmbkz:
15590	case VFMADDSUB231PSZmk:
15591	case VFMADDSUB231PSZmkz:
15592	case VFMADDSUB231PSZr:
15593	case VFMADDSUB231PSZrb:
15594	case VFMADDSUB231PSZrbk:
15595	case VFMADDSUB231PSZrbkz:
15596	case VFMADDSUB231PSZrk:
15597	case VFMADDSUB231PSZrkz:
15598	case VFMADDSUB231PSm:
15599	case VFMADDSUB231PSr:
15600		return true;
15601	}
15602	return false;
15603}
15604
15605bool isTDPBUUD(unsigned Opcode) {
15606	return Opcode == TDPBUUD;
15607}
15608
15609bool isVBLENDMPD(unsigned Opcode) {
15610	switch (Opcode) {
15611	case VBLENDMPDZ128rm:
15612	case VBLENDMPDZ128rmb:
15613	case VBLENDMPDZ128rmbk:
15614	case VBLENDMPDZ128rmbkz:
15615	case VBLENDMPDZ128rmk:
15616	case VBLENDMPDZ128rmkz:
15617	case VBLENDMPDZ128rr:
15618	case VBLENDMPDZ128rrk:
15619	case VBLENDMPDZ128rrkz:
15620	case VBLENDMPDZ256rm:
15621	case VBLENDMPDZ256rmb:
15622	case VBLENDMPDZ256rmbk:
15623	case VBLENDMPDZ256rmbkz:
15624	case VBLENDMPDZ256rmk:
15625	case VBLENDMPDZ256rmkz:
15626	case VBLENDMPDZ256rr:
15627	case VBLENDMPDZ256rrk:
15628	case VBLENDMPDZ256rrkz:
15629	case VBLENDMPDZrm:
15630	case VBLENDMPDZrmb:
15631	case VBLENDMPDZrmbk:
15632	case VBLENDMPDZrmbkz:
15633	case VBLENDMPDZrmk:
15634	case VBLENDMPDZrmkz:
15635	case VBLENDMPDZrr:
15636	case VBLENDMPDZrrk:
15637	case VBLENDMPDZrrkz:
15638		return true;
15639	}
15640	return false;
15641}
15642
15643bool isPFACC(unsigned Opcode) {
15644	switch (Opcode) {
15645	case PFACCrm:
15646	case PFACCrr:
15647		return true;
15648	}
15649	return false;
15650}
15651
15652bool isBLENDVPS(unsigned Opcode) {
15653	switch (Opcode) {
15654	case BLENDVPSrm0:
15655	case BLENDVPSrr0:
15656		return true;
15657	}
15658	return false;
15659}
15660
15661bool isVPERM2I128(unsigned Opcode) {
15662	switch (Opcode) {
15663	case VPERM2I128rm:
15664	case VPERM2I128rr:
15665		return true;
15666	}
15667	return false;
15668}
15669
15670bool isVPCMPGTB(unsigned Opcode) {
15671	switch (Opcode) {
15672	case VPCMPGTBYrm:
15673	case VPCMPGTBYrr:
15674	case VPCMPGTBZ128rm:
15675	case VPCMPGTBZ128rmk:
15676	case VPCMPGTBZ128rr:
15677	case VPCMPGTBZ128rrk:
15678	case VPCMPGTBZ256rm:
15679	case VPCMPGTBZ256rmk:
15680	case VPCMPGTBZ256rr:
15681	case VPCMPGTBZ256rrk:
15682	case VPCMPGTBZrm:
15683	case VPCMPGTBZrmk:
15684	case VPCMPGTBZrr:
15685	case VPCMPGTBZrrk:
15686	case VPCMPGTBrm:
15687	case VPCMPGTBrr:
15688		return true;
15689	}
15690	return false;
15691}
15692
15693bool isLLWPCB(unsigned Opcode) {
15694	switch (Opcode) {
15695	case LLWPCB:
15696	case LLWPCB64:
15697		return true;
15698	}
15699	return false;
15700}
15701
15702bool isVPCMPGTD(unsigned Opcode) {
15703	switch (Opcode) {
15704	case VPCMPGTDYrm:
15705	case VPCMPGTDYrr:
15706	case VPCMPGTDZ128rm:
15707	case VPCMPGTDZ128rmb:
15708	case VPCMPGTDZ128rmbk:
15709	case VPCMPGTDZ128rmk:
15710	case VPCMPGTDZ128rr:
15711	case VPCMPGTDZ128rrk:
15712	case VPCMPGTDZ256rm:
15713	case VPCMPGTDZ256rmb:
15714	case VPCMPGTDZ256rmbk:
15715	case VPCMPGTDZ256rmk:
15716	case VPCMPGTDZ256rr:
15717	case VPCMPGTDZ256rrk:
15718	case VPCMPGTDZrm:
15719	case VPCMPGTDZrmb:
15720	case VPCMPGTDZrmbk:
15721	case VPCMPGTDZrmk:
15722	case VPCMPGTDZrr:
15723	case VPCMPGTDZrrk:
15724	case VPCMPGTDrm:
15725	case VPCMPGTDrr:
15726		return true;
15727	}
15728	return false;
15729}
15730
15731bool isVFMSUBADD213PD(unsigned Opcode) {
15732	switch (Opcode) {
15733	case VFMSUBADD213PDYm:
15734	case VFMSUBADD213PDYr:
15735	case VFMSUBADD213PDZ128m:
15736	case VFMSUBADD213PDZ128mb:
15737	case VFMSUBADD213PDZ128mbk:
15738	case VFMSUBADD213PDZ128mbkz:
15739	case VFMSUBADD213PDZ128mk:
15740	case VFMSUBADD213PDZ128mkz:
15741	case VFMSUBADD213PDZ128r:
15742	case VFMSUBADD213PDZ128rk:
15743	case VFMSUBADD213PDZ128rkz:
15744	case VFMSUBADD213PDZ256m:
15745	case VFMSUBADD213PDZ256mb:
15746	case VFMSUBADD213PDZ256mbk:
15747	case VFMSUBADD213PDZ256mbkz:
15748	case VFMSUBADD213PDZ256mk:
15749	case VFMSUBADD213PDZ256mkz:
15750	case VFMSUBADD213PDZ256r:
15751	case VFMSUBADD213PDZ256rk:
15752	case VFMSUBADD213PDZ256rkz:
15753	case VFMSUBADD213PDZm:
15754	case VFMSUBADD213PDZmb:
15755	case VFMSUBADD213PDZmbk:
15756	case VFMSUBADD213PDZmbkz:
15757	case VFMSUBADD213PDZmk:
15758	case VFMSUBADD213PDZmkz:
15759	case VFMSUBADD213PDZr:
15760	case VFMSUBADD213PDZrb:
15761	case VFMSUBADD213PDZrbk:
15762	case VFMSUBADD213PDZrbkz:
15763	case VFMSUBADD213PDZrk:
15764	case VFMSUBADD213PDZrkz:
15765	case VFMSUBADD213PDm:
15766	case VFMSUBADD213PDr:
15767		return true;
15768	}
15769	return false;
15770}
15771
15772bool isVFMSUBADD213PH(unsigned Opcode) {
15773	switch (Opcode) {
15774	case VFMSUBADD213PHZ128m:
15775	case VFMSUBADD213PHZ128mb:
15776	case VFMSUBADD213PHZ128mbk:
15777	case VFMSUBADD213PHZ128mbkz:
15778	case VFMSUBADD213PHZ128mk:
15779	case VFMSUBADD213PHZ128mkz:
15780	case VFMSUBADD213PHZ128r:
15781	case VFMSUBADD213PHZ128rk:
15782	case VFMSUBADD213PHZ128rkz:
15783	case VFMSUBADD213PHZ256m:
15784	case VFMSUBADD213PHZ256mb:
15785	case VFMSUBADD213PHZ256mbk:
15786	case VFMSUBADD213PHZ256mbkz:
15787	case VFMSUBADD213PHZ256mk:
15788	case VFMSUBADD213PHZ256mkz:
15789	case VFMSUBADD213PHZ256r:
15790	case VFMSUBADD213PHZ256rk:
15791	case VFMSUBADD213PHZ256rkz:
15792	case VFMSUBADD213PHZm:
15793	case VFMSUBADD213PHZmb:
15794	case VFMSUBADD213PHZmbk:
15795	case VFMSUBADD213PHZmbkz:
15796	case VFMSUBADD213PHZmk:
15797	case VFMSUBADD213PHZmkz:
15798	case VFMSUBADD213PHZr:
15799	case VFMSUBADD213PHZrb:
15800	case VFMSUBADD213PHZrbk:
15801	case VFMSUBADD213PHZrbkz:
15802	case VFMSUBADD213PHZrk:
15803	case VFMSUBADD213PHZrkz:
15804		return true;
15805	}
15806	return false;
15807}
15808
15809bool isVBLENDMPS(unsigned Opcode) {
15810	switch (Opcode) {
15811	case VBLENDMPSZ128rm:
15812	case VBLENDMPSZ128rmb:
15813	case VBLENDMPSZ128rmbk:
15814	case VBLENDMPSZ128rmbkz:
15815	case VBLENDMPSZ128rmk:
15816	case VBLENDMPSZ128rmkz:
15817	case VBLENDMPSZ128rr:
15818	case VBLENDMPSZ128rrk:
15819	case VBLENDMPSZ128rrkz:
15820	case VBLENDMPSZ256rm:
15821	case VBLENDMPSZ256rmb:
15822	case VBLENDMPSZ256rmbk:
15823	case VBLENDMPSZ256rmbkz:
15824	case VBLENDMPSZ256rmk:
15825	case VBLENDMPSZ256rmkz:
15826	case VBLENDMPSZ256rr:
15827	case VBLENDMPSZ256rrk:
15828	case VBLENDMPSZ256rrkz:
15829	case VBLENDMPSZrm:
15830	case VBLENDMPSZrmb:
15831	case VBLENDMPSZrmbk:
15832	case VBLENDMPSZrmbkz:
15833	case VBLENDMPSZrmk:
15834	case VBLENDMPSZrmkz:
15835	case VBLENDMPSZrr:
15836	case VBLENDMPSZrrk:
15837	case VBLENDMPSZrrkz:
15838		return true;
15839	}
15840	return false;
15841}
15842
15843bool isVCMPSD(unsigned Opcode) {
15844	switch (Opcode) {
15845	case VCMPSDZrm_Int:
15846	case VCMPSDZrm_Intk:
15847	case VCMPSDZrr_Int:
15848	case VCMPSDZrr_Intk:
15849	case VCMPSDZrrb_Int:
15850	case VCMPSDZrrb_Intk:
15851	case VCMPSDrm_Int:
15852	case VCMPSDrr_Int:
15853		return true;
15854	}
15855	return false;
15856}
15857
15858bool isVCMPSH(unsigned Opcode) {
15859	switch (Opcode) {
15860	case VCMPSHZrm_Int:
15861	case VCMPSHZrm_Intk:
15862	case VCMPSHZrr_Int:
15863	case VCMPSHZrr_Intk:
15864	case VCMPSHZrrb_Int:
15865	case VCMPSHZrrb_Intk:
15866		return true;
15867	}
15868	return false;
15869}
15870
15871bool isVPCMPGTQ(unsigned Opcode) {
15872	switch (Opcode) {
15873	case VPCMPGTQYrm:
15874	case VPCMPGTQYrr:
15875	case VPCMPGTQZ128rm:
15876	case VPCMPGTQZ128rmb:
15877	case VPCMPGTQZ128rmbk:
15878	case VPCMPGTQZ128rmk:
15879	case VPCMPGTQZ128rr:
15880	case VPCMPGTQZ128rrk:
15881	case VPCMPGTQZ256rm:
15882	case VPCMPGTQZ256rmb:
15883	case VPCMPGTQZ256rmbk:
15884	case VPCMPGTQZ256rmk:
15885	case VPCMPGTQZ256rr:
15886	case VPCMPGTQZ256rrk:
15887	case VPCMPGTQZrm:
15888	case VPCMPGTQZrmb:
15889	case VPCMPGTQZrmbk:
15890	case VPCMPGTQZrmk:
15891	case VPCMPGTQZrr:
15892	case VPCMPGTQZrrk:
15893	case VPCMPGTQrm:
15894	case VPCMPGTQrr:
15895		return true;
15896	}
15897	return false;
15898}
15899
15900bool isANDNPD(unsigned Opcode) {
15901	switch (Opcode) {
15902	case ANDNPDrm:
15903	case ANDNPDrr:
15904		return true;
15905	}
15906	return false;
15907}
15908
15909bool isENDBR64(unsigned Opcode) {
15910	return Opcode == ENDBR64;
15911}
15912
15913bool isVFMSUBADD213PS(unsigned Opcode) {
15914	switch (Opcode) {
15915	case VFMSUBADD213PSYm:
15916	case VFMSUBADD213PSYr:
15917	case VFMSUBADD213PSZ128m:
15918	case VFMSUBADD213PSZ128mb:
15919	case VFMSUBADD213PSZ128mbk:
15920	case VFMSUBADD213PSZ128mbkz:
15921	case VFMSUBADD213PSZ128mk:
15922	case VFMSUBADD213PSZ128mkz:
15923	case VFMSUBADD213PSZ128r:
15924	case VFMSUBADD213PSZ128rk:
15925	case VFMSUBADD213PSZ128rkz:
15926	case VFMSUBADD213PSZ256m:
15927	case VFMSUBADD213PSZ256mb:
15928	case VFMSUBADD213PSZ256mbk:
15929	case VFMSUBADD213PSZ256mbkz:
15930	case VFMSUBADD213PSZ256mk:
15931	case VFMSUBADD213PSZ256mkz:
15932	case VFMSUBADD213PSZ256r:
15933	case VFMSUBADD213PSZ256rk:
15934	case VFMSUBADD213PSZ256rkz:
15935	case VFMSUBADD213PSZm:
15936	case VFMSUBADD213PSZmb:
15937	case VFMSUBADD213PSZmbk:
15938	case VFMSUBADD213PSZmbkz:
15939	case VFMSUBADD213PSZmk:
15940	case VFMSUBADD213PSZmkz:
15941	case VFMSUBADD213PSZr:
15942	case VFMSUBADD213PSZrb:
15943	case VFMSUBADD213PSZrbk:
15944	case VFMSUBADD213PSZrbkz:
15945	case VFMSUBADD213PSZrk:
15946	case VFMSUBADD213PSZrkz:
15947	case VFMSUBADD213PSm:
15948	case VFMSUBADD213PSr:
15949		return true;
15950	}
15951	return false;
15952}
15953
15954bool isVPCMPGTW(unsigned Opcode) {
15955	switch (Opcode) {
15956	case VPCMPGTWYrm:
15957	case VPCMPGTWYrr:
15958	case VPCMPGTWZ128rm:
15959	case VPCMPGTWZ128rmk:
15960	case VPCMPGTWZ128rr:
15961	case VPCMPGTWZ128rrk:
15962	case VPCMPGTWZ256rm:
15963	case VPCMPGTWZ256rmk:
15964	case VPCMPGTWZ256rr:
15965	case VPCMPGTWZ256rrk:
15966	case VPCMPGTWZrm:
15967	case VPCMPGTWZrmk:
15968	case VPCMPGTWZrr:
15969	case VPCMPGTWZrrk:
15970	case VPCMPGTWrm:
15971	case VPCMPGTWrr:
15972		return true;
15973	}
15974	return false;
15975}
15976
15977bool isVCMPSS(unsigned Opcode) {
15978	switch (Opcode) {
15979	case VCMPSSZrm_Int:
15980	case VCMPSSZrm_Intk:
15981	case VCMPSSZrr_Int:
15982	case VCMPSSZrr_Intk:
15983	case VCMPSSZrrb_Int:
15984	case VCMPSSZrrb_Intk:
15985	case VCMPSSrm_Int:
15986	case VCMPSSrr_Int:
15987		return true;
15988	}
15989	return false;
15990}
15991
15992bool isPFADD(unsigned Opcode) {
15993	switch (Opcode) {
15994	case PFADDrm:
15995	case PFADDrr:
15996		return true;
15997	}
15998	return false;
15999}
16000
16001bool isVMOVLHPS(unsigned Opcode) {
16002	switch (Opcode) {
16003	case VMOVLHPSZrr:
16004	case VMOVLHPSrr:
16005		return true;
16006	}
16007	return false;
16008}
16009
16010bool isVPMINSD(unsigned Opcode) {
16011	switch (Opcode) {
16012	case VPMINSDYrm:
16013	case VPMINSDYrr:
16014	case VPMINSDZ128rm:
16015	case VPMINSDZ128rmb:
16016	case VPMINSDZ128rmbk:
16017	case VPMINSDZ128rmbkz:
16018	case VPMINSDZ128rmk:
16019	case VPMINSDZ128rmkz:
16020	case VPMINSDZ128rr:
16021	case VPMINSDZ128rrk:
16022	case VPMINSDZ128rrkz:
16023	case VPMINSDZ256rm:
16024	case VPMINSDZ256rmb:
16025	case VPMINSDZ256rmbk:
16026	case VPMINSDZ256rmbkz:
16027	case VPMINSDZ256rmk:
16028	case VPMINSDZ256rmkz:
16029	case VPMINSDZ256rr:
16030	case VPMINSDZ256rrk:
16031	case VPMINSDZ256rrkz:
16032	case VPMINSDZrm:
16033	case VPMINSDZrmb:
16034	case VPMINSDZrmbk:
16035	case VPMINSDZrmbkz:
16036	case VPMINSDZrmk:
16037	case VPMINSDZrmkz:
16038	case VPMINSDZrr:
16039	case VPMINSDZrrk:
16040	case VPMINSDZrrkz:
16041	case VPMINSDrm:
16042	case VPMINSDrr:
16043		return true;
16044	}
16045	return false;
16046}
16047
16048bool isVPMINSB(unsigned Opcode) {
16049	switch (Opcode) {
16050	case VPMINSBYrm:
16051	case VPMINSBYrr:
16052	case VPMINSBZ128rm:
16053	case VPMINSBZ128rmk:
16054	case VPMINSBZ128rmkz:
16055	case VPMINSBZ128rr:
16056	case VPMINSBZ128rrk:
16057	case VPMINSBZ128rrkz:
16058	case VPMINSBZ256rm:
16059	case VPMINSBZ256rmk:
16060	case VPMINSBZ256rmkz:
16061	case VPMINSBZ256rr:
16062	case VPMINSBZ256rrk:
16063	case VPMINSBZ256rrkz:
16064	case VPMINSBZrm:
16065	case VPMINSBZrmk:
16066	case VPMINSBZrmkz:
16067	case VPMINSBZrr:
16068	case VPMINSBZrrk:
16069	case VPMINSBZrrkz:
16070	case VPMINSBrm:
16071	case VPMINSBrr:
16072		return true;
16073	}
16074	return false;
16075}
16076
16077bool isANDNPS(unsigned Opcode) {
16078	switch (Opcode) {
16079	case ANDNPSrm:
16080	case ANDNPSrr:
16081		return true;
16082	}
16083	return false;
16084}
16085
16086bool isPHADDSW(unsigned Opcode) {
16087	switch (Opcode) {
16088	case MMX_PHADDSWrm:
16089	case MMX_PHADDSWrr:
16090	case PHADDSWrm:
16091	case PHADDSWrr:
16092		return true;
16093	}
16094	return false;
16095}
16096
16097bool isVPSLLVD(unsigned Opcode) {
16098	switch (Opcode) {
16099	case VPSLLVDYrm:
16100	case VPSLLVDYrr:
16101	case VPSLLVDZ128rm:
16102	case VPSLLVDZ128rmb:
16103	case VPSLLVDZ128rmbk:
16104	case VPSLLVDZ128rmbkz:
16105	case VPSLLVDZ128rmk:
16106	case VPSLLVDZ128rmkz:
16107	case VPSLLVDZ128rr:
16108	case VPSLLVDZ128rrk:
16109	case VPSLLVDZ128rrkz:
16110	case VPSLLVDZ256rm:
16111	case VPSLLVDZ256rmb:
16112	case VPSLLVDZ256rmbk:
16113	case VPSLLVDZ256rmbkz:
16114	case VPSLLVDZ256rmk:
16115	case VPSLLVDZ256rmkz:
16116	case VPSLLVDZ256rr:
16117	case VPSLLVDZ256rrk:
16118	case VPSLLVDZ256rrkz:
16119	case VPSLLVDZrm:
16120	case VPSLLVDZrmb:
16121	case VPSLLVDZrmbk:
16122	case VPSLLVDZrmbkz:
16123	case VPSLLVDZrmk:
16124	case VPSLLVDZrmkz:
16125	case VPSLLVDZrr:
16126	case VPSLLVDZrrk:
16127	case VPSLLVDZrrkz:
16128	case VPSLLVDrm:
16129	case VPSLLVDrr:
16130		return true;
16131	}
16132	return false;
16133}
16134
16135bool isVDIVPD(unsigned Opcode) {
16136	switch (Opcode) {
16137	case VDIVPDYrm:
16138	case VDIVPDYrr:
16139	case VDIVPDZ128rm:
16140	case VDIVPDZ128rmb:
16141	case VDIVPDZ128rmbk:
16142	case VDIVPDZ128rmbkz:
16143	case VDIVPDZ128rmk:
16144	case VDIVPDZ128rmkz:
16145	case VDIVPDZ128rr:
16146	case VDIVPDZ128rrk:
16147	case VDIVPDZ128rrkz:
16148	case VDIVPDZ256rm:
16149	case VDIVPDZ256rmb:
16150	case VDIVPDZ256rmbk:
16151	case VDIVPDZ256rmbkz:
16152	case VDIVPDZ256rmk:
16153	case VDIVPDZ256rmkz:
16154	case VDIVPDZ256rr:
16155	case VDIVPDZ256rrk:
16156	case VDIVPDZ256rrkz:
16157	case VDIVPDZrm:
16158	case VDIVPDZrmb:
16159	case VDIVPDZrmbk:
16160	case VDIVPDZrmbkz:
16161	case VDIVPDZrmk:
16162	case VDIVPDZrmkz:
16163	case VDIVPDZrr:
16164	case VDIVPDZrrb:
16165	case VDIVPDZrrbk:
16166	case VDIVPDZrrbkz:
16167	case VDIVPDZrrk:
16168	case VDIVPDZrrkz:
16169	case VDIVPDrm:
16170	case VDIVPDrr:
16171		return true;
16172	}
16173	return false;
16174}
16175
16176bool isVPMINSQ(unsigned Opcode) {
16177	switch (Opcode) {
16178	case VPMINSQZ128rm:
16179	case VPMINSQZ128rmb:
16180	case VPMINSQZ128rmbk:
16181	case VPMINSQZ128rmbkz:
16182	case VPMINSQZ128rmk:
16183	case VPMINSQZ128rmkz:
16184	case VPMINSQZ128rr:
16185	case VPMINSQZ128rrk:
16186	case VPMINSQZ128rrkz:
16187	case VPMINSQZ256rm:
16188	case VPMINSQZ256rmb:
16189	case VPMINSQZ256rmbk:
16190	case VPMINSQZ256rmbkz:
16191	case VPMINSQZ256rmk:
16192	case VPMINSQZ256rmkz:
16193	case VPMINSQZ256rr:
16194	case VPMINSQZ256rrk:
16195	case VPMINSQZ256rrkz:
16196	case VPMINSQZrm:
16197	case VPMINSQZrmb:
16198	case VPMINSQZrmbk:
16199	case VPMINSQZrmbkz:
16200	case VPMINSQZrmk:
16201	case VPMINSQZrmkz:
16202	case VPMINSQZrr:
16203	case VPMINSQZrrk:
16204	case VPMINSQZrrkz:
16205		return true;
16206	}
16207	return false;
16208}
16209
16210bool isVDIVPH(unsigned Opcode) {
16211	switch (Opcode) {
16212	case VDIVPHZ128rm:
16213	case VDIVPHZ128rmb:
16214	case VDIVPHZ128rmbk:
16215	case VDIVPHZ128rmbkz:
16216	case VDIVPHZ128rmk:
16217	case VDIVPHZ128rmkz:
16218	case VDIVPHZ128rr:
16219	case VDIVPHZ128rrk:
16220	case VDIVPHZ128rrkz:
16221	case VDIVPHZ256rm:
16222	case VDIVPHZ256rmb:
16223	case VDIVPHZ256rmbk:
16224	case VDIVPHZ256rmbkz:
16225	case VDIVPHZ256rmk:
16226	case VDIVPHZ256rmkz:
16227	case VDIVPHZ256rr:
16228	case VDIVPHZ256rrk:
16229	case VDIVPHZ256rrkz:
16230	case VDIVPHZrm:
16231	case VDIVPHZrmb:
16232	case VDIVPHZrmbk:
16233	case VDIVPHZrmbkz:
16234	case VDIVPHZrmk:
16235	case VDIVPHZrmkz:
16236	case VDIVPHZrr:
16237	case VDIVPHZrrb:
16238	case VDIVPHZrrbk:
16239	case VDIVPHZrrbkz:
16240	case VDIVPHZrrk:
16241	case VDIVPHZrrkz:
16242		return true;
16243	}
16244	return false;
16245}
16246
16247bool isVPMINSW(unsigned Opcode) {
16248	switch (Opcode) {
16249	case VPMINSWYrm:
16250	case VPMINSWYrr:
16251	case VPMINSWZ128rm:
16252	case VPMINSWZ128rmk:
16253	case VPMINSWZ128rmkz:
16254	case VPMINSWZ128rr:
16255	case VPMINSWZ128rrk:
16256	case VPMINSWZ128rrkz:
16257	case VPMINSWZ256rm:
16258	case VPMINSWZ256rmk:
16259	case VPMINSWZ256rmkz:
16260	case VPMINSWZ256rr:
16261	case VPMINSWZ256rrk:
16262	case VPMINSWZ256rrkz:
16263	case VPMINSWZrm:
16264	case VPMINSWZrmk:
16265	case VPMINSWZrmkz:
16266	case VPMINSWZrr:
16267	case VPMINSWZrrk:
16268	case VPMINSWZrrkz:
16269	case VPMINSWrm:
16270	case VPMINSWrr:
16271		return true;
16272	}
16273	return false;
16274}
16275
16276bool isVFNMSUBPD(unsigned Opcode) {
16277	switch (Opcode) {
16278	case VFNMSUBPD4Ymr:
16279	case VFNMSUBPD4Yrm:
16280	case VFNMSUBPD4Yrr:
16281	case VFNMSUBPD4Yrr_REV:
16282	case VFNMSUBPD4mr:
16283	case VFNMSUBPD4rm:
16284	case VFNMSUBPD4rr:
16285	case VFNMSUBPD4rr_REV:
16286		return true;
16287	}
16288	return false;
16289}
16290
16291bool isLWPVAL(unsigned Opcode) {
16292	switch (Opcode) {
16293	case LWPVAL32rmi:
16294	case LWPVAL32rri:
16295	case LWPVAL64rmi:
16296	case LWPVAL64rri:
16297		return true;
16298	}
16299	return false;
16300}
16301
16302bool isAESDEC128KL(unsigned Opcode) {
16303	return Opcode == AESDEC128KL;
16304}
16305
16306bool isFIADD(unsigned Opcode) {
16307	switch (Opcode) {
16308	case ADD_FI16m:
16309	case ADD_FI32m:
16310		return true;
16311	}
16312	return false;
16313}
16314
16315bool isVPAND(unsigned Opcode) {
16316	switch (Opcode) {
16317	case VPANDYrm:
16318	case VPANDYrr:
16319	case VPANDrm:
16320	case VPANDrr:
16321		return true;
16322	}
16323	return false;
16324}
16325
16326bool isMOVSLDUP(unsigned Opcode) {
16327	switch (Opcode) {
16328	case MOVSLDUPrm:
16329	case MOVSLDUPrr:
16330		return true;
16331	}
16332	return false;
16333}
16334
16335bool isVPSLLVQ(unsigned Opcode) {
16336	switch (Opcode) {
16337	case VPSLLVQYrm:
16338	case VPSLLVQYrr:
16339	case VPSLLVQZ128rm:
16340	case VPSLLVQZ128rmb:
16341	case VPSLLVQZ128rmbk:
16342	case VPSLLVQZ128rmbkz:
16343	case VPSLLVQZ128rmk:
16344	case VPSLLVQZ128rmkz:
16345	case VPSLLVQZ128rr:
16346	case VPSLLVQZ128rrk:
16347	case VPSLLVQZ128rrkz:
16348	case VPSLLVQZ256rm:
16349	case VPSLLVQZ256rmb:
16350	case VPSLLVQZ256rmbk:
16351	case VPSLLVQZ256rmbkz:
16352	case VPSLLVQZ256rmk:
16353	case VPSLLVQZ256rmkz:
16354	case VPSLLVQZ256rr:
16355	case VPSLLVQZ256rrk:
16356	case VPSLLVQZ256rrkz:
16357	case VPSLLVQZrm:
16358	case VPSLLVQZrmb:
16359	case VPSLLVQZrmbk:
16360	case VPSLLVQZrmbkz:
16361	case VPSLLVQZrmk:
16362	case VPSLLVQZrmkz:
16363	case VPSLLVQZrr:
16364	case VPSLLVQZrrk:
16365	case VPSLLVQZrrkz:
16366	case VPSLLVQrm:
16367	case VPSLLVQrr:
16368		return true;
16369	}
16370	return false;
16371}
16372
16373bool isVDIVPS(unsigned Opcode) {
16374	switch (Opcode) {
16375	case VDIVPSYrm:
16376	case VDIVPSYrr:
16377	case VDIVPSZ128rm:
16378	case VDIVPSZ128rmb:
16379	case VDIVPSZ128rmbk:
16380	case VDIVPSZ128rmbkz:
16381	case VDIVPSZ128rmk:
16382	case VDIVPSZ128rmkz:
16383	case VDIVPSZ128rr:
16384	case VDIVPSZ128rrk:
16385	case VDIVPSZ128rrkz:
16386	case VDIVPSZ256rm:
16387	case VDIVPSZ256rmb:
16388	case VDIVPSZ256rmbk:
16389	case VDIVPSZ256rmbkz:
16390	case VDIVPSZ256rmk:
16391	case VDIVPSZ256rmkz:
16392	case VDIVPSZ256rr:
16393	case VDIVPSZ256rrk:
16394	case VDIVPSZ256rrkz:
16395	case VDIVPSZrm:
16396	case VDIVPSZrmb:
16397	case VDIVPSZrmbk:
16398	case VDIVPSZrmbkz:
16399	case VDIVPSZrmk:
16400	case VDIVPSZrmkz:
16401	case VDIVPSZrr:
16402	case VDIVPSZrrb:
16403	case VDIVPSZrrbk:
16404	case VDIVPSZrrbkz:
16405	case VDIVPSZrrk:
16406	case VDIVPSZrrkz:
16407	case VDIVPSrm:
16408	case VDIVPSrr:
16409		return true;
16410	}
16411	return false;
16412}
16413
16414bool isCWD(unsigned Opcode) {
16415	return Opcode == CWD;
16416}
16417
16418bool isVPSLLVW(unsigned Opcode) {
16419	switch (Opcode) {
16420	case VPSLLVWZ128rm:
16421	case VPSLLVWZ128rmk:
16422	case VPSLLVWZ128rmkz:
16423	case VPSLLVWZ128rr:
16424	case VPSLLVWZ128rrk:
16425	case VPSLLVWZ128rrkz:
16426	case VPSLLVWZ256rm:
16427	case VPSLLVWZ256rmk:
16428	case VPSLLVWZ256rmkz:
16429	case VPSLLVWZ256rr:
16430	case VPSLLVWZ256rrk:
16431	case VPSLLVWZ256rrkz:
16432	case VPSLLVWZrm:
16433	case VPSLLVWZrmk:
16434	case VPSLLVWZrmkz:
16435	case VPSLLVWZrr:
16436	case VPSLLVWZrrk:
16437	case VPSLLVWZrrkz:
16438		return true;
16439	}
16440	return false;
16441}
16442
16443bool isCWDE(unsigned Opcode) {
16444	return Opcode == CWDE;
16445}
16446
16447bool isVFNMSUBPS(unsigned Opcode) {
16448	switch (Opcode) {
16449	case VFNMSUBPS4Ymr:
16450	case VFNMSUBPS4Yrm:
16451	case VFNMSUBPS4Yrr:
16452	case VFNMSUBPS4Yrr_REV:
16453	case VFNMSUBPS4mr:
16454	case VFNMSUBPS4rm:
16455	case VFNMSUBPS4rr:
16456	case VFNMSUBPS4rr_REV:
16457		return true;
16458	}
16459	return false;
16460}
16461
16462bool isVFMSUBADD231PD(unsigned Opcode) {
16463	switch (Opcode) {
16464	case VFMSUBADD231PDYm:
16465	case VFMSUBADD231PDYr:
16466	case VFMSUBADD231PDZ128m:
16467	case VFMSUBADD231PDZ128mb:
16468	case VFMSUBADD231PDZ128mbk:
16469	case VFMSUBADD231PDZ128mbkz:
16470	case VFMSUBADD231PDZ128mk:
16471	case VFMSUBADD231PDZ128mkz:
16472	case VFMSUBADD231PDZ128r:
16473	case VFMSUBADD231PDZ128rk:
16474	case VFMSUBADD231PDZ128rkz:
16475	case VFMSUBADD231PDZ256m:
16476	case VFMSUBADD231PDZ256mb:
16477	case VFMSUBADD231PDZ256mbk:
16478	case VFMSUBADD231PDZ256mbkz:
16479	case VFMSUBADD231PDZ256mk:
16480	case VFMSUBADD231PDZ256mkz:
16481	case VFMSUBADD231PDZ256r:
16482	case VFMSUBADD231PDZ256rk:
16483	case VFMSUBADD231PDZ256rkz:
16484	case VFMSUBADD231PDZm:
16485	case VFMSUBADD231PDZmb:
16486	case VFMSUBADD231PDZmbk:
16487	case VFMSUBADD231PDZmbkz:
16488	case VFMSUBADD231PDZmk:
16489	case VFMSUBADD231PDZmkz:
16490	case VFMSUBADD231PDZr:
16491	case VFMSUBADD231PDZrb:
16492	case VFMSUBADD231PDZrbk:
16493	case VFMSUBADD231PDZrbkz:
16494	case VFMSUBADD231PDZrk:
16495	case VFMSUBADD231PDZrkz:
16496	case VFMSUBADD231PDm:
16497	case VFMSUBADD231PDr:
16498		return true;
16499	}
16500	return false;
16501}
16502
16503bool isVPDPBUSD(unsigned Opcode) {
16504	switch (Opcode) {
16505	case VPDPBUSDYrm:
16506	case VPDPBUSDYrr:
16507	case VPDPBUSDZ128m:
16508	case VPDPBUSDZ128mb:
16509	case VPDPBUSDZ128mbk:
16510	case VPDPBUSDZ128mbkz:
16511	case VPDPBUSDZ128mk:
16512	case VPDPBUSDZ128mkz:
16513	case VPDPBUSDZ128r:
16514	case VPDPBUSDZ128rk:
16515	case VPDPBUSDZ128rkz:
16516	case VPDPBUSDZ256m:
16517	case VPDPBUSDZ256mb:
16518	case VPDPBUSDZ256mbk:
16519	case VPDPBUSDZ256mbkz:
16520	case VPDPBUSDZ256mk:
16521	case VPDPBUSDZ256mkz:
16522	case VPDPBUSDZ256r:
16523	case VPDPBUSDZ256rk:
16524	case VPDPBUSDZ256rkz:
16525	case VPDPBUSDZm:
16526	case VPDPBUSDZmb:
16527	case VPDPBUSDZmbk:
16528	case VPDPBUSDZmbkz:
16529	case VPDPBUSDZmk:
16530	case VPDPBUSDZmkz:
16531	case VPDPBUSDZr:
16532	case VPDPBUSDZrk:
16533	case VPDPBUSDZrkz:
16534	case VPDPBUSDrm:
16535	case VPDPBUSDrr:
16536		return true;
16537	}
16538	return false;
16539}
16540
16541bool isVFMSUBADD231PH(unsigned Opcode) {
16542	switch (Opcode) {
16543	case VFMSUBADD231PHZ128m:
16544	case VFMSUBADD231PHZ128mb:
16545	case VFMSUBADD231PHZ128mbk:
16546	case VFMSUBADD231PHZ128mbkz:
16547	case VFMSUBADD231PHZ128mk:
16548	case VFMSUBADD231PHZ128mkz:
16549	case VFMSUBADD231PHZ128r:
16550	case VFMSUBADD231PHZ128rk:
16551	case VFMSUBADD231PHZ128rkz:
16552	case VFMSUBADD231PHZ256m:
16553	case VFMSUBADD231PHZ256mb:
16554	case VFMSUBADD231PHZ256mbk:
16555	case VFMSUBADD231PHZ256mbkz:
16556	case VFMSUBADD231PHZ256mk:
16557	case VFMSUBADD231PHZ256mkz:
16558	case VFMSUBADD231PHZ256r:
16559	case VFMSUBADD231PHZ256rk:
16560	case VFMSUBADD231PHZ256rkz:
16561	case VFMSUBADD231PHZm:
16562	case VFMSUBADD231PHZmb:
16563	case VFMSUBADD231PHZmbk:
16564	case VFMSUBADD231PHZmbkz:
16565	case VFMSUBADD231PHZmk:
16566	case VFMSUBADD231PHZmkz:
16567	case VFMSUBADD231PHZr:
16568	case VFMSUBADD231PHZrb:
16569	case VFMSUBADD231PHZrbk:
16570	case VFMSUBADD231PHZrbkz:
16571	case VFMSUBADD231PHZrk:
16572	case VFMSUBADD231PHZrkz:
16573		return true;
16574	}
16575	return false;
16576}
16577
16578bool isPFNACC(unsigned Opcode) {
16579	switch (Opcode) {
16580	case PFNACCrm:
16581	case PFNACCrr:
16582		return true;
16583	}
16584	return false;
16585}
16586
16587bool isPFRSQRT(unsigned Opcode) {
16588	switch (Opcode) {
16589	case PFRSQRTrm:
16590	case PFRSQRTrr:
16591		return true;
16592	}
16593	return false;
16594}
16595
16596bool isVPMACSDD(unsigned Opcode) {
16597	switch (Opcode) {
16598	case VPMACSDDrm:
16599	case VPMACSDDrr:
16600		return true;
16601	}
16602	return false;
16603}
16604
16605bool isVFMSUBADD231PS(unsigned Opcode) {
16606	switch (Opcode) {
16607	case VFMSUBADD231PSYm:
16608	case VFMSUBADD231PSYr:
16609	case VFMSUBADD231PSZ128m:
16610	case VFMSUBADD231PSZ128mb:
16611	case VFMSUBADD231PSZ128mbk:
16612	case VFMSUBADD231PSZ128mbkz:
16613	case VFMSUBADD231PSZ128mk:
16614	case VFMSUBADD231PSZ128mkz:
16615	case VFMSUBADD231PSZ128r:
16616	case VFMSUBADD231PSZ128rk:
16617	case VFMSUBADD231PSZ128rkz:
16618	case VFMSUBADD231PSZ256m:
16619	case VFMSUBADD231PSZ256mb:
16620	case VFMSUBADD231PSZ256mbk:
16621	case VFMSUBADD231PSZ256mbkz:
16622	case VFMSUBADD231PSZ256mk:
16623	case VFMSUBADD231PSZ256mkz:
16624	case VFMSUBADD231PSZ256r:
16625	case VFMSUBADD231PSZ256rk:
16626	case VFMSUBADD231PSZ256rkz:
16627	case VFMSUBADD231PSZm:
16628	case VFMSUBADD231PSZmb:
16629	case VFMSUBADD231PSZmbk:
16630	case VFMSUBADD231PSZmbkz:
16631	case VFMSUBADD231PSZmk:
16632	case VFMSUBADD231PSZmkz:
16633	case VFMSUBADD231PSZr:
16634	case VFMSUBADD231PSZrb:
16635	case VFMSUBADD231PSZrbk:
16636	case VFMSUBADD231PSZrbkz:
16637	case VFMSUBADD231PSZrk:
16638	case VFMSUBADD231PSZrkz:
16639	case VFMSUBADD231PSm:
16640	case VFMSUBADD231PSr:
16641		return true;
16642	}
16643	return false;
16644}
16645
16646bool isFRSTOR(unsigned Opcode) {
16647	return Opcode == FRSTORm;
16648}
16649
16650bool isVPMINUB(unsigned Opcode) {
16651	switch (Opcode) {
16652	case VPMINUBYrm:
16653	case VPMINUBYrr:
16654	case VPMINUBZ128rm:
16655	case VPMINUBZ128rmk:
16656	case VPMINUBZ128rmkz:
16657	case VPMINUBZ128rr:
16658	case VPMINUBZ128rrk:
16659	case VPMINUBZ128rrkz:
16660	case VPMINUBZ256rm:
16661	case VPMINUBZ256rmk:
16662	case VPMINUBZ256rmkz:
16663	case VPMINUBZ256rr:
16664	case VPMINUBZ256rrk:
16665	case VPMINUBZ256rrkz:
16666	case VPMINUBZrm:
16667	case VPMINUBZrmk:
16668	case VPMINUBZrmkz:
16669	case VPMINUBZrr:
16670	case VPMINUBZrrk:
16671	case VPMINUBZrrkz:
16672	case VPMINUBrm:
16673	case VPMINUBrr:
16674		return true;
16675	}
16676	return false;
16677}
16678
16679bool isVPMINUD(unsigned Opcode) {
16680	switch (Opcode) {
16681	case VPMINUDYrm:
16682	case VPMINUDYrr:
16683	case VPMINUDZ128rm:
16684	case VPMINUDZ128rmb:
16685	case VPMINUDZ128rmbk:
16686	case VPMINUDZ128rmbkz:
16687	case VPMINUDZ128rmk:
16688	case VPMINUDZ128rmkz:
16689	case VPMINUDZ128rr:
16690	case VPMINUDZ128rrk:
16691	case VPMINUDZ128rrkz:
16692	case VPMINUDZ256rm:
16693	case VPMINUDZ256rmb:
16694	case VPMINUDZ256rmbk:
16695	case VPMINUDZ256rmbkz:
16696	case VPMINUDZ256rmk:
16697	case VPMINUDZ256rmkz:
16698	case VPMINUDZ256rr:
16699	case VPMINUDZ256rrk:
16700	case VPMINUDZ256rrkz:
16701	case VPMINUDZrm:
16702	case VPMINUDZrmb:
16703	case VPMINUDZrmbk:
16704	case VPMINUDZrmbkz:
16705	case VPMINUDZrmk:
16706	case VPMINUDZrmkz:
16707	case VPMINUDZrr:
16708	case VPMINUDZrrk:
16709	case VPMINUDZrrkz:
16710	case VPMINUDrm:
16711	case VPMINUDrr:
16712		return true;
16713	}
16714	return false;
16715}
16716
16717bool isKUNPCKBW(unsigned Opcode) {
16718	return Opcode == KUNPCKBWrr;
16719}
16720
16721bool isDPPD(unsigned Opcode) {
16722	switch (Opcode) {
16723	case DPPDrmi:
16724	case DPPDrri:
16725		return true;
16726	}
16727	return false;
16728}
16729
16730bool isVAESIMC(unsigned Opcode) {
16731	switch (Opcode) {
16732	case VAESIMCrm:
16733	case VAESIMCrr:
16734		return true;
16735	}
16736	return false;
16737}
16738
16739bool isPTEST(unsigned Opcode) {
16740	switch (Opcode) {
16741	case PTESTrm:
16742	case PTESTrr:
16743		return true;
16744	}
16745	return false;
16746}
16747
16748bool isVPMINUQ(unsigned Opcode) {
16749	switch (Opcode) {
16750	case VPMINUQZ128rm:
16751	case VPMINUQZ128rmb:
16752	case VPMINUQZ128rmbk:
16753	case VPMINUQZ128rmbkz:
16754	case VPMINUQZ128rmk:
16755	case VPMINUQZ128rmkz:
16756	case VPMINUQZ128rr:
16757	case VPMINUQZ128rrk:
16758	case VPMINUQZ128rrkz:
16759	case VPMINUQZ256rm:
16760	case VPMINUQZ256rmb:
16761	case VPMINUQZ256rmbk:
16762	case VPMINUQZ256rmbkz:
16763	case VPMINUQZ256rmk:
16764	case VPMINUQZ256rmkz:
16765	case VPMINUQZ256rr:
16766	case VPMINUQZ256rrk:
16767	case VPMINUQZ256rrkz:
16768	case VPMINUQZrm:
16769	case VPMINUQZrmb:
16770	case VPMINUQZrmbk:
16771	case VPMINUQZrmbkz:
16772	case VPMINUQZrmk:
16773	case VPMINUQZrmkz:
16774	case VPMINUQZrr:
16775	case VPMINUQZrrk:
16776	case VPMINUQZrrkz:
16777		return true;
16778	}
16779	return false;
16780}
16781
16782bool isUCOMISD(unsigned Opcode) {
16783	switch (Opcode) {
16784	case UCOMISDrm:
16785	case UCOMISDrr:
16786		return true;
16787	}
16788	return false;
16789}
16790
16791bool isVPMINUW(unsigned Opcode) {
16792	switch (Opcode) {
16793	case VPMINUWYrm:
16794	case VPMINUWYrr:
16795	case VPMINUWZ128rm:
16796	case VPMINUWZ128rmk:
16797	case VPMINUWZ128rmkz:
16798	case VPMINUWZ128rr:
16799	case VPMINUWZ128rrk:
16800	case VPMINUWZ128rrkz:
16801	case VPMINUWZ256rm:
16802	case VPMINUWZ256rmk:
16803	case VPMINUWZ256rmkz:
16804	case VPMINUWZ256rr:
16805	case VPMINUWZ256rrk:
16806	case VPMINUWZ256rrkz:
16807	case VPMINUWZrm:
16808	case VPMINUWZrmk:
16809	case VPMINUWZrmkz:
16810	case VPMINUWZrr:
16811	case VPMINUWZrrk:
16812	case VPMINUWZrrkz:
16813	case VPMINUWrm:
16814	case VPMINUWrr:
16815		return true;
16816	}
16817	return false;
16818}
16819
16820bool isDPPS(unsigned Opcode) {
16821	switch (Opcode) {
16822	case DPPSrmi:
16823	case DPPSrri:
16824		return true;
16825	}
16826	return false;
16827}
16828
16829bool isFLDLG2(unsigned Opcode) {
16830	return Opcode == FLDLG2;
16831}
16832
16833bool isVPMOVD2M(unsigned Opcode) {
16834	switch (Opcode) {
16835	case VPMOVD2MZ128rr:
16836	case VPMOVD2MZ256rr:
16837	case VPMOVD2MZrr:
16838		return true;
16839	}
16840	return false;
16841}
16842
16843bool isVMOVAPD(unsigned Opcode) {
16844	switch (Opcode) {
16845	case VMOVAPDYmr:
16846	case VMOVAPDYrm:
16847	case VMOVAPDYrr:
16848	case VMOVAPDYrr_REV:
16849	case VMOVAPDZ128mr:
16850	case VMOVAPDZ128mrk:
16851	case VMOVAPDZ128rm:
16852	case VMOVAPDZ128rmk:
16853	case VMOVAPDZ128rmkz:
16854	case VMOVAPDZ128rr:
16855	case VMOVAPDZ128rr_REV:
16856	case VMOVAPDZ128rrk:
16857	case VMOVAPDZ128rrk_REV:
16858	case VMOVAPDZ128rrkz:
16859	case VMOVAPDZ128rrkz_REV:
16860	case VMOVAPDZ256mr:
16861	case VMOVAPDZ256mrk:
16862	case VMOVAPDZ256rm:
16863	case VMOVAPDZ256rmk:
16864	case VMOVAPDZ256rmkz:
16865	case VMOVAPDZ256rr:
16866	case VMOVAPDZ256rr_REV:
16867	case VMOVAPDZ256rrk:
16868	case VMOVAPDZ256rrk_REV:
16869	case VMOVAPDZ256rrkz:
16870	case VMOVAPDZ256rrkz_REV:
16871	case VMOVAPDZmr:
16872	case VMOVAPDZmrk:
16873	case VMOVAPDZrm:
16874	case VMOVAPDZrmk:
16875	case VMOVAPDZrmkz:
16876	case VMOVAPDZrr:
16877	case VMOVAPDZrr_REV:
16878	case VMOVAPDZrrk:
16879	case VMOVAPDZrrk_REV:
16880	case VMOVAPDZrrkz:
16881	case VMOVAPDZrrkz_REV:
16882	case VMOVAPDmr:
16883	case VMOVAPDrm:
16884	case VMOVAPDrr:
16885	case VMOVAPDrr_REV:
16886		return true;
16887	}
16888	return false;
16889}
16890
16891bool isVPSRLD(unsigned Opcode) {
16892	switch (Opcode) {
16893	case VPSRLDYri:
16894	case VPSRLDYrm:
16895	case VPSRLDYrr:
16896	case VPSRLDZ128mbi:
16897	case VPSRLDZ128mbik:
16898	case VPSRLDZ128mbikz:
16899	case VPSRLDZ128mi:
16900	case VPSRLDZ128mik:
16901	case VPSRLDZ128mikz:
16902	case VPSRLDZ128ri:
16903	case VPSRLDZ128rik:
16904	case VPSRLDZ128rikz:
16905	case VPSRLDZ128rm:
16906	case VPSRLDZ128rmk:
16907	case VPSRLDZ128rmkz:
16908	case VPSRLDZ128rr:
16909	case VPSRLDZ128rrk:
16910	case VPSRLDZ128rrkz:
16911	case VPSRLDZ256mbi:
16912	case VPSRLDZ256mbik:
16913	case VPSRLDZ256mbikz:
16914	case VPSRLDZ256mi:
16915	case VPSRLDZ256mik:
16916	case VPSRLDZ256mikz:
16917	case VPSRLDZ256ri:
16918	case VPSRLDZ256rik:
16919	case VPSRLDZ256rikz:
16920	case VPSRLDZ256rm:
16921	case VPSRLDZ256rmk:
16922	case VPSRLDZ256rmkz:
16923	case VPSRLDZ256rr:
16924	case VPSRLDZ256rrk:
16925	case VPSRLDZ256rrkz:
16926	case VPSRLDZmbi:
16927	case VPSRLDZmbik:
16928	case VPSRLDZmbikz:
16929	case VPSRLDZmi:
16930	case VPSRLDZmik:
16931	case VPSRLDZmikz:
16932	case VPSRLDZri:
16933	case VPSRLDZrik:
16934	case VPSRLDZrikz:
16935	case VPSRLDZrm:
16936	case VPSRLDZrmk:
16937	case VPSRLDZrmkz:
16938	case VPSRLDZrr:
16939	case VPSRLDZrrk:
16940	case VPSRLDZrrkz:
16941	case VPSRLDri:
16942	case VPSRLDrm:
16943	case VPSRLDrr:
16944		return true;
16945	}
16946	return false;
16947}
16948
16949bool isTLBSYNC(unsigned Opcode) {
16950	return Opcode == TLBSYNC;
16951}
16952
16953bool isXLATB(unsigned Opcode) {
16954	return Opcode == XLAT;
16955}
16956
16957bool isUCOMISS(unsigned Opcode) {
16958	switch (Opcode) {
16959	case UCOMISSrm:
16960	case UCOMISSrr:
16961		return true;
16962	}
16963	return false;
16964}
16965
16966bool isVPSRLQ(unsigned Opcode) {
16967	switch (Opcode) {
16968	case VPSRLQYri:
16969	case VPSRLQYrm:
16970	case VPSRLQYrr:
16971	case VPSRLQZ128mbi:
16972	case VPSRLQZ128mbik:
16973	case VPSRLQZ128mbikz:
16974	case VPSRLQZ128mi:
16975	case VPSRLQZ128mik:
16976	case VPSRLQZ128mikz:
16977	case VPSRLQZ128ri:
16978	case VPSRLQZ128rik:
16979	case VPSRLQZ128rikz:
16980	case VPSRLQZ128rm:
16981	case VPSRLQZ128rmk:
16982	case VPSRLQZ128rmkz:
16983	case VPSRLQZ128rr:
16984	case VPSRLQZ128rrk:
16985	case VPSRLQZ128rrkz:
16986	case VPSRLQZ256mbi:
16987	case VPSRLQZ256mbik:
16988	case VPSRLQZ256mbikz:
16989	case VPSRLQZ256mi:
16990	case VPSRLQZ256mik:
16991	case VPSRLQZ256mikz:
16992	case VPSRLQZ256ri:
16993	case VPSRLQZ256rik:
16994	case VPSRLQZ256rikz:
16995	case VPSRLQZ256rm:
16996	case VPSRLQZ256rmk:
16997	case VPSRLQZ256rmkz:
16998	case VPSRLQZ256rr:
16999	case VPSRLQZ256rrk:
17000	case VPSRLQZ256rrkz:
17001	case VPSRLQZmbi:
17002	case VPSRLQZmbik:
17003	case VPSRLQZmbikz:
17004	case VPSRLQZmi:
17005	case VPSRLQZmik:
17006	case VPSRLQZmikz:
17007	case VPSRLQZri:
17008	case VPSRLQZrik:
17009	case VPSRLQZrikz:
17010	case VPSRLQZrm:
17011	case VPSRLQZrmk:
17012	case VPSRLQZrmkz:
17013	case VPSRLQZrr:
17014	case VPSRLQZrrk:
17015	case VPSRLQZrrkz:
17016	case VPSRLQri:
17017	case VPSRLQrm:
17018	case VPSRLQrr:
17019		return true;
17020	}
17021	return false;
17022}
17023
17024bool isPDEP(unsigned Opcode) {
17025	switch (Opcode) {
17026	case PDEP32rm:
17027	case PDEP32rr:
17028	case PDEP64rm:
17029	case PDEP64rr:
17030		return true;
17031	}
17032	return false;
17033}
17034
17035bool isVPDPBUUD(unsigned Opcode) {
17036	switch (Opcode) {
17037	case VPDPBUUDYrm:
17038	case VPDPBUUDYrr:
17039	case VPDPBUUDrm:
17040	case VPDPBUUDrr:
17041		return true;
17042	}
17043	return false;
17044}
17045
17046bool isVEXTRACTI32X4(unsigned Opcode) {
17047	switch (Opcode) {
17048	case VEXTRACTI32x4Z256mr:
17049	case VEXTRACTI32x4Z256mrk:
17050	case VEXTRACTI32x4Z256rr:
17051	case VEXTRACTI32x4Z256rrk:
17052	case VEXTRACTI32x4Z256rrkz:
17053	case VEXTRACTI32x4Zmr:
17054	case VEXTRACTI32x4Zmrk:
17055	case VEXTRACTI32x4Zrr:
17056	case VEXTRACTI32x4Zrrk:
17057	case VEXTRACTI32x4Zrrkz:
17058		return true;
17059	}
17060	return false;
17061}
17062
17063bool isPFCMPEQ(unsigned Opcode) {
17064	switch (Opcode) {
17065	case PFCMPEQrm:
17066	case PFCMPEQrr:
17067		return true;
17068	}
17069	return false;
17070}
17071
17072bool isBLSIC(unsigned Opcode) {
17073	switch (Opcode) {
17074	case BLSIC32rm:
17075	case BLSIC32rr:
17076	case BLSIC64rm:
17077	case BLSIC64rr:
17078		return true;
17079	}
17080	return false;
17081}
17082
17083bool isVPSRLW(unsigned Opcode) {
17084	switch (Opcode) {
17085	case VPSRLWYri:
17086	case VPSRLWYrm:
17087	case VPSRLWYrr:
17088	case VPSRLWZ128mi:
17089	case VPSRLWZ128mik:
17090	case VPSRLWZ128mikz:
17091	case VPSRLWZ128ri:
17092	case VPSRLWZ128rik:
17093	case VPSRLWZ128rikz:
17094	case VPSRLWZ128rm:
17095	case VPSRLWZ128rmk:
17096	case VPSRLWZ128rmkz:
17097	case VPSRLWZ128rr:
17098	case VPSRLWZ128rrk:
17099	case VPSRLWZ128rrkz:
17100	case VPSRLWZ256mi:
17101	case VPSRLWZ256mik:
17102	case VPSRLWZ256mikz:
17103	case VPSRLWZ256ri:
17104	case VPSRLWZ256rik:
17105	case VPSRLWZ256rikz:
17106	case VPSRLWZ256rm:
17107	case VPSRLWZ256rmk:
17108	case VPSRLWZ256rmkz:
17109	case VPSRLWZ256rr:
17110	case VPSRLWZ256rrk:
17111	case VPSRLWZ256rrkz:
17112	case VPSRLWZmi:
17113	case VPSRLWZmik:
17114	case VPSRLWZmikz:
17115	case VPSRLWZri:
17116	case VPSRLWZrik:
17117	case VPSRLWZrikz:
17118	case VPSRLWZrm:
17119	case VPSRLWZrmk:
17120	case VPSRLWZrmkz:
17121	case VPSRLWZrr:
17122	case VPSRLWZrrk:
17123	case VPSRLWZrrkz:
17124	case VPSRLWri:
17125	case VPSRLWrm:
17126	case VPSRLWrr:
17127		return true;
17128	}
17129	return false;
17130}
17131
17132bool isVEXTRACTI32X8(unsigned Opcode) {
17133	switch (Opcode) {
17134	case VEXTRACTI32x8Zmr:
17135	case VEXTRACTI32x8Zmrk:
17136	case VEXTRACTI32x8Zrr:
17137	case VEXTRACTI32x8Zrrk:
17138	case VEXTRACTI32x8Zrrkz:
17139		return true;
17140	}
17141	return false;
17142}
17143
17144bool isVDIVSD(unsigned Opcode) {
17145	switch (Opcode) {
17146	case VDIVSDZrm_Int:
17147	case VDIVSDZrm_Intk:
17148	case VDIVSDZrm_Intkz:
17149	case VDIVSDZrr_Int:
17150	case VDIVSDZrr_Intk:
17151	case VDIVSDZrr_Intkz:
17152	case VDIVSDZrrb_Int:
17153	case VDIVSDZrrb_Intk:
17154	case VDIVSDZrrb_Intkz:
17155	case VDIVSDrm_Int:
17156	case VDIVSDrr_Int:
17157		return true;
17158	}
17159	return false;
17160}
17161
17162bool isVFCMADDCPH(unsigned Opcode) {
17163	switch (Opcode) {
17164	case VFCMADDCPHZ128m:
17165	case VFCMADDCPHZ128mb:
17166	case VFCMADDCPHZ128mbk:
17167	case VFCMADDCPHZ128mbkz:
17168	case VFCMADDCPHZ128mk:
17169	case VFCMADDCPHZ128mkz:
17170	case VFCMADDCPHZ128r:
17171	case VFCMADDCPHZ128rk:
17172	case VFCMADDCPHZ128rkz:
17173	case VFCMADDCPHZ256m:
17174	case VFCMADDCPHZ256mb:
17175	case VFCMADDCPHZ256mbk:
17176	case VFCMADDCPHZ256mbkz:
17177	case VFCMADDCPHZ256mk:
17178	case VFCMADDCPHZ256mkz:
17179	case VFCMADDCPHZ256r:
17180	case VFCMADDCPHZ256rk:
17181	case VFCMADDCPHZ256rkz:
17182	case VFCMADDCPHZm:
17183	case VFCMADDCPHZmb:
17184	case VFCMADDCPHZmbk:
17185	case VFCMADDCPHZmbkz:
17186	case VFCMADDCPHZmk:
17187	case VFCMADDCPHZmkz:
17188	case VFCMADDCPHZr:
17189	case VFCMADDCPHZrb:
17190	case VFCMADDCPHZrbk:
17191	case VFCMADDCPHZrbkz:
17192	case VFCMADDCPHZrk:
17193	case VFCMADDCPHZrkz:
17194		return true;
17195	}
17196	return false;
17197}
17198
17199bool isVMOVAPS(unsigned Opcode) {
17200	switch (Opcode) {
17201	case VMOVAPSYmr:
17202	case VMOVAPSYrm:
17203	case VMOVAPSYrr:
17204	case VMOVAPSYrr_REV:
17205	case VMOVAPSZ128mr:
17206	case VMOVAPSZ128mrk:
17207	case VMOVAPSZ128rm:
17208	case VMOVAPSZ128rmk:
17209	case VMOVAPSZ128rmkz:
17210	case VMOVAPSZ128rr:
17211	case VMOVAPSZ128rr_REV:
17212	case VMOVAPSZ128rrk:
17213	case VMOVAPSZ128rrk_REV:
17214	case VMOVAPSZ128rrkz:
17215	case VMOVAPSZ128rrkz_REV:
17216	case VMOVAPSZ256mr:
17217	case VMOVAPSZ256mrk:
17218	case VMOVAPSZ256rm:
17219	case VMOVAPSZ256rmk:
17220	case VMOVAPSZ256rmkz:
17221	case VMOVAPSZ256rr:
17222	case VMOVAPSZ256rr_REV:
17223	case VMOVAPSZ256rrk:
17224	case VMOVAPSZ256rrk_REV:
17225	case VMOVAPSZ256rrkz:
17226	case VMOVAPSZ256rrkz_REV:
17227	case VMOVAPSZmr:
17228	case VMOVAPSZmrk:
17229	case VMOVAPSZrm:
17230	case VMOVAPSZrmk:
17231	case VMOVAPSZrmkz:
17232	case VMOVAPSZrr:
17233	case VMOVAPSZrr_REV:
17234	case VMOVAPSZrrk:
17235	case VMOVAPSZrrk_REV:
17236	case VMOVAPSZrrkz:
17237	case VMOVAPSZrrkz_REV:
17238	case VMOVAPSmr:
17239	case VMOVAPSrm:
17240	case VMOVAPSrr:
17241	case VMOVAPSrr_REV:
17242		return true;
17243	}
17244	return false;
17245}
17246
17247bool isFNOP(unsigned Opcode) {
17248	return Opcode == FNOP;
17249}
17250
17251bool isVDIVSH(unsigned Opcode) {
17252	switch (Opcode) {
17253	case VDIVSHZrm_Int:
17254	case VDIVSHZrm_Intk:
17255	case VDIVSHZrm_Intkz:
17256	case VDIVSHZrr_Int:
17257	case VDIVSHZrr_Intk:
17258	case VDIVSHZrr_Intkz:
17259	case VDIVSHZrrb_Int:
17260	case VDIVSHZrrb_Intk:
17261	case VDIVSHZrrb_Intkz:
17262		return true;
17263	}
17264	return false;
17265}
17266
17267bool isBT(unsigned Opcode) {
17268	switch (Opcode) {
17269	case BT16mi8:
17270	case BT16mr:
17271	case BT16ri8:
17272	case BT16rr:
17273	case BT32mi8:
17274	case BT32mr:
17275	case BT32ri8:
17276	case BT32rr:
17277	case BT64mi8:
17278	case BT64mr:
17279	case BT64ri8:
17280	case BT64rr:
17281		return true;
17282	}
17283	return false;
17284}
17285
17286bool isVFNMSUBSD(unsigned Opcode) {
17287	switch (Opcode) {
17288	case VFNMSUBSD4mr:
17289	case VFNMSUBSD4rm:
17290	case VFNMSUBSD4rr:
17291	case VFNMSUBSD4rr_REV:
17292		return true;
17293	}
17294	return false;
17295}
17296
17297bool isVPHMINPOSUW(unsigned Opcode) {
17298	switch (Opcode) {
17299	case VPHMINPOSUWrm:
17300	case VPHMINPOSUWrr:
17301		return true;
17302	}
17303	return false;
17304}
17305
17306bool isVDIVSS(unsigned Opcode) {
17307	switch (Opcode) {
17308	case VDIVSSZrm_Int:
17309	case VDIVSSZrm_Intk:
17310	case VDIVSSZrm_Intkz:
17311	case VDIVSSZrr_Int:
17312	case VDIVSSZrr_Intk:
17313	case VDIVSSZrr_Intkz:
17314	case VDIVSSZrrb_Int:
17315	case VDIVSSZrrb_Intk:
17316	case VDIVSSZrrb_Intkz:
17317	case VDIVSSrm_Int:
17318	case VDIVSSrr_Int:
17319		return true;
17320	}
17321	return false;
17322}
17323
17324bool isVCVTTSH2SI(unsigned Opcode) {
17325	switch (Opcode) {
17326	case VCVTTSH2SI64Zrm_Int:
17327	case VCVTTSH2SI64Zrr_Int:
17328	case VCVTTSH2SI64Zrrb_Int:
17329	case VCVTTSH2SIZrm_Int:
17330	case VCVTTSH2SIZrr_Int:
17331	case VCVTTSH2SIZrrb_Int:
17332		return true;
17333	}
17334	return false;
17335}
17336
17337bool isKUNPCKDQ(unsigned Opcode) {
17338	return Opcode == KUNPCKDQrr;
17339}
17340
17341bool isMULPD(unsigned Opcode) {
17342	switch (Opcode) {
17343	case MULPDrm:
17344	case MULPDrr:
17345		return true;
17346	}
17347	return false;
17348}
17349
17350bool isBEXTR(unsigned Opcode) {
17351	switch (Opcode) {
17352	case BEXTR32rm:
17353	case BEXTR32rr:
17354	case BEXTR64rm:
17355	case BEXTR64rr:
17356	case BEXTRI32mi:
17357	case BEXTRI32ri:
17358	case BEXTRI64mi:
17359	case BEXTRI64ri:
17360		return true;
17361	}
17362	return false;
17363}
17364
17365bool isVFNMSUBSS(unsigned Opcode) {
17366	switch (Opcode) {
17367	case VFNMSUBSS4mr:
17368	case VFNMSUBSS4rm:
17369	case VFNMSUBSS4rr:
17370	case VFNMSUBSS4rr_REV:
17371		return true;
17372	}
17373	return false;
17374}
17375
17376bool isMPSADBW(unsigned Opcode) {
17377	switch (Opcode) {
17378	case MPSADBWrmi:
17379	case MPSADBWrri:
17380		return true;
17381	}
17382	return false;
17383}
17384
17385bool isMULPS(unsigned Opcode) {
17386	switch (Opcode) {
17387	case MULPSrm:
17388	case MULPSrr:
17389		return true;
17390	}
17391	return false;
17392}
17393
17394bool isSHA256MSG1(unsigned Opcode) {
17395	switch (Opcode) {
17396	case SHA256MSG1rm:
17397	case SHA256MSG1rr:
17398		return true;
17399	}
17400	return false;
17401}
17402
17403bool isSHA256MSG2(unsigned Opcode) {
17404	switch (Opcode) {
17405	case SHA256MSG2rm:
17406	case SHA256MSG2rr:
17407		return true;
17408	}
17409	return false;
17410}
17411
17412bool isPOPF(unsigned Opcode) {
17413	return Opcode == POPF16;
17414}
17415
17416bool isVERR(unsigned Opcode) {
17417	switch (Opcode) {
17418	case VERRm:
17419	case VERRr:
17420		return true;
17421	}
17422	return false;
17423}
17424
17425bool isPFCMPGE(unsigned Opcode) {
17426	switch (Opcode) {
17427	case PFCMPGErm:
17428	case PFCMPGErr:
17429		return true;
17430	}
17431	return false;
17432}
17433
17434bool isVCVTPS2UDQ(unsigned Opcode) {
17435	switch (Opcode) {
17436	case VCVTPS2UDQZ128rm:
17437	case VCVTPS2UDQZ128rmb:
17438	case VCVTPS2UDQZ128rmbk:
17439	case VCVTPS2UDQZ128rmbkz:
17440	case VCVTPS2UDQZ128rmk:
17441	case VCVTPS2UDQZ128rmkz:
17442	case VCVTPS2UDQZ128rr:
17443	case VCVTPS2UDQZ128rrk:
17444	case VCVTPS2UDQZ128rrkz:
17445	case VCVTPS2UDQZ256rm:
17446	case VCVTPS2UDQZ256rmb:
17447	case VCVTPS2UDQZ256rmbk:
17448	case VCVTPS2UDQZ256rmbkz:
17449	case VCVTPS2UDQZ256rmk:
17450	case VCVTPS2UDQZ256rmkz:
17451	case VCVTPS2UDQZ256rr:
17452	case VCVTPS2UDQZ256rrk:
17453	case VCVTPS2UDQZ256rrkz:
17454	case VCVTPS2UDQZrm:
17455	case VCVTPS2UDQZrmb:
17456	case VCVTPS2UDQZrmbk:
17457	case VCVTPS2UDQZrmbkz:
17458	case VCVTPS2UDQZrmk:
17459	case VCVTPS2UDQZrmkz:
17460	case VCVTPS2UDQZrr:
17461	case VCVTPS2UDQZrrb:
17462	case VCVTPS2UDQZrrbk:
17463	case VCVTPS2UDQZrrbkz:
17464	case VCVTPS2UDQZrrk:
17465	case VCVTPS2UDQZrrkz:
17466		return true;
17467	}
17468	return false;
17469}
17470
17471bool isVERW(unsigned Opcode) {
17472	switch (Opcode) {
17473	case VERWm:
17474	case VERWr:
17475		return true;
17476	}
17477	return false;
17478}
17479
17480bool isVFMSUBADDPD(unsigned Opcode) {
17481	switch (Opcode) {
17482	case VFMSUBADDPD4Ymr:
17483	case VFMSUBADDPD4Yrm:
17484	case VFMSUBADDPD4Yrr:
17485	case VFMSUBADDPD4Yrr_REV:
17486	case VFMSUBADDPD4mr:
17487	case VFMSUBADDPD4rm:
17488	case VFMSUBADDPD4rr:
17489	case VFMSUBADDPD4rr_REV:
17490		return true;
17491	}
17492	return false;
17493}
17494
17495bool isPFCMPGT(unsigned Opcode) {
17496	switch (Opcode) {
17497	case PFCMPGTrm:
17498	case PFCMPGTrr:
17499		return true;
17500	}
17501	return false;
17502}
17503
17504bool isVEXTRACTI128(unsigned Opcode) {
17505	switch (Opcode) {
17506	case VEXTRACTI128mr:
17507	case VEXTRACTI128rr:
17508		return true;
17509	}
17510	return false;
17511}
17512
17513bool isVGF2P8AFFINEQB(unsigned Opcode) {
17514	switch (Opcode) {
17515	case VGF2P8AFFINEQBYrmi:
17516	case VGF2P8AFFINEQBYrri:
17517	case VGF2P8AFFINEQBZ128rmbi:
17518	case VGF2P8AFFINEQBZ128rmbik:
17519	case VGF2P8AFFINEQBZ128rmbikz:
17520	case VGF2P8AFFINEQBZ128rmi:
17521	case VGF2P8AFFINEQBZ128rmik:
17522	case VGF2P8AFFINEQBZ128rmikz:
17523	case VGF2P8AFFINEQBZ128rri:
17524	case VGF2P8AFFINEQBZ128rrik:
17525	case VGF2P8AFFINEQBZ128rrikz:
17526	case VGF2P8AFFINEQBZ256rmbi:
17527	case VGF2P8AFFINEQBZ256rmbik:
17528	case VGF2P8AFFINEQBZ256rmbikz:
17529	case VGF2P8AFFINEQBZ256rmi:
17530	case VGF2P8AFFINEQBZ256rmik:
17531	case VGF2P8AFFINEQBZ256rmikz:
17532	case VGF2P8AFFINEQBZ256rri:
17533	case VGF2P8AFFINEQBZ256rrik:
17534	case VGF2P8AFFINEQBZ256rrikz:
17535	case VGF2P8AFFINEQBZrmbi:
17536	case VGF2P8AFFINEQBZrmbik:
17537	case VGF2P8AFFINEQBZrmbikz:
17538	case VGF2P8AFFINEQBZrmi:
17539	case VGF2P8AFFINEQBZrmik:
17540	case VGF2P8AFFINEQBZrmikz:
17541	case VGF2P8AFFINEQBZrri:
17542	case VGF2P8AFFINEQBZrrik:
17543	case VGF2P8AFFINEQBZrrikz:
17544	case VGF2P8AFFINEQBrmi:
17545	case VGF2P8AFFINEQBrri:
17546		return true;
17547	}
17548	return false;
17549}
17550
17551bool isPSLLD(unsigned Opcode) {
17552	switch (Opcode) {
17553	case MMX_PSLLDri:
17554	case MMX_PSLLDrm:
17555	case MMX_PSLLDrr:
17556	case PSLLDri:
17557	case PSLLDrm:
17558	case PSLLDrr:
17559		return true;
17560	}
17561	return false;
17562}
17563
17564bool isFSUBP(unsigned Opcode) {
17565	return Opcode == SUB_FPrST0;
17566}
17567
17568bool isFSUBR(unsigned Opcode) {
17569	switch (Opcode) {
17570	case SUBR_F32m:
17571	case SUBR_F64m:
17572	case SUBR_FST0r:
17573	case SUBR_FrST0:
17574		return true;
17575	}
17576	return false;
17577}
17578
17579bool isVBROADCASTF64X2(unsigned Opcode) {
17580	switch (Opcode) {
17581	case VBROADCASTF64X2Z128rm:
17582	case VBROADCASTF64X2Z128rmk:
17583	case VBROADCASTF64X2Z128rmkz:
17584	case VBROADCASTF64X2rm:
17585	case VBROADCASTF64X2rmk:
17586	case VBROADCASTF64X2rmkz:
17587		return true;
17588	}
17589	return false;
17590}
17591
17592bool isFCHS(unsigned Opcode) {
17593	return Opcode == CHS_F;
17594}
17595
17596bool isCMPXCHG8B(unsigned Opcode) {
17597	return Opcode == CMPXCHG8B;
17598}
17599
17600bool isVBROADCASTF64X4(unsigned Opcode) {
17601	switch (Opcode) {
17602	case VBROADCASTF64X4rm:
17603	case VBROADCASTF64X4rmk:
17604	case VBROADCASTF64X4rmkz:
17605		return true;
17606	}
17607	return false;
17608}
17609
17610bool isVINSERTI32X4(unsigned Opcode) {
17611	switch (Opcode) {
17612	case VINSERTI32x4Z256rm:
17613	case VINSERTI32x4Z256rmk:
17614	case VINSERTI32x4Z256rmkz:
17615	case VINSERTI32x4Z256rr:
17616	case VINSERTI32x4Z256rrk:
17617	case VINSERTI32x4Z256rrkz:
17618	case VINSERTI32x4Zrm:
17619	case VINSERTI32x4Zrmk:
17620	case VINSERTI32x4Zrmkz:
17621	case VINSERTI32x4Zrr:
17622	case VINSERTI32x4Zrrk:
17623	case VINSERTI32x4Zrrkz:
17624		return true;
17625	}
17626	return false;
17627}
17628
17629bool isVFMSUBADDPS(unsigned Opcode) {
17630	switch (Opcode) {
17631	case VFMSUBADDPS4Ymr:
17632	case VFMSUBADDPS4Yrm:
17633	case VFMSUBADDPS4Yrr:
17634	case VFMSUBADDPS4Yrr_REV:
17635	case VFMSUBADDPS4mr:
17636	case VFMSUBADDPS4rm:
17637	case VFMSUBADDPS4rr:
17638	case VFMSUBADDPS4rr_REV:
17639		return true;
17640	}
17641	return false;
17642}
17643
17644bool isVBROADCASTF128(unsigned Opcode) {
17645	return Opcode == VBROADCASTF128;
17646}
17647
17648bool isVPERMIL2PD(unsigned Opcode) {
17649	switch (Opcode) {
17650	case VPERMIL2PDYmr:
17651	case VPERMIL2PDYrm:
17652	case VPERMIL2PDYrr:
17653	case VPERMIL2PDYrr_REV:
17654	case VPERMIL2PDmr:
17655	case VPERMIL2PDrm:
17656	case VPERMIL2PDrr:
17657	case VPERMIL2PDrr_REV:
17658		return true;
17659	}
17660	return false;
17661}
17662
17663bool isPSLLQ(unsigned Opcode) {
17664	switch (Opcode) {
17665	case MMX_PSLLQri:
17666	case MMX_PSLLQrm:
17667	case MMX_PSLLQrr:
17668	case PSLLQri:
17669	case PSLLQrm:
17670	case PSLLQrr:
17671		return true;
17672	}
17673	return false;
17674}
17675
17676bool isVINSERTI32X8(unsigned Opcode) {
17677	switch (Opcode) {
17678	case VINSERTI32x8Zrm:
17679	case VINSERTI32x8Zrmk:
17680	case VINSERTI32x8Zrmkz:
17681	case VINSERTI32x8Zrr:
17682	case VINSERTI32x8Zrrk:
17683	case VINSERTI32x8Zrrkz:
17684		return true;
17685	}
17686	return false;
17687}
17688
17689bool isLLDT(unsigned Opcode) {
17690	switch (Opcode) {
17691	case LLDT16m:
17692	case LLDT16r:
17693		return true;
17694	}
17695	return false;
17696}
17697
17698bool isMOVMSKPD(unsigned Opcode) {
17699	return Opcode == MOVMSKPDrr;
17700}
17701
17702bool isPSLLW(unsigned Opcode) {
17703	switch (Opcode) {
17704	case MMX_PSLLWri:
17705	case MMX_PSLLWrm:
17706	case MMX_PSLLWrr:
17707	case PSLLWri:
17708	case PSLLWrm:
17709	case PSLLWrr:
17710		return true;
17711	}
17712	return false;
17713}
17714
17715bool isVFCMADDCSH(unsigned Opcode) {
17716	switch (Opcode) {
17717	case VFCMADDCSHZm:
17718	case VFCMADDCSHZmk:
17719	case VFCMADDCSHZmkz:
17720	case VFCMADDCSHZr:
17721	case VFCMADDCSHZrb:
17722	case VFCMADDCSHZrbk:
17723	case VFCMADDCSHZrbkz:
17724	case VFCMADDCSHZrk:
17725	case VFCMADDCSHZrkz:
17726		return true;
17727	}
17728	return false;
17729}
17730
17731bool isVPERMIL2PS(unsigned Opcode) {
17732	switch (Opcode) {
17733	case VPERMIL2PSYmr:
17734	case VPERMIL2PSYrm:
17735	case VPERMIL2PSYrr:
17736	case VPERMIL2PSYrr_REV:
17737	case VPERMIL2PSmr:
17738	case VPERMIL2PSrm:
17739	case VPERMIL2PSrr:
17740	case VPERMIL2PSrr_REV:
17741		return true;
17742	}
17743	return false;
17744}
17745
17746bool isPF2ID(unsigned Opcode) {
17747	switch (Opcode) {
17748	case PF2IDrm:
17749	case PF2IDrr:
17750		return true;
17751	}
17752	return false;
17753}
17754
17755bool isVPUNPCKHQDQ(unsigned Opcode) {
17756	switch (Opcode) {
17757	case VPUNPCKHQDQYrm:
17758	case VPUNPCKHQDQYrr:
17759	case VPUNPCKHQDQZ128rm:
17760	case VPUNPCKHQDQZ128rmb:
17761	case VPUNPCKHQDQZ128rmbk:
17762	case VPUNPCKHQDQZ128rmbkz:
17763	case VPUNPCKHQDQZ128rmk:
17764	case VPUNPCKHQDQZ128rmkz:
17765	case VPUNPCKHQDQZ128rr:
17766	case VPUNPCKHQDQZ128rrk:
17767	case VPUNPCKHQDQZ128rrkz:
17768	case VPUNPCKHQDQZ256rm:
17769	case VPUNPCKHQDQZ256rmb:
17770	case VPUNPCKHQDQZ256rmbk:
17771	case VPUNPCKHQDQZ256rmbkz:
17772	case VPUNPCKHQDQZ256rmk:
17773	case VPUNPCKHQDQZ256rmkz:
17774	case VPUNPCKHQDQZ256rr:
17775	case VPUNPCKHQDQZ256rrk:
17776	case VPUNPCKHQDQZ256rrkz:
17777	case VPUNPCKHQDQZrm:
17778	case VPUNPCKHQDQZrmb:
17779	case VPUNPCKHQDQZrmbk:
17780	case VPUNPCKHQDQZrmbkz:
17781	case VPUNPCKHQDQZrmk:
17782	case VPUNPCKHQDQZrmkz:
17783	case VPUNPCKHQDQZrr:
17784	case VPUNPCKHQDQZrrk:
17785	case VPUNPCKHQDQZrrkz:
17786	case VPUNPCKHQDQrm:
17787	case VPUNPCKHQDQrr:
17788		return true;
17789	}
17790	return false;
17791}
17792
17793bool isMOVMSKPS(unsigned Opcode) {
17794	return Opcode == MOVMSKPSrr;
17795}
17796
17797bool isMULSD(unsigned Opcode) {
17798	switch (Opcode) {
17799	case MULSDrm_Int:
17800	case MULSDrr_Int:
17801		return true;
17802	}
17803	return false;
17804}
17805
17806bool isPF2IW(unsigned Opcode) {
17807	switch (Opcode) {
17808	case PF2IWrm:
17809	case PF2IWrr:
17810		return true;
17811	}
17812	return false;
17813}
17814
17815bool isVBLENDPD(unsigned Opcode) {
17816	switch (Opcode) {
17817	case VBLENDPDYrmi:
17818	case VBLENDPDYrri:
17819	case VBLENDPDrmi:
17820	case VBLENDPDrri:
17821		return true;
17822	}
17823	return false;
17824}
17825
17826bool isCLAC(unsigned Opcode) {
17827	return Opcode == CLAC;
17828}
17829
17830bool isMULSS(unsigned Opcode) {
17831	switch (Opcode) {
17832	case MULSSrm_Int:
17833	case MULSSrr_Int:
17834		return true;
17835	}
17836	return false;
17837}
17838
17839bool isORPD(unsigned Opcode) {
17840	switch (Opcode) {
17841	case ORPDrm:
17842	case ORPDrr:
17843		return true;
17844	}
17845	return false;
17846}
17847
17848bool isCDQE(unsigned Opcode) {
17849	return Opcode == CDQE;
17850}
17851
17852bool isVBLENDPS(unsigned Opcode) {
17853	switch (Opcode) {
17854	case VBLENDPSYrmi:
17855	case VBLENDPSYrri:
17856	case VBLENDPSrmi:
17857	case VBLENDPSrri:
17858		return true;
17859	}
17860	return false;
17861}
17862
17863bool isTILESTORED(unsigned Opcode) {
17864	return Opcode == TILESTORED;
17865}
17866
17867bool isORPS(unsigned Opcode) {
17868	switch (Opcode) {
17869	case ORPSrm:
17870	case ORPSrr:
17871		return true;
17872	}
17873	return false;
17874}
17875
17876bool isVPINSRB(unsigned Opcode) {
17877	switch (Opcode) {
17878	case VPINSRBZrm:
17879	case VPINSRBZrr:
17880	case VPINSRBrm:
17881	case VPINSRBrr:
17882		return true;
17883	}
17884	return false;
17885}
17886
17887bool isVPINSRD(unsigned Opcode) {
17888	switch (Opcode) {
17889	case VPINSRDZrm:
17890	case VPINSRDZrr:
17891	case VPINSRDrm:
17892	case VPINSRDrr:
17893		return true;
17894	}
17895	return false;
17896}
17897
17898bool isBZHI(unsigned Opcode) {
17899	switch (Opcode) {
17900	case BZHI32rm:
17901	case BZHI32rr:
17902	case BZHI64rm:
17903	case BZHI64rr:
17904		return true;
17905	}
17906	return false;
17907}
17908
17909bool isPUNPCKHBW(unsigned Opcode) {
17910	switch (Opcode) {
17911	case MMX_PUNPCKHBWrm:
17912	case MMX_PUNPCKHBWrr:
17913	case PUNPCKHBWrm:
17914	case PUNPCKHBWrr:
17915		return true;
17916	}
17917	return false;
17918}
17919
17920bool isVCVTPD2UDQ(unsigned Opcode) {
17921	switch (Opcode) {
17922	case VCVTPD2UDQZ128rm:
17923	case VCVTPD2UDQZ128rmb:
17924	case VCVTPD2UDQZ128rmbk:
17925	case VCVTPD2UDQZ128rmbkz:
17926	case VCVTPD2UDQZ128rmk:
17927	case VCVTPD2UDQZ128rmkz:
17928	case VCVTPD2UDQZ128rr:
17929	case VCVTPD2UDQZ128rrk:
17930	case VCVTPD2UDQZ128rrkz:
17931	case VCVTPD2UDQZ256rm:
17932	case VCVTPD2UDQZ256rmb:
17933	case VCVTPD2UDQZ256rmbk:
17934	case VCVTPD2UDQZ256rmbkz:
17935	case VCVTPD2UDQZ256rmk:
17936	case VCVTPD2UDQZ256rmkz:
17937	case VCVTPD2UDQZ256rr:
17938	case VCVTPD2UDQZ256rrk:
17939	case VCVTPD2UDQZ256rrkz:
17940	case VCVTPD2UDQZrm:
17941	case VCVTPD2UDQZrmb:
17942	case VCVTPD2UDQZrmbk:
17943	case VCVTPD2UDQZrmbkz:
17944	case VCVTPD2UDQZrmk:
17945	case VCVTPD2UDQZrmkz:
17946	case VCVTPD2UDQZrr:
17947	case VCVTPD2UDQZrrb:
17948	case VCVTPD2UDQZrrbk:
17949	case VCVTPD2UDQZrrbkz:
17950	case VCVTPD2UDQZrrk:
17951	case VCVTPD2UDQZrrkz:
17952		return true;
17953	}
17954	return false;
17955}
17956
17957bool isVPINSRQ(unsigned Opcode) {
17958	switch (Opcode) {
17959	case VPINSRQZrm:
17960	case VPINSRQZrr:
17961	case VPINSRQrm:
17962	case VPINSRQrr:
17963		return true;
17964	}
17965	return false;
17966}
17967
17968bool isVPINSRW(unsigned Opcode) {
17969	switch (Opcode) {
17970	case VPINSRWZrm:
17971	case VPINSRWZrr:
17972	case VPINSRWrm:
17973	case VPINSRWrr:
17974		return true;
17975	}
17976	return false;
17977}
17978
17979bool isVPMACSSDQH(unsigned Opcode) {
17980	switch (Opcode) {
17981	case VPMACSSDQHrm:
17982	case VPMACSSDQHrr:
17983		return true;
17984	}
17985	return false;
17986}
17987
17988bool isGETSEC(unsigned Opcode) {
17989	return Opcode == GETSEC;
17990}
17991
17992bool isCVTSS2SD(unsigned Opcode) {
17993	switch (Opcode) {
17994	case CVTSS2SDrm_Int:
17995	case CVTSS2SDrr_Int:
17996		return true;
17997	}
17998	return false;
17999}
18000
18001bool isVPMACSSDQL(unsigned Opcode) {
18002	switch (Opcode) {
18003	case VPMACSSDQLrm:
18004	case VPMACSSDQLrr:
18005		return true;
18006	}
18007	return false;
18008}
18009
18010bool isANDN(unsigned Opcode) {
18011	switch (Opcode) {
18012	case ANDN32rm:
18013	case ANDN32rr:
18014	case ANDN64rm:
18015	case ANDN64rr:
18016		return true;
18017	}
18018	return false;
18019}
18020
18021bool isCVTSS2SI(unsigned Opcode) {
18022	switch (Opcode) {
18023	case CVTSS2SI64rm_Int:
18024	case CVTSS2SI64rr_Int:
18025	case CVTSS2SIrm_Int:
18026	case CVTSS2SIrr_Int:
18027		return true;
18028	}
18029	return false;
18030}
18031
18032bool isAESDEC(unsigned Opcode) {
18033	switch (Opcode) {
18034	case AESDECrm:
18035	case AESDECrr:
18036		return true;
18037	}
18038	return false;
18039}
18040
18041bool isMOVSB(unsigned Opcode) {
18042	return Opcode == MOVSB;
18043}
18044
18045bool isMOVSD(unsigned Opcode) {
18046	switch (Opcode) {
18047	case MOVSDmr:
18048	case MOVSDrm:
18049	case MOVSDrr:
18050	case MOVSDrr_REV:
18051	case MOVSL:
18052		return true;
18053	}
18054	return false;
18055}
18056
18057bool isVFNMSUB213PD(unsigned Opcode) {
18058	switch (Opcode) {
18059	case VFNMSUB213PDYm:
18060	case VFNMSUB213PDYr:
18061	case VFNMSUB213PDZ128m:
18062	case VFNMSUB213PDZ128mb:
18063	case VFNMSUB213PDZ128mbk:
18064	case VFNMSUB213PDZ128mbkz:
18065	case VFNMSUB213PDZ128mk:
18066	case VFNMSUB213PDZ128mkz:
18067	case VFNMSUB213PDZ128r:
18068	case VFNMSUB213PDZ128rk:
18069	case VFNMSUB213PDZ128rkz:
18070	case VFNMSUB213PDZ256m:
18071	case VFNMSUB213PDZ256mb:
18072	case VFNMSUB213PDZ256mbk:
18073	case VFNMSUB213PDZ256mbkz:
18074	case VFNMSUB213PDZ256mk:
18075	case VFNMSUB213PDZ256mkz:
18076	case VFNMSUB213PDZ256r:
18077	case VFNMSUB213PDZ256rk:
18078	case VFNMSUB213PDZ256rkz:
18079	case VFNMSUB213PDZm:
18080	case VFNMSUB213PDZmb:
18081	case VFNMSUB213PDZmbk:
18082	case VFNMSUB213PDZmbkz:
18083	case VFNMSUB213PDZmk:
18084	case VFNMSUB213PDZmkz:
18085	case VFNMSUB213PDZr:
18086	case VFNMSUB213PDZrb:
18087	case VFNMSUB213PDZrbk:
18088	case VFNMSUB213PDZrbkz:
18089	case VFNMSUB213PDZrk:
18090	case VFNMSUB213PDZrkz:
18091	case VFNMSUB213PDm:
18092	case VFNMSUB213PDr:
18093		return true;
18094	}
18095	return false;
18096}
18097
18098bool isVPMOVW2M(unsigned Opcode) {
18099	switch (Opcode) {
18100	case VPMOVW2MZ128rr:
18101	case VPMOVW2MZ256rr:
18102	case VPMOVW2MZrr:
18103		return true;
18104	}
18105	return false;
18106}
18107
18108bool isVFNMSUB213PH(unsigned Opcode) {
18109	switch (Opcode) {
18110	case VFNMSUB213PHZ128m:
18111	case VFNMSUB213PHZ128mb:
18112	case VFNMSUB213PHZ128mbk:
18113	case VFNMSUB213PHZ128mbkz:
18114	case VFNMSUB213PHZ128mk:
18115	case VFNMSUB213PHZ128mkz:
18116	case VFNMSUB213PHZ128r:
18117	case VFNMSUB213PHZ128rk:
18118	case VFNMSUB213PHZ128rkz:
18119	case VFNMSUB213PHZ256m:
18120	case VFNMSUB213PHZ256mb:
18121	case VFNMSUB213PHZ256mbk:
18122	case VFNMSUB213PHZ256mbkz:
18123	case VFNMSUB213PHZ256mk:
18124	case VFNMSUB213PHZ256mkz:
18125	case VFNMSUB213PHZ256r:
18126	case VFNMSUB213PHZ256rk:
18127	case VFNMSUB213PHZ256rkz:
18128	case VFNMSUB213PHZm:
18129	case VFNMSUB213PHZmb:
18130	case VFNMSUB213PHZmbk:
18131	case VFNMSUB213PHZmbkz:
18132	case VFNMSUB213PHZmk:
18133	case VFNMSUB213PHZmkz:
18134	case VFNMSUB213PHZr:
18135	case VFNMSUB213PHZrb:
18136	case VFNMSUB213PHZrbk:
18137	case VFNMSUB213PHZrbkz:
18138	case VFNMSUB213PHZrk:
18139	case VFNMSUB213PHZrkz:
18140		return true;
18141	}
18142	return false;
18143}
18144
18145bool isVPACKSSWB(unsigned Opcode) {
18146	switch (Opcode) {
18147	case VPACKSSWBYrm:
18148	case VPACKSSWBYrr:
18149	case VPACKSSWBZ128rm:
18150	case VPACKSSWBZ128rmk:
18151	case VPACKSSWBZ128rmkz:
18152	case VPACKSSWBZ128rr:
18153	case VPACKSSWBZ128rrk:
18154	case VPACKSSWBZ128rrkz:
18155	case VPACKSSWBZ256rm:
18156	case VPACKSSWBZ256rmk:
18157	case VPACKSSWBZ256rmkz:
18158	case VPACKSSWBZ256rr:
18159	case VPACKSSWBZ256rrk:
18160	case VPACKSSWBZ256rrkz:
18161	case VPACKSSWBZrm:
18162	case VPACKSSWBZrmk:
18163	case VPACKSSWBZrmkz:
18164	case VPACKSSWBZrr:
18165	case VPACKSSWBZrrk:
18166	case VPACKSSWBZrrkz:
18167	case VPACKSSWBrm:
18168	case VPACKSSWBrr:
18169		return true;
18170	}
18171	return false;
18172}
18173
18174bool isMOVSQ(unsigned Opcode) {
18175	return Opcode == MOVSQ;
18176}
18177
18178bool isMOVSS(unsigned Opcode) {
18179	switch (Opcode) {
18180	case MOVSSmr:
18181	case MOVSSrm:
18182	case MOVSSrr:
18183	case MOVSSrr_REV:
18184		return true;
18185	}
18186	return false;
18187}
18188
18189bool isVPMULHRSW(unsigned Opcode) {
18190	switch (Opcode) {
18191	case VPMULHRSWYrm:
18192	case VPMULHRSWYrr:
18193	case VPMULHRSWZ128rm:
18194	case VPMULHRSWZ128rmk:
18195	case VPMULHRSWZ128rmkz:
18196	case VPMULHRSWZ128rr:
18197	case VPMULHRSWZ128rrk:
18198	case VPMULHRSWZ128rrkz:
18199	case VPMULHRSWZ256rm:
18200	case VPMULHRSWZ256rmk:
18201	case VPMULHRSWZ256rmkz:
18202	case VPMULHRSWZ256rr:
18203	case VPMULHRSWZ256rrk:
18204	case VPMULHRSWZ256rrkz:
18205	case VPMULHRSWZrm:
18206	case VPMULHRSWZrmk:
18207	case VPMULHRSWZrmkz:
18208	case VPMULHRSWZrr:
18209	case VPMULHRSWZrrk:
18210	case VPMULHRSWZrrkz:
18211	case VPMULHRSWrm:
18212	case VPMULHRSWrr:
18213		return true;
18214	}
18215	return false;
18216}
18217
18218bool isVFNMSUB213PS(unsigned Opcode) {
18219	switch (Opcode) {
18220	case VFNMSUB213PSYm:
18221	case VFNMSUB213PSYr:
18222	case VFNMSUB213PSZ128m:
18223	case VFNMSUB213PSZ128mb:
18224	case VFNMSUB213PSZ128mbk:
18225	case VFNMSUB213PSZ128mbkz:
18226	case VFNMSUB213PSZ128mk:
18227	case VFNMSUB213PSZ128mkz:
18228	case VFNMSUB213PSZ128r:
18229	case VFNMSUB213PSZ128rk:
18230	case VFNMSUB213PSZ128rkz:
18231	case VFNMSUB213PSZ256m:
18232	case VFNMSUB213PSZ256mb:
18233	case VFNMSUB213PSZ256mbk:
18234	case VFNMSUB213PSZ256mbkz:
18235	case VFNMSUB213PSZ256mk:
18236	case VFNMSUB213PSZ256mkz:
18237	case VFNMSUB213PSZ256r:
18238	case VFNMSUB213PSZ256rk:
18239	case VFNMSUB213PSZ256rkz:
18240	case VFNMSUB213PSZm:
18241	case VFNMSUB213PSZmb:
18242	case VFNMSUB213PSZmbk:
18243	case VFNMSUB213PSZmbkz:
18244	case VFNMSUB213PSZmk:
18245	case VFNMSUB213PSZmkz:
18246	case VFNMSUB213PSZr:
18247	case VFNMSUB213PSZrb:
18248	case VFNMSUB213PSZrbk:
18249	case VFNMSUB213PSZrbkz:
18250	case VFNMSUB213PSZrk:
18251	case VFNMSUB213PSZrkz:
18252	case VFNMSUB213PSm:
18253	case VFNMSUB213PSr:
18254		return true;
18255	}
18256	return false;
18257}
18258
18259bool isCMOVCC(unsigned Opcode) {
18260	switch (Opcode) {
18261	case CMOV16rm:
18262	case CMOV16rr:
18263	case CMOV32rm:
18264	case CMOV32rr:
18265	case CMOV64rm:
18266	case CMOV64rr:
18267		return true;
18268	}
18269	return false;
18270}
18271
18272bool isMOVSW(unsigned Opcode) {
18273	return Opcode == MOVSW;
18274}
18275
18276bool isMOVSX(unsigned Opcode) {
18277	switch (Opcode) {
18278	case MOVSX16rm16:
18279	case MOVSX16rm8:
18280	case MOVSX16rr16:
18281	case MOVSX16rr8:
18282	case MOVSX32rm16:
18283	case MOVSX32rm8:
18284	case MOVSX32rr16:
18285	case MOVSX32rr8:
18286	case MOVSX64rm16:
18287	case MOVSX64rm8:
18288	case MOVSX64rr16:
18289	case MOVSX64rr8:
18290		return true;
18291	}
18292	return false;
18293}
18294
18295bool isVPCOMUD(unsigned Opcode) {
18296	switch (Opcode) {
18297	case VPCOMUDmi:
18298	case VPCOMUDri:
18299		return true;
18300	}
18301	return false;
18302}
18303
18304bool isVPCOMUB(unsigned Opcode) {
18305	switch (Opcode) {
18306	case VPCOMUBmi:
18307	case VPCOMUBri:
18308		return true;
18309	}
18310	return false;
18311}
18312
18313bool isVPDPBSUDS(unsigned Opcode) {
18314	switch (Opcode) {
18315	case VPDPBSUDSYrm:
18316	case VPDPBSUDSYrr:
18317	case VPDPBSUDSrm:
18318	case VPDPBSUDSrr:
18319		return true;
18320	}
18321	return false;
18322}
18323
18324bool isFLDLN2(unsigned Opcode) {
18325	return Opcode == FLDLN2;
18326}
18327
18328bool isPACKUSDW(unsigned Opcode) {
18329	switch (Opcode) {
18330	case PACKUSDWrm:
18331	case PACKUSDWrr:
18332		return true;
18333	}
18334	return false;
18335}
18336
18337bool isVPCOMUQ(unsigned Opcode) {
18338	switch (Opcode) {
18339	case VPCOMUQmi:
18340	case VPCOMUQri:
18341		return true;
18342	}
18343	return false;
18344}
18345
18346bool isMONTMUL(unsigned Opcode) {
18347	return Opcode == MONTMUL;
18348}
18349
18350bool isPUNPCKHDQ(unsigned Opcode) {
18351	switch (Opcode) {
18352	case MMX_PUNPCKHDQrm:
18353	case MMX_PUNPCKHDQrr:
18354	case PUNPCKHDQrm:
18355	case PUNPCKHDQrr:
18356		return true;
18357	}
18358	return false;
18359}
18360
18361bool isVPCOMUW(unsigned Opcode) {
18362	switch (Opcode) {
18363	case VPCOMUWmi:
18364	case VPCOMUWri:
18365		return true;
18366	}
18367	return false;
18368}
18369
18370bool isPMULDQ(unsigned Opcode) {
18371	switch (Opcode) {
18372	case PMULDQrm:
18373	case PMULDQrr:
18374		return true;
18375	}
18376	return false;
18377}
18378
18379bool isT1MSKC(unsigned Opcode) {
18380	switch (Opcode) {
18381	case T1MSKC32rm:
18382	case T1MSKC32rr:
18383	case T1MSKC64rm:
18384	case T1MSKC64rr:
18385		return true;
18386	}
18387	return false;
18388}
18389
18390bool isIN(unsigned Opcode) {
18391	switch (Opcode) {
18392	case IN16ri:
18393	case IN16rr:
18394	case IN32ri:
18395	case IN32rr:
18396	case IN8ri:
18397	case IN8rr:
18398		return true;
18399	}
18400	return false;
18401}
18402
18403bool isVPHADDBD(unsigned Opcode) {
18404	switch (Opcode) {
18405	case VPHADDBDrm:
18406	case VPHADDBDrr:
18407		return true;
18408	}
18409	return false;
18410}
18411
18412bool isSAR(unsigned Opcode) {
18413	switch (Opcode) {
18414	case SAR16m1:
18415	case SAR16mCL:
18416	case SAR16mi:
18417	case SAR16r1:
18418	case SAR16rCL:
18419	case SAR16ri:
18420	case SAR32m1:
18421	case SAR32mCL:
18422	case SAR32mi:
18423	case SAR32r1:
18424	case SAR32rCL:
18425	case SAR32ri:
18426	case SAR64m1:
18427	case SAR64mCL:
18428	case SAR64mi:
18429	case SAR64r1:
18430	case SAR64rCL:
18431	case SAR64ri:
18432	case SAR8m1:
18433	case SAR8mCL:
18434	case SAR8mi:
18435	case SAR8r1:
18436	case SAR8rCL:
18437	case SAR8ri:
18438		return true;
18439	}
18440	return false;
18441}
18442
18443bool isVPHADDBQ(unsigned Opcode) {
18444	switch (Opcode) {
18445	case VPHADDBQrm:
18446	case VPHADDBQrr:
18447		return true;
18448	}
18449	return false;
18450}
18451
18452bool isVFNMSUB231PD(unsigned Opcode) {
18453	switch (Opcode) {
18454	case VFNMSUB231PDYm:
18455	case VFNMSUB231PDYr:
18456	case VFNMSUB231PDZ128m:
18457	case VFNMSUB231PDZ128mb:
18458	case VFNMSUB231PDZ128mbk:
18459	case VFNMSUB231PDZ128mbkz:
18460	case VFNMSUB231PDZ128mk:
18461	case VFNMSUB231PDZ128mkz:
18462	case VFNMSUB231PDZ128r:
18463	case VFNMSUB231PDZ128rk:
18464	case VFNMSUB231PDZ128rkz:
18465	case VFNMSUB231PDZ256m:
18466	case VFNMSUB231PDZ256mb:
18467	case VFNMSUB231PDZ256mbk:
18468	case VFNMSUB231PDZ256mbkz:
18469	case VFNMSUB231PDZ256mk:
18470	case VFNMSUB231PDZ256mkz:
18471	case VFNMSUB231PDZ256r:
18472	case VFNMSUB231PDZ256rk:
18473	case VFNMSUB231PDZ256rkz:
18474	case VFNMSUB231PDZm:
18475	case VFNMSUB231PDZmb:
18476	case VFNMSUB231PDZmbk:
18477	case VFNMSUB231PDZmbkz:
18478	case VFNMSUB231PDZmk:
18479	case VFNMSUB231PDZmkz:
18480	case VFNMSUB231PDZr:
18481	case VFNMSUB231PDZrb:
18482	case VFNMSUB231PDZrbk:
18483	case VFNMSUB231PDZrbkz:
18484	case VFNMSUB231PDZrk:
18485	case VFNMSUB231PDZrkz:
18486	case VFNMSUB231PDm:
18487	case VFNMSUB231PDr:
18488		return true;
18489	}
18490	return false;
18491}
18492
18493bool isVPSHLDVD(unsigned Opcode) {
18494	switch (Opcode) {
18495	case VPSHLDVDZ128m:
18496	case VPSHLDVDZ128mb:
18497	case VPSHLDVDZ128mbk:
18498	case VPSHLDVDZ128mbkz:
18499	case VPSHLDVDZ128mk:
18500	case VPSHLDVDZ128mkz:
18501	case VPSHLDVDZ128r:
18502	case VPSHLDVDZ128rk:
18503	case VPSHLDVDZ128rkz:
18504	case VPSHLDVDZ256m:
18505	case VPSHLDVDZ256mb:
18506	case VPSHLDVDZ256mbk:
18507	case VPSHLDVDZ256mbkz:
18508	case VPSHLDVDZ256mk:
18509	case VPSHLDVDZ256mkz:
18510	case VPSHLDVDZ256r:
18511	case VPSHLDVDZ256rk:
18512	case VPSHLDVDZ256rkz:
18513	case VPSHLDVDZm:
18514	case VPSHLDVDZmb:
18515	case VPSHLDVDZmbk:
18516	case VPSHLDVDZmbkz:
18517	case VPSHLDVDZmk:
18518	case VPSHLDVDZmkz:
18519	case VPSHLDVDZr:
18520	case VPSHLDVDZrk:
18521	case VPSHLDVDZrkz:
18522		return true;
18523	}
18524	return false;
18525}
18526
18527bool isFSCALE(unsigned Opcode) {
18528	return Opcode == FSCALE;
18529}
18530
18531bool isVFNMSUB231PH(unsigned Opcode) {
18532	switch (Opcode) {
18533	case VFNMSUB231PHZ128m:
18534	case VFNMSUB231PHZ128mb:
18535	case VFNMSUB231PHZ128mbk:
18536	case VFNMSUB231PHZ128mbkz:
18537	case VFNMSUB231PHZ128mk:
18538	case VFNMSUB231PHZ128mkz:
18539	case VFNMSUB231PHZ128r:
18540	case VFNMSUB231PHZ128rk:
18541	case VFNMSUB231PHZ128rkz:
18542	case VFNMSUB231PHZ256m:
18543	case VFNMSUB231PHZ256mb:
18544	case VFNMSUB231PHZ256mbk:
18545	case VFNMSUB231PHZ256mbkz:
18546	case VFNMSUB231PHZ256mk:
18547	case VFNMSUB231PHZ256mkz:
18548	case VFNMSUB231PHZ256r:
18549	case VFNMSUB231PHZ256rk:
18550	case VFNMSUB231PHZ256rkz:
18551	case VFNMSUB231PHZm:
18552	case VFNMSUB231PHZmb:
18553	case VFNMSUB231PHZmbk:
18554	case VFNMSUB231PHZmbkz:
18555	case VFNMSUB231PHZmk:
18556	case VFNMSUB231PHZmkz:
18557	case VFNMSUB231PHZr:
18558	case VFNMSUB231PHZrb:
18559	case VFNMSUB231PHZrbk:
18560	case VFNMSUB231PHZrbkz:
18561	case VFNMSUB231PHZrk:
18562	case VFNMSUB231PHZrkz:
18563		return true;
18564	}
18565	return false;
18566}
18567
18568bool isVPHADDBW(unsigned Opcode) {
18569	switch (Opcode) {
18570	case VPHADDBWrm:
18571	case VPHADDBWrr:
18572		return true;
18573	}
18574	return false;
18575}
18576
18577bool isSBB(unsigned Opcode) {
18578	switch (Opcode) {
18579	case SBB16i16:
18580	case SBB16mi:
18581	case SBB16mi8:
18582	case SBB16mr:
18583	case SBB16ri:
18584	case SBB16ri8:
18585	case SBB16rm:
18586	case SBB16rr:
18587	case SBB16rr_REV:
18588	case SBB32i32:
18589	case SBB32mi:
18590	case SBB32mi8:
18591	case SBB32mr:
18592	case SBB32ri:
18593	case SBB32ri8:
18594	case SBB32rm:
18595	case SBB32rr:
18596	case SBB32rr_REV:
18597	case SBB64i32:
18598	case SBB64mi32:
18599	case SBB64mi8:
18600	case SBB64mr:
18601	case SBB64ri32:
18602	case SBB64ri8:
18603	case SBB64rm:
18604	case SBB64rr:
18605	case SBB64rr_REV:
18606	case SBB8i8:
18607	case SBB8mi:
18608	case SBB8mi8:
18609	case SBB8mr:
18610	case SBB8ri:
18611	case SBB8ri8:
18612	case SBB8rm:
18613	case SBB8rr:
18614	case SBB8rr_REV:
18615		return true;
18616	}
18617	return false;
18618}
18619
18620bool isVPSHLDVQ(unsigned Opcode) {
18621	switch (Opcode) {
18622	case VPSHLDVQZ128m:
18623	case VPSHLDVQZ128mb:
18624	case VPSHLDVQZ128mbk:
18625	case VPSHLDVQZ128mbkz:
18626	case VPSHLDVQZ128mk:
18627	case VPSHLDVQZ128mkz:
18628	case VPSHLDVQZ128r:
18629	case VPSHLDVQZ128rk:
18630	case VPSHLDVQZ128rkz:
18631	case VPSHLDVQZ256m:
18632	case VPSHLDVQZ256mb:
18633	case VPSHLDVQZ256mbk:
18634	case VPSHLDVQZ256mbkz:
18635	case VPSHLDVQZ256mk:
18636	case VPSHLDVQZ256mkz:
18637	case VPSHLDVQZ256r:
18638	case VPSHLDVQZ256rk:
18639	case VPSHLDVQZ256rkz:
18640	case VPSHLDVQZm:
18641	case VPSHLDVQZmb:
18642	case VPSHLDVQZmbk:
18643	case VPSHLDVQZmbkz:
18644	case VPSHLDVQZmk:
18645	case VPSHLDVQZmkz:
18646	case VPSHLDVQZr:
18647	case VPSHLDVQZrk:
18648	case VPSHLDVQZrkz:
18649		return true;
18650	}
18651	return false;
18652}
18653
18654bool isVFNMSUB231PS(unsigned Opcode) {
18655	switch (Opcode) {
18656	case VFNMSUB231PSYm:
18657	case VFNMSUB231PSYr:
18658	case VFNMSUB231PSZ128m:
18659	case VFNMSUB231PSZ128mb:
18660	case VFNMSUB231PSZ128mbk:
18661	case VFNMSUB231PSZ128mbkz:
18662	case VFNMSUB231PSZ128mk:
18663	case VFNMSUB231PSZ128mkz:
18664	case VFNMSUB231PSZ128r:
18665	case VFNMSUB231PSZ128rk:
18666	case VFNMSUB231PSZ128rkz:
18667	case VFNMSUB231PSZ256m:
18668	case VFNMSUB231PSZ256mb:
18669	case VFNMSUB231PSZ256mbk:
18670	case VFNMSUB231PSZ256mbkz:
18671	case VFNMSUB231PSZ256mk:
18672	case VFNMSUB231PSZ256mkz:
18673	case VFNMSUB231PSZ256r:
18674	case VFNMSUB231PSZ256rk:
18675	case VFNMSUB231PSZ256rkz:
18676	case VFNMSUB231PSZm:
18677	case VFNMSUB231PSZmb:
18678	case VFNMSUB231PSZmbk:
18679	case VFNMSUB231PSZmbkz:
18680	case VFNMSUB231PSZmk:
18681	case VFNMSUB231PSZmkz:
18682	case VFNMSUB231PSZr:
18683	case VFNMSUB231PSZrb:
18684	case VFNMSUB231PSZrbk:
18685	case VFNMSUB231PSZrbkz:
18686	case VFNMSUB231PSZrk:
18687	case VFNMSUB231PSZrkz:
18688	case VFNMSUB231PSm:
18689	case VFNMSUB231PSr:
18690		return true;
18691	}
18692	return false;
18693}
18694
18695bool isVPDPBUSDS(unsigned Opcode) {
18696	switch (Opcode) {
18697	case VPDPBUSDSYrm:
18698	case VPDPBUSDSYrr:
18699	case VPDPBUSDSZ128m:
18700	case VPDPBUSDSZ128mb:
18701	case VPDPBUSDSZ128mbk:
18702	case VPDPBUSDSZ128mbkz:
18703	case VPDPBUSDSZ128mk:
18704	case VPDPBUSDSZ128mkz:
18705	case VPDPBUSDSZ128r:
18706	case VPDPBUSDSZ128rk:
18707	case VPDPBUSDSZ128rkz:
18708	case VPDPBUSDSZ256m:
18709	case VPDPBUSDSZ256mb:
18710	case VPDPBUSDSZ256mbk:
18711	case VPDPBUSDSZ256mbkz:
18712	case VPDPBUSDSZ256mk:
18713	case VPDPBUSDSZ256mkz:
18714	case VPDPBUSDSZ256r:
18715	case VPDPBUSDSZ256rk:
18716	case VPDPBUSDSZ256rkz:
18717	case VPDPBUSDSZm:
18718	case VPDPBUSDSZmb:
18719	case VPDPBUSDSZmbk:
18720	case VPDPBUSDSZmbkz:
18721	case VPDPBUSDSZmk:
18722	case VPDPBUSDSZmkz:
18723	case VPDPBUSDSZr:
18724	case VPDPBUSDSZrk:
18725	case VPDPBUSDSZrkz:
18726	case VPDPBUSDSrm:
18727	case VPDPBUSDSrr:
18728		return true;
18729	}
18730	return false;
18731}
18732
18733bool isFCOMPI(unsigned Opcode) {
18734	return Opcode == COM_FIPr;
18735}
18736
18737bool isRSQRTPS(unsigned Opcode) {
18738	switch (Opcode) {
18739	case RSQRTPSm:
18740	case RSQRTPSr:
18741		return true;
18742	}
18743	return false;
18744}
18745
18746bool isVSHUFPD(unsigned Opcode) {
18747	switch (Opcode) {
18748	case VSHUFPDYrmi:
18749	case VSHUFPDYrri:
18750	case VSHUFPDZ128rmbi:
18751	case VSHUFPDZ128rmbik:
18752	case VSHUFPDZ128rmbikz:
18753	case VSHUFPDZ128rmi:
18754	case VSHUFPDZ128rmik:
18755	case VSHUFPDZ128rmikz:
18756	case VSHUFPDZ128rri:
18757	case VSHUFPDZ128rrik:
18758	case VSHUFPDZ128rrikz:
18759	case VSHUFPDZ256rmbi:
18760	case VSHUFPDZ256rmbik:
18761	case VSHUFPDZ256rmbikz:
18762	case VSHUFPDZ256rmi:
18763	case VSHUFPDZ256rmik:
18764	case VSHUFPDZ256rmikz:
18765	case VSHUFPDZ256rri:
18766	case VSHUFPDZ256rrik:
18767	case VSHUFPDZ256rrikz:
18768	case VSHUFPDZrmbi:
18769	case VSHUFPDZrmbik:
18770	case VSHUFPDZrmbikz:
18771	case VSHUFPDZrmi:
18772	case VSHUFPDZrmik:
18773	case VSHUFPDZrmikz:
18774	case VSHUFPDZrri:
18775	case VSHUFPDZrrik:
18776	case VSHUFPDZrrikz:
18777	case VSHUFPDrmi:
18778	case VSHUFPDrri:
18779		return true;
18780	}
18781	return false;
18782}
18783
18784bool isVPSHLDVW(unsigned Opcode) {
18785	switch (Opcode) {
18786	case VPSHLDVWZ128m:
18787	case VPSHLDVWZ128mk:
18788	case VPSHLDVWZ128mkz:
18789	case VPSHLDVWZ128r:
18790	case VPSHLDVWZ128rk:
18791	case VPSHLDVWZ128rkz:
18792	case VPSHLDVWZ256m:
18793	case VPSHLDVWZ256mk:
18794	case VPSHLDVWZ256mkz:
18795	case VPSHLDVWZ256r:
18796	case VPSHLDVWZ256rk:
18797	case VPSHLDVWZ256rkz:
18798	case VPSHLDVWZm:
18799	case VPSHLDVWZmk:
18800	case VPSHLDVWZmkz:
18801	case VPSHLDVWZr:
18802	case VPSHLDVWZrk:
18803	case VPSHLDVWZrkz:
18804		return true;
18805	}
18806	return false;
18807}
18808
18809bool isVPADDSB(unsigned Opcode) {
18810	switch (Opcode) {
18811	case VPADDSBYrm:
18812	case VPADDSBYrr:
18813	case VPADDSBZ128rm:
18814	case VPADDSBZ128rmk:
18815	case VPADDSBZ128rmkz:
18816	case VPADDSBZ128rr:
18817	case VPADDSBZ128rrk:
18818	case VPADDSBZ128rrkz:
18819	case VPADDSBZ256rm:
18820	case VPADDSBZ256rmk:
18821	case VPADDSBZ256rmkz:
18822	case VPADDSBZ256rr:
18823	case VPADDSBZ256rrk:
18824	case VPADDSBZ256rrkz:
18825	case VPADDSBZrm:
18826	case VPADDSBZrmk:
18827	case VPADDSBZrmkz:
18828	case VPADDSBZrr:
18829	case VPADDSBZrrk:
18830	case VPADDSBZrrkz:
18831	case VPADDSBrm:
18832	case VPADDSBrr:
18833		return true;
18834	}
18835	return false;
18836}
18837
18838bool isFCOMPP(unsigned Opcode) {
18839	return Opcode == FCOMPP;
18840}
18841
18842bool isDAA(unsigned Opcode) {
18843	return Opcode == DAA;
18844}
18845
18846bool isVFNMSUB213SD(unsigned Opcode) {
18847	switch (Opcode) {
18848	case VFNMSUB213SDZm_Int:
18849	case VFNMSUB213SDZm_Intk:
18850	case VFNMSUB213SDZm_Intkz:
18851	case VFNMSUB213SDZr_Int:
18852	case VFNMSUB213SDZr_Intk:
18853	case VFNMSUB213SDZr_Intkz:
18854	case VFNMSUB213SDZrb_Int:
18855	case VFNMSUB213SDZrb_Intk:
18856	case VFNMSUB213SDZrb_Intkz:
18857	case VFNMSUB213SDm_Int:
18858	case VFNMSUB213SDr_Int:
18859		return true;
18860	}
18861	return false;
18862}
18863
18864bool isVSHUFPS(unsigned Opcode) {
18865	switch (Opcode) {
18866	case VSHUFPSYrmi:
18867	case VSHUFPSYrri:
18868	case VSHUFPSZ128rmbi:
18869	case VSHUFPSZ128rmbik:
18870	case VSHUFPSZ128rmbikz:
18871	case VSHUFPSZ128rmi:
18872	case VSHUFPSZ128rmik:
18873	case VSHUFPSZ128rmikz:
18874	case VSHUFPSZ128rri:
18875	case VSHUFPSZ128rrik:
18876	case VSHUFPSZ128rrikz:
18877	case VSHUFPSZ256rmbi:
18878	case VSHUFPSZ256rmbik:
18879	case VSHUFPSZ256rmbikz:
18880	case VSHUFPSZ256rmi:
18881	case VSHUFPSZ256rmik:
18882	case VSHUFPSZ256rmikz:
18883	case VSHUFPSZ256rri:
18884	case VSHUFPSZ256rrik:
18885	case VSHUFPSZ256rrikz:
18886	case VSHUFPSZrmbi:
18887	case VSHUFPSZrmbik:
18888	case VSHUFPSZrmbikz:
18889	case VSHUFPSZrmi:
18890	case VSHUFPSZrmik:
18891	case VSHUFPSZrmikz:
18892	case VSHUFPSZrri:
18893	case VSHUFPSZrrik:
18894	case VSHUFPSZrrikz:
18895	case VSHUFPSrmi:
18896	case VSHUFPSrri:
18897		return true;
18898	}
18899	return false;
18900}
18901
18902bool isINVLPGA(unsigned Opcode) {
18903	switch (Opcode) {
18904	case INVLPGA32:
18905	case INVLPGA64:
18906		return true;
18907	}
18908	return false;
18909}
18910
18911bool isINVLPGB(unsigned Opcode) {
18912	switch (Opcode) {
18913	case INVLPGB32:
18914	case INVLPGB64:
18915		return true;
18916	}
18917	return false;
18918}
18919
18920bool isVFNMSUB213SH(unsigned Opcode) {
18921	switch (Opcode) {
18922	case VFNMSUB213SHZm_Int:
18923	case VFNMSUB213SHZm_Intk:
18924	case VFNMSUB213SHZm_Intkz:
18925	case VFNMSUB213SHZr_Int:
18926	case VFNMSUB213SHZr_Intk:
18927	case VFNMSUB213SHZr_Intkz:
18928	case VFNMSUB213SHZrb_Int:
18929	case VFNMSUB213SHZrb_Intk:
18930	case VFNMSUB213SHZrb_Intkz:
18931		return true;
18932	}
18933	return false;
18934}
18935
18936bool isDAS(unsigned Opcode) {
18937	return Opcode == DAS;
18938}
18939
18940bool isVPADDSW(unsigned Opcode) {
18941	switch (Opcode) {
18942	case VPADDSWYrm:
18943	case VPADDSWYrr:
18944	case VPADDSWZ128rm:
18945	case VPADDSWZ128rmk:
18946	case VPADDSWZ128rmkz:
18947	case VPADDSWZ128rr:
18948	case VPADDSWZ128rrk:
18949	case VPADDSWZ128rrkz:
18950	case VPADDSWZ256rm:
18951	case VPADDSWZ256rmk:
18952	case VPADDSWZ256rmkz:
18953	case VPADDSWZ256rr:
18954	case VPADDSWZ256rrk:
18955	case VPADDSWZ256rrkz:
18956	case VPADDSWZrm:
18957	case VPADDSWZrmk:
18958	case VPADDSWZrmkz:
18959	case VPADDSWZrr:
18960	case VPADDSWZrrk:
18961	case VPADDSWZrrkz:
18962	case VPADDSWrm:
18963	case VPADDSWrr:
18964		return true;
18965	}
18966	return false;
18967}
18968
18969bool isVFNMSUB213SS(unsigned Opcode) {
18970	switch (Opcode) {
18971	case VFNMSUB213SSZm_Int:
18972	case VFNMSUB213SSZm_Intk:
18973	case VFNMSUB213SSZm_Intkz:
18974	case VFNMSUB213SSZr_Int:
18975	case VFNMSUB213SSZr_Intk:
18976	case VFNMSUB213SSZr_Intkz:
18977	case VFNMSUB213SSZrb_Int:
18978	case VFNMSUB213SSZrb_Intk:
18979	case VFNMSUB213SSZrb_Intkz:
18980	case VFNMSUB213SSm_Int:
18981	case VFNMSUB213SSr_Int:
18982		return true;
18983	}
18984	return false;
18985}
18986
18987bool isFCOM(unsigned Opcode) {
18988	switch (Opcode) {
18989	case COM_FST0r:
18990	case FCOM32m:
18991	case FCOM64m:
18992		return true;
18993	}
18994	return false;
18995}
18996
18997bool isKXORB(unsigned Opcode) {
18998	return Opcode == KXORBrr;
18999}
19000
19001bool isKXORD(unsigned Opcode) {
19002	return Opcode == KXORDrr;
19003}
19004
19005bool isFCOS(unsigned Opcode) {
19006	return Opcode == FCOS;
19007}
19008
19009bool isVPHADDDQ(unsigned Opcode) {
19010	switch (Opcode) {
19011	case VPHADDDQrm:
19012	case VPHADDDQrr:
19013		return true;
19014	}
19015	return false;
19016}
19017
19018bool isCLDEMOTE(unsigned Opcode) {
19019	return Opcode == CLDEMOTE;
19020}
19021
19022bool isKXORQ(unsigned Opcode) {
19023	return Opcode == KXORQrr;
19024}
19025
19026bool isKXORW(unsigned Opcode) {
19027	return Opcode == KXORWrr;
19028}
19029
19030bool isVDPBF16PS(unsigned Opcode) {
19031	switch (Opcode) {
19032	case VDPBF16PSZ128m:
19033	case VDPBF16PSZ128mb:
19034	case VDPBF16PSZ128mbk:
19035	case VDPBF16PSZ128mbkz:
19036	case VDPBF16PSZ128mk:
19037	case VDPBF16PSZ128mkz:
19038	case VDPBF16PSZ128r:
19039	case VDPBF16PSZ128rk:
19040	case VDPBF16PSZ128rkz:
19041	case VDPBF16PSZ256m:
19042	case VDPBF16PSZ256mb:
19043	case VDPBF16PSZ256mbk:
19044	case VDPBF16PSZ256mbkz:
19045	case VDPBF16PSZ256mk:
19046	case VDPBF16PSZ256mkz:
19047	case VDPBF16PSZ256r:
19048	case VDPBF16PSZ256rk:
19049	case VDPBF16PSZ256rkz:
19050	case VDPBF16PSZm:
19051	case VDPBF16PSZmb:
19052	case VDPBF16PSZmbk:
19053	case VDPBF16PSZmbkz:
19054	case VDPBF16PSZmk:
19055	case VDPBF16PSZmkz:
19056	case VDPBF16PSZr:
19057	case VDPBF16PSZrk:
19058	case VDPBF16PSZrkz:
19059		return true;
19060	}
19061	return false;
19062}
19063
19064bool isCLGI(unsigned Opcode) {
19065	return Opcode == CLGI;
19066}
19067
19068bool isVMREAD(unsigned Opcode) {
19069	switch (Opcode) {
19070	case VMREAD32mr:
19071	case VMREAD32rr:
19072	case VMREAD64mr:
19073	case VMREAD64rr:
19074		return true;
19075	}
19076	return false;
19077}
19078
19079bool isANDPD(unsigned Opcode) {
19080	switch (Opcode) {
19081	case ANDPDrm:
19082	case ANDPDrr:
19083		return true;
19084	}
19085	return false;
19086}
19087
19088bool isVFMSUBPD(unsigned Opcode) {
19089	switch (Opcode) {
19090	case VFMSUBPD4Ymr:
19091	case VFMSUBPD4Yrm:
19092	case VFMSUBPD4Yrr:
19093	case VFMSUBPD4Yrr_REV:
19094	case VFMSUBPD4mr:
19095	case VFMSUBPD4rm:
19096	case VFMSUBPD4rr:
19097	case VFMSUBPD4rr_REV:
19098		return true;
19099	}
19100	return false;
19101}
19102
19103bool isVFNMADD213PD(unsigned Opcode) {
19104	switch (Opcode) {
19105	case VFNMADD213PDYm:
19106	case VFNMADD213PDYr:
19107	case VFNMADD213PDZ128m:
19108	case VFNMADD213PDZ128mb:
19109	case VFNMADD213PDZ128mbk:
19110	case VFNMADD213PDZ128mbkz:
19111	case VFNMADD213PDZ128mk:
19112	case VFNMADD213PDZ128mkz:
19113	case VFNMADD213PDZ128r:
19114	case VFNMADD213PDZ128rk:
19115	case VFNMADD213PDZ128rkz:
19116	case VFNMADD213PDZ256m:
19117	case VFNMADD213PDZ256mb:
19118	case VFNMADD213PDZ256mbk:
19119	case VFNMADD213PDZ256mbkz:
19120	case VFNMADD213PDZ256mk:
19121	case VFNMADD213PDZ256mkz:
19122	case VFNMADD213PDZ256r:
19123	case VFNMADD213PDZ256rk:
19124	case VFNMADD213PDZ256rkz:
19125	case VFNMADD213PDZm:
19126	case VFNMADD213PDZmb:
19127	case VFNMADD213PDZmbk:
19128	case VFNMADD213PDZmbkz:
19129	case VFNMADD213PDZmk:
19130	case VFNMADD213PDZmkz:
19131	case VFNMADD213PDZr:
19132	case VFNMADD213PDZrb:
19133	case VFNMADD213PDZrbk:
19134	case VFNMADD213PDZrbkz:
19135	case VFNMADD213PDZrk:
19136	case VFNMADD213PDZrkz:
19137	case VFNMADD213PDm:
19138	case VFNMADD213PDr:
19139		return true;
19140	}
19141	return false;
19142}
19143
19144bool isVFNMADD213PH(unsigned Opcode) {
19145	switch (Opcode) {
19146	case VFNMADD213PHZ128m:
19147	case VFNMADD213PHZ128mb:
19148	case VFNMADD213PHZ128mbk:
19149	case VFNMADD213PHZ128mbkz:
19150	case VFNMADD213PHZ128mk:
19151	case VFNMADD213PHZ128mkz:
19152	case VFNMADD213PHZ128r:
19153	case VFNMADD213PHZ128rk:
19154	case VFNMADD213PHZ128rkz:
19155	case VFNMADD213PHZ256m:
19156	case VFNMADD213PHZ256mb:
19157	case VFNMADD213PHZ256mbk:
19158	case VFNMADD213PHZ256mbkz:
19159	case VFNMADD213PHZ256mk:
19160	case VFNMADD213PHZ256mkz:
19161	case VFNMADD213PHZ256r:
19162	case VFNMADD213PHZ256rk:
19163	case VFNMADD213PHZ256rkz:
19164	case VFNMADD213PHZm:
19165	case VFNMADD213PHZmb:
19166	case VFNMADD213PHZmbk:
19167	case VFNMADD213PHZmbkz:
19168	case VFNMADD213PHZmk:
19169	case VFNMADD213PHZmkz:
19170	case VFNMADD213PHZr:
19171	case VFNMADD213PHZrb:
19172	case VFNMADD213PHZrbk:
19173	case VFNMADD213PHZrbkz:
19174	case VFNMADD213PHZrk:
19175	case VFNMADD213PHZrkz:
19176		return true;
19177	}
19178	return false;
19179}
19180
19181bool isVFNMSUB231SD(unsigned Opcode) {
19182	switch (Opcode) {
19183	case VFNMSUB231SDZm_Int:
19184	case VFNMSUB231SDZm_Intk:
19185	case VFNMSUB231SDZm_Intkz:
19186	case VFNMSUB231SDZr_Int:
19187	case VFNMSUB231SDZr_Intk:
19188	case VFNMSUB231SDZr_Intkz:
19189	case VFNMSUB231SDZrb_Int:
19190	case VFNMSUB231SDZrb_Intk:
19191	case VFNMSUB231SDZrb_Intkz:
19192	case VFNMSUB231SDm_Int:
19193	case VFNMSUB231SDr_Int:
19194		return true;
19195	}
19196	return false;
19197}
19198
19199bool isFSQRT(unsigned Opcode) {
19200	return Opcode == SQRT_F;
19201}
19202
19203bool isVFNMSUB231SH(unsigned Opcode) {
19204	switch (Opcode) {
19205	case VFNMSUB231SHZm_Int:
19206	case VFNMSUB231SHZm_Intk:
19207	case VFNMSUB231SHZm_Intkz:
19208	case VFNMSUB231SHZr_Int:
19209	case VFNMSUB231SHZr_Intk:
19210	case VFNMSUB231SHZr_Intkz:
19211	case VFNMSUB231SHZrb_Int:
19212	case VFNMSUB231SHZrb_Intk:
19213	case VFNMSUB231SHZrb_Intkz:
19214		return true;
19215	}
19216	return false;
19217}
19218
19219bool isPCLMULQDQ(unsigned Opcode) {
19220	switch (Opcode) {
19221	case PCLMULQDQrm:
19222	case PCLMULQDQrr:
19223		return true;
19224	}
19225	return false;
19226}
19227
19228bool isVRCP14PD(unsigned Opcode) {
19229	switch (Opcode) {
19230	case VRCP14PDZ128m:
19231	case VRCP14PDZ128mb:
19232	case VRCP14PDZ128mbk:
19233	case VRCP14PDZ128mbkz:
19234	case VRCP14PDZ128mk:
19235	case VRCP14PDZ128mkz:
19236	case VRCP14PDZ128r:
19237	case VRCP14PDZ128rk:
19238	case VRCP14PDZ128rkz:
19239	case VRCP14PDZ256m:
19240	case VRCP14PDZ256mb:
19241	case VRCP14PDZ256mbk:
19242	case VRCP14PDZ256mbkz:
19243	case VRCP14PDZ256mk:
19244	case VRCP14PDZ256mkz:
19245	case VRCP14PDZ256r:
19246	case VRCP14PDZ256rk:
19247	case VRCP14PDZ256rkz:
19248	case VRCP14PDZm:
19249	case VRCP14PDZmb:
19250	case VRCP14PDZmbk:
19251	case VRCP14PDZmbkz:
19252	case VRCP14PDZmk:
19253	case VRCP14PDZmkz:
19254	case VRCP14PDZr:
19255	case VRCP14PDZrk:
19256	case VRCP14PDZrkz:
19257		return true;
19258	}
19259	return false;
19260}
19261
19262bool isANDPS(unsigned Opcode) {
19263	switch (Opcode) {
19264	case ANDPSrm:
19265	case ANDPSrr:
19266		return true;
19267	}
19268	return false;
19269}
19270
19271bool isVFMSUBPS(unsigned Opcode) {
19272	switch (Opcode) {
19273	case VFMSUBPS4Ymr:
19274	case VFMSUBPS4Yrm:
19275	case VFMSUBPS4Yrr:
19276	case VFMSUBPS4Yrr_REV:
19277	case VFMSUBPS4mr:
19278	case VFMSUBPS4rm:
19279	case VFMSUBPS4rr:
19280	case VFMSUBPS4rr_REV:
19281		return true;
19282	}
19283	return false;
19284}
19285
19286bool isVFNMADD213PS(unsigned Opcode) {
19287	switch (Opcode) {
19288	case VFNMADD213PSYm:
19289	case VFNMADD213PSYr:
19290	case VFNMADD213PSZ128m:
19291	case VFNMADD213PSZ128mb:
19292	case VFNMADD213PSZ128mbk:
19293	case VFNMADD213PSZ128mbkz:
19294	case VFNMADD213PSZ128mk:
19295	case VFNMADD213PSZ128mkz:
19296	case VFNMADD213PSZ128r:
19297	case VFNMADD213PSZ128rk:
19298	case VFNMADD213PSZ128rkz:
19299	case VFNMADD213PSZ256m:
19300	case VFNMADD213PSZ256mb:
19301	case VFNMADD213PSZ256mbk:
19302	case VFNMADD213PSZ256mbkz:
19303	case VFNMADD213PSZ256mk:
19304	case VFNMADD213PSZ256mkz:
19305	case VFNMADD213PSZ256r:
19306	case VFNMADD213PSZ256rk:
19307	case VFNMADD213PSZ256rkz:
19308	case VFNMADD213PSZm:
19309	case VFNMADD213PSZmb:
19310	case VFNMADD213PSZmbk:
19311	case VFNMADD213PSZmbkz:
19312	case VFNMADD213PSZmk:
19313	case VFNMADD213PSZmkz:
19314	case VFNMADD213PSZr:
19315	case VFNMADD213PSZrb:
19316	case VFNMADD213PSZrbk:
19317	case VFNMADD213PSZrbkz:
19318	case VFNMADD213PSZrk:
19319	case VFNMADD213PSZrkz:
19320	case VFNMADD213PSm:
19321	case VFNMADD213PSr:
19322		return true;
19323	}
19324	return false;
19325}
19326
19327bool isPMULHW(unsigned Opcode) {
19328	switch (Opcode) {
19329	case MMX_PMULHWrm:
19330	case MMX_PMULHWrr:
19331	case PMULHWrm:
19332	case PMULHWrr:
19333		return true;
19334	}
19335	return false;
19336}
19337
19338bool isVFNMSUB231SS(unsigned Opcode) {
19339	switch (Opcode) {
19340	case VFNMSUB231SSZm_Int:
19341	case VFNMSUB231SSZm_Intk:
19342	case VFNMSUB231SSZm_Intkz:
19343	case VFNMSUB231SSZr_Int:
19344	case VFNMSUB231SSZr_Intk:
19345	case VFNMSUB231SSZr_Intkz:
19346	case VFNMSUB231SSZrb_Int:
19347	case VFNMSUB231SSZrb_Intk:
19348	case VFNMSUB231SSZrb_Intkz:
19349	case VFNMSUB231SSm_Int:
19350	case VFNMSUB231SSr_Int:
19351		return true;
19352	}
19353	return false;
19354}
19355
19356bool isAESDECWIDE256KL(unsigned Opcode) {
19357	return Opcode == AESDECWIDE256KL;
19358}
19359
19360bool isRSQRTSS(unsigned Opcode) {
19361	switch (Opcode) {
19362	case RSQRTSSm_Int:
19363	case RSQRTSSr_Int:
19364		return true;
19365	}
19366	return false;
19367}
19368
19369bool isVRCP14PS(unsigned Opcode) {
19370	switch (Opcode) {
19371	case VRCP14PSZ128m:
19372	case VRCP14PSZ128mb:
19373	case VRCP14PSZ128mbk:
19374	case VRCP14PSZ128mbkz:
19375	case VRCP14PSZ128mk:
19376	case VRCP14PSZ128mkz:
19377	case VRCP14PSZ128r:
19378	case VRCP14PSZ128rk:
19379	case VRCP14PSZ128rkz:
19380	case VRCP14PSZ256m:
19381	case VRCP14PSZ256mb:
19382	case VRCP14PSZ256mbk:
19383	case VRCP14PSZ256mbkz:
19384	case VRCP14PSZ256mk:
19385	case VRCP14PSZ256mkz:
19386	case VRCP14PSZ256r:
19387	case VRCP14PSZ256rk:
19388	case VRCP14PSZ256rkz:
19389	case VRCP14PSZm:
19390	case VRCP14PSZmb:
19391	case VRCP14PSZmbk:
19392	case VRCP14PSZmbkz:
19393	case VRCP14PSZmk:
19394	case VRCP14PSZmkz:
19395	case VRCP14PSZr:
19396	case VRCP14PSZrk:
19397	case VRCP14PSZrkz:
19398		return true;
19399	}
19400	return false;
19401}
19402
19403bool isVZEROUPPER(unsigned Opcode) {
19404	return Opcode == VZEROUPPER;
19405}
19406
19407bool isVPAVGB(unsigned Opcode) {
19408	switch (Opcode) {
19409	case VPAVGBYrm:
19410	case VPAVGBYrr:
19411	case VPAVGBZ128rm:
19412	case VPAVGBZ128rmk:
19413	case VPAVGBZ128rmkz:
19414	case VPAVGBZ128rr:
19415	case VPAVGBZ128rrk:
19416	case VPAVGBZ128rrkz:
19417	case VPAVGBZ256rm:
19418	case VPAVGBZ256rmk:
19419	case VPAVGBZ256rmkz:
19420	case VPAVGBZ256rr:
19421	case VPAVGBZ256rrk:
19422	case VPAVGBZ256rrkz:
19423	case VPAVGBZrm:
19424	case VPAVGBZrmk:
19425	case VPAVGBZrmkz:
19426	case VPAVGBZrr:
19427	case VPAVGBZrrk:
19428	case VPAVGBZrrkz:
19429	case VPAVGBrm:
19430	case VPAVGBrr:
19431		return true;
19432	}
19433	return false;
19434}
19435
19436bool isVPMOVSXBD(unsigned Opcode) {
19437	switch (Opcode) {
19438	case VPMOVSXBDYrm:
19439	case VPMOVSXBDYrr:
19440	case VPMOVSXBDZ128rm:
19441	case VPMOVSXBDZ128rmk:
19442	case VPMOVSXBDZ128rmkz:
19443	case VPMOVSXBDZ128rr:
19444	case VPMOVSXBDZ128rrk:
19445	case VPMOVSXBDZ128rrkz:
19446	case VPMOVSXBDZ256rm:
19447	case VPMOVSXBDZ256rmk:
19448	case VPMOVSXBDZ256rmkz:
19449	case VPMOVSXBDZ256rr:
19450	case VPMOVSXBDZ256rrk:
19451	case VPMOVSXBDZ256rrkz:
19452	case VPMOVSXBDZrm:
19453	case VPMOVSXBDZrmk:
19454	case VPMOVSXBDZrmkz:
19455	case VPMOVSXBDZrr:
19456	case VPMOVSXBDZrrk:
19457	case VPMOVSXBDZrrkz:
19458	case VPMOVSXBDrm:
19459	case VPMOVSXBDrr:
19460		return true;
19461	}
19462	return false;
19463}
19464
19465bool isRDGSBASE(unsigned Opcode) {
19466	switch (Opcode) {
19467	case RDGSBASE:
19468	case RDGSBASE64:
19469		return true;
19470	}
19471	return false;
19472}
19473
19474bool isFLDCW(unsigned Opcode) {
19475	return Opcode == FLDCW16m;
19476}
19477
19478bool isLIDTD(unsigned Opcode) {
19479	return Opcode == LIDT32m;
19480}
19481
19482bool isVGATHERPF1DPD(unsigned Opcode) {
19483	return Opcode == VGATHERPF1DPDm;
19484}
19485
19486bool isSFENCE(unsigned Opcode) {
19487	return Opcode == SFENCE;
19488}
19489
19490bool isVPMOVSXBQ(unsigned Opcode) {
19491	switch (Opcode) {
19492	case VPMOVSXBQYrm:
19493	case VPMOVSXBQYrr:
19494	case VPMOVSXBQZ128rm:
19495	case VPMOVSXBQZ128rmk:
19496	case VPMOVSXBQZ128rmkz:
19497	case VPMOVSXBQZ128rr:
19498	case VPMOVSXBQZ128rrk:
19499	case VPMOVSXBQZ128rrkz:
19500	case VPMOVSXBQZ256rm:
19501	case VPMOVSXBQZ256rmk:
19502	case VPMOVSXBQZ256rmkz:
19503	case VPMOVSXBQZ256rr:
19504	case VPMOVSXBQZ256rrk:
19505	case VPMOVSXBQZ256rrkz:
19506	case VPMOVSXBQZrm:
19507	case VPMOVSXBQZrmk:
19508	case VPMOVSXBQZrmkz:
19509	case VPMOVSXBQZrr:
19510	case VPMOVSXBQZrrk:
19511	case VPMOVSXBQZrrkz:
19512	case VPMOVSXBQrm:
19513	case VPMOVSXBQrr:
19514		return true;
19515	}
19516	return false;
19517}
19518
19519bool isVPAVGW(unsigned Opcode) {
19520	switch (Opcode) {
19521	case VPAVGWYrm:
19522	case VPAVGWYrr:
19523	case VPAVGWZ128rm:
19524	case VPAVGWZ128rmk:
19525	case VPAVGWZ128rmkz:
19526	case VPAVGWZ128rr:
19527	case VPAVGWZ128rrk:
19528	case VPAVGWZ128rrkz:
19529	case VPAVGWZ256rm:
19530	case VPAVGWZ256rmk:
19531	case VPAVGWZ256rmkz:
19532	case VPAVGWZ256rr:
19533	case VPAVGWZ256rrk:
19534	case VPAVGWZ256rrkz:
19535	case VPAVGWZrm:
19536	case VPAVGWZrmk:
19537	case VPAVGWZrmkz:
19538	case VPAVGWZrr:
19539	case VPAVGWZrrk:
19540	case VPAVGWZrrkz:
19541	case VPAVGWrm:
19542	case VPAVGWrr:
19543		return true;
19544	}
19545	return false;
19546}
19547
19548bool isVPMOVSXBW(unsigned Opcode) {
19549	switch (Opcode) {
19550	case VPMOVSXBWYrm:
19551	case VPMOVSXBWYrr:
19552	case VPMOVSXBWZ128rm:
19553	case VPMOVSXBWZ128rmk:
19554	case VPMOVSXBWZ128rmkz:
19555	case VPMOVSXBWZ128rr:
19556	case VPMOVSXBWZ128rrk:
19557	case VPMOVSXBWZ128rrkz:
19558	case VPMOVSXBWZ256rm:
19559	case VPMOVSXBWZ256rmk:
19560	case VPMOVSXBWZ256rmkz:
19561	case VPMOVSXBWZ256rr:
19562	case VPMOVSXBWZ256rrk:
19563	case VPMOVSXBWZ256rrkz:
19564	case VPMOVSXBWZrm:
19565	case VPMOVSXBWZrmk:
19566	case VPMOVSXBWZrmkz:
19567	case VPMOVSXBWZrr:
19568	case VPMOVSXBWZrrk:
19569	case VPMOVSXBWZrrkz:
19570	case VPMOVSXBWrm:
19571	case VPMOVSXBWrr:
19572		return true;
19573	}
19574	return false;
19575}
19576
19577bool isFCMOVB(unsigned Opcode) {
19578	return Opcode == CMOVB_F;
19579}
19580
19581bool isVMASKMOVDQU(unsigned Opcode) {
19582	return Opcode == VMASKMOVDQU64;
19583}
19584
19585bool isVGATHERPF1DPS(unsigned Opcode) {
19586	return Opcode == VGATHERPF1DPSm;
19587}
19588
19589bool isFCMOVE(unsigned Opcode) {
19590	return Opcode == CMOVE_F;
19591}
19592
19593bool isVMLOAD(unsigned Opcode) {
19594	switch (Opcode) {
19595	case VMLOAD32:
19596	case VMLOAD64:
19597		return true;
19598	}
19599	return false;
19600}
19601
19602bool isLIDTW(unsigned Opcode) {
19603	return Opcode == LIDT16m;
19604}
19605
19606bool isVFNMADD231PD(unsigned Opcode) {
19607	switch (Opcode) {
19608	case VFNMADD231PDYm:
19609	case VFNMADD231PDYr:
19610	case VFNMADD231PDZ128m:
19611	case VFNMADD231PDZ128mb:
19612	case VFNMADD231PDZ128mbk:
19613	case VFNMADD231PDZ128mbkz:
19614	case VFNMADD231PDZ128mk:
19615	case VFNMADD231PDZ128mkz:
19616	case VFNMADD231PDZ128r:
19617	case VFNMADD231PDZ128rk:
19618	case VFNMADD231PDZ128rkz:
19619	case VFNMADD231PDZ256m:
19620	case VFNMADD231PDZ256mb:
19621	case VFNMADD231PDZ256mbk:
19622	case VFNMADD231PDZ256mbkz:
19623	case VFNMADD231PDZ256mk:
19624	case VFNMADD231PDZ256mkz:
19625	case VFNMADD231PDZ256r:
19626	case VFNMADD231PDZ256rk:
19627	case VFNMADD231PDZ256rkz:
19628	case VFNMADD231PDZm:
19629	case VFNMADD231PDZmb:
19630	case VFNMADD231PDZmbk:
19631	case VFNMADD231PDZmbkz:
19632	case VFNMADD231PDZmk:
19633	case VFNMADD231PDZmkz:
19634	case VFNMADD231PDZr:
19635	case VFNMADD231PDZrb:
19636	case VFNMADD231PDZrbk:
19637	case VFNMADD231PDZrbkz:
19638	case VFNMADD231PDZrk:
19639	case VFNMADD231PDZrkz:
19640	case VFNMADD231PDm:
19641	case VFNMADD231PDr:
19642		return true;
19643	}
19644	return false;
19645}
19646
19647bool isDEC(unsigned Opcode) {
19648	switch (Opcode) {
19649	case DEC16m:
19650	case DEC16r:
19651	case DEC16r_alt:
19652	case DEC32m:
19653	case DEC32r:
19654	case DEC32r_alt:
19655	case DEC64m:
19656	case DEC64r:
19657	case DEC8m:
19658	case DEC8r:
19659		return true;
19660	}
19661	return false;
19662}
19663
19664bool isVFNMADD231PH(unsigned Opcode) {
19665	switch (Opcode) {
19666	case VFNMADD231PHZ128m:
19667	case VFNMADD231PHZ128mb:
19668	case VFNMADD231PHZ128mbk:
19669	case VFNMADD231PHZ128mbkz:
19670	case VFNMADD231PHZ128mk:
19671	case VFNMADD231PHZ128mkz:
19672	case VFNMADD231PHZ128r:
19673	case VFNMADD231PHZ128rk:
19674	case VFNMADD231PHZ128rkz:
19675	case VFNMADD231PHZ256m:
19676	case VFNMADD231PHZ256mb:
19677	case VFNMADD231PHZ256mbk:
19678	case VFNMADD231PHZ256mbkz:
19679	case VFNMADD231PHZ256mk:
19680	case VFNMADD231PHZ256mkz:
19681	case VFNMADD231PHZ256r:
19682	case VFNMADD231PHZ256rk:
19683	case VFNMADD231PHZ256rkz:
19684	case VFNMADD231PHZm:
19685	case VFNMADD231PHZmb:
19686	case VFNMADD231PHZmbk:
19687	case VFNMADD231PHZmbkz:
19688	case VFNMADD231PHZmk:
19689	case VFNMADD231PHZmkz:
19690	case VFNMADD231PHZr:
19691	case VFNMADD231PHZrb:
19692	case VFNMADD231PHZrbk:
19693	case VFNMADD231PHZrbkz:
19694	case VFNMADD231PHZrk:
19695	case VFNMADD231PHZrkz:
19696		return true;
19697	}
19698	return false;
19699}
19700
19701bool isFCMOVU(unsigned Opcode) {
19702	return Opcode == CMOVP_F;
19703}
19704
19705bool isRSTORSSP(unsigned Opcode) {
19706	return Opcode == RSTORSSP;
19707}
19708
19709bool isVMAXPD(unsigned Opcode) {
19710	switch (Opcode) {
19711	case VMAXPDYrm:
19712	case VMAXPDYrr:
19713	case VMAXPDZ128rm:
19714	case VMAXPDZ128rmb:
19715	case VMAXPDZ128rmbk:
19716	case VMAXPDZ128rmbkz:
19717	case VMAXPDZ128rmk:
19718	case VMAXPDZ128rmkz:
19719	case VMAXPDZ128rr:
19720	case VMAXPDZ128rrk:
19721	case VMAXPDZ128rrkz:
19722	case VMAXPDZ256rm:
19723	case VMAXPDZ256rmb:
19724	case VMAXPDZ256rmbk:
19725	case VMAXPDZ256rmbkz:
19726	case VMAXPDZ256rmk:
19727	case VMAXPDZ256rmkz:
19728	case VMAXPDZ256rr:
19729	case VMAXPDZ256rrk:
19730	case VMAXPDZ256rrkz:
19731	case VMAXPDZrm:
19732	case VMAXPDZrmb:
19733	case VMAXPDZrmbk:
19734	case VMAXPDZrmbkz:
19735	case VMAXPDZrmk:
19736	case VMAXPDZrmkz:
19737	case VMAXPDZrr:
19738	case VMAXPDZrrb:
19739	case VMAXPDZrrbk:
19740	case VMAXPDZrrbkz:
19741	case VMAXPDZrrk:
19742	case VMAXPDZrrkz:
19743	case VMAXPDrm:
19744	case VMAXPDrr:
19745		return true;
19746	}
19747	return false;
19748}
19749
19750bool isVMAXPH(unsigned Opcode) {
19751	switch (Opcode) {
19752	case VMAXPHZ128rm:
19753	case VMAXPHZ128rmb:
19754	case VMAXPHZ128rmbk:
19755	case VMAXPHZ128rmbkz:
19756	case VMAXPHZ128rmk:
19757	case VMAXPHZ128rmkz:
19758	case VMAXPHZ128rr:
19759	case VMAXPHZ128rrk:
19760	case VMAXPHZ128rrkz:
19761	case VMAXPHZ256rm:
19762	case VMAXPHZ256rmb:
19763	case VMAXPHZ256rmbk:
19764	case VMAXPHZ256rmbkz:
19765	case VMAXPHZ256rmk:
19766	case VMAXPHZ256rmkz:
19767	case VMAXPHZ256rr:
19768	case VMAXPHZ256rrk:
19769	case VMAXPHZ256rrkz:
19770	case VMAXPHZrm:
19771	case VMAXPHZrmb:
19772	case VMAXPHZrmbk:
19773	case VMAXPHZrmbkz:
19774	case VMAXPHZrmk:
19775	case VMAXPHZrmkz:
19776	case VMAXPHZrr:
19777	case VMAXPHZrrb:
19778	case VMAXPHZrrbk:
19779	case VMAXPHZrrbkz:
19780	case VMAXPHZrrk:
19781	case VMAXPHZrrkz:
19782		return true;
19783	}
19784	return false;
19785}
19786
19787bool isPUNPCKLBW(unsigned Opcode) {
19788	switch (Opcode) {
19789	case MMX_PUNPCKLBWrm:
19790	case MMX_PUNPCKLBWrr:
19791	case PUNPCKLBWrm:
19792	case PUNPCKLBWrr:
19793		return true;
19794	}
19795	return false;
19796}
19797
19798bool isIMUL(unsigned Opcode) {
19799	switch (Opcode) {
19800	case IMUL16m:
19801	case IMUL16r:
19802	case IMUL16rm:
19803	case IMUL16rmi:
19804	case IMUL16rmi8:
19805	case IMUL16rr:
19806	case IMUL16rri:
19807	case IMUL16rri8:
19808	case IMUL32m:
19809	case IMUL32r:
19810	case IMUL32rm:
19811	case IMUL32rmi:
19812	case IMUL32rmi8:
19813	case IMUL32rr:
19814	case IMUL32rri:
19815	case IMUL32rri8:
19816	case IMUL64m:
19817	case IMUL64r:
19818	case IMUL64rm:
19819	case IMUL64rmi32:
19820	case IMUL64rmi8:
19821	case IMUL64rr:
19822	case IMUL64rri32:
19823	case IMUL64rri8:
19824	case IMUL8m:
19825	case IMUL8r:
19826		return true;
19827	}
19828	return false;
19829}
19830
19831bool isTILELOADDT1(unsigned Opcode) {
19832	return Opcode == TILELOADDT1;
19833}
19834
19835bool isVFNMADD231PS(unsigned Opcode) {
19836	switch (Opcode) {
19837	case VFNMADD231PSYm:
19838	case VFNMADD231PSYr:
19839	case VFNMADD231PSZ128m:
19840	case VFNMADD231PSZ128mb:
19841	case VFNMADD231PSZ128mbk:
19842	case VFNMADD231PSZ128mbkz:
19843	case VFNMADD231PSZ128mk:
19844	case VFNMADD231PSZ128mkz:
19845	case VFNMADD231PSZ128r:
19846	case VFNMADD231PSZ128rk:
19847	case VFNMADD231PSZ128rkz:
19848	case VFNMADD231PSZ256m:
19849	case VFNMADD231PSZ256mb:
19850	case VFNMADD231PSZ256mbk:
19851	case VFNMADD231PSZ256mbkz:
19852	case VFNMADD231PSZ256mk:
19853	case VFNMADD231PSZ256mkz:
19854	case VFNMADD231PSZ256r:
19855	case VFNMADD231PSZ256rk:
19856	case VFNMADD231PSZ256rkz:
19857	case VFNMADD231PSZm:
19858	case VFNMADD231PSZmb:
19859	case VFNMADD231PSZmbk:
19860	case VFNMADD231PSZmbkz:
19861	case VFNMADD231PSZmk:
19862	case VFNMADD231PSZmkz:
19863	case VFNMADD231PSZr:
19864	case VFNMADD231PSZrb:
19865	case VFNMADD231PSZrbk:
19866	case VFNMADD231PSZrbkz:
19867	case VFNMADD231PSZrk:
19868	case VFNMADD231PSZrkz:
19869	case VFNMADD231PSm:
19870	case VFNMADD231PSr:
19871		return true;
19872	}
19873	return false;
19874}
19875
19876bool isVMAXPS(unsigned Opcode) {
19877	switch (Opcode) {
19878	case VMAXPSYrm:
19879	case VMAXPSYrr:
19880	case VMAXPSZ128rm:
19881	case VMAXPSZ128rmb:
19882	case VMAXPSZ128rmbk:
19883	case VMAXPSZ128rmbkz:
19884	case VMAXPSZ128rmk:
19885	case VMAXPSZ128rmkz:
19886	case VMAXPSZ128rr:
19887	case VMAXPSZ128rrk:
19888	case VMAXPSZ128rrkz:
19889	case VMAXPSZ256rm:
19890	case VMAXPSZ256rmb:
19891	case VMAXPSZ256rmbk:
19892	case VMAXPSZ256rmbkz:
19893	case VMAXPSZ256rmk:
19894	case VMAXPSZ256rmkz:
19895	case VMAXPSZ256rr:
19896	case VMAXPSZ256rrk:
19897	case VMAXPSZ256rrkz:
19898	case VMAXPSZrm:
19899	case VMAXPSZrmb:
19900	case VMAXPSZrmbk:
19901	case VMAXPSZrmbkz:
19902	case VMAXPSZrmk:
19903	case VMAXPSZrmkz:
19904	case VMAXPSZrr:
19905	case VMAXPSZrrb:
19906	case VMAXPSZrrbk:
19907	case VMAXPSZrrbkz:
19908	case VMAXPSZrrk:
19909	case VMAXPSZrrkz:
19910	case VMAXPSrm:
19911	case VMAXPSrr:
19912		return true;
19913	}
19914	return false;
19915}
19916
19917bool isVPXOR(unsigned Opcode) {
19918	switch (Opcode) {
19919	case VPXORYrm:
19920	case VPXORYrr:
19921	case VPXORrm:
19922	case VPXORrr:
19923		return true;
19924	}
19925	return false;
19926}
19927
19928bool isOR(unsigned Opcode) {
19929	switch (Opcode) {
19930	case OR16i16:
19931	case OR16mi:
19932	case OR16mi8:
19933	case OR16mr:
19934	case OR16ri:
19935	case OR16ri8:
19936	case OR16rm:
19937	case OR16rr:
19938	case OR16rr_REV:
19939	case OR32i32:
19940	case OR32mi:
19941	case OR32mi8:
19942	case OR32mr:
19943	case OR32ri:
19944	case OR32ri8:
19945	case OR32rm:
19946	case OR32rr:
19947	case OR32rr_REV:
19948	case OR64i32:
19949	case OR64mi32:
19950	case OR64mi8:
19951	case OR64mr:
19952	case OR64ri32:
19953	case OR64ri8:
19954	case OR64rm:
19955	case OR64rr:
19956	case OR64rr_REV:
19957	case OR8i8:
19958	case OR8mi:
19959	case OR8mi8:
19960	case OR8mr:
19961	case OR8ri:
19962	case OR8ri8:
19963	case OR8rm:
19964	case OR8rr:
19965	case OR8rr_REV:
19966		return true;
19967	}
19968	return false;
19969}
19970
19971bool isMOVZX(unsigned Opcode) {
19972	switch (Opcode) {
19973	case MOVZX16rm16:
19974	case MOVZX16rm8:
19975	case MOVZX16rr16:
19976	case MOVZX16rr8:
19977	case MOVZX32rm16:
19978	case MOVZX32rm8:
19979	case MOVZX32rr16:
19980	case MOVZX32rr8:
19981	case MOVZX64rm16:
19982	case MOVZX64rm8:
19983	case MOVZX64rr16:
19984	case MOVZX64rr8:
19985		return true;
19986	}
19987	return false;
19988}
19989
19990bool isXSAVES64(unsigned Opcode) {
19991	return Opcode == XSAVES64;
19992}
19993
19994bool isVPUNPCKHBW(unsigned Opcode) {
19995	switch (Opcode) {
19996	case VPUNPCKHBWYrm:
19997	case VPUNPCKHBWYrr:
19998	case VPUNPCKHBWZ128rm:
19999	case VPUNPCKHBWZ128rmk:
20000	case VPUNPCKHBWZ128rmkz:
20001	case VPUNPCKHBWZ128rr:
20002	case VPUNPCKHBWZ128rrk:
20003	case VPUNPCKHBWZ128rrkz:
20004	case VPUNPCKHBWZ256rm:
20005	case VPUNPCKHBWZ256rmk:
20006	case VPUNPCKHBWZ256rmkz:
20007	case VPUNPCKHBWZ256rr:
20008	case VPUNPCKHBWZ256rrk:
20009	case VPUNPCKHBWZ256rrkz:
20010	case VPUNPCKHBWZrm:
20011	case VPUNPCKHBWZrmk:
20012	case VPUNPCKHBWZrmkz:
20013	case VPUNPCKHBWZrr:
20014	case VPUNPCKHBWZrrk:
20015	case VPUNPCKHBWZrrkz:
20016	case VPUNPCKHBWrm:
20017	case VPUNPCKHBWrr:
20018		return true;
20019	}
20020	return false;
20021}
20022
20023bool isSYSRET(unsigned Opcode) {
20024	return Opcode == SYSRET;
20025}
20026
20027bool isVFMSUBSD(unsigned Opcode) {
20028	switch (Opcode) {
20029	case VFMSUBSD4mr:
20030	case VFMSUBSD4rm:
20031	case VFMSUBSD4rr:
20032	case VFMSUBSD4rr_REV:
20033		return true;
20034	}
20035	return false;
20036}
20037
20038bool isVFNMADD213SD(unsigned Opcode) {
20039	switch (Opcode) {
20040	case VFNMADD213SDZm_Int:
20041	case VFNMADD213SDZm_Intk:
20042	case VFNMADD213SDZm_Intkz:
20043	case VFNMADD213SDZr_Int:
20044	case VFNMADD213SDZr_Intk:
20045	case VFNMADD213SDZr_Intkz:
20046	case VFNMADD213SDZrb_Int:
20047	case VFNMADD213SDZrb_Intk:
20048	case VFNMADD213SDZrb_Intkz:
20049	case VFNMADD213SDm_Int:
20050	case VFNMADD213SDr_Int:
20051		return true;
20052	}
20053	return false;
20054}
20055
20056bool isVFNMADD213SH(unsigned Opcode) {
20057	switch (Opcode) {
20058	case VFNMADD213SHZm_Int:
20059	case VFNMADD213SHZm_Intk:
20060	case VFNMADD213SHZm_Intkz:
20061	case VFNMADD213SHZr_Int:
20062	case VFNMADD213SHZr_Intk:
20063	case VFNMADD213SHZr_Intkz:
20064	case VFNMADD213SHZrb_Int:
20065	case VFNMADD213SHZrb_Intk:
20066	case VFNMADD213SHZrb_Intkz:
20067		return true;
20068	}
20069	return false;
20070}
20071
20072bool isSGDT(unsigned Opcode) {
20073	return Opcode == SGDT64m;
20074}
20075
20076bool isVRCP14SD(unsigned Opcode) {
20077	switch (Opcode) {
20078	case VRCP14SDZrm:
20079	case VRCP14SDZrmk:
20080	case VRCP14SDZrmkz:
20081	case VRCP14SDZrr:
20082	case VRCP14SDZrrk:
20083	case VRCP14SDZrrkz:
20084		return true;
20085	}
20086	return false;
20087}
20088
20089bool isVPMOVSXDQ(unsigned Opcode) {
20090	switch (Opcode) {
20091	case VPMOVSXDQYrm:
20092	case VPMOVSXDQYrr:
20093	case VPMOVSXDQZ128rm:
20094	case VPMOVSXDQZ128rmk:
20095	case VPMOVSXDQZ128rmkz:
20096	case VPMOVSXDQZ128rr:
20097	case VPMOVSXDQZ128rrk:
20098	case VPMOVSXDQZ128rrkz:
20099	case VPMOVSXDQZ256rm:
20100	case VPMOVSXDQZ256rmk:
20101	case VPMOVSXDQZ256rmkz:
20102	case VPMOVSXDQZ256rr:
20103	case VPMOVSXDQZ256rrk:
20104	case VPMOVSXDQZ256rrkz:
20105	case VPMOVSXDQZrm:
20106	case VPMOVSXDQZrmk:
20107	case VPMOVSXDQZrmkz:
20108	case VPMOVSXDQZrr:
20109	case VPMOVSXDQZrrk:
20110	case VPMOVSXDQZrrkz:
20111	case VPMOVSXDQrm:
20112	case VPMOVSXDQrr:
20113		return true;
20114	}
20115	return false;
20116}
20117
20118bool isSYSEXIT(unsigned Opcode) {
20119	return Opcode == SYSEXIT;
20120}
20121
20122bool isPMOVZXBD(unsigned Opcode) {
20123	switch (Opcode) {
20124	case PMOVZXBDrm:
20125	case PMOVZXBDrr:
20126		return true;
20127	}
20128	return false;
20129}
20130
20131bool isVFNMADD213SS(unsigned Opcode) {
20132	switch (Opcode) {
20133	case VFNMADD213SSZm_Int:
20134	case VFNMADD213SSZm_Intk:
20135	case VFNMADD213SSZm_Intkz:
20136	case VFNMADD213SSZr_Int:
20137	case VFNMADD213SSZr_Intk:
20138	case VFNMADD213SSZr_Intkz:
20139	case VFNMADD213SSZrb_Int:
20140	case VFNMADD213SSZrb_Intk:
20141	case VFNMADD213SSZrb_Intkz:
20142	case VFNMADD213SSm_Int:
20143	case VFNMADD213SSr_Int:
20144		return true;
20145	}
20146	return false;
20147}
20148
20149bool isVPMADCSSWD(unsigned Opcode) {
20150	switch (Opcode) {
20151	case VPMADCSSWDrm:
20152	case VPMADCSSWDrr:
20153		return true;
20154	}
20155	return false;
20156}
20157
20158bool isVPMULUDQ(unsigned Opcode) {
20159	switch (Opcode) {
20160	case VPMULUDQYrm:
20161	case VPMULUDQYrr:
20162	case VPMULUDQZ128rm:
20163	case VPMULUDQZ128rmb:
20164	case VPMULUDQZ128rmbk:
20165	case VPMULUDQZ128rmbkz:
20166	case VPMULUDQZ128rmk:
20167	case VPMULUDQZ128rmkz:
20168	case VPMULUDQZ128rr:
20169	case VPMULUDQZ128rrk:
20170	case VPMULUDQZ128rrkz:
20171	case VPMULUDQZ256rm:
20172	case VPMULUDQZ256rmb:
20173	case VPMULUDQZ256rmbk:
20174	case VPMULUDQZ256rmbkz:
20175	case VPMULUDQZ256rmk:
20176	case VPMULUDQZ256rmkz:
20177	case VPMULUDQZ256rr:
20178	case VPMULUDQZ256rrk:
20179	case VPMULUDQZ256rrkz:
20180	case VPMULUDQZrm:
20181	case VPMULUDQZrmb:
20182	case VPMULUDQZrmbk:
20183	case VPMULUDQZrmbkz:
20184	case VPMULUDQZrmk:
20185	case VPMULUDQZrmkz:
20186	case VPMULUDQZrr:
20187	case VPMULUDQZrrk:
20188	case VPMULUDQZrrkz:
20189	case VPMULUDQrm:
20190	case VPMULUDQrr:
20191		return true;
20192	}
20193	return false;
20194}
20195
20196bool isVFMSUBSS(unsigned Opcode) {
20197	switch (Opcode) {
20198	case VFMSUBSS4mr:
20199	case VFMSUBSS4rm:
20200	case VFMSUBSS4rr:
20201	case VFMSUBSS4rr_REV:
20202		return true;
20203	}
20204	return false;
20205}
20206
20207bool isVPXORD(unsigned Opcode) {
20208	switch (Opcode) {
20209	case VPXORDZ128rm:
20210	case VPXORDZ128rmb:
20211	case VPXORDZ128rmbk:
20212	case VPXORDZ128rmbkz:
20213	case VPXORDZ128rmk:
20214	case VPXORDZ128rmkz:
20215	case VPXORDZ128rr:
20216	case VPXORDZ128rrk:
20217	case VPXORDZ128rrkz:
20218	case VPXORDZ256rm:
20219	case VPXORDZ256rmb:
20220	case VPXORDZ256rmbk:
20221	case VPXORDZ256rmbkz:
20222	case VPXORDZ256rmk:
20223	case VPXORDZ256rmkz:
20224	case VPXORDZ256rr:
20225	case VPXORDZ256rrk:
20226	case VPXORDZ256rrkz:
20227	case VPXORDZrm:
20228	case VPXORDZrmb:
20229	case VPXORDZrmbk:
20230	case VPXORDZrmbkz:
20231	case VPXORDZrmk:
20232	case VPXORDZrmkz:
20233	case VPXORDZrr:
20234	case VPXORDZrrk:
20235	case VPXORDZrrkz:
20236		return true;
20237	}
20238	return false;
20239}
20240
20241bool isXSAVEOPT64(unsigned Opcode) {
20242	return Opcode == XSAVEOPT64;
20243}
20244
20245bool isXSHA1(unsigned Opcode) {
20246	return Opcode == XSHA1;
20247}
20248
20249bool isVRCP14SS(unsigned Opcode) {
20250	switch (Opcode) {
20251	case VRCP14SSZrm:
20252	case VRCP14SSZrmk:
20253	case VRCP14SSZrmkz:
20254	case VRCP14SSZrr:
20255	case VRCP14SSZrrk:
20256	case VRCP14SSZrrkz:
20257		return true;
20258	}
20259	return false;
20260}
20261
20262bool isPMOVZXBQ(unsigned Opcode) {
20263	switch (Opcode) {
20264	case PMOVZXBQrm:
20265	case PMOVZXBQrr:
20266		return true;
20267	}
20268	return false;
20269}
20270
20271bool isSHL(unsigned Opcode) {
20272	switch (Opcode) {
20273	case SHL16m1:
20274	case SHL16mCL:
20275	case SHL16mi:
20276	case SHL16r1:
20277	case SHL16rCL:
20278	case SHL16ri:
20279	case SHL32m1:
20280	case SHL32mCL:
20281	case SHL32mi:
20282	case SHL32r1:
20283	case SHL32rCL:
20284	case SHL32ri:
20285	case SHL64m1:
20286	case SHL64mCL:
20287	case SHL64mi:
20288	case SHL64r1:
20289	case SHL64rCL:
20290	case SHL64ri:
20291	case SHL8m1:
20292	case SHL8mCL:
20293	case SHL8mi:
20294	case SHL8r1:
20295	case SHL8rCL:
20296	case SHL8ri:
20297		return true;
20298	}
20299	return false;
20300}
20301
20302bool isPMOVZXBW(unsigned Opcode) {
20303	switch (Opcode) {
20304	case PMOVZXBWrm:
20305	case PMOVZXBWrr:
20306		return true;
20307	}
20308	return false;
20309}
20310
20311bool isPMULLD(unsigned Opcode) {
20312	switch (Opcode) {
20313	case PMULLDrm:
20314	case PMULLDrr:
20315		return true;
20316	}
20317	return false;
20318}
20319
20320bool isVCVTPS2UQQ(unsigned Opcode) {
20321	switch (Opcode) {
20322	case VCVTPS2UQQZ128rm:
20323	case VCVTPS2UQQZ128rmb:
20324	case VCVTPS2UQQZ128rmbk:
20325	case VCVTPS2UQQZ128rmbkz:
20326	case VCVTPS2UQQZ128rmk:
20327	case VCVTPS2UQQZ128rmkz:
20328	case VCVTPS2UQQZ128rr:
20329	case VCVTPS2UQQZ128rrk:
20330	case VCVTPS2UQQZ128rrkz:
20331	case VCVTPS2UQQZ256rm:
20332	case VCVTPS2UQQZ256rmb:
20333	case VCVTPS2UQQZ256rmbk:
20334	case VCVTPS2UQQZ256rmbkz:
20335	case VCVTPS2UQQZ256rmk:
20336	case VCVTPS2UQQZ256rmkz:
20337	case VCVTPS2UQQZ256rr:
20338	case VCVTPS2UQQZ256rrk:
20339	case VCVTPS2UQQZ256rrkz:
20340	case VCVTPS2UQQZrm:
20341	case VCVTPS2UQQZrmb:
20342	case VCVTPS2UQQZrmbk:
20343	case VCVTPS2UQQZrmbkz:
20344	case VCVTPS2UQQZrmk:
20345	case VCVTPS2UQQZrmkz:
20346	case VCVTPS2UQQZrr:
20347	case VCVTPS2UQQZrrb:
20348	case VCVTPS2UQQZrrbk:
20349	case VCVTPS2UQQZrrbkz:
20350	case VCVTPS2UQQZrrk:
20351	case VCVTPS2UQQZrrkz:
20352		return true;
20353	}
20354	return false;
20355}
20356
20357bool isVPBLENDD(unsigned Opcode) {
20358	switch (Opcode) {
20359	case VPBLENDDYrmi:
20360	case VPBLENDDYrri:
20361	case VPBLENDDrmi:
20362	case VPBLENDDrri:
20363		return true;
20364	}
20365	return false;
20366}
20367
20368bool isVPXORQ(unsigned Opcode) {
20369	switch (Opcode) {
20370	case VPXORQZ128rm:
20371	case VPXORQZ128rmb:
20372	case VPXORQZ128rmbk:
20373	case VPXORQZ128rmbkz:
20374	case VPXORQZ128rmk:
20375	case VPXORQZ128rmkz:
20376	case VPXORQZ128rr:
20377	case VPXORQZ128rrk:
20378	case VPXORQZ128rrkz:
20379	case VPXORQZ256rm:
20380	case VPXORQZ256rmb:
20381	case VPXORQZ256rmbk:
20382	case VPXORQZ256rmbkz:
20383	case VPXORQZ256rmk:
20384	case VPXORQZ256rmkz:
20385	case VPXORQZ256rr:
20386	case VPXORQZ256rrk:
20387	case VPXORQZ256rrkz:
20388	case VPXORQZrm:
20389	case VPXORQZrmb:
20390	case VPXORQZrmbk:
20391	case VPXORQZrmbkz:
20392	case VPXORQZrmk:
20393	case VPXORQZrmkz:
20394	case VPXORQZrr:
20395	case VPXORQZrrk:
20396	case VPXORQZrrkz:
20397		return true;
20398	}
20399	return false;
20400}
20401
20402bool isPUNPCKLDQ(unsigned Opcode) {
20403	switch (Opcode) {
20404	case MMX_PUNPCKLDQrm:
20405	case MMX_PUNPCKLDQrr:
20406	case PUNPCKLDQrm:
20407	case PUNPCKLDQrr:
20408		return true;
20409	}
20410	return false;
20411}
20412
20413bool isSHR(unsigned Opcode) {
20414	switch (Opcode) {
20415	case SHR16m1:
20416	case SHR16mCL:
20417	case SHR16mi:
20418	case SHR16r1:
20419	case SHR16rCL:
20420	case SHR16ri:
20421	case SHR32m1:
20422	case SHR32mCL:
20423	case SHR32mi:
20424	case SHR32r1:
20425	case SHR32rCL:
20426	case SHR32ri:
20427	case SHR64m1:
20428	case SHR64mCL:
20429	case SHR64mi:
20430	case SHR64r1:
20431	case SHR64rCL:
20432	case SHR64ri:
20433	case SHR8m1:
20434	case SHR8mCL:
20435	case SHR8mi:
20436	case SHR8r1:
20437	case SHR8rCL:
20438	case SHR8ri:
20439		return true;
20440	}
20441	return false;
20442}
20443
20444bool isVPUNPCKLQDQ(unsigned Opcode) {
20445	switch (Opcode) {
20446	case VPUNPCKLQDQYrm:
20447	case VPUNPCKLQDQYrr:
20448	case VPUNPCKLQDQZ128rm:
20449	case VPUNPCKLQDQZ128rmb:
20450	case VPUNPCKLQDQZ128rmbk:
20451	case VPUNPCKLQDQZ128rmbkz:
20452	case VPUNPCKLQDQZ128rmk:
20453	case VPUNPCKLQDQZ128rmkz:
20454	case VPUNPCKLQDQZ128rr:
20455	case VPUNPCKLQDQZ128rrk:
20456	case VPUNPCKLQDQZ128rrkz:
20457	case VPUNPCKLQDQZ256rm:
20458	case VPUNPCKLQDQZ256rmb:
20459	case VPUNPCKLQDQZ256rmbk:
20460	case VPUNPCKLQDQZ256rmbkz:
20461	case VPUNPCKLQDQZ256rmk:
20462	case VPUNPCKLQDQZ256rmkz:
20463	case VPUNPCKLQDQZ256rr:
20464	case VPUNPCKLQDQZ256rrk:
20465	case VPUNPCKLQDQZ256rrkz:
20466	case VPUNPCKLQDQZrm:
20467	case VPUNPCKLQDQZrmb:
20468	case VPUNPCKLQDQZrmbk:
20469	case VPUNPCKLQDQZrmbkz:
20470	case VPUNPCKLQDQZrmk:
20471	case VPUNPCKLQDQZrmkz:
20472	case VPUNPCKLQDQZrr:
20473	case VPUNPCKLQDQZrrk:
20474	case VPUNPCKLQDQZrrkz:
20475	case VPUNPCKLQDQrm:
20476	case VPUNPCKLQDQrr:
20477		return true;
20478	}
20479	return false;
20480}
20481
20482bool isVCVTPD2DQ(unsigned Opcode) {
20483	switch (Opcode) {
20484	case VCVTPD2DQYrm:
20485	case VCVTPD2DQYrr:
20486	case VCVTPD2DQZ128rm:
20487	case VCVTPD2DQZ128rmb:
20488	case VCVTPD2DQZ128rmbk:
20489	case VCVTPD2DQZ128rmbkz:
20490	case VCVTPD2DQZ128rmk:
20491	case VCVTPD2DQZ128rmkz:
20492	case VCVTPD2DQZ128rr:
20493	case VCVTPD2DQZ128rrk:
20494	case VCVTPD2DQZ128rrkz:
20495	case VCVTPD2DQZ256rm:
20496	case VCVTPD2DQZ256rmb:
20497	case VCVTPD2DQZ256rmbk:
20498	case VCVTPD2DQZ256rmbkz:
20499	case VCVTPD2DQZ256rmk:
20500	case VCVTPD2DQZ256rmkz:
20501	case VCVTPD2DQZ256rr:
20502	case VCVTPD2DQZ256rrk:
20503	case VCVTPD2DQZ256rrkz:
20504	case VCVTPD2DQZrm:
20505	case VCVTPD2DQZrmb:
20506	case VCVTPD2DQZrmbk:
20507	case VCVTPD2DQZrmbkz:
20508	case VCVTPD2DQZrmk:
20509	case VCVTPD2DQZrmkz:
20510	case VCVTPD2DQZrr:
20511	case VCVTPD2DQZrrb:
20512	case VCVTPD2DQZrrbk:
20513	case VCVTPD2DQZrrbkz:
20514	case VCVTPD2DQZrrk:
20515	case VCVTPD2DQZrrkz:
20516	case VCVTPD2DQrm:
20517	case VCVTPD2DQrr:
20518		return true;
20519	}
20520	return false;
20521}
20522
20523bool isPMULLW(unsigned Opcode) {
20524	switch (Opcode) {
20525	case MMX_PMULLWrm:
20526	case MMX_PMULLWrr:
20527	case PMULLWrm:
20528	case PMULLWrr:
20529		return true;
20530	}
20531	return false;
20532}
20533
20534bool isVPBLENDW(unsigned Opcode) {
20535	switch (Opcode) {
20536	case VPBLENDWYrmi:
20537	case VPBLENDWYrri:
20538	case VPBLENDWrmi:
20539	case VPBLENDWrri:
20540		return true;
20541	}
20542	return false;
20543}
20544
20545bool isAESENCLAST(unsigned Opcode) {
20546	switch (Opcode) {
20547	case AESENCLASTrm:
20548	case AESENCLASTrr:
20549		return true;
20550	}
20551	return false;
20552}
20553
20554bool isVPUNPCKHDQ(unsigned Opcode) {
20555	switch (Opcode) {
20556	case VPUNPCKHDQYrm:
20557	case VPUNPCKHDQYrr:
20558	case VPUNPCKHDQZ128rm:
20559	case VPUNPCKHDQZ128rmb:
20560	case VPUNPCKHDQZ128rmbk:
20561	case VPUNPCKHDQZ128rmbkz:
20562	case VPUNPCKHDQZ128rmk:
20563	case VPUNPCKHDQZ128rmkz:
20564	case VPUNPCKHDQZ128rr:
20565	case VPUNPCKHDQZ128rrk:
20566	case VPUNPCKHDQZ128rrkz:
20567	case VPUNPCKHDQZ256rm:
20568	case VPUNPCKHDQZ256rmb:
20569	case VPUNPCKHDQZ256rmbk:
20570	case VPUNPCKHDQZ256rmbkz:
20571	case VPUNPCKHDQZ256rmk:
20572	case VPUNPCKHDQZ256rmkz:
20573	case VPUNPCKHDQZ256rr:
20574	case VPUNPCKHDQZ256rrk:
20575	case VPUNPCKHDQZ256rrkz:
20576	case VPUNPCKHDQZrm:
20577	case VPUNPCKHDQZrmb:
20578	case VPUNPCKHDQZrmbk:
20579	case VPUNPCKHDQZrmbkz:
20580	case VPUNPCKHDQZrmk:
20581	case VPUNPCKHDQZrmkz:
20582	case VPUNPCKHDQZrr:
20583	case VPUNPCKHDQZrrk:
20584	case VPUNPCKHDQZrrkz:
20585	case VPUNPCKHDQrm:
20586	case VPUNPCKHDQrr:
20587		return true;
20588	}
20589	return false;
20590}
20591
20592bool isVFNMADD231SD(unsigned Opcode) {
20593	switch (Opcode) {
20594	case VFNMADD231SDZm_Int:
20595	case VFNMADD231SDZm_Intk:
20596	case VFNMADD231SDZm_Intkz:
20597	case VFNMADD231SDZr_Int:
20598	case VFNMADD231SDZr_Intk:
20599	case VFNMADD231SDZr_Intkz:
20600	case VFNMADD231SDZrb_Int:
20601	case VFNMADD231SDZrb_Intk:
20602	case VFNMADD231SDZrb_Intkz:
20603	case VFNMADD231SDm_Int:
20604	case VFNMADD231SDr_Int:
20605		return true;
20606	}
20607	return false;
20608}
20609
20610bool isVFNMADD231SH(unsigned Opcode) {
20611	switch (Opcode) {
20612	case VFNMADD231SHZm_Int:
20613	case VFNMADD231SHZm_Intk:
20614	case VFNMADD231SHZm_Intkz:
20615	case VFNMADD231SHZr_Int:
20616	case VFNMADD231SHZr_Intk:
20617	case VFNMADD231SHZr_Intkz:
20618	case VFNMADD231SHZrb_Int:
20619	case VFNMADD231SHZrb_Intk:
20620	case VFNMADD231SHZrb_Intkz:
20621		return true;
20622	}
20623	return false;
20624}
20625
20626bool isVPMOVSDB(unsigned Opcode) {
20627	switch (Opcode) {
20628	case VPMOVSDBZ128mr:
20629	case VPMOVSDBZ128mrk:
20630	case VPMOVSDBZ128rr:
20631	case VPMOVSDBZ128rrk:
20632	case VPMOVSDBZ128rrkz:
20633	case VPMOVSDBZ256mr:
20634	case VPMOVSDBZ256mrk:
20635	case VPMOVSDBZ256rr:
20636	case VPMOVSDBZ256rrk:
20637	case VPMOVSDBZ256rrkz:
20638	case VPMOVSDBZmr:
20639	case VPMOVSDBZmrk:
20640	case VPMOVSDBZrr:
20641	case VPMOVSDBZrrk:
20642	case VPMOVSDBZrrkz:
20643		return true;
20644	}
20645	return false;
20646}
20647
20648bool isVMAXSD(unsigned Opcode) {
20649	switch (Opcode) {
20650	case VMAXSDZrm_Int:
20651	case VMAXSDZrm_Intk:
20652	case VMAXSDZrm_Intkz:
20653	case VMAXSDZrr_Int:
20654	case VMAXSDZrr_Intk:
20655	case VMAXSDZrr_Intkz:
20656	case VMAXSDZrrb_Int:
20657	case VMAXSDZrrb_Intk:
20658	case VMAXSDZrrb_Intkz:
20659	case VMAXSDrm_Int:
20660	case VMAXSDrr_Int:
20661		return true;
20662	}
20663	return false;
20664}
20665
20666bool isVMAXSH(unsigned Opcode) {
20667	switch (Opcode) {
20668	case VMAXSHZrm_Int:
20669	case VMAXSHZrm_Intk:
20670	case VMAXSHZrm_Intkz:
20671	case VMAXSHZrr_Int:
20672	case VMAXSHZrr_Intk:
20673	case VMAXSHZrr_Intkz:
20674	case VMAXSHZrrb_Int:
20675	case VMAXSHZrrb_Intk:
20676	case VMAXSHZrrb_Intkz:
20677		return true;
20678	}
20679	return false;
20680}
20681
20682bool isLAHF(unsigned Opcode) {
20683	return Opcode == LAHF;
20684}
20685
20686bool isCVTTPD2DQ(unsigned Opcode) {
20687	switch (Opcode) {
20688	case CVTTPD2DQrm:
20689	case CVTTPD2DQrr:
20690		return true;
20691	}
20692	return false;
20693}
20694
20695bool isUNPCKHPD(unsigned Opcode) {
20696	switch (Opcode) {
20697	case UNPCKHPDrm:
20698	case UNPCKHPDrr:
20699		return true;
20700	}
20701	return false;
20702}
20703
20704bool isVFNMADD231SS(unsigned Opcode) {
20705	switch (Opcode) {
20706	case VFNMADD231SSZm_Int:
20707	case VFNMADD231SSZm_Intk:
20708	case VFNMADD231SSZm_Intkz:
20709	case VFNMADD231SSZr_Int:
20710	case VFNMADD231SSZr_Intk:
20711	case VFNMADD231SSZr_Intkz:
20712	case VFNMADD231SSZrb_Int:
20713	case VFNMADD231SSZrb_Intk:
20714	case VFNMADD231SSZrb_Intkz:
20715	case VFNMADD231SSm_Int:
20716	case VFNMADD231SSr_Int:
20717		return true;
20718	}
20719	return false;
20720}
20721
20722bool isVMAXSS(unsigned Opcode) {
20723	switch (Opcode) {
20724	case VMAXSSZrm_Int:
20725	case VMAXSSZrm_Intk:
20726	case VMAXSSZrm_Intkz:
20727	case VMAXSSZrr_Int:
20728	case VMAXSSZrr_Intk:
20729	case VMAXSSZrr_Intkz:
20730	case VMAXSSZrrb_Int:
20731	case VMAXSSZrrb_Intk:
20732	case VMAXSSZrrb_Intkz:
20733	case VMAXSSrm_Int:
20734	case VMAXSSrr_Int:
20735		return true;
20736	}
20737	return false;
20738}
20739
20740bool isVPMACSSDD(unsigned Opcode) {
20741	switch (Opcode) {
20742	case VPMACSSDDrm:
20743	case VPMACSSDDrr:
20744		return true;
20745	}
20746	return false;
20747}
20748
20749bool isVPMOVSDW(unsigned Opcode) {
20750	switch (Opcode) {
20751	case VPMOVSDWZ128mr:
20752	case VPMOVSDWZ128mrk:
20753	case VPMOVSDWZ128rr:
20754	case VPMOVSDWZ128rrk:
20755	case VPMOVSDWZ128rrkz:
20756	case VPMOVSDWZ256mr:
20757	case VPMOVSDWZ256mrk:
20758	case VPMOVSDWZ256rr:
20759	case VPMOVSDWZ256rrk:
20760	case VPMOVSDWZ256rrkz:
20761	case VPMOVSDWZmr:
20762	case VPMOVSDWZmrk:
20763	case VPMOVSDWZrr:
20764	case VPMOVSDWZrrk:
20765	case VPMOVSDWZrrkz:
20766		return true;
20767	}
20768	return false;
20769}
20770
20771bool isPMOVZXDQ(unsigned Opcode) {
20772	switch (Opcode) {
20773	case PMOVZXDQrm:
20774	case PMOVZXDQrr:
20775		return true;
20776	}
20777	return false;
20778}
20779
20780bool isUNPCKHPS(unsigned Opcode) {
20781	switch (Opcode) {
20782	case UNPCKHPSrm:
20783	case UNPCKHPSrr:
20784		return true;
20785	}
20786	return false;
20787}
20788
20789bool isFCOMI(unsigned Opcode) {
20790	return Opcode == COM_FIr;
20791}
20792
20793bool isCLFLUSH(unsigned Opcode) {
20794	return Opcode == CLFLUSH;
20795}
20796
20797bool isTILELOADD(unsigned Opcode) {
20798	return Opcode == TILELOADD;
20799}
20800
20801bool isFCOMP(unsigned Opcode) {
20802	switch (Opcode) {
20803	case COMP_FST0r:
20804	case FCOMP32m:
20805	case FCOMP64m:
20806		return true;
20807	}
20808	return false;
20809}
20810
20811bool isDIV(unsigned Opcode) {
20812	switch (Opcode) {
20813	case DIV16m:
20814	case DIV16r:
20815	case DIV32m:
20816	case DIV32r:
20817	case DIV64m:
20818	case DIV64r:
20819	case DIV8m:
20820	case DIV8r:
20821		return true;
20822	}
20823	return false;
20824}
20825
20826bool isVPMACSWD(unsigned Opcode) {
20827	switch (Opcode) {
20828	case VPMACSWDrm:
20829	case VPMACSWDrr:
20830		return true;
20831	}
20832	return false;
20833}
20834
20835bool isFPREM1(unsigned Opcode) {
20836	return Opcode == FPREM1;
20837}
20838
20839bool isVSCATTERQPD(unsigned Opcode) {
20840	switch (Opcode) {
20841	case VSCATTERQPDZ128mr:
20842	case VSCATTERQPDZ256mr:
20843	case VSCATTERQPDZmr:
20844		return true;
20845	}
20846	return false;
20847}
20848
20849bool isFYL2X(unsigned Opcode) {
20850	return Opcode == FYL2X;
20851}
20852
20853bool isVPMACSWW(unsigned Opcode) {
20854	switch (Opcode) {
20855	case VPMACSWWrm:
20856	case VPMACSWWrr:
20857		return true;
20858	}
20859	return false;
20860}
20861
20862bool isPFMAX(unsigned Opcode) {
20863	switch (Opcode) {
20864	case PFMAXrm:
20865	case PFMAXrr:
20866		return true;
20867	}
20868	return false;
20869}
20870
20871bool isVPSHUFB(unsigned Opcode) {
20872	switch (Opcode) {
20873	case VPSHUFBYrm:
20874	case VPSHUFBYrr:
20875	case VPSHUFBZ128rm:
20876	case VPSHUFBZ128rmk:
20877	case VPSHUFBZ128rmkz:
20878	case VPSHUFBZ128rr:
20879	case VPSHUFBZ128rrk:
20880	case VPSHUFBZ128rrkz:
20881	case VPSHUFBZ256rm:
20882	case VPSHUFBZ256rmk:
20883	case VPSHUFBZ256rmkz:
20884	case VPSHUFBZ256rr:
20885	case VPSHUFBZ256rrk:
20886	case VPSHUFBZ256rrkz:
20887	case VPSHUFBZrm:
20888	case VPSHUFBZrmk:
20889	case VPSHUFBZrmkz:
20890	case VPSHUFBZrr:
20891	case VPSHUFBZrrk:
20892	case VPSHUFBZrrkz:
20893	case VPSHUFBrm:
20894	case VPSHUFBrr:
20895		return true;
20896	}
20897	return false;
20898}
20899
20900bool isVCVTPD2UQQ(unsigned Opcode) {
20901	switch (Opcode) {
20902	case VCVTPD2UQQZ128rm:
20903	case VCVTPD2UQQZ128rmb:
20904	case VCVTPD2UQQZ128rmbk:
20905	case VCVTPD2UQQZ128rmbkz:
20906	case VCVTPD2UQQZ128rmk:
20907	case VCVTPD2UQQZ128rmkz:
20908	case VCVTPD2UQQZ128rr:
20909	case VCVTPD2UQQZ128rrk:
20910	case VCVTPD2UQQZ128rrkz:
20911	case VCVTPD2UQQZ256rm:
20912	case VCVTPD2UQQZ256rmb:
20913	case VCVTPD2UQQZ256rmbk:
20914	case VCVTPD2UQQZ256rmbkz:
20915	case VCVTPD2UQQZ256rmk:
20916	case VCVTPD2UQQZ256rmkz:
20917	case VCVTPD2UQQZ256rr:
20918	case VCVTPD2UQQZ256rrk:
20919	case VCVTPD2UQQZ256rrkz:
20920	case VCVTPD2UQQZrm:
20921	case VCVTPD2UQQZrmb:
20922	case VCVTPD2UQQZrmbk:
20923	case VCVTPD2UQQZrmbkz:
20924	case VCVTPD2UQQZrmk:
20925	case VCVTPD2UQQZrmkz:
20926	case VCVTPD2UQQZrr:
20927	case VCVTPD2UQQZrrb:
20928	case VCVTPD2UQQZrrbk:
20929	case VCVTPD2UQQZrrbkz:
20930	case VCVTPD2UQQZrrk:
20931	case VCVTPD2UQQZrrkz:
20932		return true;
20933	}
20934	return false;
20935}
20936
20937bool isVPSHUFD(unsigned Opcode) {
20938	switch (Opcode) {
20939	case VPSHUFDYmi:
20940	case VPSHUFDYri:
20941	case VPSHUFDZ128mbi:
20942	case VPSHUFDZ128mbik:
20943	case VPSHUFDZ128mbikz:
20944	case VPSHUFDZ128mi:
20945	case VPSHUFDZ128mik:
20946	case VPSHUFDZ128mikz:
20947	case VPSHUFDZ128ri:
20948	case VPSHUFDZ128rik:
20949	case VPSHUFDZ128rikz:
20950	case VPSHUFDZ256mbi:
20951	case VPSHUFDZ256mbik:
20952	case VPSHUFDZ256mbikz:
20953	case VPSHUFDZ256mi:
20954	case VPSHUFDZ256mik:
20955	case VPSHUFDZ256mikz:
20956	case VPSHUFDZ256ri:
20957	case VPSHUFDZ256rik:
20958	case VPSHUFDZ256rikz:
20959	case VPSHUFDZmbi:
20960	case VPSHUFDZmbik:
20961	case VPSHUFDZmbikz:
20962	case VPSHUFDZmi:
20963	case VPSHUFDZmik:
20964	case VPSHUFDZmikz:
20965	case VPSHUFDZri:
20966	case VPSHUFDZrik:
20967	case VPSHUFDZrikz:
20968	case VPSHUFDmi:
20969	case VPSHUFDri:
20970		return true;
20971	}
20972	return false;
20973}
20974
20975bool isVSCATTERQPS(unsigned Opcode) {
20976	switch (Opcode) {
20977	case VSCATTERQPSZ128mr:
20978	case VSCATTERQPSZ256mr:
20979	case VSCATTERQPSZmr:
20980		return true;
20981	}
20982	return false;
20983}
20984
20985bool isGF2P8AFFINEINVQB(unsigned Opcode) {
20986	switch (Opcode) {
20987	case GF2P8AFFINEINVQBrmi:
20988	case GF2P8AFFINEINVQBrri:
20989		return true;
20990	}
20991	return false;
20992}
20993
20994bool isFEMMS(unsigned Opcode) {
20995	return Opcode == FEMMS;
20996}
20997
20998bool isKUNPCKWD(unsigned Opcode) {
20999	return Opcode == KUNPCKWDrr;
21000}
21001
21002bool isVPCLMULQDQ(unsigned Opcode) {
21003	switch (Opcode) {
21004	case VPCLMULQDQYrm:
21005	case VPCLMULQDQYrr:
21006	case VPCLMULQDQZ128rm:
21007	case VPCLMULQDQZ128rr:
21008	case VPCLMULQDQZ256rm:
21009	case VPCLMULQDQZ256rr:
21010	case VPCLMULQDQZrm:
21011	case VPCLMULQDQZrr:
21012	case VPCLMULQDQrm:
21013	case VPCLMULQDQrr:
21014		return true;
21015	}
21016	return false;
21017}
21018
21019bool isKORB(unsigned Opcode) {
21020	return Opcode == KORBrr;
21021}
21022
21023bool isVINSERTPS(unsigned Opcode) {
21024	switch (Opcode) {
21025	case VINSERTPSZrm:
21026	case VINSERTPSZrr:
21027	case VINSERTPSrm:
21028	case VINSERTPSrr:
21029		return true;
21030	}
21031	return false;
21032}
21033
21034bool isKORD(unsigned Opcode) {
21035	return Opcode == KORDrr;
21036}
21037
21038bool isVMFUNC(unsigned Opcode) {
21039	return Opcode == VMFUNC;
21040}
21041
21042bool isCPUID(unsigned Opcode) {
21043	return Opcode == CPUID;
21044}
21045
21046bool isVSCATTERPF0QPD(unsigned Opcode) {
21047	return Opcode == VSCATTERPF0QPDm;
21048}
21049
21050bool isOUT(unsigned Opcode) {
21051	switch (Opcode) {
21052	case OUT16ir:
21053	case OUT16rr:
21054	case OUT32ir:
21055	case OUT32rr:
21056	case OUT8ir:
21057	case OUT8rr:
21058		return true;
21059	}
21060	return false;
21061}
21062
21063bool isKORQ(unsigned Opcode) {
21064	return Opcode == KORQrr;
21065}
21066
21067bool isKORW(unsigned Opcode) {
21068	return Opcode == KORWrr;
21069}
21070
21071bool isVSCATTERPF0QPS(unsigned Opcode) {
21072	return Opcode == VSCATTERPF0QPSm;
21073}
21074
21075bool isPHSUBSW(unsigned Opcode) {
21076	switch (Opcode) {
21077	case MMX_PHSUBSWrm:
21078	case MMX_PHSUBSWrr:
21079	case PHSUBSWrm:
21080	case PHSUBSWrr:
21081		return true;
21082	}
21083	return false;
21084}
21085
21086bool isPFSUBR(unsigned Opcode) {
21087	switch (Opcode) {
21088	case PFSUBRrm:
21089	case PFSUBRrr:
21090		return true;
21091	}
21092	return false;
21093}
21094
21095bool isVCVTPH2UDQ(unsigned Opcode) {
21096	switch (Opcode) {
21097	case VCVTPH2UDQZ128rm:
21098	case VCVTPH2UDQZ128rmb:
21099	case VCVTPH2UDQZ128rmbk:
21100	case VCVTPH2UDQZ128rmbkz:
21101	case VCVTPH2UDQZ128rmk:
21102	case VCVTPH2UDQZ128rmkz:
21103	case VCVTPH2UDQZ128rr:
21104	case VCVTPH2UDQZ128rrk:
21105	case VCVTPH2UDQZ128rrkz:
21106	case VCVTPH2UDQZ256rm:
21107	case VCVTPH2UDQZ256rmb:
21108	case VCVTPH2UDQZ256rmbk:
21109	case VCVTPH2UDQZ256rmbkz:
21110	case VCVTPH2UDQZ256rmk:
21111	case VCVTPH2UDQZ256rmkz:
21112	case VCVTPH2UDQZ256rr:
21113	case VCVTPH2UDQZ256rrk:
21114	case VCVTPH2UDQZ256rrkz:
21115	case VCVTPH2UDQZrm:
21116	case VCVTPH2UDQZrmb:
21117	case VCVTPH2UDQZrmbk:
21118	case VCVTPH2UDQZrmbkz:
21119	case VCVTPH2UDQZrmk:
21120	case VCVTPH2UDQZrmkz:
21121	case VCVTPH2UDQZrr:
21122	case VCVTPH2UDQZrrb:
21123	case VCVTPH2UDQZrrbk:
21124	case VCVTPH2UDQZrrbkz:
21125	case VCVTPH2UDQZrrk:
21126	case VCVTPH2UDQZrrkz:
21127		return true;
21128	}
21129	return false;
21130}
21131
21132bool isVBROADCASTF32X2(unsigned Opcode) {
21133	switch (Opcode) {
21134	case VBROADCASTF32X2Z256rm:
21135	case VBROADCASTF32X2Z256rmk:
21136	case VBROADCASTF32X2Z256rmkz:
21137	case VBROADCASTF32X2Z256rr:
21138	case VBROADCASTF32X2Z256rrk:
21139	case VBROADCASTF32X2Z256rrkz:
21140	case VBROADCASTF32X2Zrm:
21141	case VBROADCASTF32X2Zrmk:
21142	case VBROADCASTF32X2Zrmkz:
21143	case VBROADCASTF32X2Zrr:
21144	case VBROADCASTF32X2Zrrk:
21145	case VBROADCASTF32X2Zrrkz:
21146		return true;
21147	}
21148	return false;
21149}
21150
21151bool isVBROADCASTF32X4(unsigned Opcode) {
21152	switch (Opcode) {
21153	case VBROADCASTF32X4Z256rm:
21154	case VBROADCASTF32X4Z256rmk:
21155	case VBROADCASTF32X4Z256rmkz:
21156	case VBROADCASTF32X4rm:
21157	case VBROADCASTF32X4rmk:
21158	case VBROADCASTF32X4rmkz:
21159		return true;
21160	}
21161	return false;
21162}
21163
21164bool isSHA256RNDS2(unsigned Opcode) {
21165	switch (Opcode) {
21166	case SHA256RNDS2rm:
21167	case SHA256RNDS2rr:
21168		return true;
21169	}
21170	return false;
21171}
21172
21173bool isVBROADCASTF32X8(unsigned Opcode) {
21174	switch (Opcode) {
21175	case VBROADCASTF32X8rm:
21176	case VBROADCASTF32X8rmk:
21177	case VBROADCASTF32X8rmkz:
21178		return true;
21179	}
21180	return false;
21181}
21182
21183bool isVPERMB(unsigned Opcode) {
21184	switch (Opcode) {
21185	case VPERMBZ128rm:
21186	case VPERMBZ128rmk:
21187	case VPERMBZ128rmkz:
21188	case VPERMBZ128rr:
21189	case VPERMBZ128rrk:
21190	case VPERMBZ128rrkz:
21191	case VPERMBZ256rm:
21192	case VPERMBZ256rmk:
21193	case VPERMBZ256rmkz:
21194	case VPERMBZ256rr:
21195	case VPERMBZ256rrk:
21196	case VPERMBZ256rrkz:
21197	case VPERMBZrm:
21198	case VPERMBZrmk:
21199	case VPERMBZrmkz:
21200	case VPERMBZrr:
21201	case VPERMBZrrk:
21202	case VPERMBZrrkz:
21203		return true;
21204	}
21205	return false;
21206}
21207
21208bool isVPUNPCKLBW(unsigned Opcode) {
21209	switch (Opcode) {
21210	case VPUNPCKLBWYrm:
21211	case VPUNPCKLBWYrr:
21212	case VPUNPCKLBWZ128rm:
21213	case VPUNPCKLBWZ128rmk:
21214	case VPUNPCKLBWZ128rmkz:
21215	case VPUNPCKLBWZ128rr:
21216	case VPUNPCKLBWZ128rrk:
21217	case VPUNPCKLBWZ128rrkz:
21218	case VPUNPCKLBWZ256rm:
21219	case VPUNPCKLBWZ256rmk:
21220	case VPUNPCKLBWZ256rmkz:
21221	case VPUNPCKLBWZ256rr:
21222	case VPUNPCKLBWZ256rrk:
21223	case VPUNPCKLBWZ256rrkz:
21224	case VPUNPCKLBWZrm:
21225	case VPUNPCKLBWZrmk:
21226	case VPUNPCKLBWZrmkz:
21227	case VPUNPCKLBWZrr:
21228	case VPUNPCKLBWZrrk:
21229	case VPUNPCKLBWZrrkz:
21230	case VPUNPCKLBWrm:
21231	case VPUNPCKLBWrr:
21232		return true;
21233	}
21234	return false;
21235}
21236
21237bool isVPERMD(unsigned Opcode) {
21238	switch (Opcode) {
21239	case VPERMDYrm:
21240	case VPERMDYrr:
21241	case VPERMDZ256rm:
21242	case VPERMDZ256rmb:
21243	case VPERMDZ256rmbk:
21244	case VPERMDZ256rmbkz:
21245	case VPERMDZ256rmk:
21246	case VPERMDZ256rmkz:
21247	case VPERMDZ256rr:
21248	case VPERMDZ256rrk:
21249	case VPERMDZ256rrkz:
21250	case VPERMDZrm:
21251	case VPERMDZrmb:
21252	case VPERMDZrmbk:
21253	case VPERMDZrmbkz:
21254	case VPERMDZrmk:
21255	case VPERMDZrmkz:
21256	case VPERMDZrr:
21257	case VPERMDZrrk:
21258	case VPERMDZrrkz:
21259		return true;
21260	}
21261	return false;
21262}
21263
21264bool isXCRYPTECB(unsigned Opcode) {
21265	return Opcode == XCRYPTECB;
21266}
21267
21268bool isVPERMQ(unsigned Opcode) {
21269	switch (Opcode) {
21270	case VPERMQYmi:
21271	case VPERMQYri:
21272	case VPERMQZ256mbi:
21273	case VPERMQZ256mbik:
21274	case VPERMQZ256mbikz:
21275	case VPERMQZ256mi:
21276	case VPERMQZ256mik:
21277	case VPERMQZ256mikz:
21278	case VPERMQZ256ri:
21279	case VPERMQZ256rik:
21280	case VPERMQZ256rikz:
21281	case VPERMQZ256rm:
21282	case VPERMQZ256rmb:
21283	case VPERMQZ256rmbk:
21284	case VPERMQZ256rmbkz:
21285	case VPERMQZ256rmk:
21286	case VPERMQZ256rmkz:
21287	case VPERMQZ256rr:
21288	case VPERMQZ256rrk:
21289	case VPERMQZ256rrkz:
21290	case VPERMQZmbi:
21291	case VPERMQZmbik:
21292	case VPERMQZmbikz:
21293	case VPERMQZmi:
21294	case VPERMQZmik:
21295	case VPERMQZmikz:
21296	case VPERMQZri:
21297	case VPERMQZrik:
21298	case VPERMQZrikz:
21299	case VPERMQZrm:
21300	case VPERMQZrmb:
21301	case VPERMQZrmbk:
21302	case VPERMQZrmbkz:
21303	case VPERMQZrmk:
21304	case VPERMQZrmkz:
21305	case VPERMQZrr:
21306	case VPERMQZrrk:
21307	case VPERMQZrrkz:
21308		return true;
21309	}
21310	return false;
21311}
21312
21313bool isEXTRACTPS(unsigned Opcode) {
21314	switch (Opcode) {
21315	case EXTRACTPSmr:
21316	case EXTRACTPSrr:
21317		return true;
21318	}
21319	return false;
21320}
21321
21322bool isVPERMW(unsigned Opcode) {
21323	switch (Opcode) {
21324	case VPERMWZ128rm:
21325	case VPERMWZ128rmk:
21326	case VPERMWZ128rmkz:
21327	case VPERMWZ128rr:
21328	case VPERMWZ128rrk:
21329	case VPERMWZ128rrkz:
21330	case VPERMWZ256rm:
21331	case VPERMWZ256rmk:
21332	case VPERMWZ256rmkz:
21333	case VPERMWZ256rr:
21334	case VPERMWZ256rrk:
21335	case VPERMWZ256rrkz:
21336	case VPERMWZrm:
21337	case VPERMWZrmk:
21338	case VPERMWZrmkz:
21339	case VPERMWZrr:
21340	case VPERMWZrrk:
21341	case VPERMWZrrkz:
21342		return true;
21343	}
21344	return false;
21345}
21346
21347bool isHADDPD(unsigned Opcode) {
21348	switch (Opcode) {
21349	case HADDPDrm:
21350	case HADDPDrr:
21351		return true;
21352	}
21353	return false;
21354}
21355
21356bool isFXSAVE(unsigned Opcode) {
21357	return Opcode == FXSAVE;
21358}
21359
21360bool isVRCPPH(unsigned Opcode) {
21361	switch (Opcode) {
21362	case VRCPPHZ128m:
21363	case VRCPPHZ128mb:
21364	case VRCPPHZ128mbk:
21365	case VRCPPHZ128mbkz:
21366	case VRCPPHZ128mk:
21367	case VRCPPHZ128mkz:
21368	case VRCPPHZ128r:
21369	case VRCPPHZ128rk:
21370	case VRCPPHZ128rkz:
21371	case VRCPPHZ256m:
21372	case VRCPPHZ256mb:
21373	case VRCPPHZ256mbk:
21374	case VRCPPHZ256mbkz:
21375	case VRCPPHZ256mk:
21376	case VRCPPHZ256mkz:
21377	case VRCPPHZ256r:
21378	case VRCPPHZ256rk:
21379	case VRCPPHZ256rkz:
21380	case VRCPPHZm:
21381	case VRCPPHZmb:
21382	case VRCPPHZmbk:
21383	case VRCPPHZmbkz:
21384	case VRCPPHZmk:
21385	case VRCPPHZmkz:
21386	case VRCPPHZr:
21387	case VRCPPHZrk:
21388	case VRCPPHZrkz:
21389		return true;
21390	}
21391	return false;
21392}
21393
21394bool isHADDPS(unsigned Opcode) {
21395	switch (Opcode) {
21396	case HADDPSrm:
21397	case HADDPSrr:
21398		return true;
21399	}
21400	return false;
21401}
21402
21403bool isVPSADBW(unsigned Opcode) {
21404	switch (Opcode) {
21405	case VPSADBWYrm:
21406	case VPSADBWYrr:
21407	case VPSADBWZ128rm:
21408	case VPSADBWZ128rr:
21409	case VPSADBWZ256rm:
21410	case VPSADBWZ256rr:
21411	case VPSADBWZrm:
21412	case VPSADBWZrr:
21413	case VPSADBWrm:
21414	case VPSADBWrr:
21415		return true;
21416	}
21417	return false;
21418}
21419
21420bool isRDRAND(unsigned Opcode) {
21421	switch (Opcode) {
21422	case RDRAND16r:
21423	case RDRAND32r:
21424	case RDRAND64r:
21425		return true;
21426	}
21427	return false;
21428}
21429
21430bool isVRCPPS(unsigned Opcode) {
21431	switch (Opcode) {
21432	case VRCPPSYm:
21433	case VRCPPSYr:
21434	case VRCPPSm:
21435	case VRCPPSr:
21436		return true;
21437	}
21438	return false;
21439}
21440
21441bool isVXORPD(unsigned Opcode) {
21442	switch (Opcode) {
21443	case VXORPDYrm:
21444	case VXORPDYrr:
21445	case VXORPDZ128rm:
21446	case VXORPDZ128rmb:
21447	case VXORPDZ128rmbk:
21448	case VXORPDZ128rmbkz:
21449	case VXORPDZ128rmk:
21450	case VXORPDZ128rmkz:
21451	case VXORPDZ128rr:
21452	case VXORPDZ128rrk:
21453	case VXORPDZ128rrkz:
21454	case VXORPDZ256rm:
21455	case VXORPDZ256rmb:
21456	case VXORPDZ256rmbk:
21457	case VXORPDZ256rmbkz:
21458	case VXORPDZ256rmk:
21459	case VXORPDZ256rmkz:
21460	case VXORPDZ256rr:
21461	case VXORPDZ256rrk:
21462	case VXORPDZ256rrkz:
21463	case VXORPDZrm:
21464	case VXORPDZrmb:
21465	case VXORPDZrmbk:
21466	case VXORPDZrmbkz:
21467	case VXORPDZrmk:
21468	case VXORPDZrmkz:
21469	case VXORPDZrr:
21470	case VXORPDZrrk:
21471	case VXORPDZrrkz:
21472	case VXORPDrm:
21473	case VXORPDrr:
21474		return true;
21475	}
21476	return false;
21477}
21478
21479bool isFFREE(unsigned Opcode) {
21480	return Opcode == FFREE;
21481}
21482
21483bool isPCMPEQB(unsigned Opcode) {
21484	switch (Opcode) {
21485	case MMX_PCMPEQBrm:
21486	case MMX_PCMPEQBrr:
21487	case PCMPEQBrm:
21488	case PCMPEQBrr:
21489		return true;
21490	}
21491	return false;
21492}
21493
21494bool isPCMPEQD(unsigned Opcode) {
21495	switch (Opcode) {
21496	case MMX_PCMPEQDrm:
21497	case MMX_PCMPEQDrr:
21498	case PCMPEQDrm:
21499	case PCMPEQDrr:
21500		return true;
21501	}
21502	return false;
21503}
21504
21505bool isVPUNPCKLDQ(unsigned Opcode) {
21506	switch (Opcode) {
21507	case VPUNPCKLDQYrm:
21508	case VPUNPCKLDQYrr:
21509	case VPUNPCKLDQZ128rm:
21510	case VPUNPCKLDQZ128rmb:
21511	case VPUNPCKLDQZ128rmbk:
21512	case VPUNPCKLDQZ128rmbkz:
21513	case VPUNPCKLDQZ128rmk:
21514	case VPUNPCKLDQZ128rmkz:
21515	case VPUNPCKLDQZ128rr:
21516	case VPUNPCKLDQZ128rrk:
21517	case VPUNPCKLDQZ128rrkz:
21518	case VPUNPCKLDQZ256rm:
21519	case VPUNPCKLDQZ256rmb:
21520	case VPUNPCKLDQZ256rmbk:
21521	case VPUNPCKLDQZ256rmbkz:
21522	case VPUNPCKLDQZ256rmk:
21523	case VPUNPCKLDQZ256rmkz:
21524	case VPUNPCKLDQZ256rr:
21525	case VPUNPCKLDQZ256rrk:
21526	case VPUNPCKLDQZ256rrkz:
21527	case VPUNPCKLDQZrm:
21528	case VPUNPCKLDQZrmb:
21529	case VPUNPCKLDQZrmbk:
21530	case VPUNPCKLDQZrmbkz:
21531	case VPUNPCKLDQZrmk:
21532	case VPUNPCKLDQZrmkz:
21533	case VPUNPCKLDQZrr:
21534	case VPUNPCKLDQZrrk:
21535	case VPUNPCKLDQZrrkz:
21536	case VPUNPCKLDQrm:
21537	case VPUNPCKLDQrr:
21538		return true;
21539	}
21540	return false;
21541}
21542
21543bool isVTESTPD(unsigned Opcode) {
21544	switch (Opcode) {
21545	case VTESTPDYrm:
21546	case VTESTPDYrr:
21547	case VTESTPDrm:
21548	case VTESTPDrr:
21549		return true;
21550	}
21551	return false;
21552}
21553
21554bool isVXORPS(unsigned Opcode) {
21555	switch (Opcode) {
21556	case VXORPSYrm:
21557	case VXORPSYrr:
21558	case VXORPSZ128rm:
21559	case VXORPSZ128rmb:
21560	case VXORPSZ128rmbk:
21561	case VXORPSZ128rmbkz:
21562	case VXORPSZ128rmk:
21563	case VXORPSZ128rmkz:
21564	case VXORPSZ128rr:
21565	case VXORPSZ128rrk:
21566	case VXORPSZ128rrkz:
21567	case VXORPSZ256rm:
21568	case VXORPSZ256rmb:
21569	case VXORPSZ256rmbk:
21570	case VXORPSZ256rmbkz:
21571	case VXORPSZ256rmk:
21572	case VXORPSZ256rmkz:
21573	case VXORPSZ256rr:
21574	case VXORPSZ256rrk:
21575	case VXORPSZ256rrkz:
21576	case VXORPSZrm:
21577	case VXORPSZrmb:
21578	case VXORPSZrmbk:
21579	case VXORPSZrmbkz:
21580	case VXORPSZrmk:
21581	case VXORPSZrmkz:
21582	case VXORPSZrr:
21583	case VXORPSZrrk:
21584	case VXORPSZrrkz:
21585	case VXORPSrm:
21586	case VXORPSrr:
21587		return true;
21588	}
21589	return false;
21590}
21591
21592bool isTZCNT(unsigned Opcode) {
21593	switch (Opcode) {
21594	case TZCNT16rm:
21595	case TZCNT16rr:
21596	case TZCNT32rm:
21597	case TZCNT32rr:
21598	case TZCNT64rm:
21599	case TZCNT64rr:
21600		return true;
21601	}
21602	return false;
21603}
21604
21605bool isCLTS(unsigned Opcode) {
21606	return Opcode == CLTS;
21607}
21608
21609bool isPCMPEQQ(unsigned Opcode) {
21610	switch (Opcode) {
21611	case PCMPEQQrm:
21612	case PCMPEQQrr:
21613		return true;
21614	}
21615	return false;
21616}
21617
21618bool isVFPCLASSPD(unsigned Opcode) {
21619	switch (Opcode) {
21620	case VFPCLASSPDZ128rm:
21621	case VFPCLASSPDZ128rmb:
21622	case VFPCLASSPDZ128rmbk:
21623	case VFPCLASSPDZ128rmk:
21624	case VFPCLASSPDZ128rr:
21625	case VFPCLASSPDZ128rrk:
21626	case VFPCLASSPDZ256rm:
21627	case VFPCLASSPDZ256rmb:
21628	case VFPCLASSPDZ256rmbk:
21629	case VFPCLASSPDZ256rmk:
21630	case VFPCLASSPDZ256rr:
21631	case VFPCLASSPDZ256rrk:
21632	case VFPCLASSPDZrm:
21633	case VFPCLASSPDZrmb:
21634	case VFPCLASSPDZrmbk:
21635	case VFPCLASSPDZrmk:
21636	case VFPCLASSPDZrr:
21637	case VFPCLASSPDZrrk:
21638		return true;
21639	}
21640	return false;
21641}
21642
21643bool isVFPCLASSPH(unsigned Opcode) {
21644	switch (Opcode) {
21645	case VFPCLASSPHZ128rm:
21646	case VFPCLASSPHZ128rmb:
21647	case VFPCLASSPHZ128rmbk:
21648	case VFPCLASSPHZ128rmk:
21649	case VFPCLASSPHZ128rr:
21650	case VFPCLASSPHZ128rrk:
21651	case VFPCLASSPHZ256rm:
21652	case VFPCLASSPHZ256rmb:
21653	case VFPCLASSPHZ256rmbk:
21654	case VFPCLASSPHZ256rmk:
21655	case VFPCLASSPHZ256rr:
21656	case VFPCLASSPHZ256rrk:
21657	case VFPCLASSPHZrm:
21658	case VFPCLASSPHZrmb:
21659	case VFPCLASSPHZrmbk:
21660	case VFPCLASSPHZrmk:
21661	case VFPCLASSPHZrr:
21662	case VFPCLASSPHZrrk:
21663		return true;
21664	}
21665	return false;
21666}
21667
21668bool isVTESTPS(unsigned Opcode) {
21669	switch (Opcode) {
21670	case VTESTPSYrm:
21671	case VTESTPSYrr:
21672	case VTESTPSrm:
21673	case VTESTPSrr:
21674		return true;
21675	}
21676	return false;
21677}
21678
21679bool isPCMPEQW(unsigned Opcode) {
21680	switch (Opcode) {
21681	case MMX_PCMPEQWrm:
21682	case MMX_PCMPEQWrr:
21683	case PCMPEQWrm:
21684	case PCMPEQWrr:
21685		return true;
21686	}
21687	return false;
21688}
21689
21690bool isUNPCKLPD(unsigned Opcode) {
21691	switch (Opcode) {
21692	case UNPCKLPDrm:
21693	case UNPCKLPDrr:
21694		return true;
21695	}
21696	return false;
21697}
21698
21699bool isVMOVDQA32(unsigned Opcode) {
21700	switch (Opcode) {
21701	case VMOVDQA32Z128mr:
21702	case VMOVDQA32Z128mrk:
21703	case VMOVDQA32Z128rm:
21704	case VMOVDQA32Z128rmk:
21705	case VMOVDQA32Z128rmkz:
21706	case VMOVDQA32Z128rr:
21707	case VMOVDQA32Z128rr_REV:
21708	case VMOVDQA32Z128rrk:
21709	case VMOVDQA32Z128rrk_REV:
21710	case VMOVDQA32Z128rrkz:
21711	case VMOVDQA32Z128rrkz_REV:
21712	case VMOVDQA32Z256mr:
21713	case VMOVDQA32Z256mrk:
21714	case VMOVDQA32Z256rm:
21715	case VMOVDQA32Z256rmk:
21716	case VMOVDQA32Z256rmkz:
21717	case VMOVDQA32Z256rr:
21718	case VMOVDQA32Z256rr_REV:
21719	case VMOVDQA32Z256rrk:
21720	case VMOVDQA32Z256rrk_REV:
21721	case VMOVDQA32Z256rrkz:
21722	case VMOVDQA32Z256rrkz_REV:
21723	case VMOVDQA32Zmr:
21724	case VMOVDQA32Zmrk:
21725	case VMOVDQA32Zrm:
21726	case VMOVDQA32Zrmk:
21727	case VMOVDQA32Zrmkz:
21728	case VMOVDQA32Zrr:
21729	case VMOVDQA32Zrr_REV:
21730	case VMOVDQA32Zrrk:
21731	case VMOVDQA32Zrrk_REV:
21732	case VMOVDQA32Zrrkz:
21733	case VMOVDQA32Zrrkz_REV:
21734		return true;
21735	}
21736	return false;
21737}
21738
21739bool isVFPCLASSPS(unsigned Opcode) {
21740	switch (Opcode) {
21741	case VFPCLASSPSZ128rm:
21742	case VFPCLASSPSZ128rmb:
21743	case VFPCLASSPSZ128rmbk:
21744	case VFPCLASSPSZ128rmk:
21745	case VFPCLASSPSZ128rr:
21746	case VFPCLASSPSZ128rrk:
21747	case VFPCLASSPSZ256rm:
21748	case VFPCLASSPSZ256rmb:
21749	case VFPCLASSPSZ256rmbk:
21750	case VFPCLASSPSZ256rmk:
21751	case VFPCLASSPSZ256rr:
21752	case VFPCLASSPSZ256rrk:
21753	case VFPCLASSPSZrm:
21754	case VFPCLASSPSZrmb:
21755	case VFPCLASSPSZrmbk:
21756	case VFPCLASSPSZrmk:
21757	case VFPCLASSPSZrr:
21758	case VFPCLASSPSZrrk:
21759		return true;
21760	}
21761	return false;
21762}
21763
21764bool isVPMOVMSKB(unsigned Opcode) {
21765	switch (Opcode) {
21766	case VPMOVMSKBYrr:
21767	case VPMOVMSKBrr:
21768		return true;
21769	}
21770	return false;
21771}
21772
21773bool isFDECSTP(unsigned Opcode) {
21774	return Opcode == FDECSTP;
21775}
21776
21777bool isCLUI(unsigned Opcode) {
21778	return Opcode == CLUI;
21779}
21780
21781bool isFLDPI(unsigned Opcode) {
21782	return Opcode == FLDPI;
21783}
21784
21785bool isUNPCKLPS(unsigned Opcode) {
21786	switch (Opcode) {
21787	case UNPCKLPSrm:
21788	case UNPCKLPSrr:
21789		return true;
21790	}
21791	return false;
21792}
21793
21794bool isVCVTTPD2DQ(unsigned Opcode) {
21795	switch (Opcode) {
21796	case VCVTTPD2DQYrm:
21797	case VCVTTPD2DQYrr:
21798	case VCVTTPD2DQZ128rm:
21799	case VCVTTPD2DQZ128rmb:
21800	case VCVTTPD2DQZ128rmbk:
21801	case VCVTTPD2DQZ128rmbkz:
21802	case VCVTTPD2DQZ128rmk:
21803	case VCVTTPD2DQZ128rmkz:
21804	case VCVTTPD2DQZ128rr:
21805	case VCVTTPD2DQZ128rrk:
21806	case VCVTTPD2DQZ128rrkz:
21807	case VCVTTPD2DQZ256rm:
21808	case VCVTTPD2DQZ256rmb:
21809	case VCVTTPD2DQZ256rmbk:
21810	case VCVTTPD2DQZ256rmbkz:
21811	case VCVTTPD2DQZ256rmk:
21812	case VCVTTPD2DQZ256rmkz:
21813	case VCVTTPD2DQZ256rr:
21814	case VCVTTPD2DQZ256rrk:
21815	case VCVTTPD2DQZ256rrkz:
21816	case VCVTTPD2DQZrm:
21817	case VCVTTPD2DQZrmb:
21818	case VCVTTPD2DQZrmbk:
21819	case VCVTTPD2DQZrmbkz:
21820	case VCVTTPD2DQZrmk:
21821	case VCVTTPD2DQZrmkz:
21822	case VCVTTPD2DQZrr:
21823	case VCVTTPD2DQZrrb:
21824	case VCVTTPD2DQZrrbk:
21825	case VCVTTPD2DQZrrbkz:
21826	case VCVTTPD2DQZrrk:
21827	case VCVTTPD2DQZrrkz:
21828	case VCVTTPD2DQrm:
21829	case VCVTTPD2DQrr:
21830		return true;
21831	}
21832	return false;
21833}
21834
21835bool isPAVGUSB(unsigned Opcode) {
21836	switch (Opcode) {
21837	case PAVGUSBrm:
21838	case PAVGUSBrr:
21839		return true;
21840	}
21841	return false;
21842}
21843
21844bool isCALL(unsigned Opcode) {
21845	switch (Opcode) {
21846	case CALL16m:
21847	case CALL16r:
21848	case CALL32m:
21849	case CALL32r:
21850	case CALL64m:
21851	case CALL64pcrel32:
21852	case CALL64r:
21853	case CALLpcrel16:
21854	case CALLpcrel32:
21855	case FARCALL32m:
21856		return true;
21857	}
21858	return false;
21859}
21860
21861bool isFLDENV(unsigned Opcode) {
21862	return Opcode == FLDENVm;
21863}
21864
21865bool isPACKUSWB(unsigned Opcode) {
21866	switch (Opcode) {
21867	case MMX_PACKUSWBrm:
21868	case MMX_PACKUSWBrr:
21869	case PACKUSWBrm:
21870	case PACKUSWBrr:
21871		return true;
21872	}
21873	return false;
21874}
21875
21876bool isVPHADDSW(unsigned Opcode) {
21877	switch (Opcode) {
21878	case VPHADDSWYrm:
21879	case VPHADDSWYrr:
21880	case VPHADDSWrm:
21881	case VPHADDSWrr:
21882		return true;
21883	}
21884	return false;
21885}
21886
21887bool isLAR(unsigned Opcode) {
21888	switch (Opcode) {
21889	case LAR16rm:
21890	case LAR16rr:
21891	case LAR32rm:
21892	case LAR32rr:
21893	case LAR64rm:
21894	case LAR64rr:
21895		return true;
21896	}
21897	return false;
21898}
21899
21900bool isCLFLUSHOPT(unsigned Opcode) {
21901	return Opcode == CLFLUSHOPT;
21902}
21903
21904bool isVMMCALL(unsigned Opcode) {
21905	return Opcode == VMMCALL;
21906}
21907
21908bool isARPL(unsigned Opcode) {
21909	switch (Opcode) {
21910	case ARPL16mr:
21911	case ARPL16rr:
21912		return true;
21913	}
21914	return false;
21915}
21916
21917bool isXABORT(unsigned Opcode) {
21918	return Opcode == XABORT;
21919}
21920
21921bool isPUNPCKHWD(unsigned Opcode) {
21922	switch (Opcode) {
21923	case MMX_PUNPCKHWDrm:
21924	case MMX_PUNPCKHWDrr:
21925	case PUNPCKHWDrm:
21926	case PUNPCKHWDrr:
21927		return true;
21928	}
21929	return false;
21930}
21931
21932bool isVRCPSH(unsigned Opcode) {
21933	switch (Opcode) {
21934	case VRCPSHZrm:
21935	case VRCPSHZrmk:
21936	case VRCPSHZrmkz:
21937	case VRCPSHZrr:
21938	case VRCPSHZrrk:
21939	case VRCPSHZrrkz:
21940		return true;
21941	}
21942	return false;
21943}
21944
21945bool isLDDQU(unsigned Opcode) {
21946	return Opcode == LDDQUrm;
21947}
21948
21949bool isPFMIN(unsigned Opcode) {
21950	switch (Opcode) {
21951	case PFMINrm:
21952	case PFMINrr:
21953		return true;
21954	}
21955	return false;
21956}
21957
21958bool isSYSRETQ(unsigned Opcode) {
21959	return Opcode == SYSRET64;
21960}
21961
21962bool isVRCPSS(unsigned Opcode) {
21963	switch (Opcode) {
21964	case VRCPSSm_Int:
21965	case VRCPSSr_Int:
21966		return true;
21967	}
21968	return false;
21969}
21970
21971bool isCLWB(unsigned Opcode) {
21972	return Opcode == CLWB;
21973}
21974
21975bool isSTC(unsigned Opcode) {
21976	return Opcode == STC;
21977}
21978
21979bool isSTD(unsigned Opcode) {
21980	return Opcode == STD;
21981}
21982
21983bool isVMOVDQU8(unsigned Opcode) {
21984	switch (Opcode) {
21985	case VMOVDQU8Z128mr:
21986	case VMOVDQU8Z128mrk:
21987	case VMOVDQU8Z128rm:
21988	case VMOVDQU8Z128rmk:
21989	case VMOVDQU8Z128rmkz:
21990	case VMOVDQU8Z128rr:
21991	case VMOVDQU8Z128rr_REV:
21992	case VMOVDQU8Z128rrk:
21993	case VMOVDQU8Z128rrk_REV:
21994	case VMOVDQU8Z128rrkz:
21995	case VMOVDQU8Z128rrkz_REV:
21996	case VMOVDQU8Z256mr:
21997	case VMOVDQU8Z256mrk:
21998	case VMOVDQU8Z256rm:
21999	case VMOVDQU8Z256rmk:
22000	case VMOVDQU8Z256rmkz:
22001	case VMOVDQU8Z256rr:
22002	case VMOVDQU8Z256rr_REV:
22003	case VMOVDQU8Z256rrk:
22004	case VMOVDQU8Z256rrk_REV:
22005	case VMOVDQU8Z256rrkz:
22006	case VMOVDQU8Z256rrkz_REV:
22007	case VMOVDQU8Zmr:
22008	case VMOVDQU8Zmrk:
22009	case VMOVDQU8Zrm:
22010	case VMOVDQU8Zrmk:
22011	case VMOVDQU8Zrmkz:
22012	case VMOVDQU8Zrr:
22013	case VMOVDQU8Zrr_REV:
22014	case VMOVDQU8Zrrk:
22015	case VMOVDQU8Zrrk_REV:
22016	case VMOVDQU8Zrrkz:
22017	case VMOVDQU8Zrrkz_REV:
22018		return true;
22019	}
22020	return false;
22021}
22022
22023bool isSTI(unsigned Opcode) {
22024	return Opcode == STI;
22025}
22026
22027bool isSTR(unsigned Opcode) {
22028	switch (Opcode) {
22029	case STR16r:
22030	case STR32r:
22031	case STR64r:
22032	case STRm:
22033		return true;
22034	}
22035	return false;
22036}
22037
22038bool isVFPCLASSSD(unsigned Opcode) {
22039	switch (Opcode) {
22040	case VFPCLASSSDZrm:
22041	case VFPCLASSSDZrmk:
22042	case VFPCLASSSDZrr:
22043	case VFPCLASSSDZrrk:
22044		return true;
22045	}
22046	return false;
22047}
22048
22049bool isLDMXCSR(unsigned Opcode) {
22050	return Opcode == LDMXCSR;
22051}
22052
22053bool isVFPCLASSSH(unsigned Opcode) {
22054	switch (Opcode) {
22055	case VFPCLASSSHZrm:
22056	case VFPCLASSSHZrmk:
22057	case VFPCLASSSHZrr:
22058	case VFPCLASSSHZrrk:
22059		return true;
22060	}
22061	return false;
22062}
22063
22064bool isVCVTPD2PH(unsigned Opcode) {
22065	switch (Opcode) {
22066	case VCVTPD2PHZ128rm:
22067	case VCVTPD2PHZ128rmb:
22068	case VCVTPD2PHZ128rmbk:
22069	case VCVTPD2PHZ128rmbkz:
22070	case VCVTPD2PHZ128rmk:
22071	case VCVTPD2PHZ128rmkz:
22072	case VCVTPD2PHZ128rr:
22073	case VCVTPD2PHZ128rrk:
22074	case VCVTPD2PHZ128rrkz:
22075	case VCVTPD2PHZ256rm:
22076	case VCVTPD2PHZ256rmb:
22077	case VCVTPD2PHZ256rmbk:
22078	case VCVTPD2PHZ256rmbkz:
22079	case VCVTPD2PHZ256rmk:
22080	case VCVTPD2PHZ256rmkz:
22081	case VCVTPD2PHZ256rr:
22082	case VCVTPD2PHZ256rrk:
22083	case VCVTPD2PHZ256rrkz:
22084	case VCVTPD2PHZrm:
22085	case VCVTPD2PHZrmb:
22086	case VCVTPD2PHZrmbk:
22087	case VCVTPD2PHZrmbkz:
22088	case VCVTPD2PHZrmk:
22089	case VCVTPD2PHZrmkz:
22090	case VCVTPD2PHZrr:
22091	case VCVTPD2PHZrrb:
22092	case VCVTPD2PHZrrbk:
22093	case VCVTPD2PHZrrbkz:
22094	case VCVTPD2PHZrrk:
22095	case VCVTPD2PHZrrkz:
22096		return true;
22097	}
22098	return false;
22099}
22100
22101bool isVCVTPH2DQ(unsigned Opcode) {
22102	switch (Opcode) {
22103	case VCVTPH2DQZ128rm:
22104	case VCVTPH2DQZ128rmb:
22105	case VCVTPH2DQZ128rmbk:
22106	case VCVTPH2DQZ128rmbkz:
22107	case VCVTPH2DQZ128rmk:
22108	case VCVTPH2DQZ128rmkz:
22109	case VCVTPH2DQZ128rr:
22110	case VCVTPH2DQZ128rrk:
22111	case VCVTPH2DQZ128rrkz:
22112	case VCVTPH2DQZ256rm:
22113	case VCVTPH2DQZ256rmb:
22114	case VCVTPH2DQZ256rmbk:
22115	case VCVTPH2DQZ256rmbkz:
22116	case VCVTPH2DQZ256rmk:
22117	case VCVTPH2DQZ256rmkz:
22118	case VCVTPH2DQZ256rr:
22119	case VCVTPH2DQZ256rrk:
22120	case VCVTPH2DQZ256rrkz:
22121	case VCVTPH2DQZrm:
22122	case VCVTPH2DQZrmb:
22123	case VCVTPH2DQZrmbk:
22124	case VCVTPH2DQZrmbkz:
22125	case VCVTPH2DQZrmk:
22126	case VCVTPH2DQZrmkz:
22127	case VCVTPH2DQZrr:
22128	case VCVTPH2DQZrrb:
22129	case VCVTPH2DQZrrbk:
22130	case VCVTPH2DQZrrbkz:
22131	case VCVTPH2DQZrrk:
22132	case VCVTPH2DQZrrkz:
22133		return true;
22134	}
22135	return false;
22136}
22137
22138bool isVFPCLASSSS(unsigned Opcode) {
22139	switch (Opcode) {
22140	case VFPCLASSSSZrm:
22141	case VFPCLASSSSZrmk:
22142	case VFPCLASSSSZrr:
22143	case VFPCLASSSSZrrk:
22144		return true;
22145	}
22146	return false;
22147}
22148
22149bool isVMOVDQA64(unsigned Opcode) {
22150	switch (Opcode) {
22151	case VMOVDQA64Z128mr:
22152	case VMOVDQA64Z128mrk:
22153	case VMOVDQA64Z128rm:
22154	case VMOVDQA64Z128rmk:
22155	case VMOVDQA64Z128rmkz:
22156	case VMOVDQA64Z128rr:
22157	case VMOVDQA64Z128rr_REV:
22158	case VMOVDQA64Z128rrk:
22159	case VMOVDQA64Z128rrk_REV:
22160	case VMOVDQA64Z128rrkz:
22161	case VMOVDQA64Z128rrkz_REV:
22162	case VMOVDQA64Z256mr:
22163	case VMOVDQA64Z256mrk:
22164	case VMOVDQA64Z256rm:
22165	case VMOVDQA64Z256rmk:
22166	case VMOVDQA64Z256rmkz:
22167	case VMOVDQA64Z256rr:
22168	case VMOVDQA64Z256rr_REV:
22169	case VMOVDQA64Z256rrk:
22170	case VMOVDQA64Z256rrk_REV:
22171	case VMOVDQA64Z256rrkz:
22172	case VMOVDQA64Z256rrkz_REV:
22173	case VMOVDQA64Zmr:
22174	case VMOVDQA64Zmrk:
22175	case VMOVDQA64Zrm:
22176	case VMOVDQA64Zrmk:
22177	case VMOVDQA64Zrmkz:
22178	case VMOVDQA64Zrr:
22179	case VMOVDQA64Zrr_REV:
22180	case VMOVDQA64Zrrk:
22181	case VMOVDQA64Zrrk_REV:
22182	case VMOVDQA64Zrrkz:
22183	case VMOVDQA64Zrrkz_REV:
22184		return true;
22185	}
22186	return false;
22187}
22188
22189bool isSUB(unsigned Opcode) {
22190	switch (Opcode) {
22191	case SUB16i16:
22192	case SUB16mi:
22193	case SUB16mi8:
22194	case SUB16mr:
22195	case SUB16ri:
22196	case SUB16ri8:
22197	case SUB16rm:
22198	case SUB16rr:
22199	case SUB16rr_REV:
22200	case SUB32i32:
22201	case SUB32mi:
22202	case SUB32mi8:
22203	case SUB32mr:
22204	case SUB32ri:
22205	case SUB32ri8:
22206	case SUB32rm:
22207	case SUB32rr:
22208	case SUB32rr_REV:
22209	case SUB64i32:
22210	case SUB64mi32:
22211	case SUB64mi8:
22212	case SUB64mr:
22213	case SUB64ri32:
22214	case SUB64ri8:
22215	case SUB64rm:
22216	case SUB64rr:
22217	case SUB64rr_REV:
22218	case SUB8i8:
22219	case SUB8mi:
22220	case SUB8mi8:
22221	case SUB8mr:
22222	case SUB8ri:
22223	case SUB8ri8:
22224	case SUB8rm:
22225	case SUB8rr:
22226	case SUB8rr_REV:
22227		return true;
22228	}
22229	return false;
22230}
22231
22232bool isVUCOMISD(unsigned Opcode) {
22233	switch (Opcode) {
22234	case VUCOMISDZrm:
22235	case VUCOMISDZrr:
22236	case VUCOMISDZrrb:
22237	case VUCOMISDrm:
22238	case VUCOMISDrr:
22239		return true;
22240	}
22241	return false;
22242}
22243
22244bool isVCVTPD2PS(unsigned Opcode) {
22245	switch (Opcode) {
22246	case VCVTPD2PSYrm:
22247	case VCVTPD2PSYrr:
22248	case VCVTPD2PSZ128rm:
22249	case VCVTPD2PSZ128rmb:
22250	case VCVTPD2PSZ128rmbk:
22251	case VCVTPD2PSZ128rmbkz:
22252	case VCVTPD2PSZ128rmk:
22253	case VCVTPD2PSZ128rmkz:
22254	case VCVTPD2PSZ128rr:
22255	case VCVTPD2PSZ128rrk:
22256	case VCVTPD2PSZ128rrkz:
22257	case VCVTPD2PSZ256rm:
22258	case VCVTPD2PSZ256rmb:
22259	case VCVTPD2PSZ256rmbk:
22260	case VCVTPD2PSZ256rmbkz:
22261	case VCVTPD2PSZ256rmk:
22262	case VCVTPD2PSZ256rmkz:
22263	case VCVTPD2PSZ256rr:
22264	case VCVTPD2PSZ256rrk:
22265	case VCVTPD2PSZ256rrkz:
22266	case VCVTPD2PSZrm:
22267	case VCVTPD2PSZrmb:
22268	case VCVTPD2PSZrmbk:
22269	case VCVTPD2PSZrmbkz:
22270	case VCVTPD2PSZrmk:
22271	case VCVTPD2PSZrmkz:
22272	case VCVTPD2PSZrr:
22273	case VCVTPD2PSZrrb:
22274	case VCVTPD2PSZrrbk:
22275	case VCVTPD2PSZrrbkz:
22276	case VCVTPD2PSZrrk:
22277	case VCVTPD2PSZrrkz:
22278	case VCVTPD2PSrm:
22279	case VCVTPD2PSrr:
22280		return true;
22281	}
22282	return false;
22283}
22284
22285bool isLEAVE(unsigned Opcode) {
22286	switch (Opcode) {
22287	case LEAVE:
22288	case LEAVE64:
22289		return true;
22290	}
22291	return false;
22292}
22293
22294bool isOUTSB(unsigned Opcode) {
22295	return Opcode == OUTSB;
22296}
22297
22298bool isOUTSD(unsigned Opcode) {
22299	return Opcode == OUTSL;
22300}
22301
22302bool isVUCOMISH(unsigned Opcode) {
22303	switch (Opcode) {
22304	case VUCOMISHZrm:
22305	case VUCOMISHZrr:
22306	case VUCOMISHZrrb:
22307		return true;
22308	}
22309	return false;
22310}
22311
22312bool isEXTRQ(unsigned Opcode) {
22313	switch (Opcode) {
22314	case EXTRQ:
22315	case EXTRQI:
22316		return true;
22317	}
22318	return false;
22319}
22320
22321bool isVUCOMISS(unsigned Opcode) {
22322	switch (Opcode) {
22323	case VUCOMISSZrm:
22324	case VUCOMISSZrr:
22325	case VUCOMISSZrrb:
22326	case VUCOMISSrm:
22327	case VUCOMISSrr:
22328		return true;
22329	}
22330	return false;
22331}
22332
22333bool isCVTTPD2PI(unsigned Opcode) {
22334	switch (Opcode) {
22335	case MMX_CVTTPD2PIrm:
22336	case MMX_CVTTPD2PIrr:
22337		return true;
22338	}
22339	return false;
22340}
22341
22342bool isOUTSW(unsigned Opcode) {
22343	return Opcode == OUTSW;
22344}
22345
22346bool isLDS(unsigned Opcode) {
22347	switch (Opcode) {
22348	case LDS16rm:
22349	case LDS32rm:
22350		return true;
22351	}
22352	return false;
22353}
22354
22355bool isPSHUFHW(unsigned Opcode) {
22356	switch (Opcode) {
22357	case PSHUFHWmi:
22358	case PSHUFHWri:
22359		return true;
22360	}
22361	return false;
22362}
22363
22364bool isPHSUBD(unsigned Opcode) {
22365	switch (Opcode) {
22366	case MMX_PHSUBDrm:
22367	case MMX_PHSUBDrr:
22368	case PHSUBDrm:
22369	case PHSUBDrr:
22370		return true;
22371	}
22372	return false;
22373}
22374
22375bool isHLT(unsigned Opcode) {
22376	return Opcode == HLT;
22377}
22378
22379bool isVCVTPD2QQ(unsigned Opcode) {
22380	switch (Opcode) {
22381	case VCVTPD2QQZ128rm:
22382	case VCVTPD2QQZ128rmb:
22383	case VCVTPD2QQZ128rmbk:
22384	case VCVTPD2QQZ128rmbkz:
22385	case VCVTPD2QQZ128rmk:
22386	case VCVTPD2QQZ128rmkz:
22387	case VCVTPD2QQZ128rr:
22388	case VCVTPD2QQZ128rrk:
22389	case VCVTPD2QQZ128rrkz:
22390	case VCVTPD2QQZ256rm:
22391	case VCVTPD2QQZ256rmb:
22392	case VCVTPD2QQZ256rmbk:
22393	case VCVTPD2QQZ256rmbkz:
22394	case VCVTPD2QQZ256rmk:
22395	case VCVTPD2QQZ256rmkz:
22396	case VCVTPD2QQZ256rr:
22397	case VCVTPD2QQZ256rrk:
22398	case VCVTPD2QQZ256rrkz:
22399	case VCVTPD2QQZrm:
22400	case VCVTPD2QQZrmb:
22401	case VCVTPD2QQZrmbk:
22402	case VCVTPD2QQZrmbkz:
22403	case VCVTPD2QQZrmk:
22404	case VCVTPD2QQZrmkz:
22405	case VCVTPD2QQZrr:
22406	case VCVTPD2QQZrrb:
22407	case VCVTPD2QQZrrbk:
22408	case VCVTPD2QQZrrbkz:
22409	case VCVTPD2QQZrrk:
22410	case VCVTPD2QQZrrkz:
22411		return true;
22412	}
22413	return false;
22414}
22415
22416bool isLIDT(unsigned Opcode) {
22417	return Opcode == LIDT64m;
22418}
22419
22420bool isVPTERNLOGD(unsigned Opcode) {
22421	switch (Opcode) {
22422	case VPTERNLOGDZ128rmbi:
22423	case VPTERNLOGDZ128rmbik:
22424	case VPTERNLOGDZ128rmbikz:
22425	case VPTERNLOGDZ128rmi:
22426	case VPTERNLOGDZ128rmik:
22427	case VPTERNLOGDZ128rmikz:
22428	case VPTERNLOGDZ128rri:
22429	case VPTERNLOGDZ128rrik:
22430	case VPTERNLOGDZ128rrikz:
22431	case VPTERNLOGDZ256rmbi:
22432	case VPTERNLOGDZ256rmbik:
22433	case VPTERNLOGDZ256rmbikz:
22434	case VPTERNLOGDZ256rmi:
22435	case VPTERNLOGDZ256rmik:
22436	case VPTERNLOGDZ256rmikz:
22437	case VPTERNLOGDZ256rri:
22438	case VPTERNLOGDZ256rrik:
22439	case VPTERNLOGDZ256rrikz:
22440	case VPTERNLOGDZrmbi:
22441	case VPTERNLOGDZrmbik:
22442	case VPTERNLOGDZrmbikz:
22443	case VPTERNLOGDZrmi:
22444	case VPTERNLOGDZrmik:
22445	case VPTERNLOGDZrmikz:
22446	case VPTERNLOGDZrri:
22447	case VPTERNLOGDZrrik:
22448	case VPTERNLOGDZrrikz:
22449		return true;
22450	}
22451	return false;
22452}
22453
22454bool isLEA(unsigned Opcode) {
22455	switch (Opcode) {
22456	case LEA16r:
22457	case LEA32r:
22458	case LEA64_32r:
22459	case LEA64r:
22460		return true;
22461	}
22462	return false;
22463}
22464
22465bool isVPHADDWD(unsigned Opcode) {
22466	switch (Opcode) {
22467	case VPHADDWDrm:
22468	case VPHADDWDrr:
22469		return true;
22470	}
22471	return false;
22472}
22473
22474bool isPREFETCHNTA(unsigned Opcode) {
22475	return Opcode == PREFETCHNTA;
22476}
22477
22478bool isVPTERNLOGQ(unsigned Opcode) {
22479	switch (Opcode) {
22480	case VPTERNLOGQZ128rmbi:
22481	case VPTERNLOGQZ128rmbik:
22482	case VPTERNLOGQZ128rmbikz:
22483	case VPTERNLOGQZ128rmi:
22484	case VPTERNLOGQZ128rmik:
22485	case VPTERNLOGQZ128rmikz:
22486	case VPTERNLOGQZ128rri:
22487	case VPTERNLOGQZ128rrik:
22488	case VPTERNLOGQZ128rrikz:
22489	case VPTERNLOGQZ256rmbi:
22490	case VPTERNLOGQZ256rmbik:
22491	case VPTERNLOGQZ256rmbikz:
22492	case VPTERNLOGQZ256rmi:
22493	case VPTERNLOGQZ256rmik:
22494	case VPTERNLOGQZ256rmikz:
22495	case VPTERNLOGQZ256rri:
22496	case VPTERNLOGQZ256rrik:
22497	case VPTERNLOGQZ256rrikz:
22498	case VPTERNLOGQZrmbi:
22499	case VPTERNLOGQZrmbik:
22500	case VPTERNLOGQZrmbikz:
22501	case VPTERNLOGQZrmi:
22502	case VPTERNLOGQZrmik:
22503	case VPTERNLOGQZrmikz:
22504	case VPTERNLOGQZrri:
22505	case VPTERNLOGQZrrik:
22506	case VPTERNLOGQZrrikz:
22507		return true;
22508	}
22509	return false;
22510}
22511
22512bool isKSHIFTLB(unsigned Opcode) {
22513	return Opcode == KSHIFTLBri;
22514}
22515
22516bool isKSHIFTLD(unsigned Opcode) {
22517	return Opcode == KSHIFTLDri;
22518}
22519
22520bool isPHSUBW(unsigned Opcode) {
22521	switch (Opcode) {
22522	case MMX_PHSUBWrm:
22523	case MMX_PHSUBWrr:
22524	case PHSUBWrm:
22525	case PHSUBWrr:
22526		return true;
22527	}
22528	return false;
22529}
22530
22531bool isVPMOVSQB(unsigned Opcode) {
22532	switch (Opcode) {
22533	case VPMOVSQBZ128mr:
22534	case VPMOVSQBZ128mrk:
22535	case VPMOVSQBZ128rr:
22536	case VPMOVSQBZ128rrk:
22537	case VPMOVSQBZ128rrkz:
22538	case VPMOVSQBZ256mr:
22539	case VPMOVSQBZ256mrk:
22540	case VPMOVSQBZ256rr:
22541	case VPMOVSQBZ256rrk:
22542	case VPMOVSQBZ256rrkz:
22543	case VPMOVSQBZmr:
22544	case VPMOVSQBZmrk:
22545	case VPMOVSQBZrr:
22546	case VPMOVSQBZrrk:
22547	case VPMOVSQBZrrkz:
22548		return true;
22549	}
22550	return false;
22551}
22552
22553bool isVPHADDWQ(unsigned Opcode) {
22554	switch (Opcode) {
22555	case VPHADDWQrm:
22556	case VPHADDWQrr:
22557		return true;
22558	}
22559	return false;
22560}
22561
22562bool isVCVTTSS2USI(unsigned Opcode) {
22563	switch (Opcode) {
22564	case VCVTTSS2USI64Zrm_Int:
22565	case VCVTTSS2USI64Zrr_Int:
22566	case VCVTTSS2USI64Zrrb_Int:
22567	case VCVTTSS2USIZrm_Int:
22568	case VCVTTSS2USIZrr_Int:
22569	case VCVTTSS2USIZrrb_Int:
22570		return true;
22571	}
22572	return false;
22573}
22574
22575bool isVPMOVSQD(unsigned Opcode) {
22576	switch (Opcode) {
22577	case VPMOVSQDZ128mr:
22578	case VPMOVSQDZ128mrk:
22579	case VPMOVSQDZ128rr:
22580	case VPMOVSQDZ128rrk:
22581	case VPMOVSQDZ128rrkz:
22582	case VPMOVSQDZ256mr:
22583	case VPMOVSQDZ256mrk:
22584	case VPMOVSQDZ256rr:
22585	case VPMOVSQDZ256rrk:
22586	case VPMOVSQDZ256rrkz:
22587	case VPMOVSQDZmr:
22588	case VPMOVSQDZmrk:
22589	case VPMOVSQDZrr:
22590	case VPMOVSQDZrrk:
22591	case VPMOVSQDZrrkz:
22592		return true;
22593	}
22594	return false;
22595}
22596
22597bool isLES(unsigned Opcode) {
22598	switch (Opcode) {
22599	case LES16rm:
22600	case LES32rm:
22601		return true;
22602	}
22603	return false;
22604}
22605
22606bool isVMPSADBW(unsigned Opcode) {
22607	switch (Opcode) {
22608	case VMPSADBWYrmi:
22609	case VMPSADBWYrri:
22610	case VMPSADBWrmi:
22611	case VMPSADBWrri:
22612		return true;
22613	}
22614	return false;
22615}
22616
22617bool isKSHIFTLQ(unsigned Opcode) {
22618	return Opcode == KSHIFTLQri;
22619}
22620
22621bool isADDSUBPD(unsigned Opcode) {
22622	switch (Opcode) {
22623	case ADDSUBPDrm:
22624	case ADDSUBPDrr:
22625		return true;
22626	}
22627	return false;
22628}
22629
22630bool isKSHIFTLW(unsigned Opcode) {
22631	return Opcode == KSHIFTLWri;
22632}
22633
22634bool isXSAVE64(unsigned Opcode) {
22635	return Opcode == XSAVE64;
22636}
22637
22638bool isVPMOVSQW(unsigned Opcode) {
22639	switch (Opcode) {
22640	case VPMOVSQWZ128mr:
22641	case VPMOVSQWZ128mrk:
22642	case VPMOVSQWZ128rr:
22643	case VPMOVSQWZ128rrk:
22644	case VPMOVSQWZ128rrkz:
22645	case VPMOVSQWZ256mr:
22646	case VPMOVSQWZ256mrk:
22647	case VPMOVSQWZ256rr:
22648	case VPMOVSQWZ256rrk:
22649	case VPMOVSQWZ256rrkz:
22650	case VPMOVSQWZmr:
22651	case VPMOVSQWZmrk:
22652	case VPMOVSQWZrr:
22653	case VPMOVSQWZrrk:
22654	case VPMOVSQWZrrkz:
22655		return true;
22656	}
22657	return false;
22658}
22659
22660bool isADDSUBPS(unsigned Opcode) {
22661	switch (Opcode) {
22662	case ADDSUBPSrm:
22663	case ADDSUBPSrr:
22664		return true;
22665	}
22666	return false;
22667}
22668
22669bool isENQCMD(unsigned Opcode) {
22670	switch (Opcode) {
22671	case ENQCMD16:
22672	case ENQCMD32:
22673	case ENQCMD64:
22674		return true;
22675	}
22676	return false;
22677}
22678
22679bool isVCVTTPH2W(unsigned Opcode) {
22680	switch (Opcode) {
22681	case VCVTTPH2WZ128rm:
22682	case VCVTTPH2WZ128rmb:
22683	case VCVTTPH2WZ128rmbk:
22684	case VCVTTPH2WZ128rmbkz:
22685	case VCVTTPH2WZ128rmk:
22686	case VCVTTPH2WZ128rmkz:
22687	case VCVTTPH2WZ128rr:
22688	case VCVTTPH2WZ128rrk:
22689	case VCVTTPH2WZ128rrkz:
22690	case VCVTTPH2WZ256rm:
22691	case VCVTTPH2WZ256rmb:
22692	case VCVTTPH2WZ256rmbk:
22693	case VCVTTPH2WZ256rmbkz:
22694	case VCVTTPH2WZ256rmk:
22695	case VCVTTPH2WZ256rmkz:
22696	case VCVTTPH2WZ256rr:
22697	case VCVTTPH2WZ256rrk:
22698	case VCVTTPH2WZ256rrkz:
22699	case VCVTTPH2WZrm:
22700	case VCVTTPH2WZrmb:
22701	case VCVTTPH2WZrmbk:
22702	case VCVTTPH2WZrmbkz:
22703	case VCVTTPH2WZrmk:
22704	case VCVTTPH2WZrmkz:
22705	case VCVTTPH2WZrr:
22706	case VCVTTPH2WZrrb:
22707	case VCVTTPH2WZrrbk:
22708	case VCVTTPH2WZrrbkz:
22709	case VCVTTPH2WZrrk:
22710	case VCVTTPH2WZrrkz:
22711		return true;
22712	}
22713	return false;
22714}
22715
22716bool isVMRUN(unsigned Opcode) {
22717	switch (Opcode) {
22718	case VMRUN32:
22719	case VMRUN64:
22720		return true;
22721	}
22722	return false;
22723}
22724
22725bool isWRFSBASE(unsigned Opcode) {
22726	switch (Opcode) {
22727	case WRFSBASE:
22728	case WRFSBASE64:
22729		return true;
22730	}
22731	return false;
22732}
22733
22734bool isCOMISD(unsigned Opcode) {
22735	switch (Opcode) {
22736	case COMISDrm:
22737	case COMISDrr:
22738		return true;
22739	}
22740	return false;
22741}
22742
22743bool isLFS(unsigned Opcode) {
22744	switch (Opcode) {
22745	case LFS16rm:
22746	case LFS32rm:
22747	case LFS64rm:
22748		return true;
22749	}
22750	return false;
22751}
22752
22753bool isSTOSB(unsigned Opcode) {
22754	return Opcode == STOSB;
22755}
22756
22757bool isSTOSD(unsigned Opcode) {
22758	return Opcode == STOSL;
22759}
22760
22761bool isCOMISS(unsigned Opcode) {
22762	switch (Opcode) {
22763	case COMISSrm:
22764	case COMISSrr:
22765		return true;
22766	}
22767	return false;
22768}
22769
22770bool isVZEROALL(unsigned Opcode) {
22771	return Opcode == VZEROALL;
22772}
22773
22774bool isVFMADDSUBPD(unsigned Opcode) {
22775	switch (Opcode) {
22776	case VFMADDSUBPD4Ymr:
22777	case VFMADDSUBPD4Yrm:
22778	case VFMADDSUBPD4Yrr:
22779	case VFMADDSUBPD4Yrr_REV:
22780	case VFMADDSUBPD4mr:
22781	case VFMADDSUBPD4rm:
22782	case VFMADDSUBPD4rr:
22783	case VFMADDSUBPD4rr_REV:
22784		return true;
22785	}
22786	return false;
22787}
22788
22789bool isVEXTRACTPS(unsigned Opcode) {
22790	switch (Opcode) {
22791	case VEXTRACTPSZmr:
22792	case VEXTRACTPSZrr:
22793	case VEXTRACTPSmr:
22794	case VEXTRACTPSrr:
22795		return true;
22796	}
22797	return false;
22798}
22799
22800bool isKADDB(unsigned Opcode) {
22801	return Opcode == KADDBrr;
22802}
22803
22804bool isKADDD(unsigned Opcode) {
22805	return Opcode == KADDDrr;
22806}
22807
22808bool isXTEST(unsigned Opcode) {
22809	return Opcode == XTEST;
22810}
22811
22812bool isFISTTP(unsigned Opcode) {
22813	switch (Opcode) {
22814	case ISTT_FP16m:
22815	case ISTT_FP32m:
22816	case ISTT_FP64m:
22817		return true;
22818	}
22819	return false;
22820}
22821
22822bool isSTOSQ(unsigned Opcode) {
22823	return Opcode == STOSQ;
22824}
22825
22826bool isJCXZ(unsigned Opcode) {
22827	return Opcode == JCXZ;
22828}
22829
22830bool isSTOSW(unsigned Opcode) {
22831	return Opcode == STOSW;
22832}
22833
22834bool isVFMADDSUBPS(unsigned Opcode) {
22835	switch (Opcode) {
22836	case VFMADDSUBPS4Ymr:
22837	case VFMADDSUBPS4Yrm:
22838	case VFMADDSUBPS4Yrr:
22839	case VFMADDSUBPS4Yrr_REV:
22840	case VFMADDSUBPS4mr:
22841	case VFMADDSUBPS4rm:
22842	case VFMADDSUBPS4rr:
22843	case VFMADDSUBPS4rr_REV:
22844		return true;
22845	}
22846	return false;
22847}
22848
22849bool isVPSHAB(unsigned Opcode) {
22850	switch (Opcode) {
22851	case VPSHABmr:
22852	case VPSHABrm:
22853	case VPSHABrr:
22854	case VPSHABrr_REV:
22855		return true;
22856	}
22857	return false;
22858}
22859
22860bool isKADDQ(unsigned Opcode) {
22861	return Opcode == KADDQrr;
22862}
22863
22864bool isLGS(unsigned Opcode) {
22865	switch (Opcode) {
22866	case LGS16rm:
22867	case LGS32rm:
22868	case LGS64rm:
22869		return true;
22870	}
22871	return false;
22872}
22873
22874bool isVPMACSDQH(unsigned Opcode) {
22875	switch (Opcode) {
22876	case VPMACSDQHrm:
22877	case VPMACSDQHrr:
22878		return true;
22879	}
22880	return false;
22881}
22882
22883bool isMOVDQA(unsigned Opcode) {
22884	switch (Opcode) {
22885	case MOVDQAmr:
22886	case MOVDQArm:
22887	case MOVDQArr:
22888	case MOVDQArr_REV:
22889		return true;
22890	}
22891	return false;
22892}
22893
22894bool isVPSHAD(unsigned Opcode) {
22895	switch (Opcode) {
22896	case VPSHADmr:
22897	case VPSHADrm:
22898	case VPSHADrr:
22899	case VPSHADrr_REV:
22900		return true;
22901	}
22902	return false;
22903}
22904
22905bool isKADDW(unsigned Opcode) {
22906	return Opcode == KADDWrr;
22907}
22908
22909bool isPSMASH(unsigned Opcode) {
22910	return Opcode == PSMASH;
22911}
22912
22913bool isPBLENDVB(unsigned Opcode) {
22914	switch (Opcode) {
22915	case PBLENDVBrm0:
22916	case PBLENDVBrr0:
22917		return true;
22918	}
22919	return false;
22920}
22921
22922bool isVPMACSDQL(unsigned Opcode) {
22923	switch (Opcode) {
22924	case VPMACSDQLrm:
22925	case VPMACSDQLrr:
22926		return true;
22927	}
22928	return false;
22929}
22930
22931bool isVPHSUBBW(unsigned Opcode) {
22932	switch (Opcode) {
22933	case VPHSUBBWrm:
22934	case VPHSUBBWrr:
22935		return true;
22936	}
22937	return false;
22938}
22939
22940bool isVPSHAQ(unsigned Opcode) {
22941	switch (Opcode) {
22942	case VPSHAQmr:
22943	case VPSHAQrm:
22944	case VPSHAQrr:
22945	case VPSHAQrr_REV:
22946		return true;
22947	}
22948	return false;
22949}
22950
22951bool isVSQRTPD(unsigned Opcode) {
22952	switch (Opcode) {
22953	case VSQRTPDYm:
22954	case VSQRTPDYr:
22955	case VSQRTPDZ128m:
22956	case VSQRTPDZ128mb:
22957	case VSQRTPDZ128mbk:
22958	case VSQRTPDZ128mbkz:
22959	case VSQRTPDZ128mk:
22960	case VSQRTPDZ128mkz:
22961	case VSQRTPDZ128r:
22962	case VSQRTPDZ128rk:
22963	case VSQRTPDZ128rkz:
22964	case VSQRTPDZ256m:
22965	case VSQRTPDZ256mb:
22966	case VSQRTPDZ256mbk:
22967	case VSQRTPDZ256mbkz:
22968	case VSQRTPDZ256mk:
22969	case VSQRTPDZ256mkz:
22970	case VSQRTPDZ256r:
22971	case VSQRTPDZ256rk:
22972	case VSQRTPDZ256rkz:
22973	case VSQRTPDZm:
22974	case VSQRTPDZmb:
22975	case VSQRTPDZmbk:
22976	case VSQRTPDZmbkz:
22977	case VSQRTPDZmk:
22978	case VSQRTPDZmkz:
22979	case VSQRTPDZr:
22980	case VSQRTPDZrb:
22981	case VSQRTPDZrbk:
22982	case VSQRTPDZrbkz:
22983	case VSQRTPDZrk:
22984	case VSQRTPDZrkz:
22985	case VSQRTPDm:
22986	case VSQRTPDr:
22987		return true;
22988	}
22989	return false;
22990}
22991
22992bool isCLRSSBSY(unsigned Opcode) {
22993	return Opcode == CLRSSBSY;
22994}
22995
22996bool isMINPD(unsigned Opcode) {
22997	switch (Opcode) {
22998	case MINPDrm:
22999	case MINPDrr:
23000		return true;
23001	}
23002	return false;
23003}
23004
23005bool isVPSHAW(unsigned Opcode) {
23006	switch (Opcode) {
23007	case VPSHAWmr:
23008	case VPSHAWrm:
23009	case VPSHAWrr:
23010	case VPSHAWrr_REV:
23011		return true;
23012	}
23013	return false;
23014}
23015
23016bool isVSQRTPH(unsigned Opcode) {
23017	switch (Opcode) {
23018	case VSQRTPHZ128m:
23019	case VSQRTPHZ128mb:
23020	case VSQRTPHZ128mbk:
23021	case VSQRTPHZ128mbkz:
23022	case VSQRTPHZ128mk:
23023	case VSQRTPHZ128mkz:
23024	case VSQRTPHZ128r:
23025	case VSQRTPHZ128rk:
23026	case VSQRTPHZ128rkz:
23027	case VSQRTPHZ256m:
23028	case VSQRTPHZ256mb:
23029	case VSQRTPHZ256mbk:
23030	case VSQRTPHZ256mbkz:
23031	case VSQRTPHZ256mk:
23032	case VSQRTPHZ256mkz:
23033	case VSQRTPHZ256r:
23034	case VSQRTPHZ256rk:
23035	case VSQRTPHZ256rkz:
23036	case VSQRTPHZm:
23037	case VSQRTPHZmb:
23038	case VSQRTPHZmbk:
23039	case VSQRTPHZmbkz:
23040	case VSQRTPHZmk:
23041	case VSQRTPHZmkz:
23042	case VSQRTPHZr:
23043	case VSQRTPHZrb:
23044	case VSQRTPHZrbk:
23045	case VSQRTPHZrbkz:
23046	case VSQRTPHZrk:
23047	case VSQRTPHZrkz:
23048		return true;
23049	}
23050	return false;
23051}
23052
23053bool isMOVDQU(unsigned Opcode) {
23054	switch (Opcode) {
23055	case MOVDQUmr:
23056	case MOVDQUrm:
23057	case MOVDQUrr:
23058	case MOVDQUrr_REV:
23059		return true;
23060	}
23061	return false;
23062}
23063
23064bool isVSQRTPS(unsigned Opcode) {
23065	switch (Opcode) {
23066	case VSQRTPSYm:
23067	case VSQRTPSYr:
23068	case VSQRTPSZ128m:
23069	case VSQRTPSZ128mb:
23070	case VSQRTPSZ128mbk:
23071	case VSQRTPSZ128mbkz:
23072	case VSQRTPSZ128mk:
23073	case VSQRTPSZ128mkz:
23074	case VSQRTPSZ128r:
23075	case VSQRTPSZ128rk:
23076	case VSQRTPSZ128rkz:
23077	case VSQRTPSZ256m:
23078	case VSQRTPSZ256mb:
23079	case VSQRTPSZ256mbk:
23080	case VSQRTPSZ256mbkz:
23081	case VSQRTPSZ256mk:
23082	case VSQRTPSZ256mkz:
23083	case VSQRTPSZ256r:
23084	case VSQRTPSZ256rk:
23085	case VSQRTPSZ256rkz:
23086	case VSQRTPSZm:
23087	case VSQRTPSZmb:
23088	case VSQRTPSZmbk:
23089	case VSQRTPSZmbkz:
23090	case VSQRTPSZmk:
23091	case VSQRTPSZmkz:
23092	case VSQRTPSZr:
23093	case VSQRTPSZrb:
23094	case VSQRTPSZrbk:
23095	case VSQRTPSZrbkz:
23096	case VSQRTPSZrk:
23097	case VSQRTPSZrkz:
23098	case VSQRTPSm:
23099	case VSQRTPSr:
23100		return true;
23101	}
23102	return false;
23103}
23104
23105bool isVPSUBSB(unsigned Opcode) {
23106	switch (Opcode) {
23107	case VPSUBSBYrm:
23108	case VPSUBSBYrr:
23109	case VPSUBSBZ128rm:
23110	case VPSUBSBZ128rmk:
23111	case VPSUBSBZ128rmkz:
23112	case VPSUBSBZ128rr:
23113	case VPSUBSBZ128rrk:
23114	case VPSUBSBZ128rrkz:
23115	case VPSUBSBZ256rm:
23116	case VPSUBSBZ256rmk:
23117	case VPSUBSBZ256rmkz:
23118	case VPSUBSBZ256rr:
23119	case VPSUBSBZ256rrk:
23120	case VPSUBSBZ256rrkz:
23121	case VPSUBSBZrm:
23122	case VPSUBSBZrmk:
23123	case VPSUBSBZrmkz:
23124	case VPSUBSBZrr:
23125	case VPSUBSBZrrk:
23126	case VPSUBSBZrrkz:
23127	case VPSUBSBrm:
23128	case VPSUBSBrr:
23129		return true;
23130	}
23131	return false;
23132}
23133
23134bool isMULX(unsigned Opcode) {
23135	switch (Opcode) {
23136	case MULX32rm:
23137	case MULX32rr:
23138	case MULX64rm:
23139	case MULX64rr:
23140		return true;
23141	}
23142	return false;
23143}
23144
23145bool isMINPS(unsigned Opcode) {
23146	switch (Opcode) {
23147	case MINPSrm:
23148	case MINPSrr:
23149		return true;
23150	}
23151	return false;
23152}
23153
23154bool isPSHUFLW(unsigned Opcode) {
23155	switch (Opcode) {
23156	case PSHUFLWmi:
23157	case PSHUFLWri:
23158		return true;
23159	}
23160	return false;
23161}
23162
23163bool isVEXTRACTF64X2(unsigned Opcode) {
23164	switch (Opcode) {
23165	case VEXTRACTF64x2Z256mr:
23166	case VEXTRACTF64x2Z256mrk:
23167	case VEXTRACTF64x2Z256rr:
23168	case VEXTRACTF64x2Z256rrk:
23169	case VEXTRACTF64x2Z256rrkz:
23170	case VEXTRACTF64x2Zmr:
23171	case VEXTRACTF64x2Zmrk:
23172	case VEXTRACTF64x2Zrr:
23173	case VEXTRACTF64x2Zrrk:
23174	case VEXTRACTF64x2Zrrkz:
23175		return true;
23176	}
23177	return false;
23178}
23179
23180bool isVEXTRACTF64X4(unsigned Opcode) {
23181	switch (Opcode) {
23182	case VEXTRACTF64x4Zmr:
23183	case VEXTRACTF64x4Zmrk:
23184	case VEXTRACTF64x4Zrr:
23185	case VEXTRACTF64x4Zrrk:
23186	case VEXTRACTF64x4Zrrkz:
23187		return true;
23188	}
23189	return false;
23190}
23191
23192bool isVCVTTSD2USI(unsigned Opcode) {
23193	switch (Opcode) {
23194	case VCVTTSD2USI64Zrm_Int:
23195	case VCVTTSD2USI64Zrr_Int:
23196	case VCVTTSD2USI64Zrrb_Int:
23197	case VCVTTSD2USIZrm_Int:
23198	case VCVTTSD2USIZrr_Int:
23199	case VCVTTSD2USIZrrb_Int:
23200		return true;
23201	}
23202	return false;
23203}
23204
23205bool isINCSSPD(unsigned Opcode) {
23206	return Opcode == INCSSPD;
23207}
23208
23209bool isVPSIGNB(unsigned Opcode) {
23210	switch (Opcode) {
23211	case VPSIGNBYrm:
23212	case VPSIGNBYrr:
23213	case VPSIGNBrm:
23214	case VPSIGNBrr:
23215		return true;
23216	}
23217	return false;
23218}
23219
23220bool isVPSUBSW(unsigned Opcode) {
23221	switch (Opcode) {
23222	case VPSUBSWYrm:
23223	case VPSUBSWYrr:
23224	case VPSUBSWZ128rm:
23225	case VPSUBSWZ128rmk:
23226	case VPSUBSWZ128rmkz:
23227	case VPSUBSWZ128rr:
23228	case VPSUBSWZ128rrk:
23229	case VPSUBSWZ128rrkz:
23230	case VPSUBSWZ256rm:
23231	case VPSUBSWZ256rmk:
23232	case VPSUBSWZ256rmkz:
23233	case VPSUBSWZ256rr:
23234	case VPSUBSWZ256rrk:
23235	case VPSUBSWZ256rrkz:
23236	case VPSUBSWZrm:
23237	case VPSUBSWZrmk:
23238	case VPSUBSWZrmkz:
23239	case VPSUBSWZrr:
23240	case VPSUBSWZrrk:
23241	case VPSUBSWZrrkz:
23242	case VPSUBSWrm:
23243	case VPSUBSWrr:
23244		return true;
23245	}
23246	return false;
23247}
23248
23249bool isVPSIGND(unsigned Opcode) {
23250	switch (Opcode) {
23251	case VPSIGNDYrm:
23252	case VPSIGNDYrr:
23253	case VPSIGNDrm:
23254	case VPSIGNDrr:
23255		return true;
23256	}
23257	return false;
23258}
23259
23260bool isXSAVEOPT(unsigned Opcode) {
23261	return Opcode == XSAVEOPT;
23262}
23263
23264bool isVPMOVSXWD(unsigned Opcode) {
23265	switch (Opcode) {
23266	case VPMOVSXWDYrm:
23267	case VPMOVSXWDYrr:
23268	case VPMOVSXWDZ128rm:
23269	case VPMOVSXWDZ128rmk:
23270	case VPMOVSXWDZ128rmkz:
23271	case VPMOVSXWDZ128rr:
23272	case VPMOVSXWDZ128rrk:
23273	case VPMOVSXWDZ128rrkz:
23274	case VPMOVSXWDZ256rm:
23275	case VPMOVSXWDZ256rmk:
23276	case VPMOVSXWDZ256rmkz:
23277	case VPMOVSXWDZ256rr:
23278	case VPMOVSXWDZ256rrk:
23279	case VPMOVSXWDZ256rrkz:
23280	case VPMOVSXWDZrm:
23281	case VPMOVSXWDZrmk:
23282	case VPMOVSXWDZrmkz:
23283	case VPMOVSXWDZrr:
23284	case VPMOVSXWDZrrk:
23285	case VPMOVSXWDZrrkz:
23286	case VPMOVSXWDrm:
23287	case VPMOVSXWDrr:
23288		return true;
23289	}
23290	return false;
23291}
23292
23293bool isINCSSPQ(unsigned Opcode) {
23294	return Opcode == INCSSPQ;
23295}
23296
23297bool isGF2P8AFFINEQB(unsigned Opcode) {
23298	switch (Opcode) {
23299	case GF2P8AFFINEQBrmi:
23300	case GF2P8AFFINEQBrri:
23301		return true;
23302	}
23303	return false;
23304}
23305
23306bool isVPMOVSXWQ(unsigned Opcode) {
23307	switch (Opcode) {
23308	case VPMOVSXWQYrm:
23309	case VPMOVSXWQYrr:
23310	case VPMOVSXWQZ128rm:
23311	case VPMOVSXWQZ128rmk:
23312	case VPMOVSXWQZ128rmkz:
23313	case VPMOVSXWQZ128rr:
23314	case VPMOVSXWQZ128rrk:
23315	case VPMOVSXWQZ128rrkz:
23316	case VPMOVSXWQZ256rm:
23317	case VPMOVSXWQZ256rmk:
23318	case VPMOVSXWQZ256rmkz:
23319	case VPMOVSXWQZ256rr:
23320	case VPMOVSXWQZ256rrk:
23321	case VPMOVSXWQZ256rrkz:
23322	case VPMOVSXWQZrm:
23323	case VPMOVSXWQZrmk:
23324	case VPMOVSXWQZrmkz:
23325	case VPMOVSXWQZrr:
23326	case VPMOVSXWQZrrk:
23327	case VPMOVSXWQZrrkz:
23328	case VPMOVSXWQrm:
23329	case VPMOVSXWQrr:
23330		return true;
23331	}
23332	return false;
23333}
23334
23335bool isVPHSUBDQ(unsigned Opcode) {
23336	switch (Opcode) {
23337	case VPHSUBDQrm:
23338	case VPHSUBDQrr:
23339		return true;
23340	}
23341	return false;
23342}
23343
23344bool isVPSIGNW(unsigned Opcode) {
23345	switch (Opcode) {
23346	case VPSIGNWYrm:
23347	case VPSIGNWYrr:
23348	case VPSIGNWrm:
23349	case VPSIGNWrr:
23350		return true;
23351	}
23352	return false;
23353}
23354
23355bool isSGDTD(unsigned Opcode) {
23356	return Opcode == SGDT32m;
23357}
23358
23359bool isPUNPCKLWD(unsigned Opcode) {
23360	switch (Opcode) {
23361	case MMX_PUNPCKLWDrm:
23362	case MMX_PUNPCKLWDrr:
23363	case PUNPCKLWDrm:
23364	case PUNPCKLWDrr:
23365		return true;
23366	}
23367	return false;
23368}
23369
23370bool isVPPERM(unsigned Opcode) {
23371	switch (Opcode) {
23372	case VPPERMrmr:
23373	case VPPERMrrm:
23374	case VPPERMrrr:
23375	case VPPERMrrr_REV:
23376		return true;
23377	}
23378	return false;
23379}
23380
23381bool isAAA(unsigned Opcode) {
23382	return Opcode == AAA;
23383}
23384
23385bool isPAND(unsigned Opcode) {
23386	switch (Opcode) {
23387	case MMX_PANDrm:
23388	case MMX_PANDrr:
23389	case PANDrm:
23390	case PANDrr:
23391		return true;
23392	}
23393	return false;
23394}
23395
23396bool isVCVTPH2UQQ(unsigned Opcode) {
23397	switch (Opcode) {
23398	case VCVTPH2UQQZ128rm:
23399	case VCVTPH2UQQZ128rmb:
23400	case VCVTPH2UQQZ128rmbk:
23401	case VCVTPH2UQQZ128rmbkz:
23402	case VCVTPH2UQQZ128rmk:
23403	case VCVTPH2UQQZ128rmkz:
23404	case VCVTPH2UQQZ128rr:
23405	case VCVTPH2UQQZ128rrk:
23406	case VCVTPH2UQQZ128rrkz:
23407	case VCVTPH2UQQZ256rm:
23408	case VCVTPH2UQQZ256rmb:
23409	case VCVTPH2UQQZ256rmbk:
23410	case VCVTPH2UQQZ256rmbkz:
23411	case VCVTPH2UQQZ256rmk:
23412	case VCVTPH2UQQZ256rmkz:
23413	case VCVTPH2UQQZ256rr:
23414	case VCVTPH2UQQZ256rrk:
23415	case VCVTPH2UQQZ256rrkz:
23416	case VCVTPH2UQQZrm:
23417	case VCVTPH2UQQZrmb:
23418	case VCVTPH2UQQZrmbk:
23419	case VCVTPH2UQQZrmbkz:
23420	case VCVTPH2UQQZrmk:
23421	case VCVTPH2UQQZrmkz:
23422	case VCVTPH2UQQZrr:
23423	case VCVTPH2UQQZrrb:
23424	case VCVTPH2UQQZrrbk:
23425	case VCVTPH2UQQZrrbkz:
23426	case VCVTPH2UQQZrrk:
23427	case VCVTPH2UQQZrrkz:
23428		return true;
23429	}
23430	return false;
23431}
23432
23433bool isAAD(unsigned Opcode) {
23434	return Opcode == AAD8i8;
23435}
23436
23437bool isSGDTW(unsigned Opcode) {
23438	return Opcode == SGDT16m;
23439}
23440
23441bool isVPUNPCKHWD(unsigned Opcode) {
23442	switch (Opcode) {
23443	case VPUNPCKHWDYrm:
23444	case VPUNPCKHWDYrr:
23445	case VPUNPCKHWDZ128rm:
23446	case VPUNPCKHWDZ128rmk:
23447	case VPUNPCKHWDZ128rmkz:
23448	case VPUNPCKHWDZ128rr:
23449	case VPUNPCKHWDZ128rrk:
23450	case VPUNPCKHWDZ128rrkz:
23451	case VPUNPCKHWDZ256rm:
23452	case VPUNPCKHWDZ256rmk:
23453	case VPUNPCKHWDZ256rmkz:
23454	case VPUNPCKHWDZ256rr:
23455	case VPUNPCKHWDZ256rrk:
23456	case VPUNPCKHWDZ256rrkz:
23457	case VPUNPCKHWDZrm:
23458	case VPUNPCKHWDZrmk:
23459	case VPUNPCKHWDZrmkz:
23460	case VPUNPCKHWDZrr:
23461	case VPUNPCKHWDZrrk:
23462	case VPUNPCKHWDZrrkz:
23463	case VPUNPCKHWDrm:
23464	case VPUNPCKHWDrr:
23465		return true;
23466	}
23467	return false;
23468}
23469
23470bool isAAM(unsigned Opcode) {
23471	return Opcode == AAM8i8;
23472}
23473
23474bool isVCVTNEOPH2PS(unsigned Opcode) {
23475	switch (Opcode) {
23476	case VCVTNEOPH2PSYrm:
23477	case VCVTNEOPH2PSrm:
23478		return true;
23479	}
23480	return false;
23481}
23482
23483bool isAAS(unsigned Opcode) {
23484	return Opcode == AAS;
23485}
23486
23487bool isVSQRTSD(unsigned Opcode) {
23488	switch (Opcode) {
23489	case VSQRTSDZm_Int:
23490	case VSQRTSDZm_Intk:
23491	case VSQRTSDZm_Intkz:
23492	case VSQRTSDZr_Int:
23493	case VSQRTSDZr_Intk:
23494	case VSQRTSDZr_Intkz:
23495	case VSQRTSDZrb_Int:
23496	case VSQRTSDZrb_Intk:
23497	case VSQRTSDZrb_Intkz:
23498	case VSQRTSDm_Int:
23499	case VSQRTSDr_Int:
23500		return true;
23501	}
23502	return false;
23503}
23504
23505bool isBLCI(unsigned Opcode) {
23506	switch (Opcode) {
23507	case BLCI32rm:
23508	case BLCI32rr:
23509	case BLCI64rm:
23510	case BLCI64rr:
23511		return true;
23512	}
23513	return false;
23514}
23515
23516bool isMINSD(unsigned Opcode) {
23517	switch (Opcode) {
23518	case MINSDrm_Int:
23519	case MINSDrr_Int:
23520		return true;
23521	}
23522	return false;
23523}
23524
23525bool isVPSHUFBITQMB(unsigned Opcode) {
23526	switch (Opcode) {
23527	case VPSHUFBITQMBZ128rm:
23528	case VPSHUFBITQMBZ128rmk:
23529	case VPSHUFBITQMBZ128rr:
23530	case VPSHUFBITQMBZ128rrk:
23531	case VPSHUFBITQMBZ256rm:
23532	case VPSHUFBITQMBZ256rmk:
23533	case VPSHUFBITQMBZ256rr:
23534	case VPSHUFBITQMBZ256rrk:
23535	case VPSHUFBITQMBZrm:
23536	case VPSHUFBITQMBZrmk:
23537	case VPSHUFBITQMBZrr:
23538	case VPSHUFBITQMBZrrk:
23539		return true;
23540	}
23541	return false;
23542}
23543
23544bool isKSHIFTRB(unsigned Opcode) {
23545	return Opcode == KSHIFTRBri;
23546}
23547
23548bool isUMONITOR(unsigned Opcode) {
23549	switch (Opcode) {
23550	case UMONITOR16:
23551	case UMONITOR32:
23552	case UMONITOR64:
23553		return true;
23554	}
23555	return false;
23556}
23557
23558bool isKSHIFTRD(unsigned Opcode) {
23559	return Opcode == KSHIFTRDri;
23560}
23561
23562bool isFNCLEX(unsigned Opcode) {
23563	return Opcode == FNCLEX;
23564}
23565
23566bool isVSQRTSH(unsigned Opcode) {
23567	switch (Opcode) {
23568	case VSQRTSHZm_Int:
23569	case VSQRTSHZm_Intk:
23570	case VSQRTSHZm_Intkz:
23571	case VSQRTSHZr_Int:
23572	case VSQRTSHZr_Intk:
23573	case VSQRTSHZr_Intkz:
23574	case VSQRTSHZrb_Int:
23575	case VSQRTSHZrb_Intk:
23576	case VSQRTSHZrb_Intkz:
23577		return true;
23578	}
23579	return false;
23580}
23581
23582bool isBLCS(unsigned Opcode) {
23583	switch (Opcode) {
23584	case BLCS32rm:
23585	case BLCS32rr:
23586	case BLCS64rm:
23587	case BLCS64rr:
23588		return true;
23589	}
23590	return false;
23591}
23592
23593bool isVINSERTF64X2(unsigned Opcode) {
23594	switch (Opcode) {
23595	case VINSERTF64x2Z256rm:
23596	case VINSERTF64x2Z256rmk:
23597	case VINSERTF64x2Z256rmkz:
23598	case VINSERTF64x2Z256rr:
23599	case VINSERTF64x2Z256rrk:
23600	case VINSERTF64x2Z256rrkz:
23601	case VINSERTF64x2Zrm:
23602	case VINSERTF64x2Zrmk:
23603	case VINSERTF64x2Zrmkz:
23604	case VINSERTF64x2Zrr:
23605	case VINSERTF64x2Zrrk:
23606	case VINSERTF64x2Zrrkz:
23607		return true;
23608	}
23609	return false;
23610}
23611
23612bool isVSQRTSS(unsigned Opcode) {
23613	switch (Opcode) {
23614	case VSQRTSSZm_Int:
23615	case VSQRTSSZm_Intk:
23616	case VSQRTSSZm_Intkz:
23617	case VSQRTSSZr_Int:
23618	case VSQRTSSZr_Intk:
23619	case VSQRTSSZr_Intkz:
23620	case VSQRTSSZrb_Int:
23621	case VSQRTSSZrb_Intk:
23622	case VSQRTSSZrb_Intkz:
23623	case VSQRTSSm_Int:
23624	case VSQRTSSr_Int:
23625		return true;
23626	}
23627	return false;
23628}
23629
23630bool isVINSERTF64X4(unsigned Opcode) {
23631	switch (Opcode) {
23632	case VINSERTF64x4Zrm:
23633	case VINSERTF64x4Zrmk:
23634	case VINSERTF64x4Zrmkz:
23635	case VINSERTF64x4Zrr:
23636	case VINSERTF64x4Zrrk:
23637	case VINSERTF64x4Zrrkz:
23638		return true;
23639	}
23640	return false;
23641}
23642
23643bool isMINSS(unsigned Opcode) {
23644	switch (Opcode) {
23645	case MINSSrm_Int:
23646	case MINSSrr_Int:
23647		return true;
23648	}
23649	return false;
23650}
23651
23652bool isVPBROADCASTMB2Q(unsigned Opcode) {
23653	switch (Opcode) {
23654	case VPBROADCASTMB2QZ128rr:
23655	case VPBROADCASTMB2QZ256rr:
23656	case VPBROADCASTMB2QZrr:
23657		return true;
23658	}
23659	return false;
23660}
23661
23662bool isKSHIFTRQ(unsigned Opcode) {
23663	return Opcode == KSHIFTRQri;
23664}
23665
23666bool isVMOVSHDUP(unsigned Opcode) {
23667	switch (Opcode) {
23668	case VMOVSHDUPYrm:
23669	case VMOVSHDUPYrr:
23670	case VMOVSHDUPZ128rm:
23671	case VMOVSHDUPZ128rmk:
23672	case VMOVSHDUPZ128rmkz:
23673	case VMOVSHDUPZ128rr:
23674	case VMOVSHDUPZ128rrk:
23675	case VMOVSHDUPZ128rrkz:
23676	case VMOVSHDUPZ256rm:
23677	case VMOVSHDUPZ256rmk:
23678	case VMOVSHDUPZ256rmkz:
23679	case VMOVSHDUPZ256rr:
23680	case VMOVSHDUPZ256rrk:
23681	case VMOVSHDUPZ256rrkz:
23682	case VMOVSHDUPZrm:
23683	case VMOVSHDUPZrmk:
23684	case VMOVSHDUPZrmkz:
23685	case VMOVSHDUPZrr:
23686	case VMOVSHDUPZrrk:
23687	case VMOVSHDUPZrrkz:
23688	case VMOVSHDUPrm:
23689	case VMOVSHDUPrr:
23690		return true;
23691	}
23692	return false;
23693}
23694
23695bool isVPMOVSWB(unsigned Opcode) {
23696	switch (Opcode) {
23697	case VPMOVSWBZ128mr:
23698	case VPMOVSWBZ128mrk:
23699	case VPMOVSWBZ128rr:
23700	case VPMOVSWBZ128rrk:
23701	case VPMOVSWBZ128rrkz:
23702	case VPMOVSWBZ256mr:
23703	case VPMOVSWBZ256mrk:
23704	case VPMOVSWBZ256rr:
23705	case VPMOVSWBZ256rrk:
23706	case VPMOVSWBZ256rrkz:
23707	case VPMOVSWBZmr:
23708	case VPMOVSWBZmrk:
23709	case VPMOVSWBZrr:
23710	case VPMOVSWBZrrk:
23711	case VPMOVSWBZrrkz:
23712		return true;
23713	}
23714	return false;
23715}
23716
23717bool isPMOVZXWD(unsigned Opcode) {
23718	switch (Opcode) {
23719	case PMOVZXWDrm:
23720	case PMOVZXWDrr:
23721		return true;
23722	}
23723	return false;
23724}
23725
23726bool isFSIN(unsigned Opcode) {
23727	return Opcode == FSIN;
23728}
23729
23730bool isPSLLDQ(unsigned Opcode) {
23731	return Opcode == PSLLDQri;
23732}
23733
23734bool isKSHIFTRW(unsigned Opcode) {
23735	return Opcode == KSHIFTRWri;
23736}
23737
23738bool isVPADDD(unsigned Opcode) {
23739	switch (Opcode) {
23740	case VPADDDYrm:
23741	case VPADDDYrr:
23742	case VPADDDZ128rm:
23743	case VPADDDZ128rmb:
23744	case VPADDDZ128rmbk:
23745	case VPADDDZ128rmbkz:
23746	case VPADDDZ128rmk:
23747	case VPADDDZ128rmkz:
23748	case VPADDDZ128rr:
23749	case VPADDDZ128rrk:
23750	case VPADDDZ128rrkz:
23751	case VPADDDZ256rm:
23752	case VPADDDZ256rmb:
23753	case VPADDDZ256rmbk:
23754	case VPADDDZ256rmbkz:
23755	case VPADDDZ256rmk:
23756	case VPADDDZ256rmkz:
23757	case VPADDDZ256rr:
23758	case VPADDDZ256rrk:
23759	case VPADDDZ256rrkz:
23760	case VPADDDZrm:
23761	case VPADDDZrmb:
23762	case VPADDDZrmbk:
23763	case VPADDDZrmbkz:
23764	case VPADDDZrmk:
23765	case VPADDDZrmkz:
23766	case VPADDDZrr:
23767	case VPADDDZrrk:
23768	case VPADDDZrrkz:
23769	case VPADDDrm:
23770	case VPADDDrr:
23771		return true;
23772	}
23773	return false;
23774}
23775
23776bool isVPADDB(unsigned Opcode) {
23777	switch (Opcode) {
23778	case VPADDBYrm:
23779	case VPADDBYrr:
23780	case VPADDBZ128rm:
23781	case VPADDBZ128rmk:
23782	case VPADDBZ128rmkz:
23783	case VPADDBZ128rr:
23784	case VPADDBZ128rrk:
23785	case VPADDBZ128rrkz:
23786	case VPADDBZ256rm:
23787	case VPADDBZ256rmk:
23788	case VPADDBZ256rmkz:
23789	case VPADDBZ256rr:
23790	case VPADDBZ256rrk:
23791	case VPADDBZ256rrkz:
23792	case VPADDBZrm:
23793	case VPADDBZrmk:
23794	case VPADDBZrmkz:
23795	case VPADDBZrr:
23796	case VPADDBZrrk:
23797	case VPADDBZrrkz:
23798	case VPADDBrm:
23799	case VPADDBrr:
23800		return true;
23801	}
23802	return false;
23803}
23804
23805bool isVPMACSSWD(unsigned Opcode) {
23806	switch (Opcode) {
23807	case VPMACSSWDrm:
23808	case VPMACSSWDrr:
23809		return true;
23810	}
23811	return false;
23812}
23813
23814bool isPMOVZXWQ(unsigned Opcode) {
23815	switch (Opcode) {
23816	case PMOVZXWQrm:
23817	case PMOVZXWQrr:
23818		return true;
23819	}
23820	return false;
23821}
23822
23823bool isVPADDQ(unsigned Opcode) {
23824	switch (Opcode) {
23825	case VPADDQYrm:
23826	case VPADDQYrr:
23827	case VPADDQZ128rm:
23828	case VPADDQZ128rmb:
23829	case VPADDQZ128rmbk:
23830	case VPADDQZ128rmbkz:
23831	case VPADDQZ128rmk:
23832	case VPADDQZ128rmkz:
23833	case VPADDQZ128rr:
23834	case VPADDQZ128rrk:
23835	case VPADDQZ128rrkz:
23836	case VPADDQZ256rm:
23837	case VPADDQZ256rmb:
23838	case VPADDQZ256rmbk:
23839	case VPADDQZ256rmbkz:
23840	case VPADDQZ256rmk:
23841	case VPADDQZ256rmkz:
23842	case VPADDQZ256rr:
23843	case VPADDQZ256rrk:
23844	case VPADDQZ256rrkz:
23845	case VPADDQZrm:
23846	case VPADDQZrmb:
23847	case VPADDQZrmbk:
23848	case VPADDQZrmbkz:
23849	case VPADDQZrmk:
23850	case VPADDQZrmkz:
23851	case VPADDQZrr:
23852	case VPADDQZrrk:
23853	case VPADDQZrrkz:
23854	case VPADDQrm:
23855	case VPADDQrr:
23856		return true;
23857	}
23858	return false;
23859}
23860
23861bool isVPADDW(unsigned Opcode) {
23862	switch (Opcode) {
23863	case VPADDWYrm:
23864	case VPADDWYrr:
23865	case VPADDWZ128rm:
23866	case VPADDWZ128rmk:
23867	case VPADDWZ128rmkz:
23868	case VPADDWZ128rr:
23869	case VPADDWZ128rrk:
23870	case VPADDWZ128rrkz:
23871	case VPADDWZ256rm:
23872	case VPADDWZ256rmk:
23873	case VPADDWZ256rmkz:
23874	case VPADDWZ256rr:
23875	case VPADDWZ256rrk:
23876	case VPADDWZ256rrkz:
23877	case VPADDWZrm:
23878	case VPADDWZrmk:
23879	case VPADDWZrmkz:
23880	case VPADDWZrr:
23881	case VPADDWZrrk:
23882	case VPADDWZrrkz:
23883	case VPADDWrm:
23884	case VPADDWrr:
23885		return true;
23886	}
23887	return false;
23888}
23889
23890bool isVRSQRTPH(unsigned Opcode) {
23891	switch (Opcode) {
23892	case VRSQRTPHZ128m:
23893	case VRSQRTPHZ128mb:
23894	case VRSQRTPHZ128mbk:
23895	case VRSQRTPHZ128mbkz:
23896	case VRSQRTPHZ128mk:
23897	case VRSQRTPHZ128mkz:
23898	case VRSQRTPHZ128r:
23899	case VRSQRTPHZ128rk:
23900	case VRSQRTPHZ128rkz:
23901	case VRSQRTPHZ256m:
23902	case VRSQRTPHZ256mb:
23903	case VRSQRTPHZ256mbk:
23904	case VRSQRTPHZ256mbkz:
23905	case VRSQRTPHZ256mk:
23906	case VRSQRTPHZ256mkz:
23907	case VRSQRTPHZ256r:
23908	case VRSQRTPHZ256rk:
23909	case VRSQRTPHZ256rkz:
23910	case VRSQRTPHZm:
23911	case VRSQRTPHZmb:
23912	case VRSQRTPHZmbk:
23913	case VRSQRTPHZmbkz:
23914	case VRSQRTPHZmk:
23915	case VRSQRTPHZmkz:
23916	case VRSQRTPHZr:
23917	case VRSQRTPHZrk:
23918	case VRSQRTPHZrkz:
23919		return true;
23920	}
23921	return false;
23922}
23923
23924bool isVPMACSSWW(unsigned Opcode) {
23925	switch (Opcode) {
23926	case VPMACSSWWrm:
23927	case VPMACSSWWrr:
23928		return true;
23929	}
23930	return false;
23931}
23932
23933bool isVRSQRTPS(unsigned Opcode) {
23934	switch (Opcode) {
23935	case VRSQRTPSYm:
23936	case VRSQRTPSYr:
23937	case VRSQRTPSm:
23938	case VRSQRTPSr:
23939		return true;
23940	}
23941	return false;
23942}
23943
23944bool isVCVTTPH2DQ(unsigned Opcode) {
23945	switch (Opcode) {
23946	case VCVTTPH2DQZ128rm:
23947	case VCVTTPH2DQZ128rmb:
23948	case VCVTTPH2DQZ128rmbk:
23949	case VCVTTPH2DQZ128rmbkz:
23950	case VCVTTPH2DQZ128rmk:
23951	case VCVTTPH2DQZ128rmkz:
23952	case VCVTTPH2DQZ128rr:
23953	case VCVTTPH2DQZ128rrk:
23954	case VCVTTPH2DQZ128rrkz:
23955	case VCVTTPH2DQZ256rm:
23956	case VCVTTPH2DQZ256rmb:
23957	case VCVTTPH2DQZ256rmbk:
23958	case VCVTTPH2DQZ256rmbkz:
23959	case VCVTTPH2DQZ256rmk:
23960	case VCVTTPH2DQZ256rmkz:
23961	case VCVTTPH2DQZ256rr:
23962	case VCVTTPH2DQZ256rrk:
23963	case VCVTTPH2DQZ256rrkz:
23964	case VCVTTPH2DQZrm:
23965	case VCVTTPH2DQZrmb:
23966	case VCVTTPH2DQZrmbk:
23967	case VCVTTPH2DQZrmbkz:
23968	case VCVTTPH2DQZrmk:
23969	case VCVTTPH2DQZrmkz:
23970	case VCVTTPH2DQZrr:
23971	case VCVTTPH2DQZrrb:
23972	case VCVTTPH2DQZrrbk:
23973	case VCVTTPH2DQZrrbkz:
23974	case VCVTTPH2DQZrrk:
23975	case VCVTTPH2DQZrrkz:
23976		return true;
23977	}
23978	return false;
23979}
23980
23981bool isWRMSR(unsigned Opcode) {
23982	return Opcode == WRMSR;
23983}
23984
23985bool isXSETBV(unsigned Opcode) {
23986	return Opcode == XSETBV;
23987}
23988
23989bool isMOVSXD(unsigned Opcode) {
23990	switch (Opcode) {
23991	case MOVSX16rm32:
23992	case MOVSX16rr32:
23993	case MOVSX32rm32:
23994	case MOVSX32rr32:
23995	case MOVSX64rm32:
23996	case MOVSX64rr32:
23997		return true;
23998	}
23999	return false;
24000}
24001
24002bool isADC(unsigned Opcode) {
24003	switch (Opcode) {
24004	case ADC16i16:
24005	case ADC16mi:
24006	case ADC16mi8:
24007	case ADC16mr:
24008	case ADC16ri:
24009	case ADC16ri8:
24010	case ADC16rm:
24011	case ADC16rr:
24012	case ADC16rr_REV:
24013	case ADC32i32:
24014	case ADC32mi:
24015	case ADC32mi8:
24016	case ADC32mr:
24017	case ADC32ri:
24018	case ADC32ri8:
24019	case ADC32rm:
24020	case ADC32rr:
24021	case ADC32rr_REV:
24022	case ADC64i32:
24023	case ADC64mi32:
24024	case ADC64mi8:
24025	case ADC64mr:
24026	case ADC64ri32:
24027	case ADC64ri8:
24028	case ADC64rm:
24029	case ADC64rr:
24030	case ADC64rr_REV:
24031	case ADC8i8:
24032	case ADC8mi:
24033	case ADC8mi8:
24034	case ADC8mr:
24035	case ADC8ri:
24036	case ADC8ri8:
24037	case ADC8rm:
24038	case ADC8rr:
24039	case ADC8rr_REV:
24040		return true;
24041	}
24042	return false;
24043}
24044
24045bool isADD(unsigned Opcode) {
24046	switch (Opcode) {
24047	case ADD16i16:
24048	case ADD16mi:
24049	case ADD16mi8:
24050	case ADD16mr:
24051	case ADD16ri:
24052	case ADD16ri8:
24053	case ADD16rm:
24054	case ADD16rr:
24055	case ADD16rr_REV:
24056	case ADD32i32:
24057	case ADD32mi:
24058	case ADD32mi8:
24059	case ADD32mr:
24060	case ADD32ri:
24061	case ADD32ri8:
24062	case ADD32rm:
24063	case ADD32rr:
24064	case ADD32rr_REV:
24065	case ADD64i32:
24066	case ADD64mi32:
24067	case ADD64mi8:
24068	case ADD64mr:
24069	case ADD64ri32:
24070	case ADD64ri8:
24071	case ADD64rm:
24072	case ADD64rr:
24073	case ADD64rr_REV:
24074	case ADD8i8:
24075	case ADD8mi:
24076	case ADD8mi8:
24077	case ADD8mr:
24078	case ADD8ri:
24079	case ADD8ri8:
24080	case ADD8rm:
24081	case ADD8rr:
24082	case ADD8rr_REV:
24083		return true;
24084	}
24085	return false;
24086}
24087
24088bool isFDIV(unsigned Opcode) {
24089	switch (Opcode) {
24090	case DIV_F32m:
24091	case DIV_F64m:
24092	case DIV_FST0r:
24093	case DIV_FrST0:
24094		return true;
24095	}
24096	return false;
24097}
24098
24099bool isAESDEC256KL(unsigned Opcode) {
24100	return Opcode == AESDEC256KL;
24101}
24102
24103bool isVPCMPUB(unsigned Opcode) {
24104	switch (Opcode) {
24105	case VPCMPUBZ128rmi:
24106	case VPCMPUBZ128rmik:
24107	case VPCMPUBZ128rri:
24108	case VPCMPUBZ128rrik:
24109	case VPCMPUBZ256rmi:
24110	case VPCMPUBZ256rmik:
24111	case VPCMPUBZ256rri:
24112	case VPCMPUBZ256rrik:
24113	case VPCMPUBZrmi:
24114	case VPCMPUBZrmik:
24115	case VPCMPUBZrri:
24116	case VPCMPUBZrrik:
24117		return true;
24118	}
24119	return false;
24120}
24121
24122bool isVCVTTPD2QQ(unsigned Opcode) {
24123	switch (Opcode) {
24124	case VCVTTPD2QQZ128rm:
24125	case VCVTTPD2QQZ128rmb:
24126	case VCVTTPD2QQZ128rmbk:
24127	case VCVTTPD2QQZ128rmbkz:
24128	case VCVTTPD2QQZ128rmk:
24129	case VCVTTPD2QQZ128rmkz:
24130	case VCVTTPD2QQZ128rr:
24131	case VCVTTPD2QQZ128rrk:
24132	case VCVTTPD2QQZ128rrkz:
24133	case VCVTTPD2QQZ256rm:
24134	case VCVTTPD2QQZ256rmb:
24135	case VCVTTPD2QQZ256rmbk:
24136	case VCVTTPD2QQZ256rmbkz:
24137	case VCVTTPD2QQZ256rmk:
24138	case VCVTTPD2QQZ256rmkz:
24139	case VCVTTPD2QQZ256rr:
24140	case VCVTTPD2QQZ256rrk:
24141	case VCVTTPD2QQZ256rrkz:
24142	case VCVTTPD2QQZrm:
24143	case VCVTTPD2QQZrmb:
24144	case VCVTTPD2QQZrmbk:
24145	case VCVTTPD2QQZrmbkz:
24146	case VCVTTPD2QQZrmk:
24147	case VCVTTPD2QQZrmkz:
24148	case VCVTTPD2QQZrr:
24149	case VCVTTPD2QQZrrb:
24150	case VCVTTPD2QQZrrbk:
24151	case VCVTTPD2QQZrrbkz:
24152	case VCVTTPD2QQZrrk:
24153	case VCVTTPD2QQZrrkz:
24154		return true;
24155	}
24156	return false;
24157}
24158
24159bool isVPCMPUD(unsigned Opcode) {
24160	switch (Opcode) {
24161	case VPCMPUDZ128rmi:
24162	case VPCMPUDZ128rmib:
24163	case VPCMPUDZ128rmibk:
24164	case VPCMPUDZ128rmik:
24165	case VPCMPUDZ128rri:
24166	case VPCMPUDZ128rrik:
24167	case VPCMPUDZ256rmi:
24168	case VPCMPUDZ256rmib:
24169	case VPCMPUDZ256rmibk:
24170	case VPCMPUDZ256rmik:
24171	case VPCMPUDZ256rri:
24172	case VPCMPUDZ256rrik:
24173	case VPCMPUDZrmi:
24174	case VPCMPUDZrmib:
24175	case VPCMPUDZrmibk:
24176	case VPCMPUDZrmik:
24177	case VPCMPUDZrri:
24178	case VPCMPUDZrrik:
24179		return true;
24180	}
24181	return false;
24182}
24183
24184bool isPFMUL(unsigned Opcode) {
24185	switch (Opcode) {
24186	case PFMULrm:
24187	case PFMULrr:
24188		return true;
24189	}
24190	return false;
24191}
24192
24193bool isPREFETCHW(unsigned Opcode) {
24194	return Opcode == PREFETCHW;
24195}
24196
24197bool isVPCMPUQ(unsigned Opcode) {
24198	switch (Opcode) {
24199	case VPCMPUQZ128rmi:
24200	case VPCMPUQZ128rmib:
24201	case VPCMPUQZ128rmibk:
24202	case VPCMPUQZ128rmik:
24203	case VPCMPUQZ128rri:
24204	case VPCMPUQZ128rrik:
24205	case VPCMPUQZ256rmi:
24206	case VPCMPUQZ256rmib:
24207	case VPCMPUQZ256rmibk:
24208	case VPCMPUQZ256rmik:
24209	case VPCMPUQZ256rri:
24210	case VPCMPUQZ256rrik:
24211	case VPCMPUQZrmi:
24212	case VPCMPUQZrmib:
24213	case VPCMPUQZrmibk:
24214	case VPCMPUQZrmik:
24215	case VPCMPUQZrri:
24216	case VPCMPUQZrrik:
24217		return true;
24218	}
24219	return false;
24220}
24221
24222bool isKORTESTB(unsigned Opcode) {
24223	return Opcode == KORTESTBrr;
24224}
24225
24226bool isMOVHPD(unsigned Opcode) {
24227	switch (Opcode) {
24228	case MOVHPDmr:
24229	case MOVHPDrm:
24230		return true;
24231	}
24232	return false;
24233}
24234
24235bool isKORTESTD(unsigned Opcode) {
24236	return Opcode == KORTESTDrr;
24237}
24238
24239bool isCVTSI2SD(unsigned Opcode) {
24240	switch (Opcode) {
24241	case CVTSI2SDrm_Int:
24242	case CVTSI2SDrr_Int:
24243	case CVTSI642SDrm_Int:
24244	case CVTSI642SDrr_Int:
24245		return true;
24246	}
24247	return false;
24248}
24249
24250bool isFSUBRP(unsigned Opcode) {
24251	return Opcode == SUBR_FPrST0;
24252}
24253
24254bool isIRET(unsigned Opcode) {
24255	return Opcode == IRET16;
24256}
24257
24258bool isPTWRITE(unsigned Opcode) {
24259	switch (Opcode) {
24260	case PTWRITE64m:
24261	case PTWRITE64r:
24262	case PTWRITEm:
24263	case PTWRITEr:
24264		return true;
24265	}
24266	return false;
24267}
24268
24269bool isVPCMPUW(unsigned Opcode) {
24270	switch (Opcode) {
24271	case VPCMPUWZ128rmi:
24272	case VPCMPUWZ128rmik:
24273	case VPCMPUWZ128rri:
24274	case VPCMPUWZ128rrik:
24275	case VPCMPUWZ256rmi:
24276	case VPCMPUWZ256rmik:
24277	case VPCMPUWZ256rri:
24278	case VPCMPUWZ256rrik:
24279	case VPCMPUWZrmi:
24280	case VPCMPUWZrmik:
24281	case VPCMPUWZrri:
24282	case VPCMPUWZrrik:
24283		return true;
24284	}
24285	return false;
24286}
24287
24288bool isKORTESTQ(unsigned Opcode) {
24289	return Opcode == KORTESTQrr;
24290}
24291
24292bool isMOVHPS(unsigned Opcode) {
24293	switch (Opcode) {
24294	case MOVHPSmr:
24295	case MOVHPSrm:
24296		return true;
24297	}
24298	return false;
24299}
24300
24301bool isFIMUL(unsigned Opcode) {
24302	switch (Opcode) {
24303	case MUL_FI16m:
24304	case MUL_FI32m:
24305		return true;
24306	}
24307	return false;
24308}
24309
24310bool isCVTSI2SS(unsigned Opcode) {
24311	switch (Opcode) {
24312	case CVTSI2SSrm_Int:
24313	case CVTSI2SSrr_Int:
24314	case CVTSI642SSrm_Int:
24315	case CVTSI642SSrr_Int:
24316		return true;
24317	}
24318	return false;
24319}
24320
24321bool isVCVTPH2PD(unsigned Opcode) {
24322	switch (Opcode) {
24323	case VCVTPH2PDZ128rm:
24324	case VCVTPH2PDZ128rmb:
24325	case VCVTPH2PDZ128rmbk:
24326	case VCVTPH2PDZ128rmbkz:
24327	case VCVTPH2PDZ128rmk:
24328	case VCVTPH2PDZ128rmkz:
24329	case VCVTPH2PDZ128rr:
24330	case VCVTPH2PDZ128rrk:
24331	case VCVTPH2PDZ128rrkz:
24332	case VCVTPH2PDZ256rm:
24333	case VCVTPH2PDZ256rmb:
24334	case VCVTPH2PDZ256rmbk:
24335	case VCVTPH2PDZ256rmbkz:
24336	case VCVTPH2PDZ256rmk:
24337	case VCVTPH2PDZ256rmkz:
24338	case VCVTPH2PDZ256rr:
24339	case VCVTPH2PDZ256rrk:
24340	case VCVTPH2PDZ256rrkz:
24341	case VCVTPH2PDZrm:
24342	case VCVTPH2PDZrmb:
24343	case VCVTPH2PDZrmbk:
24344	case VCVTPH2PDZrmbkz:
24345	case VCVTPH2PDZrmk:
24346	case VCVTPH2PDZrmkz:
24347	case VCVTPH2PDZrr:
24348	case VCVTPH2PDZrrb:
24349	case VCVTPH2PDZrrbk:
24350	case VCVTPH2PDZrrbkz:
24351	case VCVTPH2PDZrrk:
24352	case VCVTPH2PDZrrkz:
24353		return true;
24354	}
24355	return false;
24356}
24357
24358bool isKORTESTW(unsigned Opcode) {
24359	return Opcode == KORTESTWrr;
24360}
24361
24362bool isPADDUSB(unsigned Opcode) {
24363	switch (Opcode) {
24364	case MMX_PADDUSBrm:
24365	case MMX_PADDUSBrr:
24366	case PADDUSBrm:
24367	case PADDUSBrr:
24368		return true;
24369	}
24370	return false;
24371}
24372
24373bool isVSHUFI64X2(unsigned Opcode) {
24374	switch (Opcode) {
24375	case VSHUFI64X2Z256rmbi:
24376	case VSHUFI64X2Z256rmbik:
24377	case VSHUFI64X2Z256rmbikz:
24378	case VSHUFI64X2Z256rmi:
24379	case VSHUFI64X2Z256rmik:
24380	case VSHUFI64X2Z256rmikz:
24381	case VSHUFI64X2Z256rri:
24382	case VSHUFI64X2Z256rrik:
24383	case VSHUFI64X2Z256rrikz:
24384	case VSHUFI64X2Zrmbi:
24385	case VSHUFI64X2Zrmbik:
24386	case VSHUFI64X2Zrmbikz:
24387	case VSHUFI64X2Zrmi:
24388	case VSHUFI64X2Zrmik:
24389	case VSHUFI64X2Zrmikz:
24390	case VSHUFI64X2Zrri:
24391	case VSHUFI64X2Zrrik:
24392	case VSHUFI64X2Zrrikz:
24393		return true;
24394	}
24395	return false;
24396}
24397
24398bool isVRSQRTSH(unsigned Opcode) {
24399	switch (Opcode) {
24400	case VRSQRTSHZrm:
24401	case VRSQRTSHZrmk:
24402	case VRSQRTSHZrmkz:
24403	case VRSQRTSHZrr:
24404	case VRSQRTSHZrrk:
24405	case VRSQRTSHZrrkz:
24406		return true;
24407	}
24408	return false;
24409}
24410
24411bool isVMWRITE(unsigned Opcode) {
24412	switch (Opcode) {
24413	case VMWRITE32rm:
24414	case VMWRITE32rr:
24415	case VMWRITE64rm:
24416	case VMWRITE64rr:
24417		return true;
24418	}
24419	return false;
24420}
24421
24422bool isTILERELEASE(unsigned Opcode) {
24423	return Opcode == TILERELEASE;
24424}
24425
24426bool isVCVTPH2PS(unsigned Opcode) {
24427	switch (Opcode) {
24428	case VCVTPH2PSYrm:
24429	case VCVTPH2PSYrr:
24430	case VCVTPH2PSZ128rm:
24431	case VCVTPH2PSZ128rmk:
24432	case VCVTPH2PSZ128rmkz:
24433	case VCVTPH2PSZ128rr:
24434	case VCVTPH2PSZ128rrk:
24435	case VCVTPH2PSZ128rrkz:
24436	case VCVTPH2PSZ256rm:
24437	case VCVTPH2PSZ256rmk:
24438	case VCVTPH2PSZ256rmkz:
24439	case VCVTPH2PSZ256rr:
24440	case VCVTPH2PSZ256rrk:
24441	case VCVTPH2PSZ256rrkz:
24442	case VCVTPH2PSZrm:
24443	case VCVTPH2PSZrmk:
24444	case VCVTPH2PSZrmkz:
24445	case VCVTPH2PSZrr:
24446	case VCVTPH2PSZrrb:
24447	case VCVTPH2PSZrrbk:
24448	case VCVTPH2PSZrrbkz:
24449	case VCVTPH2PSZrrk:
24450	case VCVTPH2PSZrrkz:
24451	case VCVTPH2PSrm:
24452	case VCVTPH2PSrr:
24453		return true;
24454	}
24455	return false;
24456}
24457
24458bool isVMOVUPD(unsigned Opcode) {
24459	switch (Opcode) {
24460	case VMOVUPDYmr:
24461	case VMOVUPDYrm:
24462	case VMOVUPDYrr:
24463	case VMOVUPDYrr_REV:
24464	case VMOVUPDZ128mr:
24465	case VMOVUPDZ128mrk:
24466	case VMOVUPDZ128rm:
24467	case VMOVUPDZ128rmk:
24468	case VMOVUPDZ128rmkz:
24469	case VMOVUPDZ128rr:
24470	case VMOVUPDZ128rr_REV:
24471	case VMOVUPDZ128rrk:
24472	case VMOVUPDZ128rrk_REV:
24473	case VMOVUPDZ128rrkz:
24474	case VMOVUPDZ128rrkz_REV:
24475	case VMOVUPDZ256mr:
24476	case VMOVUPDZ256mrk:
24477	case VMOVUPDZ256rm:
24478	case VMOVUPDZ256rmk:
24479	case VMOVUPDZ256rmkz:
24480	case VMOVUPDZ256rr:
24481	case VMOVUPDZ256rr_REV:
24482	case VMOVUPDZ256rrk:
24483	case VMOVUPDZ256rrk_REV:
24484	case VMOVUPDZ256rrkz:
24485	case VMOVUPDZ256rrkz_REV:
24486	case VMOVUPDZmr:
24487	case VMOVUPDZmrk:
24488	case VMOVUPDZrm:
24489	case VMOVUPDZrmk:
24490	case VMOVUPDZrmkz:
24491	case VMOVUPDZrr:
24492	case VMOVUPDZrr_REV:
24493	case VMOVUPDZrrk:
24494	case VMOVUPDZrrk_REV:
24495	case VMOVUPDZrrkz:
24496	case VMOVUPDZrrkz_REV:
24497	case VMOVUPDmr:
24498	case VMOVUPDrm:
24499	case VMOVUPDrr:
24500	case VMOVUPDrr_REV:
24501		return true;
24502	}
24503	return false;
24504}
24505
24506bool isPADDUSW(unsigned Opcode) {
24507	switch (Opcode) {
24508	case MMX_PADDUSWrm:
24509	case MMX_PADDUSWrr:
24510	case PADDUSWrm:
24511	case PADDUSWrr:
24512		return true;
24513	}
24514	return false;
24515}
24516
24517bool isVRSQRTSS(unsigned Opcode) {
24518	switch (Opcode) {
24519	case VRSQRTSSm_Int:
24520	case VRSQRTSSr_Int:
24521		return true;
24522	}
24523	return false;
24524}
24525
24526bool isVPCMOV(unsigned Opcode) {
24527	switch (Opcode) {
24528	case VPCMOVYrmr:
24529	case VPCMOVYrrm:
24530	case VPCMOVYrrr:
24531	case VPCMOVYrrr_REV:
24532	case VPCMOVrmr:
24533	case VPCMOVrrm:
24534	case VPCMOVrrr:
24535	case VPCMOVrrr_REV:
24536		return true;
24537	}
24538	return false;
24539}
24540
24541bool isVCVTUSI2SD(unsigned Opcode) {
24542	switch (Opcode) {
24543	case VCVTUSI2SDZrm_Int:
24544	case VCVTUSI2SDZrr_Int:
24545	case VCVTUSI642SDZrm_Int:
24546	case VCVTUSI642SDZrr_Int:
24547	case VCVTUSI642SDZrrb_Int:
24548		return true;
24549	}
24550	return false;
24551}
24552
24553bool isVMOVUPS(unsigned Opcode) {
24554	switch (Opcode) {
24555	case VMOVUPSYmr:
24556	case VMOVUPSYrm:
24557	case VMOVUPSYrr:
24558	case VMOVUPSYrr_REV:
24559	case VMOVUPSZ128mr:
24560	case VMOVUPSZ128mrk:
24561	case VMOVUPSZ128rm:
24562	case VMOVUPSZ128rmk:
24563	case VMOVUPSZ128rmkz:
24564	case VMOVUPSZ128rr:
24565	case VMOVUPSZ128rr_REV:
24566	case VMOVUPSZ128rrk:
24567	case VMOVUPSZ128rrk_REV:
24568	case VMOVUPSZ128rrkz:
24569	case VMOVUPSZ128rrkz_REV:
24570	case VMOVUPSZ256mr:
24571	case VMOVUPSZ256mrk:
24572	case VMOVUPSZ256rm:
24573	case VMOVUPSZ256rmk:
24574	case VMOVUPSZ256rmkz:
24575	case VMOVUPSZ256rr:
24576	case VMOVUPSZ256rr_REV:
24577	case VMOVUPSZ256rrk:
24578	case VMOVUPSZ256rrk_REV:
24579	case VMOVUPSZ256rrkz:
24580	case VMOVUPSZ256rrkz_REV:
24581	case VMOVUPSZmr:
24582	case VMOVUPSZmrk:
24583	case VMOVUPSZrm:
24584	case VMOVUPSZrmk:
24585	case VMOVUPSZrmkz:
24586	case VMOVUPSZrr:
24587	case VMOVUPSZrr_REV:
24588	case VMOVUPSZrrk:
24589	case VMOVUPSZrrk_REV:
24590	case VMOVUPSZrrkz:
24591	case VMOVUPSZrrkz_REV:
24592	case VMOVUPSmr:
24593	case VMOVUPSrm:
24594	case VMOVUPSrr:
24595	case VMOVUPSrr_REV:
24596		return true;
24597	}
24598	return false;
24599}
24600
24601bool isVCVTUSI2SH(unsigned Opcode) {
24602	switch (Opcode) {
24603	case VCVTUSI2SHZrm_Int:
24604	case VCVTUSI2SHZrr_Int:
24605	case VCVTUSI2SHZrrb_Int:
24606	case VCVTUSI642SHZrm_Int:
24607	case VCVTUSI642SHZrr_Int:
24608	case VCVTUSI642SHZrrb_Int:
24609		return true;
24610	}
24611	return false;
24612}
24613
24614bool isVPCMPB(unsigned Opcode) {
24615	switch (Opcode) {
24616	case VPCMPBZ128rmi:
24617	case VPCMPBZ128rmik:
24618	case VPCMPBZ128rri:
24619	case VPCMPBZ128rrik:
24620	case VPCMPBZ256rmi:
24621	case VPCMPBZ256rmik:
24622	case VPCMPBZ256rri:
24623	case VPCMPBZ256rrik:
24624	case VPCMPBZrmi:
24625	case VPCMPBZrmik:
24626	case VPCMPBZrri:
24627	case VPCMPBZrrik:
24628		return true;
24629	}
24630	return false;
24631}
24632
24633bool isVPGATHERDD(unsigned Opcode) {
24634	switch (Opcode) {
24635	case VPGATHERDDYrm:
24636	case VPGATHERDDZ128rm:
24637	case VPGATHERDDZ256rm:
24638	case VPGATHERDDZrm:
24639	case VPGATHERDDrm:
24640		return true;
24641	}
24642	return false;
24643}
24644
24645bool isVPCMPD(unsigned Opcode) {
24646	switch (Opcode) {
24647	case VPCMPDZ128rmi:
24648	case VPCMPDZ128rmib:
24649	case VPCMPDZ128rmibk:
24650	case VPCMPDZ128rmik:
24651	case VPCMPDZ128rri:
24652	case VPCMPDZ128rrik:
24653	case VPCMPDZ256rmi:
24654	case VPCMPDZ256rmib:
24655	case VPCMPDZ256rmibk:
24656	case VPCMPDZ256rmik:
24657	case VPCMPDZ256rri:
24658	case VPCMPDZ256rrik:
24659	case VPCMPDZrmi:
24660	case VPCMPDZrmib:
24661	case VPCMPDZrmibk:
24662	case VPCMPDZrmik:
24663	case VPCMPDZrri:
24664	case VPCMPDZrrik:
24665		return true;
24666	}
24667	return false;
24668}
24669
24670bool isVCVTUSI2SS(unsigned Opcode) {
24671	switch (Opcode) {
24672	case VCVTUSI2SSZrm_Int:
24673	case VCVTUSI2SSZrr_Int:
24674	case VCVTUSI2SSZrrb_Int:
24675	case VCVTUSI642SSZrm_Int:
24676	case VCVTUSI642SSZrr_Int:
24677	case VCVTUSI642SSZrrb_Int:
24678		return true;
24679	}
24680	return false;
24681}
24682
24683bool isLFENCE(unsigned Opcode) {
24684	return Opcode == LFENCE;
24685}
24686
24687bool isVCVTPH2QQ(unsigned Opcode) {
24688	switch (Opcode) {
24689	case VCVTPH2QQZ128rm:
24690	case VCVTPH2QQZ128rmb:
24691	case VCVTPH2QQZ128rmbk:
24692	case VCVTPH2QQZ128rmbkz:
24693	case VCVTPH2QQZ128rmk:
24694	case VCVTPH2QQZ128rmkz:
24695	case VCVTPH2QQZ128rr:
24696	case VCVTPH2QQZ128rrk:
24697	case VCVTPH2QQZ128rrkz:
24698	case VCVTPH2QQZ256rm:
24699	case VCVTPH2QQZ256rmb:
24700	case VCVTPH2QQZ256rmbk:
24701	case VCVTPH2QQZ256rmbkz:
24702	case VCVTPH2QQZ256rmk:
24703	case VCVTPH2QQZ256rmkz:
24704	case VCVTPH2QQZ256rr:
24705	case VCVTPH2QQZ256rrk:
24706	case VCVTPH2QQZ256rrkz:
24707	case VCVTPH2QQZrm:
24708	case VCVTPH2QQZrmb:
24709	case VCVTPH2QQZrmbk:
24710	case VCVTPH2QQZrmbkz:
24711	case VCVTPH2QQZrmk:
24712	case VCVTPH2QQZrmkz:
24713	case VCVTPH2QQZrr:
24714	case VCVTPH2QQZrrb:
24715	case VCVTPH2QQZrrbk:
24716	case VCVTPH2QQZrrbkz:
24717	case VCVTPH2QQZrrk:
24718	case VCVTPH2QQZrrkz:
24719		return true;
24720	}
24721	return false;
24722}
24723
24724bool isVGATHERPF0DPD(unsigned Opcode) {
24725	return Opcode == VGATHERPF0DPDm;
24726}
24727
24728bool isSEAMRET(unsigned Opcode) {
24729	return Opcode == SEAMRET;
24730}
24731
24732bool isPI2FD(unsigned Opcode) {
24733	switch (Opcode) {
24734	case PI2FDrm:
24735	case PI2FDrr:
24736		return true;
24737	}
24738	return false;
24739}
24740
24741bool isVPGATHERDQ(unsigned Opcode) {
24742	switch (Opcode) {
24743	case VPGATHERDQYrm:
24744	case VPGATHERDQZ128rm:
24745	case VPGATHERDQZ256rm:
24746	case VPGATHERDQZrm:
24747	case VPGATHERDQrm:
24748		return true;
24749	}
24750	return false;
24751}
24752
24753bool isPCMPESTRI(unsigned Opcode) {
24754	switch (Opcode) {
24755	case PCMPESTRIrm:
24756	case PCMPESTRIrr:
24757		return true;
24758	}
24759	return false;
24760}
24761
24762bool isVPCMPQ(unsigned Opcode) {
24763	switch (Opcode) {
24764	case VPCMPQZ128rmi:
24765	case VPCMPQZ128rmib:
24766	case VPCMPQZ128rmibk:
24767	case VPCMPQZ128rmik:
24768	case VPCMPQZ128rri:
24769	case VPCMPQZ128rrik:
24770	case VPCMPQZ256rmi:
24771	case VPCMPQZ256rmib:
24772	case VPCMPQZ256rmibk:
24773	case VPCMPQZ256rmik:
24774	case VPCMPQZ256rri:
24775	case VPCMPQZ256rrik:
24776	case VPCMPQZrmi:
24777	case VPCMPQZrmib:
24778	case VPCMPQZrmibk:
24779	case VPCMPQZrmik:
24780	case VPCMPQZrri:
24781	case VPCMPQZrrik:
24782		return true;
24783	}
24784	return false;
24785}
24786
24787bool isPCMPESTRM(unsigned Opcode) {
24788	switch (Opcode) {
24789	case PCMPESTRMrm:
24790	case PCMPESTRMrr:
24791		return true;
24792	}
24793	return false;
24794}
24795
24796bool isVPCMPW(unsigned Opcode) {
24797	switch (Opcode) {
24798	case VPCMPWZ128rmi:
24799	case VPCMPWZ128rmik:
24800	case VPCMPWZ128rri:
24801	case VPCMPWZ128rrik:
24802	case VPCMPWZ256rmi:
24803	case VPCMPWZ256rmik:
24804	case VPCMPWZ256rri:
24805	case VPCMPWZ256rrik:
24806	case VPCMPWZrmi:
24807	case VPCMPWZrmik:
24808	case VPCMPWZrri:
24809	case VPCMPWZrrik:
24810		return true;
24811	}
24812	return false;
24813}
24814
24815bool isVGATHERPF0DPS(unsigned Opcode) {
24816	return Opcode == VGATHERPF0DPSm;
24817}
24818
24819bool isVPMOVUSDB(unsigned Opcode) {
24820	switch (Opcode) {
24821	case VPMOVUSDBZ128mr:
24822	case VPMOVUSDBZ128mrk:
24823	case VPMOVUSDBZ128rr:
24824	case VPMOVUSDBZ128rrk:
24825	case VPMOVUSDBZ128rrkz:
24826	case VPMOVUSDBZ256mr:
24827	case VPMOVUSDBZ256mrk:
24828	case VPMOVUSDBZ256rr:
24829	case VPMOVUSDBZ256rrk:
24830	case VPMOVUSDBZ256rrkz:
24831	case VPMOVUSDBZmr:
24832	case VPMOVUSDBZmrk:
24833	case VPMOVUSDBZrr:
24834	case VPMOVUSDBZrrk:
24835	case VPMOVUSDBZrrkz:
24836		return true;
24837	}
24838	return false;
24839}
24840
24841bool isPI2FW(unsigned Opcode) {
24842	switch (Opcode) {
24843	case PI2FWrm:
24844	case PI2FWrr:
24845		return true;
24846	}
24847	return false;
24848}
24849
24850bool isSYSEXITQ(unsigned Opcode) {
24851	return Opcode == SYSEXIT64;
24852}
24853
24854bool isCVTPS2DQ(unsigned Opcode) {
24855	switch (Opcode) {
24856	case CVTPS2DQrm:
24857	case CVTPS2DQrr:
24858		return true;
24859	}
24860	return false;
24861}
24862
24863bool isRDPKRU(unsigned Opcode) {
24864	return Opcode == RDPKRUr;
24865}
24866
24867bool isVPMOVUSDW(unsigned Opcode) {
24868	switch (Opcode) {
24869	case VPMOVUSDWZ128mr:
24870	case VPMOVUSDWZ128mrk:
24871	case VPMOVUSDWZ128rr:
24872	case VPMOVUSDWZ128rrk:
24873	case VPMOVUSDWZ128rrkz:
24874	case VPMOVUSDWZ256mr:
24875	case VPMOVUSDWZ256mrk:
24876	case VPMOVUSDWZ256rr:
24877	case VPMOVUSDWZ256rrk:
24878	case VPMOVUSDWZ256rrkz:
24879	case VPMOVUSDWZmr:
24880	case VPMOVUSDWZmrk:
24881	case VPMOVUSDWZrr:
24882	case VPMOVUSDWZrrk:
24883	case VPMOVUSDWZrrkz:
24884		return true;
24885	}
24886	return false;
24887}
24888
24889bool isPSUBB(unsigned Opcode) {
24890	switch (Opcode) {
24891	case MMX_PSUBBrm:
24892	case MMX_PSUBBrr:
24893	case PSUBBrm:
24894	case PSUBBrr:
24895		return true;
24896	}
24897	return false;
24898}
24899
24900bool isPSUBD(unsigned Opcode) {
24901	switch (Opcode) {
24902	case MMX_PSUBDrm:
24903	case MMX_PSUBDrr:
24904	case PSUBDrm:
24905	case PSUBDrr:
24906		return true;
24907	}
24908	return false;
24909}
24910
24911bool isVPSHRDD(unsigned Opcode) {
24912	switch (Opcode) {
24913	case VPSHRDDZ128rmbi:
24914	case VPSHRDDZ128rmbik:
24915	case VPSHRDDZ128rmbikz:
24916	case VPSHRDDZ128rmi:
24917	case VPSHRDDZ128rmik:
24918	case VPSHRDDZ128rmikz:
24919	case VPSHRDDZ128rri:
24920	case VPSHRDDZ128rrik:
24921	case VPSHRDDZ128rrikz:
24922	case VPSHRDDZ256rmbi:
24923	case VPSHRDDZ256rmbik:
24924	case VPSHRDDZ256rmbikz:
24925	case VPSHRDDZ256rmi:
24926	case VPSHRDDZ256rmik:
24927	case VPSHRDDZ256rmikz:
24928	case VPSHRDDZ256rri:
24929	case VPSHRDDZ256rrik:
24930	case VPSHRDDZ256rrikz:
24931	case VPSHRDDZrmbi:
24932	case VPSHRDDZrmbik:
24933	case VPSHRDDZrmbikz:
24934	case VPSHRDDZrmi:
24935	case VPSHRDDZrmik:
24936	case VPSHRDDZrmikz:
24937	case VPSHRDDZrri:
24938	case VPSHRDDZrrik:
24939	case VPSHRDDZrrikz:
24940		return true;
24941	}
24942	return false;
24943}
24944
24945bool isRETFQ(unsigned Opcode) {
24946	switch (Opcode) {
24947	case LRET64:
24948	case LRETI64:
24949		return true;
24950	}
24951	return false;
24952}
24953
24954bool isVPERMT2PD(unsigned Opcode) {
24955	switch (Opcode) {
24956	case VPERMT2PD128rm:
24957	case VPERMT2PD128rmb:
24958	case VPERMT2PD128rmbk:
24959	case VPERMT2PD128rmbkz:
24960	case VPERMT2PD128rmk:
24961	case VPERMT2PD128rmkz:
24962	case VPERMT2PD128rr:
24963	case VPERMT2PD128rrk:
24964	case VPERMT2PD128rrkz:
24965	case VPERMT2PD256rm:
24966	case VPERMT2PD256rmb:
24967	case VPERMT2PD256rmbk:
24968	case VPERMT2PD256rmbkz:
24969	case VPERMT2PD256rmk:
24970	case VPERMT2PD256rmkz:
24971	case VPERMT2PD256rr:
24972	case VPERMT2PD256rrk:
24973	case VPERMT2PD256rrkz:
24974	case VPERMT2PDrm:
24975	case VPERMT2PDrmb:
24976	case VPERMT2PDrmbk:
24977	case VPERMT2PDrmbkz:
24978	case VPERMT2PDrmk:
24979	case VPERMT2PDrmkz:
24980	case VPERMT2PDrr:
24981	case VPERMT2PDrrk:
24982	case VPERMT2PDrrkz:
24983		return true;
24984	}
24985	return false;
24986}
24987
24988bool isMOVABS(unsigned Opcode) {
24989	switch (Opcode) {
24990	case MOV16ao64:
24991	case MOV16o64a:
24992	case MOV32ao64:
24993	case MOV32o64a:
24994	case MOV64ao64:
24995	case MOV64o64a:
24996	case MOV64ri:
24997	case MOV8ao64:
24998	case MOV8o64a:
24999		return true;
25000	}
25001	return false;
25002}
25003
25004bool isVPSHRDQ(unsigned Opcode) {
25005	switch (Opcode) {
25006	case VPSHRDQZ128rmbi:
25007	case VPSHRDQZ128rmbik:
25008	case VPSHRDQZ128rmbikz:
25009	case VPSHRDQZ128rmi:
25010	case VPSHRDQZ128rmik:
25011	case VPSHRDQZ128rmikz:
25012	case VPSHRDQZ128rri:
25013	case VPSHRDQZ128rrik:
25014	case VPSHRDQZ128rrikz:
25015	case VPSHRDQZ256rmbi:
25016	case VPSHRDQZ256rmbik:
25017	case VPSHRDQZ256rmbikz:
25018	case VPSHRDQZ256rmi:
25019	case VPSHRDQZ256rmik:
25020	case VPSHRDQZ256rmikz:
25021	case VPSHRDQZ256rri:
25022	case VPSHRDQZ256rrik:
25023	case VPSHRDQZ256rrikz:
25024	case VPSHRDQZrmbi:
25025	case VPSHRDQZrmbik:
25026	case VPSHRDQZrmbikz:
25027	case VPSHRDQZrmi:
25028	case VPSHRDQZrmik:
25029	case VPSHRDQZrmikz:
25030	case VPSHRDQZrri:
25031	case VPSHRDQZrrik:
25032	case VPSHRDQZrrikz:
25033		return true;
25034	}
25035	return false;
25036}
25037
25038bool isPSUBQ(unsigned Opcode) {
25039	switch (Opcode) {
25040	case MMX_PSUBQrm:
25041	case MMX_PSUBQrr:
25042	case PSUBQrm:
25043	case PSUBQrr:
25044		return true;
25045	}
25046	return false;
25047}
25048
25049bool isVPSHRDW(unsigned Opcode) {
25050	switch (Opcode) {
25051	case VPSHRDWZ128rmi:
25052	case VPSHRDWZ128rmik:
25053	case VPSHRDWZ128rmikz:
25054	case VPSHRDWZ128rri:
25055	case VPSHRDWZ128rrik:
25056	case VPSHRDWZ128rrikz:
25057	case VPSHRDWZ256rmi:
25058	case VPSHRDWZ256rmik:
25059	case VPSHRDWZ256rmikz:
25060	case VPSHRDWZ256rri:
25061	case VPSHRDWZ256rrik:
25062	case VPSHRDWZ256rrikz:
25063	case VPSHRDWZrmi:
25064	case VPSHRDWZrmik:
25065	case VPSHRDWZrmikz:
25066	case VPSHRDWZrri:
25067	case VPSHRDWZrrik:
25068	case VPSHRDWZrrikz:
25069		return true;
25070	}
25071	return false;
25072}
25073
25074bool isVPSHLB(unsigned Opcode) {
25075	switch (Opcode) {
25076	case VPSHLBmr:
25077	case VPSHLBrm:
25078	case VPSHLBrr:
25079	case VPSHLBrr_REV:
25080		return true;
25081	}
25082	return false;
25083}
25084
25085bool isPSUBW(unsigned Opcode) {
25086	switch (Opcode) {
25087	case MMX_PSUBWrm:
25088	case MMX_PSUBWrr:
25089	case PSUBWrm:
25090	case PSUBWrr:
25091		return true;
25092	}
25093	return false;
25094}
25095
25096bool isVPSHLD(unsigned Opcode) {
25097	switch (Opcode) {
25098	case VPSHLDmr:
25099	case VPSHLDrm:
25100	case VPSHLDrr:
25101	case VPSHLDrr_REV:
25102		return true;
25103	}
25104	return false;
25105}
25106
25107bool isVPERMT2PS(unsigned Opcode) {
25108	switch (Opcode) {
25109	case VPERMT2PS128rm:
25110	case VPERMT2PS128rmb:
25111	case VPERMT2PS128rmbk:
25112	case VPERMT2PS128rmbkz:
25113	case VPERMT2PS128rmk:
25114	case VPERMT2PS128rmkz:
25115	case VPERMT2PS128rr:
25116	case VPERMT2PS128rrk:
25117	case VPERMT2PS128rrkz:
25118	case VPERMT2PS256rm:
25119	case VPERMT2PS256rmb:
25120	case VPERMT2PS256rmbk:
25121	case VPERMT2PS256rmbkz:
25122	case VPERMT2PS256rmk:
25123	case VPERMT2PS256rmkz:
25124	case VPERMT2PS256rr:
25125	case VPERMT2PS256rrk:
25126	case VPERMT2PS256rrkz:
25127	case VPERMT2PSrm:
25128	case VPERMT2PSrmb:
25129	case VPERMT2PSrmbk:
25130	case VPERMT2PSrmbkz:
25131	case VPERMT2PSrmk:
25132	case VPERMT2PSrmkz:
25133	case VPERMT2PSrr:
25134	case VPERMT2PSrrk:
25135	case VPERMT2PSrrkz:
25136		return true;
25137	}
25138	return false;
25139}
25140
25141bool isVPUNPCKLWD(unsigned Opcode) {
25142	switch (Opcode) {
25143	case VPUNPCKLWDYrm:
25144	case VPUNPCKLWDYrr:
25145	case VPUNPCKLWDZ128rm:
25146	case VPUNPCKLWDZ128rmk:
25147	case VPUNPCKLWDZ128rmkz:
25148	case VPUNPCKLWDZ128rr:
25149	case VPUNPCKLWDZ128rrk:
25150	case VPUNPCKLWDZ128rrkz:
25151	case VPUNPCKLWDZ256rm:
25152	case VPUNPCKLWDZ256rmk:
25153	case VPUNPCKLWDZ256rmkz:
25154	case VPUNPCKLWDZ256rr:
25155	case VPUNPCKLWDZ256rrk:
25156	case VPUNPCKLWDZ256rrkz:
25157	case VPUNPCKLWDZrm:
25158	case VPUNPCKLWDZrmk:
25159	case VPUNPCKLWDZrmkz:
25160	case VPUNPCKLWDZrr:
25161	case VPUNPCKLWDZrrk:
25162	case VPUNPCKLWDZrrkz:
25163	case VPUNPCKLWDrm:
25164	case VPUNPCKLWDrr:
25165		return true;
25166	}
25167	return false;
25168}
25169
25170bool isVPSHLQ(unsigned Opcode) {
25171	switch (Opcode) {
25172	case VPSHLQmr:
25173	case VPSHLQrm:
25174	case VPSHLQrr:
25175	case VPSHLQrr_REV:
25176		return true;
25177	}
25178	return false;
25179}
25180
25181bool isVPSHLW(unsigned Opcode) {
25182	switch (Opcode) {
25183	case VPSHLWmr:
25184	case VPSHLWrm:
25185	case VPSHLWrr:
25186	case VPSHLWrr_REV:
25187		return true;
25188	}
25189	return false;
25190}
25191
25192bool isLSL(unsigned Opcode) {
25193	switch (Opcode) {
25194	case LSL16rm:
25195	case LSL16rr:
25196	case LSL32rm:
25197	case LSL32rr:
25198	case LSL64rm:
25199	case LSL64rr:
25200		return true;
25201	}
25202	return false;
25203}
25204
25205bool isVBROADCASTI128(unsigned Opcode) {
25206	return Opcode == VBROADCASTI128;
25207}
25208
25209bool isLSS(unsigned Opcode) {
25210	switch (Opcode) {
25211	case LSS16rm:
25212	case LSS32rm:
25213	case LSS64rm:
25214		return true;
25215	}
25216	return false;
25217}
25218
25219bool isVPHADDD(unsigned Opcode) {
25220	switch (Opcode) {
25221	case VPHADDDYrm:
25222	case VPHADDDYrr:
25223	case VPHADDDrm:
25224	case VPHADDDrr:
25225		return true;
25226	}
25227	return false;
25228}
25229
25230bool isADDPD(unsigned Opcode) {
25231	switch (Opcode) {
25232	case ADDPDrm:
25233	case ADDPDrr:
25234		return true;
25235	}
25236	return false;
25237}
25238
25239bool isVMASKMOVPD(unsigned Opcode) {
25240	switch (Opcode) {
25241	case VMASKMOVPDYmr:
25242	case VMASKMOVPDYrm:
25243	case VMASKMOVPDmr:
25244	case VMASKMOVPDrm:
25245		return true;
25246	}
25247	return false;
25248}
25249
25250bool isADDPS(unsigned Opcode) {
25251	switch (Opcode) {
25252	case ADDPSrm:
25253	case ADDPSrr:
25254		return true;
25255	}
25256	return false;
25257}
25258
25259bool isINSB(unsigned Opcode) {
25260	return Opcode == INSB;
25261}
25262
25263bool isINSD(unsigned Opcode) {
25264	return Opcode == INSL;
25265}
25266
25267bool isVPHADDW(unsigned Opcode) {
25268	switch (Opcode) {
25269	case VPHADDWYrm:
25270	case VPHADDWYrr:
25271	case VPHADDWrm:
25272	case VPHADDWrr:
25273		return true;
25274	}
25275	return false;
25276}
25277
25278bool isLTR(unsigned Opcode) {
25279	switch (Opcode) {
25280	case LTRm:
25281	case LTRr:
25282		return true;
25283	}
25284	return false;
25285}
25286
25287bool isVMASKMOVPS(unsigned Opcode) {
25288	switch (Opcode) {
25289	case VMASKMOVPSYmr:
25290	case VMASKMOVPSYrm:
25291	case VMASKMOVPSmr:
25292	case VMASKMOVPSrm:
25293		return true;
25294	}
25295	return false;
25296}
25297
25298bool isVCVTPH2UW(unsigned Opcode) {
25299	switch (Opcode) {
25300	case VCVTPH2UWZ128rm:
25301	case VCVTPH2UWZ128rmb:
25302	case VCVTPH2UWZ128rmbk:
25303	case VCVTPH2UWZ128rmbkz:
25304	case VCVTPH2UWZ128rmk:
25305	case VCVTPH2UWZ128rmkz:
25306	case VCVTPH2UWZ128rr:
25307	case VCVTPH2UWZ128rrk:
25308	case VCVTPH2UWZ128rrkz:
25309	case VCVTPH2UWZ256rm:
25310	case VCVTPH2UWZ256rmb:
25311	case VCVTPH2UWZ256rmbk:
25312	case VCVTPH2UWZ256rmbkz:
25313	case VCVTPH2UWZ256rmk:
25314	case VCVTPH2UWZ256rmkz:
25315	case VCVTPH2UWZ256rr:
25316	case VCVTPH2UWZ256rrk:
25317	case VCVTPH2UWZ256rrkz:
25318	case VCVTPH2UWZrm:
25319	case VCVTPH2UWZrmb:
25320	case VCVTPH2UWZrmbk:
25321	case VCVTPH2UWZrmbkz:
25322	case VCVTPH2UWZrmk:
25323	case VCVTPH2UWZrmkz:
25324	case VCVTPH2UWZrr:
25325	case VCVTPH2UWZrrb:
25326	case VCVTPH2UWZrrbk:
25327	case VCVTPH2UWZrrbkz:
25328	case VCVTPH2UWZrrk:
25329	case VCVTPH2UWZrrkz:
25330		return true;
25331	}
25332	return false;
25333}
25334
25335bool isINT3(unsigned Opcode) {
25336	return Opcode == INT3;
25337}
25338
25339bool isKNOTB(unsigned Opcode) {
25340	return Opcode == KNOTBrr;
25341}
25342
25343bool isKNOTD(unsigned Opcode) {
25344	return Opcode == KNOTDrr;
25345}
25346
25347bool isINSW(unsigned Opcode) {
25348	return Opcode == INSW;
25349}
25350
25351bool isVBLENDVPD(unsigned Opcode) {
25352	switch (Opcode) {
25353	case VBLENDVPDYrm:
25354	case VBLENDVPDYrr:
25355	case VBLENDVPDrm:
25356	case VBLENDVPDrr:
25357		return true;
25358	}
25359	return false;
25360}
25361
25362bool isBLSFILL(unsigned Opcode) {
25363	switch (Opcode) {
25364	case BLSFILL32rm:
25365	case BLSFILL32rr:
25366	case BLSFILL64rm:
25367	case BLSFILL64rr:
25368		return true;
25369	}
25370	return false;
25371}
25372
25373bool isMONITOR(unsigned Opcode) {
25374	switch (Opcode) {
25375	case MONITOR32rrr:
25376	case MONITOR64rrr:
25377		return true;
25378	}
25379	return false;
25380}
25381
25382bool isKNOTQ(unsigned Opcode) {
25383	return Opcode == KNOTQrr;
25384}
25385
25386bool isCMPXCHG16B(unsigned Opcode) {
25387	return Opcode == CMPXCHG16B;
25388}
25389
25390bool isKNOTW(unsigned Opcode) {
25391	return Opcode == KNOTWrr;
25392}
25393
25394bool isPEXTRB(unsigned Opcode) {
25395	switch (Opcode) {
25396	case PEXTRBmr:
25397	case PEXTRBrr:
25398		return true;
25399	}
25400	return false;
25401}
25402
25403bool isVPRORVD(unsigned Opcode) {
25404	switch (Opcode) {
25405	case VPRORVDZ128rm:
25406	case VPRORVDZ128rmb:
25407	case VPRORVDZ128rmbk:
25408	case VPRORVDZ128rmbkz:
25409	case VPRORVDZ128rmk:
25410	case VPRORVDZ128rmkz:
25411	case VPRORVDZ128rr:
25412	case VPRORVDZ128rrk:
25413	case VPRORVDZ128rrkz:
25414	case VPRORVDZ256rm:
25415	case VPRORVDZ256rmb:
25416	case VPRORVDZ256rmbk:
25417	case VPRORVDZ256rmbkz:
25418	case VPRORVDZ256rmk:
25419	case VPRORVDZ256rmkz:
25420	case VPRORVDZ256rr:
25421	case VPRORVDZ256rrk:
25422	case VPRORVDZ256rrkz:
25423	case VPRORVDZrm:
25424	case VPRORVDZrmb:
25425	case VPRORVDZrmbk:
25426	case VPRORVDZrmbkz:
25427	case VPRORVDZrmk:
25428	case VPRORVDZrmkz:
25429	case VPRORVDZrr:
25430	case VPRORVDZrrk:
25431	case VPRORVDZrrkz:
25432		return true;
25433	}
25434	return false;
25435}
25436
25437bool isPEXTRD(unsigned Opcode) {
25438	switch (Opcode) {
25439	case PEXTRDmr:
25440	case PEXTRDrr:
25441		return true;
25442	}
25443	return false;
25444}
25445
25446bool isVAESENCLAST(unsigned Opcode) {
25447	switch (Opcode) {
25448	case VAESENCLASTYrm:
25449	case VAESENCLASTYrr:
25450	case VAESENCLASTZ128rm:
25451	case VAESENCLASTZ128rr:
25452	case VAESENCLASTZ256rm:
25453	case VAESENCLASTZ256rr:
25454	case VAESENCLASTZrm:
25455	case VAESENCLASTZrr:
25456	case VAESENCLASTrm:
25457	case VAESENCLASTrr:
25458		return true;
25459	}
25460	return false;
25461}
25462
25463bool isINTO(unsigned Opcode) {
25464	return Opcode == INTO;
25465}
25466
25467bool isVBLENDVPS(unsigned Opcode) {
25468	switch (Opcode) {
25469	case VBLENDVPSYrm:
25470	case VBLENDVPSYrr:
25471	case VBLENDVPSrm:
25472	case VBLENDVPSrr:
25473		return true;
25474	}
25475	return false;
25476}
25477
25478bool isVPRORVQ(unsigned Opcode) {
25479	switch (Opcode) {
25480	case VPRORVQZ128rm:
25481	case VPRORVQZ128rmb:
25482	case VPRORVQZ128rmbk:
25483	case VPRORVQZ128rmbkz:
25484	case VPRORVQZ128rmk:
25485	case VPRORVQZ128rmkz:
25486	case VPRORVQZ128rr:
25487	case VPRORVQZ128rrk:
25488	case VPRORVQZ128rrkz:
25489	case VPRORVQZ256rm:
25490	case VPRORVQZ256rmb:
25491	case VPRORVQZ256rmbk:
25492	case VPRORVQZ256rmbkz:
25493	case VPRORVQZ256rmk:
25494	case VPRORVQZ256rmkz:
25495	case VPRORVQZ256rr:
25496	case VPRORVQZ256rrk:
25497	case VPRORVQZ256rrkz:
25498	case VPRORVQZrm:
25499	case VPRORVQZrmb:
25500	case VPRORVQZrmbk:
25501	case VPRORVQZrmbkz:
25502	case VPRORVQZrmk:
25503	case VPRORVQZrmkz:
25504	case VPRORVQZrr:
25505	case VPRORVQZrrk:
25506	case VPRORVQZrrkz:
25507		return true;
25508	}
25509	return false;
25510}
25511
25512bool isPEXTRQ(unsigned Opcode) {
25513	switch (Opcode) {
25514	case PEXTRQmr:
25515	case PEXTRQrr:
25516		return true;
25517	}
25518	return false;
25519}
25520
25521bool isHSUBPD(unsigned Opcode) {
25522	switch (Opcode) {
25523	case HSUBPDrm:
25524	case HSUBPDrr:
25525		return true;
25526	}
25527	return false;
25528}
25529
25530bool isPEXTRW(unsigned Opcode) {
25531	switch (Opcode) {
25532	case MMX_PEXTRWrr:
25533	case PEXTRWmr:
25534	case PEXTRWrr:
25535	case PEXTRWrr_REV:
25536		return true;
25537	}
25538	return false;
25539}
25540
25541bool isFDIVRP(unsigned Opcode) {
25542	return Opcode == DIVR_FPrST0;
25543}
25544
25545bool isSCASB(unsigned Opcode) {
25546	return Opcode == SCASB;
25547}
25548
25549bool isF2XM1(unsigned Opcode) {
25550	return Opcode == F2XM1;
25551}
25552
25553bool isSCASD(unsigned Opcode) {
25554	return Opcode == SCASL;
25555}
25556
25557bool isFISUBR(unsigned Opcode) {
25558	switch (Opcode) {
25559	case SUBR_FI16m:
25560	case SUBR_FI32m:
25561		return true;
25562	}
25563	return false;
25564}
25565
25566bool isMOVLPD(unsigned Opcode) {
25567	switch (Opcode) {
25568	case MOVLPDmr:
25569	case MOVLPDrm:
25570		return true;
25571	}
25572	return false;
25573}
25574
25575bool isHSUBPS(unsigned Opcode) {
25576	switch (Opcode) {
25577	case HSUBPSrm:
25578	case HSUBPSrr:
25579		return true;
25580	}
25581	return false;
25582}
25583
25584bool isSCASQ(unsigned Opcode) {
25585	return Opcode == SCASQ;
25586}
25587
25588bool isFSTP(unsigned Opcode) {
25589	switch (Opcode) {
25590	case ST_FP32m:
25591	case ST_FP64m:
25592	case ST_FP80m:
25593	case ST_FPrr:
25594		return true;
25595	}
25596	return false;
25597}
25598
25599bool isVDBPSADBW(unsigned Opcode) {
25600	switch (Opcode) {
25601	case VDBPSADBWZ128rmi:
25602	case VDBPSADBWZ128rmik:
25603	case VDBPSADBWZ128rmikz:
25604	case VDBPSADBWZ128rri:
25605	case VDBPSADBWZ128rrik:
25606	case VDBPSADBWZ128rrikz:
25607	case VDBPSADBWZ256rmi:
25608	case VDBPSADBWZ256rmik:
25609	case VDBPSADBWZ256rmikz:
25610	case VDBPSADBWZ256rri:
25611	case VDBPSADBWZ256rrik:
25612	case VDBPSADBWZ256rrikz:
25613	case VDBPSADBWZrmi:
25614	case VDBPSADBWZrmik:
25615	case VDBPSADBWZrmikz:
25616	case VDBPSADBWZrri:
25617	case VDBPSADBWZrrik:
25618	case VDBPSADBWZrrikz:
25619		return true;
25620	}
25621	return false;
25622}
25623
25624bool isADDSD(unsigned Opcode) {
25625	switch (Opcode) {
25626	case ADDSDrm_Int:
25627	case ADDSDrr_Int:
25628		return true;
25629	}
25630	return false;
25631}
25632
25633bool isMOVLPS(unsigned Opcode) {
25634	switch (Opcode) {
25635	case MOVLPSmr:
25636	case MOVLPSrm:
25637		return true;
25638	}
25639	return false;
25640}
25641
25642bool isSCASW(unsigned Opcode) {
25643	return Opcode == SCASW;
25644}
25645
25646bool isVCVTW2PH(unsigned Opcode) {
25647	switch (Opcode) {
25648	case VCVTW2PHZ128rm:
25649	case VCVTW2PHZ128rmb:
25650	case VCVTW2PHZ128rmbk:
25651	case VCVTW2PHZ128rmbkz:
25652	case VCVTW2PHZ128rmk:
25653	case VCVTW2PHZ128rmkz:
25654	case VCVTW2PHZ128rr:
25655	case VCVTW2PHZ128rrk:
25656	case VCVTW2PHZ128rrkz:
25657	case VCVTW2PHZ256rm:
25658	case VCVTW2PHZ256rmb:
25659	case VCVTW2PHZ256rmbk:
25660	case VCVTW2PHZ256rmbkz:
25661	case VCVTW2PHZ256rmk:
25662	case VCVTW2PHZ256rmkz:
25663	case VCVTW2PHZ256rr:
25664	case VCVTW2PHZ256rrk:
25665	case VCVTW2PHZ256rrkz:
25666	case VCVTW2PHZrm:
25667	case VCVTW2PHZrmb:
25668	case VCVTW2PHZrmbk:
25669	case VCVTW2PHZrmbkz:
25670	case VCVTW2PHZrmk:
25671	case VCVTW2PHZrmkz:
25672	case VCVTW2PHZrr:
25673	case VCVTW2PHZrrb:
25674	case VCVTW2PHZrrbk:
25675	case VCVTW2PHZrrbkz:
25676	case VCVTW2PHZrrk:
25677	case VCVTW2PHZrrkz:
25678		return true;
25679	}
25680	return false;
25681}
25682
25683bool isVPTEST(unsigned Opcode) {
25684	switch (Opcode) {
25685	case VPTESTYrm:
25686	case VPTESTYrr:
25687	case VPTESTrm:
25688	case VPTESTrr:
25689		return true;
25690	}
25691	return false;
25692}
25693
25694bool isFLD1(unsigned Opcode) {
25695	return Opcode == LD_F1;
25696}
25697
25698bool isWBINVD(unsigned Opcode) {
25699	return Opcode == WBINVD;
25700}
25701
25702bool isADDSS(unsigned Opcode) {
25703	switch (Opcode) {
25704	case ADDSSrm_Int:
25705	case ADDSSrr_Int:
25706		return true;
25707	}
25708	return false;
25709}
25710
25711bool isPOP(unsigned Opcode) {
25712	switch (Opcode) {
25713	case POP16r:
25714	case POP16rmm:
25715	case POP16rmr:
25716	case POP32r:
25717	case POP32rmm:
25718	case POP32rmr:
25719	case POP64r:
25720	case POP64rmm:
25721	case POP64rmr:
25722	case POPDS16:
25723	case POPDS32:
25724	case POPES16:
25725	case POPES32:
25726	case POPFS16:
25727	case POPFS32:
25728	case POPFS64:
25729	case POPGS16:
25730	case POPGS32:
25731	case POPGS64:
25732	case POPSS16:
25733	case POPSS32:
25734		return true;
25735	}
25736	return false;
25737}
25738
25739bool isINVD(unsigned Opcode) {
25740	return Opcode == INVD;
25741}
25742
25743bool isPOR(unsigned Opcode) {
25744	switch (Opcode) {
25745	case MMX_PORrm:
25746	case MMX_PORrr:
25747	case PORrm:
25748	case PORrr:
25749		return true;
25750	}
25751	return false;
25752}
25753
25754bool isAND(unsigned Opcode) {
25755	switch (Opcode) {
25756	case AND16i16:
25757	case AND16mi:
25758	case AND16mi8:
25759	case AND16mr:
25760	case AND16ri:
25761	case AND16ri8:
25762	case AND16rm:
25763	case AND16rr:
25764	case AND16rr_REV:
25765	case AND32i32:
25766	case AND32mi:
25767	case AND32mi8:
25768	case AND32mr:
25769	case AND32ri:
25770	case AND32ri8:
25771	case AND32rm:
25772	case AND32rr:
25773	case AND32rr_REV:
25774	case AND64i32:
25775	case AND64mi32:
25776	case AND64mi8:
25777	case AND64mr:
25778	case AND64ri32:
25779	case AND64ri8:
25780	case AND64rm:
25781	case AND64rr:
25782	case AND64rr_REV:
25783	case AND8i8:
25784	case AND8mi:
25785	case AND8mi8:
25786	case AND8mr:
25787	case AND8ri:
25788	case AND8ri8:
25789	case AND8rm:
25790	case AND8rr:
25791	case AND8rr_REV:
25792		return true;
25793	}
25794	return false;
25795}
25796
25797bool isFYL2XP1(unsigned Opcode) {
25798	return Opcode == FYL2XP1;
25799}
25800
25801bool isFSUB(unsigned Opcode) {
25802	switch (Opcode) {
25803	case SUB_F32m:
25804	case SUB_F64m:
25805	case SUB_FST0r:
25806	case SUB_FrST0:
25807		return true;
25808	}
25809	return false;
25810}
25811
25812bool isENTER(unsigned Opcode) {
25813	return Opcode == ENTER;
25814}
25815
25816bool isVMOVSLDUP(unsigned Opcode) {
25817	switch (Opcode) {
25818	case VMOVSLDUPYrm:
25819	case VMOVSLDUPYrr:
25820	case VMOVSLDUPZ128rm:
25821	case VMOVSLDUPZ128rmk:
25822	case VMOVSLDUPZ128rmkz:
25823	case VMOVSLDUPZ128rr:
25824	case VMOVSLDUPZ128rrk:
25825	case VMOVSLDUPZ128rrkz:
25826	case VMOVSLDUPZ256rm:
25827	case VMOVSLDUPZ256rmk:
25828	case VMOVSLDUPZ256rmkz:
25829	case VMOVSLDUPZ256rr:
25830	case VMOVSLDUPZ256rrk:
25831	case VMOVSLDUPZ256rrkz:
25832	case VMOVSLDUPZrm:
25833	case VMOVSLDUPZrmk:
25834	case VMOVSLDUPZrmkz:
25835	case VMOVSLDUPZrr:
25836	case VMOVSLDUPZrrk:
25837	case VMOVSLDUPZrrkz:
25838	case VMOVSLDUPrm:
25839	case VMOVSLDUPrr:
25840		return true;
25841	}
25842	return false;
25843}
25844
25845bool isADCX(unsigned Opcode) {
25846	switch (Opcode) {
25847	case ADCX32rm:
25848	case ADCX32rr:
25849	case ADCX64rm:
25850	case ADCX64rr:
25851		return true;
25852	}
25853	return false;
25854}
25855
25856bool isXADD(unsigned Opcode) {
25857	switch (Opcode) {
25858	case XADD16rm:
25859	case XADD16rr:
25860	case XADD32rm:
25861	case XADD32rr:
25862	case XADD64rm:
25863	case XADD64rr:
25864	case XADD8rm:
25865	case XADD8rr:
25866		return true;
25867	}
25868	return false;
25869}
25870
25871bool isAESENC(unsigned Opcode) {
25872	switch (Opcode) {
25873	case AESENCrm:
25874	case AESENCrr:
25875		return true;
25876	}
25877	return false;
25878}
25879
25880bool isFLDZ(unsigned Opcode) {
25881	return Opcode == LD_F0;
25882}
25883
25884bool isXRSTORS64(unsigned Opcode) {
25885	return Opcode == XRSTORS64;
25886}
25887
25888bool isVCVTTSH2USI(unsigned Opcode) {
25889	switch (Opcode) {
25890	case VCVTTSH2USI64Zrm_Int:
25891	case VCVTTSH2USI64Zrr_Int:
25892	case VCVTTSH2USI64Zrrb_Int:
25893	case VCVTTSH2USIZrm_Int:
25894	case VCVTTSH2USIZrr_Int:
25895	case VCVTTSH2USIZrrb_Int:
25896		return true;
25897	}
25898	return false;
25899}
25900
25901bool isVMULPD(unsigned Opcode) {
25902	switch (Opcode) {
25903	case VMULPDYrm:
25904	case VMULPDYrr:
25905	case VMULPDZ128rm:
25906	case VMULPDZ128rmb:
25907	case VMULPDZ128rmbk:
25908	case VMULPDZ128rmbkz:
25909	case VMULPDZ128rmk:
25910	case VMULPDZ128rmkz:
25911	case VMULPDZ128rr:
25912	case VMULPDZ128rrk:
25913	case VMULPDZ128rrkz:
25914	case VMULPDZ256rm:
25915	case VMULPDZ256rmb:
25916	case VMULPDZ256rmbk:
25917	case VMULPDZ256rmbkz:
25918	case VMULPDZ256rmk:
25919	case VMULPDZ256rmkz:
25920	case VMULPDZ256rr:
25921	case VMULPDZ256rrk:
25922	case VMULPDZ256rrkz:
25923	case VMULPDZrm:
25924	case VMULPDZrmb:
25925	case VMULPDZrmbk:
25926	case VMULPDZrmbkz:
25927	case VMULPDZrmk:
25928	case VMULPDZrmkz:
25929	case VMULPDZrr:
25930	case VMULPDZrrb:
25931	case VMULPDZrrbk:
25932	case VMULPDZrrbkz:
25933	case VMULPDZrrk:
25934	case VMULPDZrrkz:
25935	case VMULPDrm:
25936	case VMULPDrr:
25937		return true;
25938	}
25939	return false;
25940}
25941
25942bool isFDIVP(unsigned Opcode) {
25943	return Opcode == DIV_FPrST0;
25944}
25945
25946bool isVGETMANTPD(unsigned Opcode) {
25947	switch (Opcode) {
25948	case VGETMANTPDZ128rmbi:
25949	case VGETMANTPDZ128rmbik:
25950	case VGETMANTPDZ128rmbikz:
25951	case VGETMANTPDZ128rmi:
25952	case VGETMANTPDZ128rmik:
25953	case VGETMANTPDZ128rmikz:
25954	case VGETMANTPDZ128rri:
25955	case VGETMANTPDZ128rrik:
25956	case VGETMANTPDZ128rrikz:
25957	case VGETMANTPDZ256rmbi:
25958	case VGETMANTPDZ256rmbik:
25959	case VGETMANTPDZ256rmbikz:
25960	case VGETMANTPDZ256rmi:
25961	case VGETMANTPDZ256rmik:
25962	case VGETMANTPDZ256rmikz:
25963	case VGETMANTPDZ256rri:
25964	case VGETMANTPDZ256rrik:
25965	case VGETMANTPDZ256rrikz:
25966	case VGETMANTPDZrmbi:
25967	case VGETMANTPDZrmbik:
25968	case VGETMANTPDZrmbikz:
25969	case VGETMANTPDZrmi:
25970	case VGETMANTPDZrmik:
25971	case VGETMANTPDZrmikz:
25972	case VGETMANTPDZrri:
25973	case VGETMANTPDZrrib:
25974	case VGETMANTPDZrribk:
25975	case VGETMANTPDZrribkz:
25976	case VGETMANTPDZrrik:
25977	case VGETMANTPDZrrikz:
25978		return true;
25979	}
25980	return false;
25981}
25982
25983bool isFDIVR(unsigned Opcode) {
25984	switch (Opcode) {
25985	case DIVR_F32m:
25986	case DIVR_F64m:
25987	case DIVR_FST0r:
25988	case DIVR_FrST0:
25989		return true;
25990	}
25991	return false;
25992}
25993
25994bool isVPMOVM2D(unsigned Opcode) {
25995	switch (Opcode) {
25996	case VPMOVM2DZ128rr:
25997	case VPMOVM2DZ256rr:
25998	case VPMOVM2DZrr:
25999		return true;
26000	}
26001	return false;
26002}
26003
26004bool isVMULPH(unsigned Opcode) {
26005	switch (Opcode) {
26006	case VMULPHZ128rm:
26007	case VMULPHZ128rmb:
26008	case VMULPHZ128rmbk:
26009	case VMULPHZ128rmbkz:
26010	case VMULPHZ128rmk:
26011	case VMULPHZ128rmkz:
26012	case VMULPHZ128rr:
26013	case VMULPHZ128rrk:
26014	case VMULPHZ128rrkz:
26015	case VMULPHZ256rm:
26016	case VMULPHZ256rmb:
26017	case VMULPHZ256rmbk:
26018	case VMULPHZ256rmbkz:
26019	case VMULPHZ256rmk:
26020	case VMULPHZ256rmkz:
26021	case VMULPHZ256rr:
26022	case VMULPHZ256rrk:
26023	case VMULPHZ256rrkz:
26024	case VMULPHZrm:
26025	case VMULPHZrmb:
26026	case VMULPHZrmbk:
26027	case VMULPHZrmbkz:
26028	case VMULPHZrmk:
26029	case VMULPHZrmkz:
26030	case VMULPHZrr:
26031	case VMULPHZrrb:
26032	case VMULPHZrrbk:
26033	case VMULPHZrrbkz:
26034	case VMULPHZrrk:
26035	case VMULPHZrrkz:
26036		return true;
26037	}
26038	return false;
26039}
26040
26041bool isVGETMANTPH(unsigned Opcode) {
26042	switch (Opcode) {
26043	case VGETMANTPHZ128rmbi:
26044	case VGETMANTPHZ128rmbik:
26045	case VGETMANTPHZ128rmbikz:
26046	case VGETMANTPHZ128rmi:
26047	case VGETMANTPHZ128rmik:
26048	case VGETMANTPHZ128rmikz:
26049	case VGETMANTPHZ128rri:
26050	case VGETMANTPHZ128rrik:
26051	case VGETMANTPHZ128rrikz:
26052	case VGETMANTPHZ256rmbi:
26053	case VGETMANTPHZ256rmbik:
26054	case VGETMANTPHZ256rmbikz:
26055	case VGETMANTPHZ256rmi:
26056	case VGETMANTPHZ256rmik:
26057	case VGETMANTPHZ256rmikz:
26058	case VGETMANTPHZ256rri:
26059	case VGETMANTPHZ256rrik:
26060	case VGETMANTPHZ256rrikz:
26061	case VGETMANTPHZrmbi:
26062	case VGETMANTPHZrmbik:
26063	case VGETMANTPHZrmbikz:
26064	case VGETMANTPHZrmi:
26065	case VGETMANTPHZrmik:
26066	case VGETMANTPHZrmikz:
26067	case VGETMANTPHZrri:
26068	case VGETMANTPHZrrib:
26069	case VGETMANTPHZrribk:
26070	case VGETMANTPHZrribkz:
26071	case VGETMANTPHZrrik:
26072	case VGETMANTPHZrrikz:
26073		return true;
26074	}
26075	return false;
26076}
26077
26078bool isVPMOVM2B(unsigned Opcode) {
26079	switch (Opcode) {
26080	case VPMOVM2BZ128rr:
26081	case VPMOVM2BZ256rr:
26082	case VPMOVM2BZrr:
26083		return true;
26084	}
26085	return false;
26086}
26087
26088bool isAOR(unsigned Opcode) {
26089	switch (Opcode) {
26090	case AOR32mr:
26091	case AOR64mr:
26092		return true;
26093	}
26094	return false;
26095}
26096
26097bool isVPHSUBSW(unsigned Opcode) {
26098	switch (Opcode) {
26099	case VPHSUBSWYrm:
26100	case VPHSUBSWYrr:
26101	case VPHSUBSWrm:
26102	case VPHSUBSWrr:
26103		return true;
26104	}
26105	return false;
26106}
26107
26108bool isVMULPS(unsigned Opcode) {
26109	switch (Opcode) {
26110	case VMULPSYrm:
26111	case VMULPSYrr:
26112	case VMULPSZ128rm:
26113	case VMULPSZ128rmb:
26114	case VMULPSZ128rmbk:
26115	case VMULPSZ128rmbkz:
26116	case VMULPSZ128rmk:
26117	case VMULPSZ128rmkz:
26118	case VMULPSZ128rr:
26119	case VMULPSZ128rrk:
26120	case VMULPSZ128rrkz:
26121	case VMULPSZ256rm:
26122	case VMULPSZ256rmb:
26123	case VMULPSZ256rmbk:
26124	case VMULPSZ256rmbkz:
26125	case VMULPSZ256rmk:
26126	case VMULPSZ256rmkz:
26127	case VMULPSZ256rr:
26128	case VMULPSZ256rrk:
26129	case VMULPSZ256rrkz:
26130	case VMULPSZrm:
26131	case VMULPSZrmb:
26132	case VMULPSZrmbk:
26133	case VMULPSZrmbkz:
26134	case VMULPSZrmk:
26135	case VMULPSZrmkz:
26136	case VMULPSZrr:
26137	case VMULPSZrrb:
26138	case VMULPSZrrbk:
26139	case VMULPSZrrbkz:
26140	case VMULPSZrrk:
26141	case VMULPSZrrkz:
26142	case VMULPSrm:
26143	case VMULPSrr:
26144		return true;
26145	}
26146	return false;
26147}
26148
26149bool isVPMOVM2Q(unsigned Opcode) {
26150	switch (Opcode) {
26151	case VPMOVM2QZ128rr:
26152	case VPMOVM2QZ256rr:
26153	case VPMOVM2QZrr:
26154		return true;
26155	}
26156	return false;
26157}
26158
26159bool isMOVNTDQ(unsigned Opcode) {
26160	return Opcode == MOVNTDQmr;
26161}
26162
26163bool isVGETMANTPS(unsigned Opcode) {
26164	switch (Opcode) {
26165	case VGETMANTPSZ128rmbi:
26166	case VGETMANTPSZ128rmbik:
26167	case VGETMANTPSZ128rmbikz:
26168	case VGETMANTPSZ128rmi:
26169	case VGETMANTPSZ128rmik:
26170	case VGETMANTPSZ128rmikz:
26171	case VGETMANTPSZ128rri:
26172	case VGETMANTPSZ128rrik:
26173	case VGETMANTPSZ128rrikz:
26174	case VGETMANTPSZ256rmbi:
26175	case VGETMANTPSZ256rmbik:
26176	case VGETMANTPSZ256rmbikz:
26177	case VGETMANTPSZ256rmi:
26178	case VGETMANTPSZ256rmik:
26179	case VGETMANTPSZ256rmikz:
26180	case VGETMANTPSZ256rri:
26181	case VGETMANTPSZ256rrik:
26182	case VGETMANTPSZ256rrikz:
26183	case VGETMANTPSZrmbi:
26184	case VGETMANTPSZrmbik:
26185	case VGETMANTPSZrmbikz:
26186	case VGETMANTPSZrmi:
26187	case VGETMANTPSZrmik:
26188	case VGETMANTPSZrmikz:
26189	case VGETMANTPSZrri:
26190	case VGETMANTPSZrrib:
26191	case VGETMANTPSZrribk:
26192	case VGETMANTPSZrribkz:
26193	case VGETMANTPSZrrik:
26194	case VGETMANTPSZrrikz:
26195		return true;
26196	}
26197	return false;
26198}
26199
26200bool isVPCMPESTRI(unsigned Opcode) {
26201	switch (Opcode) {
26202	case VPCMPESTRIrm:
26203	case VPCMPESTRIrr:
26204		return true;
26205	}
26206	return false;
26207}
26208
26209bool isVPMOVM2W(unsigned Opcode) {
26210	switch (Opcode) {
26211	case VPMOVM2WZ128rr:
26212	case VPMOVM2WZ256rr:
26213	case VPMOVM2WZrr:
26214		return true;
26215	}
26216	return false;
26217}
26218
26219bool isVPCMPESTRM(unsigned Opcode) {
26220	switch (Opcode) {
26221	case VPCMPESTRMrm:
26222	case VPCMPESTRMrr:
26223		return true;
26224	}
26225	return false;
26226}
26227
26228bool isSYSENTER(unsigned Opcode) {
26229	return Opcode == SYSENTER;
26230}
26231
26232bool isVPERMPD(unsigned Opcode) {
26233	switch (Opcode) {
26234	case VPERMPDYmi:
26235	case VPERMPDYri:
26236	case VPERMPDZ256mbi:
26237	case VPERMPDZ256mbik:
26238	case VPERMPDZ256mbikz:
26239	case VPERMPDZ256mi:
26240	case VPERMPDZ256mik:
26241	case VPERMPDZ256mikz:
26242	case VPERMPDZ256ri:
26243	case VPERMPDZ256rik:
26244	case VPERMPDZ256rikz:
26245	case VPERMPDZ256rm:
26246	case VPERMPDZ256rmb:
26247	case VPERMPDZ256rmbk:
26248	case VPERMPDZ256rmbkz:
26249	case VPERMPDZ256rmk:
26250	case VPERMPDZ256rmkz:
26251	case VPERMPDZ256rr:
26252	case VPERMPDZ256rrk:
26253	case VPERMPDZ256rrkz:
26254	case VPERMPDZmbi:
26255	case VPERMPDZmbik:
26256	case VPERMPDZmbikz:
26257	case VPERMPDZmi:
26258	case VPERMPDZmik:
26259	case VPERMPDZmikz:
26260	case VPERMPDZri:
26261	case VPERMPDZrik:
26262	case VPERMPDZrikz:
26263	case VPERMPDZrm:
26264	case VPERMPDZrmb:
26265	case VPERMPDZrmbk:
26266	case VPERMPDZrmbkz:
26267	case VPERMPDZrmk:
26268	case VPERMPDZrmkz:
26269	case VPERMPDZrr:
26270	case VPERMPDZrrk:
26271	case VPERMPDZrrkz:
26272		return true;
26273	}
26274	return false;
26275}
26276
26277bool isVCVTTPH2QQ(unsigned Opcode) {
26278	switch (Opcode) {
26279	case VCVTTPH2QQZ128rm:
26280	case VCVTTPH2QQZ128rmb:
26281	case VCVTTPH2QQZ128rmbk:
26282	case VCVTTPH2QQZ128rmbkz:
26283	case VCVTTPH2QQZ128rmk:
26284	case VCVTTPH2QQZ128rmkz:
26285	case VCVTTPH2QQZ128rr:
26286	case VCVTTPH2QQZ128rrk:
26287	case VCVTTPH2QQZ128rrkz:
26288	case VCVTTPH2QQZ256rm:
26289	case VCVTTPH2QQZ256rmb:
26290	case VCVTTPH2QQZ256rmbk:
26291	case VCVTTPH2QQZ256rmbkz:
26292	case VCVTTPH2QQZ256rmk:
26293	case VCVTTPH2QQZ256rmkz:
26294	case VCVTTPH2QQZ256rr:
26295	case VCVTTPH2QQZ256rrk:
26296	case VCVTTPH2QQZ256rrkz:
26297	case VCVTTPH2QQZrm:
26298	case VCVTTPH2QQZrmb:
26299	case VCVTTPH2QQZrmbk:
26300	case VCVTTPH2QQZrmbkz:
26301	case VCVTTPH2QQZrmk:
26302	case VCVTTPH2QQZrmkz:
26303	case VCVTTPH2QQZrr:
26304	case VCVTTPH2QQZrrb:
26305	case VCVTTPH2QQZrrbk:
26306	case VCVTTPH2QQZrrbkz:
26307	case VCVTTPH2QQZrrk:
26308	case VCVTTPH2QQZrrkz:
26309		return true;
26310	}
26311	return false;
26312}
26313
26314bool isPUSHF(unsigned Opcode) {
26315	return Opcode == PUSHF16;
26316}
26317
26318bool isPXOR(unsigned Opcode) {
26319	switch (Opcode) {
26320	case MMX_PXORrm:
26321	case MMX_PXORrr:
26322	case PXORrm:
26323	case PXORrr:
26324		return true;
26325	}
26326	return false;
26327}
26328
26329bool isCMPXCHG(unsigned Opcode) {
26330	switch (Opcode) {
26331	case CMPXCHG16rm:
26332	case CMPXCHG16rr:
26333	case CMPXCHG32rm:
26334	case CMPXCHG32rr:
26335	case CMPXCHG64rm:
26336	case CMPXCHG64rr:
26337	case CMPXCHG8rm:
26338	case CMPXCHG8rr:
26339		return true;
26340	}
26341	return false;
26342}
26343
26344bool isVPERMPS(unsigned Opcode) {
26345	switch (Opcode) {
26346	case VPERMPSYrm:
26347	case VPERMPSYrr:
26348	case VPERMPSZ256rm:
26349	case VPERMPSZ256rmb:
26350	case VPERMPSZ256rmbk:
26351	case VPERMPSZ256rmbkz:
26352	case VPERMPSZ256rmk:
26353	case VPERMPSZ256rmkz:
26354	case VPERMPSZ256rr:
26355	case VPERMPSZ256rrk:
26356	case VPERMPSZ256rrkz:
26357	case VPERMPSZrm:
26358	case VPERMPSZrmb:
26359	case VPERMPSZrmbk:
26360	case VPERMPSZrmbkz:
26361	case VPERMPSZrmk:
26362	case VPERMPSZrmkz:
26363	case VPERMPSZrr:
26364	case VPERMPSZrrk:
26365	case VPERMPSZrrkz:
26366		return true;
26367	}
26368	return false;
26369}
26370
26371bool isVMRESUME(unsigned Opcode) {
26372	return Opcode == VMRESUME;
26373}
26374
26375bool isVPSLLD(unsigned Opcode) {
26376	switch (Opcode) {
26377	case VPSLLDYri:
26378	case VPSLLDYrm:
26379	case VPSLLDYrr:
26380	case VPSLLDZ128mbi:
26381	case VPSLLDZ128mbik:
26382	case VPSLLDZ128mbikz:
26383	case VPSLLDZ128mi:
26384	case VPSLLDZ128mik:
26385	case VPSLLDZ128mikz:
26386	case VPSLLDZ128ri:
26387	case VPSLLDZ128rik:
26388	case VPSLLDZ128rikz:
26389	case VPSLLDZ128rm:
26390	case VPSLLDZ128rmk:
26391	case VPSLLDZ128rmkz:
26392	case VPSLLDZ128rr:
26393	case VPSLLDZ128rrk:
26394	case VPSLLDZ128rrkz:
26395	case VPSLLDZ256mbi:
26396	case VPSLLDZ256mbik:
26397	case VPSLLDZ256mbikz:
26398	case VPSLLDZ256mi:
26399	case VPSLLDZ256mik:
26400	case VPSLLDZ256mikz:
26401	case VPSLLDZ256ri:
26402	case VPSLLDZ256rik:
26403	case VPSLLDZ256rikz:
26404	case VPSLLDZ256rm:
26405	case VPSLLDZ256rmk:
26406	case VPSLLDZ256rmkz:
26407	case VPSLLDZ256rr:
26408	case VPSLLDZ256rrk:
26409	case VPSLLDZ256rrkz:
26410	case VPSLLDZmbi:
26411	case VPSLLDZmbik:
26412	case VPSLLDZmbikz:
26413	case VPSLLDZmi:
26414	case VPSLLDZmik:
26415	case VPSLLDZmikz:
26416	case VPSLLDZri:
26417	case VPSLLDZrik:
26418	case VPSLLDZrikz:
26419	case VPSLLDZrm:
26420	case VPSLLDZrmk:
26421	case VPSLLDZrmkz:
26422	case VPSLLDZrr:
26423	case VPSLLDZrrk:
26424	case VPSLLDZrrkz:
26425	case VPSLLDri:
26426	case VPSLLDrm:
26427	case VPSLLDrr:
26428		return true;
26429	}
26430	return false;
26431}
26432
26433bool isVPSLLQ(unsigned Opcode) {
26434	switch (Opcode) {
26435	case VPSLLQYri:
26436	case VPSLLQYrm:
26437	case VPSLLQYrr:
26438	case VPSLLQZ128mbi:
26439	case VPSLLQZ128mbik:
26440	case VPSLLQZ128mbikz:
26441	case VPSLLQZ128mi:
26442	case VPSLLQZ128mik:
26443	case VPSLLQZ128mikz:
26444	case VPSLLQZ128ri:
26445	case VPSLLQZ128rik:
26446	case VPSLLQZ128rikz:
26447	case VPSLLQZ128rm:
26448	case VPSLLQZ128rmk:
26449	case VPSLLQZ128rmkz:
26450	case VPSLLQZ128rr:
26451	case VPSLLQZ128rrk:
26452	case VPSLLQZ128rrkz:
26453	case VPSLLQZ256mbi:
26454	case VPSLLQZ256mbik:
26455	case VPSLLQZ256mbikz:
26456	case VPSLLQZ256mi:
26457	case VPSLLQZ256mik:
26458	case VPSLLQZ256mikz:
26459	case VPSLLQZ256ri:
26460	case VPSLLQZ256rik:
26461	case VPSLLQZ256rikz:
26462	case VPSLLQZ256rm:
26463	case VPSLLQZ256rmk:
26464	case VPSLLQZ256rmkz:
26465	case VPSLLQZ256rr:
26466	case VPSLLQZ256rrk:
26467	case VPSLLQZ256rrkz:
26468	case VPSLLQZmbi:
26469	case VPSLLQZmbik:
26470	case VPSLLQZmbikz:
26471	case VPSLLQZmi:
26472	case VPSLLQZmik:
26473	case VPSLLQZmikz:
26474	case VPSLLQZri:
26475	case VPSLLQZrik:
26476	case VPSLLQZrikz:
26477	case VPSLLQZrm:
26478	case VPSLLQZrmk:
26479	case VPSLLQZrmkz:
26480	case VPSLLQZrr:
26481	case VPSLLQZrrk:
26482	case VPSLLQZrrkz:
26483	case VPSLLQri:
26484	case VPSLLQrm:
26485	case VPSLLQrr:
26486		return true;
26487	}
26488	return false;
26489}
26490
26491bool isVEXTRACTF32X4(unsigned Opcode) {
26492	switch (Opcode) {
26493	case VEXTRACTF32x4Z256mr:
26494	case VEXTRACTF32x4Z256mrk:
26495	case VEXTRACTF32x4Z256rr:
26496	case VEXTRACTF32x4Z256rrk:
26497	case VEXTRACTF32x4Z256rrkz:
26498	case VEXTRACTF32x4Zmr:
26499	case VEXTRACTF32x4Zmrk:
26500	case VEXTRACTF32x4Zrr:
26501	case VEXTRACTF32x4Zrrk:
26502	case VEXTRACTF32x4Zrrkz:
26503		return true;
26504	}
26505	return false;
26506}
26507
26508bool isVPSLLW(unsigned Opcode) {
26509	switch (Opcode) {
26510	case VPSLLWYri:
26511	case VPSLLWYrm:
26512	case VPSLLWYrr:
26513	case VPSLLWZ128mi:
26514	case VPSLLWZ128mik:
26515	case VPSLLWZ128mikz:
26516	case VPSLLWZ128ri:
26517	case VPSLLWZ128rik:
26518	case VPSLLWZ128rikz:
26519	case VPSLLWZ128rm:
26520	case VPSLLWZ128rmk:
26521	case VPSLLWZ128rmkz:
26522	case VPSLLWZ128rr:
26523	case VPSLLWZ128rrk:
26524	case VPSLLWZ128rrkz:
26525	case VPSLLWZ256mi:
26526	case VPSLLWZ256mik:
26527	case VPSLLWZ256mikz:
26528	case VPSLLWZ256ri:
26529	case VPSLLWZ256rik:
26530	case VPSLLWZ256rikz:
26531	case VPSLLWZ256rm:
26532	case VPSLLWZ256rmk:
26533	case VPSLLWZ256rmkz:
26534	case VPSLLWZ256rr:
26535	case VPSLLWZ256rrk:
26536	case VPSLLWZ256rrkz:
26537	case VPSLLWZmi:
26538	case VPSLLWZmik:
26539	case VPSLLWZmikz:
26540	case VPSLLWZri:
26541	case VPSLLWZrik:
26542	case VPSLLWZrikz:
26543	case VPSLLWZrm:
26544	case VPSLLWZrmk:
26545	case VPSLLWZrmkz:
26546	case VPSLLWZrr:
26547	case VPSLLWZrrk:
26548	case VPSLLWZrrkz:
26549	case VPSLLWri:
26550	case VPSLLWrm:
26551	case VPSLLWrr:
26552		return true;
26553	}
26554	return false;
26555}
26556
26557bool isBLSI(unsigned Opcode) {
26558	switch (Opcode) {
26559	case BLSI32rm:
26560	case BLSI32rr:
26561	case BLSI64rm:
26562	case BLSI64rr:
26563		return true;
26564	}
26565	return false;
26566}
26567
26568bool isVEXTRACTF32X8(unsigned Opcode) {
26569	switch (Opcode) {
26570	case VEXTRACTF32x8Zmr:
26571	case VEXTRACTF32x8Zmrk:
26572	case VEXTRACTF32x8Zrr:
26573	case VEXTRACTF32x8Zrrk:
26574	case VEXTRACTF32x8Zrrkz:
26575		return true;
26576	}
26577	return false;
26578}
26579
26580bool isBLSR(unsigned Opcode) {
26581	switch (Opcode) {
26582	case BLSR32rm:
26583	case BLSR32rr:
26584	case BLSR64rm:
26585	case BLSR64rr:
26586		return true;
26587	}
26588	return false;
26589}
26590
26591bool isVMULSD(unsigned Opcode) {
26592	switch (Opcode) {
26593	case VMULSDZrm_Int:
26594	case VMULSDZrm_Intk:
26595	case VMULSDZrm_Intkz:
26596	case VMULSDZrr_Int:
26597	case VMULSDZrr_Intk:
26598	case VMULSDZrr_Intkz:
26599	case VMULSDZrrb_Int:
26600	case VMULSDZrrb_Intk:
26601	case VMULSDZrrb_Intkz:
26602	case VMULSDrm_Int:
26603	case VMULSDrr_Int:
26604		return true;
26605	}
26606	return false;
26607}
26608
26609bool isVGETMANTSD(unsigned Opcode) {
26610	switch (Opcode) {
26611	case VGETMANTSDZrmi:
26612	case VGETMANTSDZrmik:
26613	case VGETMANTSDZrmikz:
26614	case VGETMANTSDZrri:
26615	case VGETMANTSDZrrib:
26616	case VGETMANTSDZrribk:
26617	case VGETMANTSDZrribkz:
26618	case VGETMANTSDZrrik:
26619	case VGETMANTSDZrrikz:
26620		return true;
26621	}
26622	return false;
26623}
26624
26625bool isVPCMPEQB(unsigned Opcode) {
26626	switch (Opcode) {
26627	case VPCMPEQBYrm:
26628	case VPCMPEQBYrr:
26629	case VPCMPEQBZ128rm:
26630	case VPCMPEQBZ128rmk:
26631	case VPCMPEQBZ128rr:
26632	case VPCMPEQBZ128rrk:
26633	case VPCMPEQBZ256rm:
26634	case VPCMPEQBZ256rmk:
26635	case VPCMPEQBZ256rr:
26636	case VPCMPEQBZ256rrk:
26637	case VPCMPEQBZrm:
26638	case VPCMPEQBZrmk:
26639	case VPCMPEQBZrr:
26640	case VPCMPEQBZrrk:
26641	case VPCMPEQBrm:
26642	case VPCMPEQBrr:
26643		return true;
26644	}
26645	return false;
26646}
26647
26648bool isVMULSH(unsigned Opcode) {
26649	switch (Opcode) {
26650	case VMULSHZrm_Int:
26651	case VMULSHZrm_Intk:
26652	case VMULSHZrm_Intkz:
26653	case VMULSHZrr_Int:
26654	case VMULSHZrr_Intk:
26655	case VMULSHZrr_Intkz:
26656	case VMULSHZrrb_Int:
26657	case VMULSHZrrb_Intk:
26658	case VMULSHZrrb_Intkz:
26659		return true;
26660	}
26661	return false;
26662}
26663
26664bool isVPCMPEQD(unsigned Opcode) {
26665	switch (Opcode) {
26666	case VPCMPEQDYrm:
26667	case VPCMPEQDYrr:
26668	case VPCMPEQDZ128rm:
26669	case VPCMPEQDZ128rmb:
26670	case VPCMPEQDZ128rmbk:
26671	case VPCMPEQDZ128rmk:
26672	case VPCMPEQDZ128rr:
26673	case VPCMPEQDZ128rrk:
26674	case VPCMPEQDZ256rm:
26675	case VPCMPEQDZ256rmb:
26676	case VPCMPEQDZ256rmbk:
26677	case VPCMPEQDZ256rmk:
26678	case VPCMPEQDZ256rr:
26679	case VPCMPEQDZ256rrk:
26680	case VPCMPEQDZrm:
26681	case VPCMPEQDZrmb:
26682	case VPCMPEQDZrmbk:
26683	case VPCMPEQDZrmk:
26684	case VPCMPEQDZrr:
26685	case VPCMPEQDZrrk:
26686	case VPCMPEQDrm:
26687	case VPCMPEQDrr:
26688		return true;
26689	}
26690	return false;
26691}
26692
26693bool isVGETMANTSH(unsigned Opcode) {
26694	switch (Opcode) {
26695	case VGETMANTSHZrmi:
26696	case VGETMANTSHZrmik:
26697	case VGETMANTSHZrmikz:
26698	case VGETMANTSHZrri:
26699	case VGETMANTSHZrrib:
26700	case VGETMANTSHZrribk:
26701	case VGETMANTSHZrribkz:
26702	case VGETMANTSHZrrik:
26703	case VGETMANTSHZrrikz:
26704		return true;
26705	}
26706	return false;
26707}
26708
26709bool isLMSW(unsigned Opcode) {
26710	switch (Opcode) {
26711	case LMSW16m:
26712	case LMSW16r:
26713		return true;
26714	}
26715	return false;
26716}
26717
26718bool isFNSTENV(unsigned Opcode) {
26719	return Opcode == FSTENVm;
26720}
26721
26722bool isVMULSS(unsigned Opcode) {
26723	switch (Opcode) {
26724	case VMULSSZrm_Int:
26725	case VMULSSZrm_Intk:
26726	case VMULSSZrm_Intkz:
26727	case VMULSSZrr_Int:
26728	case VMULSSZrr_Intk:
26729	case VMULSSZrr_Intkz:
26730	case VMULSSZrrb_Int:
26731	case VMULSSZrrb_Intk:
26732	case VMULSSZrrb_Intkz:
26733	case VMULSSrm_Int:
26734	case VMULSSrr_Int:
26735		return true;
26736	}
26737	return false;
26738}
26739
26740bool isVGETMANTSS(unsigned Opcode) {
26741	switch (Opcode) {
26742	case VGETMANTSSZrmi:
26743	case VGETMANTSSZrmik:
26744	case VGETMANTSSZrmikz:
26745	case VGETMANTSSZrri:
26746	case VGETMANTSSZrrib:
26747	case VGETMANTSSZrribk:
26748	case VGETMANTSSZrribkz:
26749	case VGETMANTSSZrrik:
26750	case VGETMANTSSZrrikz:
26751		return true;
26752	}
26753	return false;
26754}
26755
26756bool isVPCMPEQQ(unsigned Opcode) {
26757	switch (Opcode) {
26758	case VPCMPEQQYrm:
26759	case VPCMPEQQYrr:
26760	case VPCMPEQQZ128rm:
26761	case VPCMPEQQZ128rmb:
26762	case VPCMPEQQZ128rmbk:
26763	case VPCMPEQQZ128rmk:
26764	case VPCMPEQQZ128rr:
26765	case VPCMPEQQZ128rrk:
26766	case VPCMPEQQZ256rm:
26767	case VPCMPEQQZ256rmb:
26768	case VPCMPEQQZ256rmbk:
26769	case VPCMPEQQZ256rmk:
26770	case VPCMPEQQZ256rr:
26771	case VPCMPEQQZ256rrk:
26772	case VPCMPEQQZrm:
26773	case VPCMPEQQZrmb:
26774	case VPCMPEQQZrmbk:
26775	case VPCMPEQQZrmk:
26776	case VPCMPEQQZrr:
26777	case VPCMPEQQZrrk:
26778	case VPCMPEQQrm:
26779	case VPCMPEQQrr:
26780		return true;
26781	}
26782	return false;
26783}
26784
26785bool isVPCMPEQW(unsigned Opcode) {
26786	switch (Opcode) {
26787	case VPCMPEQWYrm:
26788	case VPCMPEQWYrr:
26789	case VPCMPEQWZ128rm:
26790	case VPCMPEQWZ128rmk:
26791	case VPCMPEQWZ128rr:
26792	case VPCMPEQWZ128rrk:
26793	case VPCMPEQWZ256rm:
26794	case VPCMPEQWZ256rmk:
26795	case VPCMPEQWZ256rr:
26796	case VPCMPEQWZ256rrk:
26797	case VPCMPEQWZrm:
26798	case VPCMPEQWZrmk:
26799	case VPCMPEQWZrr:
26800	case VPCMPEQWZrrk:
26801	case VPCMPEQWrm:
26802	case VPCMPEQWrr:
26803		return true;
26804	}
26805	return false;
26806}
26807
26808bool isTDPBSSD(unsigned Opcode) {
26809	return Opcode == TDPBSSD;
26810}
26811
26812bool isVPHSUBWD(unsigned Opcode) {
26813	switch (Opcode) {
26814	case VPHSUBWDrm:
26815	case VPHSUBWDrr:
26816		return true;
26817	}
26818	return false;
26819}
26820
26821bool isUMWAIT(unsigned Opcode) {
26822	return Opcode == UMWAIT;
26823}
26824
26825bool isBSWAP(unsigned Opcode) {
26826	switch (Opcode) {
26827	case BSWAP16r_BAD:
26828	case BSWAP32r:
26829	case BSWAP64r:
26830		return true;
26831	}
26832	return false;
26833}
26834
26835bool isVCVTUQQ2PD(unsigned Opcode) {
26836	switch (Opcode) {
26837	case VCVTUQQ2PDZ128rm:
26838	case VCVTUQQ2PDZ128rmb:
26839	case VCVTUQQ2PDZ128rmbk:
26840	case VCVTUQQ2PDZ128rmbkz:
26841	case VCVTUQQ2PDZ128rmk:
26842	case VCVTUQQ2PDZ128rmkz:
26843	case VCVTUQQ2PDZ128rr:
26844	case VCVTUQQ2PDZ128rrk:
26845	case VCVTUQQ2PDZ128rrkz:
26846	case VCVTUQQ2PDZ256rm:
26847	case VCVTUQQ2PDZ256rmb:
26848	case VCVTUQQ2PDZ256rmbk:
26849	case VCVTUQQ2PDZ256rmbkz:
26850	case VCVTUQQ2PDZ256rmk:
26851	case VCVTUQQ2PDZ256rmkz:
26852	case VCVTUQQ2PDZ256rr:
26853	case VCVTUQQ2PDZ256rrk:
26854	case VCVTUQQ2PDZ256rrkz:
26855	case VCVTUQQ2PDZrm:
26856	case VCVTUQQ2PDZrmb:
26857	case VCVTUQQ2PDZrmbk:
26858	case VCVTUQQ2PDZrmbkz:
26859	case VCVTUQQ2PDZrmk:
26860	case VCVTUQQ2PDZrmkz:
26861	case VCVTUQQ2PDZrr:
26862	case VCVTUQQ2PDZrrb:
26863	case VCVTUQQ2PDZrrbk:
26864	case VCVTUQQ2PDZrrbkz:
26865	case VCVTUQQ2PDZrrk:
26866	case VCVTUQQ2PDZrrkz:
26867		return true;
26868	}
26869	return false;
26870}
26871
26872bool isPEXT(unsigned Opcode) {
26873	switch (Opcode) {
26874	case PEXT32rm:
26875	case PEXT32rr:
26876	case PEXT64rm:
26877	case PEXT64rr:
26878		return true;
26879	}
26880	return false;
26881}
26882
26883bool isVCVTUQQ2PH(unsigned Opcode) {
26884	switch (Opcode) {
26885	case VCVTUQQ2PHZ128rm:
26886	case VCVTUQQ2PHZ128rmb:
26887	case VCVTUQQ2PHZ128rmbk:
26888	case VCVTUQQ2PHZ128rmbkz:
26889	case VCVTUQQ2PHZ128rmk:
26890	case VCVTUQQ2PHZ128rmkz:
26891	case VCVTUQQ2PHZ128rr:
26892	case VCVTUQQ2PHZ128rrk:
26893	case VCVTUQQ2PHZ128rrkz:
26894	case VCVTUQQ2PHZ256rm:
26895	case VCVTUQQ2PHZ256rmb:
26896	case VCVTUQQ2PHZ256rmbk:
26897	case VCVTUQQ2PHZ256rmbkz:
26898	case VCVTUQQ2PHZ256rmk:
26899	case VCVTUQQ2PHZ256rmkz:
26900	case VCVTUQQ2PHZ256rr:
26901	case VCVTUQQ2PHZ256rrk:
26902	case VCVTUQQ2PHZ256rrkz:
26903	case VCVTUQQ2PHZrm:
26904	case VCVTUQQ2PHZrmb:
26905	case VCVTUQQ2PHZrmbk:
26906	case VCVTUQQ2PHZrmbkz:
26907	case VCVTUQQ2PHZrmk:
26908	case VCVTUQQ2PHZrmkz:
26909	case VCVTUQQ2PHZrr:
26910	case VCVTUQQ2PHZrrb:
26911	case VCVTUQQ2PHZrrbk:
26912	case VCVTUQQ2PHZrrbkz:
26913	case VCVTUQQ2PHZrrk:
26914	case VCVTUQQ2PHZrrkz:
26915		return true;
26916	}
26917	return false;
26918}
26919
26920bool isVMOVMSKPD(unsigned Opcode) {
26921	switch (Opcode) {
26922	case VMOVMSKPDYrr:
26923	case VMOVMSKPDrr:
26924		return true;
26925	}
26926	return false;
26927}
26928
26929bool isLOADIWKEY(unsigned Opcode) {
26930	return Opcode == LOADIWKEY;
26931}
26932
26933bool isPMINSB(unsigned Opcode) {
26934	switch (Opcode) {
26935	case PMINSBrm:
26936	case PMINSBrr:
26937		return true;
26938	}
26939	return false;
26940}
26941
26942bool isPMINSD(unsigned Opcode) {
26943	switch (Opcode) {
26944	case PMINSDrm:
26945	case PMINSDrr:
26946		return true;
26947	}
26948	return false;
26949}
26950
26951bool isVCVTUQQ2PS(unsigned Opcode) {
26952	switch (Opcode) {
26953	case VCVTUQQ2PSZ128rm:
26954	case VCVTUQQ2PSZ128rmb:
26955	case VCVTUQQ2PSZ128rmbk:
26956	case VCVTUQQ2PSZ128rmbkz:
26957	case VCVTUQQ2PSZ128rmk:
26958	case VCVTUQQ2PSZ128rmkz:
26959	case VCVTUQQ2PSZ128rr:
26960	case VCVTUQQ2PSZ128rrk:
26961	case VCVTUQQ2PSZ128rrkz:
26962	case VCVTUQQ2PSZ256rm:
26963	case VCVTUQQ2PSZ256rmb:
26964	case VCVTUQQ2PSZ256rmbk:
26965	case VCVTUQQ2PSZ256rmbkz:
26966	case VCVTUQQ2PSZ256rmk:
26967	case VCVTUQQ2PSZ256rmkz:
26968	case VCVTUQQ2PSZ256rr:
26969	case VCVTUQQ2PSZ256rrk:
26970	case VCVTUQQ2PSZ256rrkz:
26971	case VCVTUQQ2PSZrm:
26972	case VCVTUQQ2PSZrmb:
26973	case VCVTUQQ2PSZrmbk:
26974	case VCVTUQQ2PSZrmbkz:
26975	case VCVTUQQ2PSZrmk:
26976	case VCVTUQQ2PSZrmkz:
26977	case VCVTUQQ2PSZrr:
26978	case VCVTUQQ2PSZrrb:
26979	case VCVTUQQ2PSZrrbk:
26980	case VCVTUQQ2PSZrrbkz:
26981	case VCVTUQQ2PSZrrk:
26982	case VCVTUQQ2PSZrrkz:
26983		return true;
26984	}
26985	return false;
26986}
26987
26988bool isSTMXCSR(unsigned Opcode) {
26989	return Opcode == STMXCSR;
26990}
26991
26992bool isCVTPS2PD(unsigned Opcode) {
26993	switch (Opcode) {
26994	case CVTPS2PDrm:
26995	case CVTPS2PDrr:
26996		return true;
26997	}
26998	return false;
26999}
27000
27001bool isVMOVMSKPS(unsigned Opcode) {
27002	switch (Opcode) {
27003	case VMOVMSKPSYrr:
27004	case VMOVMSKPSrr:
27005		return true;
27006	}
27007	return false;
27008}
27009
27010bool isVPROLD(unsigned Opcode) {
27011	switch (Opcode) {
27012	case VPROLDZ128mbi:
27013	case VPROLDZ128mbik:
27014	case VPROLDZ128mbikz:
27015	case VPROLDZ128mi:
27016	case VPROLDZ128mik:
27017	case VPROLDZ128mikz:
27018	case VPROLDZ128ri:
27019	case VPROLDZ128rik:
27020	case VPROLDZ128rikz:
27021	case VPROLDZ256mbi:
27022	case VPROLDZ256mbik:
27023	case VPROLDZ256mbikz:
27024	case VPROLDZ256mi:
27025	case VPROLDZ256mik:
27026	case VPROLDZ256mikz:
27027	case VPROLDZ256ri:
27028	case VPROLDZ256rik:
27029	case VPROLDZ256rikz:
27030	case VPROLDZmbi:
27031	case VPROLDZmbik:
27032	case VPROLDZmbikz:
27033	case VPROLDZmi:
27034	case VPROLDZmik:
27035	case VPROLDZmikz:
27036	case VPROLDZri:
27037	case VPROLDZrik:
27038	case VPROLDZrikz:
27039		return true;
27040	}
27041	return false;
27042}
27043
27044bool isFPTAN(unsigned Opcode) {
27045	return Opcode == FPTAN;
27046}
27047
27048bool isCVTPS2PI(unsigned Opcode) {
27049	switch (Opcode) {
27050	case MMX_CVTPS2PIrm:
27051	case MMX_CVTPS2PIrr:
27052		return true;
27053	}
27054	return false;
27055}
27056
27057bool isVMXOFF(unsigned Opcode) {
27058	return Opcode == VMXOFF;
27059}
27060
27061bool isXRSTOR64(unsigned Opcode) {
27062	return Opcode == XRSTOR64;
27063}
27064
27065bool isPMINSW(unsigned Opcode) {
27066	switch (Opcode) {
27067	case MMX_PMINSWrm:
27068	case MMX_PMINSWrr:
27069	case PMINSWrm:
27070	case PMINSWrr:
27071		return true;
27072	}
27073	return false;
27074}
27075
27076bool isVMOVSD(unsigned Opcode) {
27077	switch (Opcode) {
27078	case VMOVSDZmr:
27079	case VMOVSDZmrk:
27080	case VMOVSDZrm:
27081	case VMOVSDZrmk:
27082	case VMOVSDZrmkz:
27083	case VMOVSDZrr:
27084	case VMOVSDZrr_REV:
27085	case VMOVSDZrrk:
27086	case VMOVSDZrrk_REV:
27087	case VMOVSDZrrkz:
27088	case VMOVSDZrrkz_REV:
27089	case VMOVSDmr:
27090	case VMOVSDrm:
27091	case VMOVSDrr:
27092	case VMOVSDrr_REV:
27093		return true;
27094	}
27095	return false;
27096}
27097
27098bool isVPGATHERQD(unsigned Opcode) {
27099	switch (Opcode) {
27100	case VPGATHERQDYrm:
27101	case VPGATHERQDZ128rm:
27102	case VPGATHERQDZ256rm:
27103	case VPGATHERQDZrm:
27104	case VPGATHERQDrm:
27105		return true;
27106	}
27107	return false;
27108}
27109
27110bool isVINSERTF32X4(unsigned Opcode) {
27111	switch (Opcode) {
27112	case VINSERTF32x4Z256rm:
27113	case VINSERTF32x4Z256rmk:
27114	case VINSERTF32x4Z256rmkz:
27115	case VINSERTF32x4Z256rr:
27116	case VINSERTF32x4Z256rrk:
27117	case VINSERTF32x4Z256rrkz:
27118	case VINSERTF32x4Zrm:
27119	case VINSERTF32x4Zrmk:
27120	case VINSERTF32x4Zrmkz:
27121	case VINSERTF32x4Zrr:
27122	case VINSERTF32x4Zrrk:
27123	case VINSERTF32x4Zrrkz:
27124		return true;
27125	}
27126	return false;
27127}
27128
27129bool isVMOVSH(unsigned Opcode) {
27130	switch (Opcode) {
27131	case VMOVSHZmr:
27132	case VMOVSHZmrk:
27133	case VMOVSHZrm:
27134	case VMOVSHZrmk:
27135	case VMOVSHZrmkz:
27136	case VMOVSHZrr:
27137	case VMOVSHZrr_REV:
27138	case VMOVSHZrrk:
27139	case VMOVSHZrrk_REV:
27140	case VMOVSHZrrkz:
27141	case VMOVSHZrrkz_REV:
27142		return true;
27143	}
27144	return false;
27145}
27146
27147bool isVPGATHERQQ(unsigned Opcode) {
27148	switch (Opcode) {
27149	case VPGATHERQQYrm:
27150	case VPGATHERQQZ128rm:
27151	case VPGATHERQQZ256rm:
27152	case VPGATHERQQZrm:
27153	case VPGATHERQQrm:
27154		return true;
27155	}
27156	return false;
27157}
27158
27159bool isVPROLQ(unsigned Opcode) {
27160	switch (Opcode) {
27161	case VPROLQZ128mbi:
27162	case VPROLQZ128mbik:
27163	case VPROLQZ128mbikz:
27164	case VPROLQZ128mi:
27165	case VPROLQZ128mik:
27166	case VPROLQZ128mikz:
27167	case VPROLQZ128ri:
27168	case VPROLQZ128rik:
27169	case VPROLQZ128rikz:
27170	case VPROLQZ256mbi:
27171	case VPROLQZ256mbik:
27172	case VPROLQZ256mbikz:
27173	case VPROLQZ256mi:
27174	case VPROLQZ256mik:
27175	case VPROLQZ256mikz:
27176	case VPROLQZ256ri:
27177	case VPROLQZ256rik:
27178	case VPROLQZ256rikz:
27179	case VPROLQZmbi:
27180	case VPROLQZmbik:
27181	case VPROLQZmbikz:
27182	case VPROLQZmi:
27183	case VPROLQZmik:
27184	case VPROLQZmikz:
27185	case VPROLQZri:
27186	case VPROLQZrik:
27187	case VPROLQZrikz:
27188		return true;
27189	}
27190	return false;
27191}
27192
27193bool isVINSERTF32X8(unsigned Opcode) {
27194	switch (Opcode) {
27195	case VINSERTF32x8Zrm:
27196	case VINSERTF32x8Zrmk:
27197	case VINSERTF32x8Zrmkz:
27198	case VINSERTF32x8Zrr:
27199	case VINSERTF32x8Zrrk:
27200	case VINSERTF32x8Zrrkz:
27201		return true;
27202	}
27203	return false;
27204}
27205
27206bool isXSAVE(unsigned Opcode) {
27207	return Opcode == XSAVE;
27208}
27209
27210bool isTDPFP16PS(unsigned Opcode) {
27211	return Opcode == TDPFP16PS;
27212}
27213
27214bool isVCVTTPH2UW(unsigned Opcode) {
27215	switch (Opcode) {
27216	case VCVTTPH2UWZ128rm:
27217	case VCVTTPH2UWZ128rmb:
27218	case VCVTTPH2UWZ128rmbk:
27219	case VCVTTPH2UWZ128rmbkz:
27220	case VCVTTPH2UWZ128rmk:
27221	case VCVTTPH2UWZ128rmkz:
27222	case VCVTTPH2UWZ128rr:
27223	case VCVTTPH2UWZ128rrk:
27224	case VCVTTPH2UWZ128rrkz:
27225	case VCVTTPH2UWZ256rm:
27226	case VCVTTPH2UWZ256rmb:
27227	case VCVTTPH2UWZ256rmbk:
27228	case VCVTTPH2UWZ256rmbkz:
27229	case VCVTTPH2UWZ256rmk:
27230	case VCVTTPH2UWZ256rmkz:
27231	case VCVTTPH2UWZ256rr:
27232	case VCVTTPH2UWZ256rrk:
27233	case VCVTTPH2UWZ256rrkz:
27234	case VCVTTPH2UWZrm:
27235	case VCVTTPH2UWZrmb:
27236	case VCVTTPH2UWZrmbk:
27237	case VCVTTPH2UWZrmbkz:
27238	case VCVTTPH2UWZrmk:
27239	case VCVTTPH2UWZrmkz:
27240	case VCVTTPH2UWZrr:
27241	case VCVTTPH2UWZrrb:
27242	case VCVTTPH2UWZrrbk:
27243	case VCVTTPH2UWZrrbkz:
27244	case VCVTTPH2UWZrrk:
27245	case VCVTTPH2UWZrrkz:
27246		return true;
27247	}
27248	return false;
27249}
27250
27251bool isVMOVSS(unsigned Opcode) {
27252	switch (Opcode) {
27253	case VMOVSSZmr:
27254	case VMOVSSZmrk:
27255	case VMOVSSZrm:
27256	case VMOVSSZrmk:
27257	case VMOVSSZrmkz:
27258	case VMOVSSZrr:
27259	case VMOVSSZrr_REV:
27260	case VMOVSSZrrk:
27261	case VMOVSSZrrk_REV:
27262	case VMOVSSZrrkz:
27263	case VMOVSSZrrkz_REV:
27264	case VMOVSSmr:
27265	case VMOVSSrm:
27266	case VMOVSSrr:
27267	case VMOVSSrr_REV:
27268		return true;
27269	}
27270	return false;
27271}
27272
27273bool isRDTSCP(unsigned Opcode) {
27274	return Opcode == RDTSCP;
27275}
27276
27277bool isVPMOVUSQB(unsigned Opcode) {
27278	switch (Opcode) {
27279	case VPMOVUSQBZ128mr:
27280	case VPMOVUSQBZ128mrk:
27281	case VPMOVUSQBZ128rr:
27282	case VPMOVUSQBZ128rrk:
27283	case VPMOVUSQBZ128rrkz:
27284	case VPMOVUSQBZ256mr:
27285	case VPMOVUSQBZ256mrk:
27286	case VPMOVUSQBZ256rr:
27287	case VPMOVUSQBZ256rrk:
27288	case VPMOVUSQBZ256rrkz:
27289	case VPMOVUSQBZmr:
27290	case VPMOVUSQBZmrk:
27291	case VPMOVUSQBZrr:
27292	case VPMOVUSQBZrrk:
27293	case VPMOVUSQBZrrkz:
27294		return true;
27295	}
27296	return false;
27297}
27298
27299bool isVPMOVUSQD(unsigned Opcode) {
27300	switch (Opcode) {
27301	case VPMOVUSQDZ128mr:
27302	case VPMOVUSQDZ128mrk:
27303	case VPMOVUSQDZ128rr:
27304	case VPMOVUSQDZ128rrk:
27305	case VPMOVUSQDZ128rrkz:
27306	case VPMOVUSQDZ256mr:
27307	case VPMOVUSQDZ256mrk:
27308	case VPMOVUSQDZ256rr:
27309	case VPMOVUSQDZ256rrk:
27310	case VPMOVUSQDZ256rrkz:
27311	case VPMOVUSQDZmr:
27312	case VPMOVUSQDZmrk:
27313	case VPMOVUSQDZrr:
27314	case VPMOVUSQDZrrk:
27315	case VPMOVUSQDZrrkz:
27316		return true;
27317	}
27318	return false;
27319}
27320
27321bool isTDPBSUD(unsigned Opcode) {
27322	return Opcode == TDPBSUD;
27323}
27324
27325bool isBLCMSK(unsigned Opcode) {
27326	switch (Opcode) {
27327	case BLCMSK32rm:
27328	case BLCMSK32rr:
27329	case BLCMSK64rm:
27330	case BLCMSK64rr:
27331		return true;
27332	}
27333	return false;
27334}
27335
27336bool isVPMOVUSQW(unsigned Opcode) {
27337	switch (Opcode) {
27338	case VPMOVUSQWZ128mr:
27339	case VPMOVUSQWZ128mrk:
27340	case VPMOVUSQWZ128rr:
27341	case VPMOVUSQWZ128rrk:
27342	case VPMOVUSQWZ128rrkz:
27343	case VPMOVUSQWZ256mr:
27344	case VPMOVUSQWZ256mrk:
27345	case VPMOVUSQWZ256rr:
27346	case VPMOVUSQWZ256rrk:
27347	case VPMOVUSQWZ256rrkz:
27348	case VPMOVUSQWZmr:
27349	case VPMOVUSQWZmrk:
27350	case VPMOVUSQWZrr:
27351	case VPMOVUSQWZrrk:
27352	case VPMOVUSQWZrrkz:
27353		return true;
27354	}
27355	return false;
27356}
27357
27358bool isVPMADCSWD(unsigned Opcode) {
27359	switch (Opcode) {
27360	case VPMADCSWDrm:
27361	case VPMADCSWDrr:
27362		return true;
27363	}
27364	return false;
27365}
27366
27367bool isVGATHERDPD(unsigned Opcode) {
27368	switch (Opcode) {
27369	case VGATHERDPDYrm:
27370	case VGATHERDPDZ128rm:
27371	case VGATHERDPDZ256rm:
27372	case VGATHERDPDZrm:
27373	case VGATHERDPDrm:
27374		return true;
27375	}
27376	return false;
27377}
27378
27379bool isSHLD(unsigned Opcode) {
27380	switch (Opcode) {
27381	case SHLD16mrCL:
27382	case SHLD16mri8:
27383	case SHLD16rrCL:
27384	case SHLD16rri8:
27385	case SHLD32mrCL:
27386	case SHLD32mri8:
27387	case SHLD32rrCL:
27388	case SHLD32rri8:
27389	case SHLD64mrCL:
27390	case SHLD64mri8:
27391	case SHLD64rrCL:
27392	case SHLD64rri8:
27393		return true;
27394	}
27395	return false;
27396}
27397
27398bool isPMINUB(unsigned Opcode) {
27399	switch (Opcode) {
27400	case MMX_PMINUBrm:
27401	case MMX_PMINUBrr:
27402	case PMINUBrm:
27403	case PMINUBrr:
27404		return true;
27405	}
27406	return false;
27407}
27408
27409bool isPMINUD(unsigned Opcode) {
27410	switch (Opcode) {
27411	case PMINUDrm:
27412	case PMINUDrr:
27413		return true;
27414	}
27415	return false;
27416}
27417
27418bool isAESIMC(unsigned Opcode) {
27419	switch (Opcode) {
27420	case AESIMCrm:
27421	case AESIMCrr:
27422		return true;
27423	}
27424	return false;
27425}
27426
27427bool isCVTSD2SI(unsigned Opcode) {
27428	switch (Opcode) {
27429	case CVTSD2SI64rm_Int:
27430	case CVTSD2SI64rr_Int:
27431	case CVTSD2SIrm_Int:
27432	case CVTSD2SIrr_Int:
27433		return true;
27434	}
27435	return false;
27436}
27437
27438bool isVLDMXCSR(unsigned Opcode) {
27439	return Opcode == VLDMXCSR;
27440}
27441
27442bool isVCVTSS2SD(unsigned Opcode) {
27443	switch (Opcode) {
27444	case VCVTSS2SDZrm_Int:
27445	case VCVTSS2SDZrm_Intk:
27446	case VCVTSS2SDZrm_Intkz:
27447	case VCVTSS2SDZrr_Int:
27448	case VCVTSS2SDZrr_Intk:
27449	case VCVTSS2SDZrr_Intkz:
27450	case VCVTSS2SDZrrb_Int:
27451	case VCVTSS2SDZrrb_Intk:
27452	case VCVTSS2SDZrrb_Intkz:
27453	case VCVTSS2SDrm_Int:
27454	case VCVTSS2SDrr_Int:
27455		return true;
27456	}
27457	return false;
27458}
27459
27460bool isVCVTSS2SH(unsigned Opcode) {
27461	switch (Opcode) {
27462	case VCVTSS2SHZrm_Int:
27463	case VCVTSS2SHZrm_Intk:
27464	case VCVTSS2SHZrm_Intkz:
27465	case VCVTSS2SHZrr_Int:
27466	case VCVTSS2SHZrr_Intk:
27467	case VCVTSS2SHZrr_Intkz:
27468	case VCVTSS2SHZrrb_Int:
27469	case VCVTSS2SHZrrb_Intk:
27470	case VCVTSS2SHZrrb_Intkz:
27471		return true;
27472	}
27473	return false;
27474}
27475
27476bool isSLDT(unsigned Opcode) {
27477	switch (Opcode) {
27478	case SLDT16m:
27479	case SLDT16r:
27480	case SLDT32r:
27481	case SLDT64r:
27482		return true;
27483	}
27484	return false;
27485}
27486
27487bool isVCVTSS2SI(unsigned Opcode) {
27488	switch (Opcode) {
27489	case VCVTSS2SI64Zrm_Int:
27490	case VCVTSS2SI64Zrr_Int:
27491	case VCVTSS2SI64Zrrb_Int:
27492	case VCVTSS2SI64rm_Int:
27493	case VCVTSS2SI64rr_Int:
27494	case VCVTSS2SIZrm_Int:
27495	case VCVTSS2SIZrr_Int:
27496	case VCVTSS2SIZrrb_Int:
27497	case VCVTSS2SIrm_Int:
27498	case VCVTSS2SIrr_Int:
27499		return true;
27500	}
27501	return false;
27502}
27503
27504bool isVGATHERDPS(unsigned Opcode) {
27505	switch (Opcode) {
27506	case VGATHERDPSYrm:
27507	case VGATHERDPSZ128rm:
27508	case VGATHERDPSZ256rm:
27509	case VGATHERDPSZrm:
27510	case VGATHERDPSrm:
27511		return true;
27512	}
27513	return false;
27514}
27515
27516bool isFABS(unsigned Opcode) {
27517	return Opcode == ABS_F;
27518}
27519
27520bool isCVTSD2SS(unsigned Opcode) {
27521	switch (Opcode) {
27522	case CVTSD2SSrm_Int:
27523	case CVTSD2SSrr_Int:
27524		return true;
27525	}
27526	return false;
27527}
27528
27529bool isSHLX(unsigned Opcode) {
27530	switch (Opcode) {
27531	case SHLX32rm:
27532	case SHLX32rr:
27533	case SHLX64rm:
27534	case SHLX64rr:
27535		return true;
27536	}
27537	return false;
27538}
27539
27540bool isMONITORX(unsigned Opcode) {
27541	switch (Opcode) {
27542	case MONITORX32rrr:
27543	case MONITORX64rrr:
27544		return true;
27545	}
27546	return false;
27547}
27548
27549bool isPMINUW(unsigned Opcode) {
27550	switch (Opcode) {
27551	case PMINUWrm:
27552	case PMINUWrr:
27553		return true;
27554	}
27555	return false;
27556}
27557
27558bool isVPMAXSB(unsigned Opcode) {
27559	switch (Opcode) {
27560	case VPMAXSBYrm:
27561	case VPMAXSBYrr:
27562	case VPMAXSBZ128rm:
27563	case VPMAXSBZ128rmk:
27564	case VPMAXSBZ128rmkz:
27565	case VPMAXSBZ128rr:
27566	case VPMAXSBZ128rrk:
27567	case VPMAXSBZ128rrkz:
27568	case VPMAXSBZ256rm:
27569	case VPMAXSBZ256rmk:
27570	case VPMAXSBZ256rmkz:
27571	case VPMAXSBZ256rr:
27572	case VPMAXSBZ256rrk:
27573	case VPMAXSBZ256rrkz:
27574	case VPMAXSBZrm:
27575	case VPMAXSBZrmk:
27576	case VPMAXSBZrmkz:
27577	case VPMAXSBZrr:
27578	case VPMAXSBZrrk:
27579	case VPMAXSBZrrkz:
27580	case VPMAXSBrm:
27581	case VPMAXSBrr:
27582		return true;
27583	}
27584	return false;
27585}
27586
27587bool isVPMAXSD(unsigned Opcode) {
27588	switch (Opcode) {
27589	case VPMAXSDYrm:
27590	case VPMAXSDYrr:
27591	case VPMAXSDZ128rm:
27592	case VPMAXSDZ128rmb:
27593	case VPMAXSDZ128rmbk:
27594	case VPMAXSDZ128rmbkz:
27595	case VPMAXSDZ128rmk:
27596	case VPMAXSDZ128rmkz:
27597	case VPMAXSDZ128rr:
27598	case VPMAXSDZ128rrk:
27599	case VPMAXSDZ128rrkz:
27600	case VPMAXSDZ256rm:
27601	case VPMAXSDZ256rmb:
27602	case VPMAXSDZ256rmbk:
27603	case VPMAXSDZ256rmbkz:
27604	case VPMAXSDZ256rmk:
27605	case VPMAXSDZ256rmkz:
27606	case VPMAXSDZ256rr:
27607	case VPMAXSDZ256rrk:
27608	case VPMAXSDZ256rrkz:
27609	case VPMAXSDZrm:
27610	case VPMAXSDZrmb:
27611	case VPMAXSDZrmbk:
27612	case VPMAXSDZrmbkz:
27613	case VPMAXSDZrmk:
27614	case VPMAXSDZrmkz:
27615	case VPMAXSDZrr:
27616	case VPMAXSDZrrk:
27617	case VPMAXSDZrrkz:
27618	case VPMAXSDrm:
27619	case VPMAXSDrr:
27620		return true;
27621	}
27622	return false;
27623}
27624
27625bool isMOVAPD(unsigned Opcode) {
27626	switch (Opcode) {
27627	case MOVAPDmr:
27628	case MOVAPDrm:
27629	case MOVAPDrr:
27630	case MOVAPDrr_REV:
27631		return true;
27632	}
27633	return false;
27634}
27635
27636bool isENQCMDS(unsigned Opcode) {
27637	switch (Opcode) {
27638	case ENQCMDS16:
27639	case ENQCMDS32:
27640	case ENQCMDS64:
27641		return true;
27642	}
27643	return false;
27644}
27645
27646bool isVMOVD(unsigned Opcode) {
27647	switch (Opcode) {
27648	case VMOVDI2PDIZrm:
27649	case VMOVDI2PDIZrr:
27650	case VMOVDI2PDIrm:
27651	case VMOVDI2PDIrr:
27652	case VMOVPDI2DIZmr:
27653	case VMOVPDI2DIZrr:
27654	case VMOVPDI2DImr:
27655	case VMOVPDI2DIrr:
27656		return true;
27657	}
27658	return false;
27659}
27660
27661bool isVPMAXSQ(unsigned Opcode) {
27662	switch (Opcode) {
27663	case VPMAXSQZ128rm:
27664	case VPMAXSQZ128rmb:
27665	case VPMAXSQZ128rmbk:
27666	case VPMAXSQZ128rmbkz:
27667	case VPMAXSQZ128rmk:
27668	case VPMAXSQZ128rmkz:
27669	case VPMAXSQZ128rr:
27670	case VPMAXSQZ128rrk:
27671	case VPMAXSQZ128rrkz:
27672	case VPMAXSQZ256rm:
27673	case VPMAXSQZ256rmb:
27674	case VPMAXSQZ256rmbk:
27675	case VPMAXSQZ256rmbkz:
27676	case VPMAXSQZ256rmk:
27677	case VPMAXSQZ256rmkz:
27678	case VPMAXSQZ256rr:
27679	case VPMAXSQZ256rrk:
27680	case VPMAXSQZ256rrkz:
27681	case VPMAXSQZrm:
27682	case VPMAXSQZrmb:
27683	case VPMAXSQZrmbk:
27684	case VPMAXSQZrmbkz:
27685	case VPMAXSQZrmk:
27686	case VPMAXSQZrmkz:
27687	case VPMAXSQZrr:
27688	case VPMAXSQZrrk:
27689	case VPMAXSQZrrkz:
27690		return true;
27691	}
27692	return false;
27693}
27694
27695bool isCVTTSS2SI(unsigned Opcode) {
27696	switch (Opcode) {
27697	case CVTTSS2SI64rm_Int:
27698	case CVTTSS2SI64rr_Int:
27699	case CVTTSS2SIrm_Int:
27700	case CVTTSS2SIrr_Int:
27701		return true;
27702	}
27703	return false;
27704}
27705
27706bool isVPMAXSW(unsigned Opcode) {
27707	switch (Opcode) {
27708	case VPMAXSWYrm:
27709	case VPMAXSWYrr:
27710	case VPMAXSWZ128rm:
27711	case VPMAXSWZ128rmk:
27712	case VPMAXSWZ128rmkz:
27713	case VPMAXSWZ128rr:
27714	case VPMAXSWZ128rrk:
27715	case VPMAXSWZ128rrkz:
27716	case VPMAXSWZ256rm:
27717	case VPMAXSWZ256rmk:
27718	case VPMAXSWZ256rmkz:
27719	case VPMAXSWZ256rr:
27720	case VPMAXSWZ256rrk:
27721	case VPMAXSWZ256rrkz:
27722	case VPMAXSWZrm:
27723	case VPMAXSWZrmk:
27724	case VPMAXSWZrmkz:
27725	case VPMAXSWZrr:
27726	case VPMAXSWZrrk:
27727	case VPMAXSWZrrkz:
27728	case VPMAXSWrm:
27729	case VPMAXSWrr:
27730		return true;
27731	}
27732	return false;
27733}
27734
27735bool isMOVAPS(unsigned Opcode) {
27736	switch (Opcode) {
27737	case MOVAPSmr:
27738	case MOVAPSrm:
27739	case MOVAPSrr:
27740	case MOVAPSrr_REV:
27741		return true;
27742	}
27743	return false;
27744}
27745
27746bool isVPACKUSDW(unsigned Opcode) {
27747	switch (Opcode) {
27748	case VPACKUSDWYrm:
27749	case VPACKUSDWYrr:
27750	case VPACKUSDWZ128rm:
27751	case VPACKUSDWZ128rmb:
27752	case VPACKUSDWZ128rmbk:
27753	case VPACKUSDWZ128rmbkz:
27754	case VPACKUSDWZ128rmk:
27755	case VPACKUSDWZ128rmkz:
27756	case VPACKUSDWZ128rr:
27757	case VPACKUSDWZ128rrk:
27758	case VPACKUSDWZ128rrkz:
27759	case VPACKUSDWZ256rm:
27760	case VPACKUSDWZ256rmb:
27761	case VPACKUSDWZ256rmbk:
27762	case VPACKUSDWZ256rmbkz:
27763	case VPACKUSDWZ256rmk:
27764	case VPACKUSDWZ256rmkz:
27765	case VPACKUSDWZ256rr:
27766	case VPACKUSDWZ256rrk:
27767	case VPACKUSDWZ256rrkz:
27768	case VPACKUSDWZrm:
27769	case VPACKUSDWZrmb:
27770	case VPACKUSDWZrmbk:
27771	case VPACKUSDWZrmbkz:
27772	case VPACKUSDWZrmk:
27773	case VPACKUSDWZrmkz:
27774	case VPACKUSDWZrr:
27775	case VPACKUSDWZrrk:
27776	case VPACKUSDWZrrkz:
27777	case VPACKUSDWrm:
27778	case VPACKUSDWrr:
27779		return true;
27780	}
27781	return false;
27782}
27783
27784bool isVFIXUPIMMPD(unsigned Opcode) {
27785	switch (Opcode) {
27786	case VFIXUPIMMPDZ128rmbi:
27787	case VFIXUPIMMPDZ128rmbik:
27788	case VFIXUPIMMPDZ128rmbikz:
27789	case VFIXUPIMMPDZ128rmi:
27790	case VFIXUPIMMPDZ128rmik:
27791	case VFIXUPIMMPDZ128rmikz:
27792	case VFIXUPIMMPDZ128rri:
27793	case VFIXUPIMMPDZ128rrik:
27794	case VFIXUPIMMPDZ128rrikz:
27795	case VFIXUPIMMPDZ256rmbi:
27796	case VFIXUPIMMPDZ256rmbik:
27797	case VFIXUPIMMPDZ256rmbikz:
27798	case VFIXUPIMMPDZ256rmi:
27799	case VFIXUPIMMPDZ256rmik:
27800	case VFIXUPIMMPDZ256rmikz:
27801	case VFIXUPIMMPDZ256rri:
27802	case VFIXUPIMMPDZ256rrik:
27803	case VFIXUPIMMPDZ256rrikz:
27804	case VFIXUPIMMPDZrmbi:
27805	case VFIXUPIMMPDZrmbik:
27806	case VFIXUPIMMPDZrmbikz:
27807	case VFIXUPIMMPDZrmi:
27808	case VFIXUPIMMPDZrmik:
27809	case VFIXUPIMMPDZrmikz:
27810	case VFIXUPIMMPDZrri:
27811	case VFIXUPIMMPDZrrib:
27812	case VFIXUPIMMPDZrribk:
27813	case VFIXUPIMMPDZrribkz:
27814	case VFIXUPIMMPDZrrik:
27815	case VFIXUPIMMPDZrrikz:
27816		return true;
27817	}
27818	return false;
27819}
27820
27821bool isVMOVQ(unsigned Opcode) {
27822	switch (Opcode) {
27823	case VMOV64toPQIZrm:
27824	case VMOV64toPQIZrr:
27825	case VMOV64toPQIrm:
27826	case VMOV64toPQIrr:
27827	case VMOVPQI2QIZmr:
27828	case VMOVPQI2QIZrr:
27829	case VMOVPQI2QImr:
27830	case VMOVPQI2QIrr:
27831	case VMOVPQIto64Zmr:
27832	case VMOVPQIto64Zrr:
27833	case VMOVPQIto64mr:
27834	case VMOVPQIto64rr:
27835	case VMOVQI2PQIZrm:
27836	case VMOVQI2PQIrm:
27837	case VMOVZPQILo2PQIZrr:
27838	case VMOVZPQILo2PQIrr:
27839		return true;
27840	}
27841	return false;
27842}
27843
27844bool isVPSHUFHW(unsigned Opcode) {
27845	switch (Opcode) {
27846	case VPSHUFHWYmi:
27847	case VPSHUFHWYri:
27848	case VPSHUFHWZ128mi:
27849	case VPSHUFHWZ128mik:
27850	case VPSHUFHWZ128mikz:
27851	case VPSHUFHWZ128ri:
27852	case VPSHUFHWZ128rik:
27853	case VPSHUFHWZ128rikz:
27854	case VPSHUFHWZ256mi:
27855	case VPSHUFHWZ256mik:
27856	case VPSHUFHWZ256mikz:
27857	case VPSHUFHWZ256ri:
27858	case VPSHUFHWZ256rik:
27859	case VPSHUFHWZ256rikz:
27860	case VPSHUFHWZmi:
27861	case VPSHUFHWZmik:
27862	case VPSHUFHWZmikz:
27863	case VPSHUFHWZri:
27864	case VPSHUFHWZrik:
27865	case VPSHUFHWZrikz:
27866	case VPSHUFHWmi:
27867	case VPSHUFHWri:
27868		return true;
27869	}
27870	return false;
27871}
27872
27873bool isPCMPISTRI(unsigned Opcode) {
27874	switch (Opcode) {
27875	case PCMPISTRIrm:
27876	case PCMPISTRIrr:
27877		return true;
27878	}
27879	return false;
27880}
27881
27882bool isVMOVW(unsigned Opcode) {
27883	switch (Opcode) {
27884	case VMOVSH2Wrr:
27885	case VMOVSHtoW64rr:
27886	case VMOVW2SHrr:
27887	case VMOVW64toSHrr:
27888	case VMOVWmr:
27889	case VMOVWrm:
27890		return true;
27891	}
27892	return false;
27893}
27894
27895#endif // GET_X86_MNEMONIC_TABLES_CPP
27896
27897} // end namespace X86
27898} // end namespace llvm