Searched refs:PCI_BASE_ADDRESS_5 (Results 1 – 20 of 20) sorted by relevance
| /external/coreboot/src/soc/intel/apollolake/ |
| D | ahci.c | 16 pci_write_config32(PCH_DEV_SATA, PCI_BASE_ADDRESS_5, AHCI_TMP_BASE_ADDR); in ahci_set_speed()
27 pci_write_config32(PCH_DEV_SATA, PCI_BASE_ADDRESS_5, 0); in ahci_set_speed()
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| /external/coreboot/src/southbridge/intel/i82801gx/ |
| D | sata.c | 95 pci_write_config32(dev, PCI_BASE_ADDRESS_5, 0); in sata_init()
132 struct resource *ahci_res = probe_resource(dev, PCI_BASE_ADDRESS_5); in sata_init()
144 pci_write_config32(dev, PCI_BASE_ADDRESS_5, 0x00000000); in sata_init()
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| /external/coreboot/src/southbridge/intel/i82801jx/ |
| D | sata.c | 25 res = probe_resource(dev, PCI_BASE_ADDRESS_5); in sata_enable_ahci_mmap()
159 pci_write_config32(dev, PCI_BASE_ADDRESS_5, 0x00000000); in sata_init()
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| /external/coreboot/src/soc/amd/picasso/ |
| D | sata.c | 23 pci_read_config32(dev, PCI_BASE_ADDRESS_5), 256); in soc_enable_sata_features()
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| /external/coreboot/src/soc/amd/stoneyridge/ |
| D | sata.c | 23 pci_read_config32(dev, PCI_BASE_ADDRESS_5), 256); in soc_enable_sata_features()
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| /external/coreboot/src/southbridge/intel/i82801ix/ |
| D | sata.c | 26 res = probe_resource(dev, PCI_BASE_ADDRESS_5); in sata_enable_ahci_mmap()
172 pci_write_config32(dev, PCI_BASE_ADDRESS_5, 0x00000000); in sata_init()
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| /external/coreboot/src/soc/intel/denverton_ns/ |
| D | sata.c | 38 abar = pci_read_config32(dev, PCI_BASE_ADDRESS_5); in sata_init()
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| /external/coreboot/payloads/libpayload/include/pci/ |
| D | pci.h | 58 #define PCI_BASE_ADDRESS_5 0x24 macro
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| /external/flashrom/ |
| D | satasii.c | 121 addr = pcidev_readbar(dev, PCI_BASE_ADDRESS_5); in satasii_init()
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| D | atapromise.c | 145 rom_base_addr = pcidev_readbar(dev, PCI_BASE_ADDRESS_5); in atapromise_init()
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| D | pcidev.c | 57 case PCI_BASE_ADDRESS_5: in pcidev_readbar()
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| /external/coreboot/src/southbridge/intel/ibexpeak/ |
| D | sata.c | 79 abar = (u32 *)(uintptr_t)pci_read_config32(dev, PCI_BASE_ADDRESS_5); in sata_init()
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| /external/coreboot/src/soc/intel/baytrail/ |
| D | sata.c | 74 u8 *abar = (u8 *)pci_read_config32(dev, PCI_BASE_ADDRESS_5); in sata_init()
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| /external/coreboot/src/southbridge/intel/lynxpoint/ |
| D | sata.c | 102 abar = (u32 *)pci_read_config32(dev, PCI_BASE_ADDRESS_5); in sata_init()
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| /external/coreboot/src/southbridge/intel/bd82x6x/ |
| D | sata.c | 129 abar = (u8 *)(uintptr_t)pci_read_config32(dev, PCI_BASE_ADDRESS_5); in sata_init()
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| /external/coreboot/src/soc/intel/broadwell/pch/ |
| D | sata.c | 82 abar = (u8 *)(pci_read_config32(dev, PCI_BASE_ADDRESS_5)); in sata_init()
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| /external/coreboot/src/include/device/ |
| D | pci_def.h | 71 #define PCI_BASE_ADDRESS_5 0x24 /* 32 bits */ macro
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| /external/pciutils/lib/ |
| D | emulated.c | 137 case PCI_BASE_ADDRESS_5: in pci_emulated_read()
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| D | header.h | 76 #define PCI_BASE_ADDRESS_5 0x24 /* 32 bits */ macro
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| /external/kernel-headers/original/uapi/linux/ |
| D | pci_regs.h | 101 #define PCI_BASE_ADDRESS_5 0x24 /* 32 bits */ macro
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