1 /* SPDX-License-Identifier: GPL-2.0-only */
2
3 #include <console/console.h>
4 #include <device/device.h>
5 #include <device/pci.h>
6 #include <device/pci_ops.h>
7 #include <device/pci_ids.h>
8 #include "chip.h"
9 #include "i82801gx.h"
10 #include "sata.h"
11
get_ich7_sata_ports(void)12 static u8 get_ich7_sata_ports(void)
13 {
14 struct device *lpc;
15
16 lpc = pcidev_on_root(31, 0);
17
18 switch (pci_read_config16(lpc, PCI_DEVICE_ID)) {
19 case 0x27b0:
20 case 0x27b8:
21 return 0xf;
22 case 0x27b9:
23 case 0x27bd:
24 return 0x5;
25 case 0x27bc:
26 return 0x3;
27 default:
28 printk(BIOS_ERR, "i82801gx_sata: error: cannot determine port config\n");
29 return 0;
30 }
31 }
32
sata_enable(struct device * dev)33 void sata_enable(struct device *dev)
34 {
35 /* Get the chip configuration */
36 struct southbridge_intel_i82801gx_config *config = dev->chip_info;
37
38 if (config->sata_mode == SATA_MODE_AHCI) {
39 /* Check if the southbridge supports AHCI */
40 struct device *lpc_dev = pcidev_on_root(31, 0);
41 if (!lpc_dev) {
42 /* According to the PCI spec function 0 on a bus:device
43 needs to be active for other functions to be enabled.
44 Since SATA is on the same bus:device as the LPC
45 bridge, it makes little sense to continue. */
46 die("Couldn't find the LPC device!\n");
47 }
48
49 const bool ahci_supported = !(pci_read_config32(lpc_dev, FDVCT)
50 & AHCI_UNSUPPORTED);
51
52 if (!ahci_supported) {
53 /* Fallback to IDE PLAIN for sata for the rest of the initialization */
54 config->sata_mode = SATA_MODE_IDE_PLAIN;
55 printk(BIOS_DEBUG, "AHCI not supported, falling back to plain mode.\n");
56 }
57 }
58
59 if (config->sata_mode == SATA_MODE_AHCI) {
60 /* Set map to ahci */
61 pci_update_config8(dev, SATA_MAP, (u8)~0xc3, 0x40);
62 } else {
63 /* Set map to ide */
64 pci_and_config8(dev, SATA_MAP, (u8)~0xc3);
65 }
66 /* At this point, the new pci id will appear on the bus */
67 }
68
sata_init(struct device * dev)69 static void sata_init(struct device *dev)
70 {
71 u32 reg32;
72 u8 ports;
73
74 /* Get the chip configuration */
75 const struct southbridge_intel_i82801gx_config *config = dev->chip_info;
76
77 printk(BIOS_DEBUG, "i82801gx_sata: initializing...\n");
78
79 if (config == NULL) {
80 printk(BIOS_ERR, "i82801gx_sata: error: device not in devicetree.cb!\n");
81 return;
82 }
83
84 /* Get ICH7 SATA port config */
85 ports = get_ich7_sata_ports();
86
87 /* Enable BARs */
88 pci_write_config16(dev, PCI_COMMAND,
89 PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO);
90
91 switch (config->sata_mode) {
92 case SATA_MODE_IDE_LEGACY_COMBINED:
93 printk(BIOS_DEBUG, "SATA controller in combined mode.\n");
94 /* No AHCI: clear AHCI base */
95 pci_write_config32(dev, PCI_BASE_ADDRESS_5, 0);
96
97 /* And without AHCI BAR no memory decoding */
98 pci_and_config16(dev, PCI_COMMAND, ~PCI_COMMAND_MEMORY);
99
100 pci_write_config8(dev, 0x09, 0x80);
101
102 /* Set timings */
103 pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE |
104 IDE_ISP_5_CLOCKS | IDE_RCT_4_CLOCKS);
105 pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE |
106 IDE_ISP_3_CLOCKS | IDE_RCT_1_CLOCKS |
107 IDE_PPE0 | IDE_IE0 | IDE_TIME0);
108
109 /* Sync DMA */
110 pci_write_config16(dev, IDE_SDMA_CNT, IDE_SSDE0);
111 pci_write_config16(dev, IDE_SDMA_TIM, 0x0200);
112
113 /* Set IDE I/O Configuration */
114 reg32 = SIG_MODE_PRI_NORMAL | FAST_PCB1 | FAST_PCB0 | PCB1 | PCB0;
115 pci_write_config32(dev, IDE_CONFIG, reg32);
116
117 /* Combine IDE - SATA configuration */
118 pci_write_config8(dev, SATA_MAP, 0x02);
119
120 /* Restrict ports - 0 and 2 only available */
121 ports &= 0x5;
122 break;
123 case SATA_MODE_AHCI:
124 printk(BIOS_DEBUG, "SATA controller in AHCI mode.\n");
125 /* Allow both Legacy and Native mode */
126 pci_write_config8(dev, 0x09, 0x8f);
127
128 /* Set Interrupt Line */
129 /* Interrupt Pin is set by D31IP.PIP */
130 pci_write_config8(dev, INTR_LN, 0x0a);
131
132 struct resource *ahci_res = probe_resource(dev, PCI_BASE_ADDRESS_5);
133 if (ahci_res != NULL)
134 /* write AHCI GHC_PI register */
135 write32(res2mmio(ahci_res, 0xc, 0), config->sata_ports_implemented);
136 break;
137 default:
138 case SATA_MODE_IDE_PLAIN:
139 printk(BIOS_DEBUG, "SATA controller in plain mode.\n");
140 /* Set Sata Controller Mode. No Mapping(?) */
141 pci_write_config8(dev, SATA_MAP, 0x00);
142
143 /* No AHCI: clear AHCI base */
144 pci_write_config32(dev, PCI_BASE_ADDRESS_5, 0x00000000);
145
146 /* And without AHCI BAR no memory decoding */
147 pci_and_config16(dev, PCI_COMMAND, ~PCI_COMMAND_MEMORY);
148
149 /* Native mode capable on both primary and secondary (0xa)
150 * or'ed with enabled (0x50) = 0xf
151 */
152 pci_write_config8(dev, 0x09, 0x8f);
153
154 /* Set Interrupt Line */
155 /* Interrupt Pin is set by D31IP.PIP */
156 pci_write_config8(dev, INTR_LN, 0xff);
157
158 /* Set timings */
159 pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE |
160 IDE_ISP_3_CLOCKS | IDE_RCT_1_CLOCKS |
161 IDE_PPE0 | IDE_IE0 | IDE_TIME0);
162 pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE |
163 IDE_SITRE | IDE_ISP_3_CLOCKS |
164 IDE_RCT_1_CLOCKS | IDE_IE0 | IDE_TIME0);
165
166 /* Sync DMA */
167 pci_write_config16(dev, IDE_SDMA_CNT, IDE_SSDE0 | IDE_PSDE0);
168 pci_write_config16(dev, IDE_SDMA_TIM, 0x0201);
169
170 /* Set IDE I/O Configuration */
171 reg32 = SIG_MODE_PRI_NORMAL | FAST_PCB1 | FAST_PCB0 | PCB1 | PCB0;
172 pci_write_config32(dev, IDE_CONFIG, reg32);
173 break;
174 }
175
176 /* Set port control */
177 pci_write_config8(dev, SATA_PCS, ports);
178
179 /* Enable clock gating for unused ports and set initialization reg */
180 pci_write_config32(dev, SATA_IR, SIF3(ports) | SIF2 | SIF1 | SCRE);
181
182 /* All configurations need this SATA initialization sequence */
183 pci_write_config8(dev, 0xa0, 0x40);
184 pci_write_config8(dev, 0xa6, 0x22);
185 pci_write_config8(dev, 0xa0, 0x78);
186 pci_write_config8(dev, 0xa6, 0x22);
187 pci_write_config8(dev, 0xa0, 0x88);
188 pci_update_config32(dev, 0xa4, 0xc0c0c0c0, 0x1b1b1212);
189 pci_write_config8(dev, 0xa0, 0x8c);
190 pci_update_config32(dev, 0xa4, 0xc0c0ff00, 0x121200aa);
191 pci_write_config8(dev, 0xa0, 0x00);
192
193 pci_write_config8(dev, PCI_INTERRUPT_LINE, 0);
194
195 /* Sata Initialization Register */
196 pci_or_config32(dev, SATA_IR, SCRD); // due to some bug
197 }
198
199 static struct device_operations sata_ops = {
200 .read_resources = pci_dev_read_resources,
201 .set_resources = pci_dev_set_resources,
202 .enable_resources = pci_dev_enable_resources,
203 .init = sata_init,
204 .enable = i82801gx_enable,
205 .ops_pci = &pci_dev_ops_pci,
206 };
207
208 static const unsigned short sata_ids[] = {
209 0x27c0, /* Desktop Non-AHCI and Non-RAID Mode: 82801GB/GR/GDH (ICH7/ICH7R/ICH7DH) */
210 0x27c1, /* Desktop AHCI Mode: 82801GB/GR/GDH (ICH7/ICH7R/ICH7DH) */
211 0x27c4, /* Mobile Non-AHCI and Non-RAID Mode: 82801GBM/GHM (ICH7-M/ICH7-M DH) */
212 0x27c5, /* Mobile AHCI Mode: 82801GBM/GHM (ICH7-M/ICH7-M DH) */
213 /* NOTE: Any of the below are not properly supported yet. */
214 0x27c3, /* Desktop RAID mode: 82801GB/GR/GDH (ICH7/ICH7R/ICH7DH) */
215 0x27c6, /* ICH7M DH Raid Mode: 82801GHM (ICH7-M DH) */
216 0
217 };
218
219 static const struct pci_driver i82801gx_sata_driver __pci_driver = {
220 .ops = &sata_ops,
221 .vendor = PCI_VID_INTEL,
222 .devices = sata_ids,
223 };
224