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Searched refs:bl32_image_ep_info (Results 1 – 25 of 61) sorted by relevance

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/external/trusty/arm-trusted-firmware/plat/imx/imx8m/imx8mn/
Dimx8mn_bl31_setup.c84 static entry_point_info_t bl32_image_ep_info; variable
176 SET_PARAM_HEAD(&bl32_image_ep_info, PARAM_EP, VERSION_1, 0); in bl31_early_platform_setup2()
177 SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE); in bl31_early_platform_setup2()
178 bl32_image_ep_info.pc = BL32_BASE; in bl31_early_platform_setup2()
179 bl32_image_ep_info.spsr = 0; in bl31_early_platform_setup2()
186 bl32_image_ep_info.args.arg0 = BL32_SIZE; in bl31_early_platform_setup2()
187 bl32_image_ep_info.args.arg1 = BL32_BASE; in bl31_early_platform_setup2()
192 bl32_image_ep_info.args.arg3 = BL32_FDT_OVERLAY_ADDR; in bl31_early_platform_setup2()
197 &bl32_image_ep_info, &bl33_image_ep_info); in bl31_early_platform_setup2()
200 &bl32_image_ep_info, &bl33_image_ep_info); in bl31_early_platform_setup2()
[all …]
/external/trusty/arm-trusted-firmware/plat/imx/imx8ulp/
Dimx8ulp_bl31_setup.c50 static entry_point_info_t bl32_image_ep_info; variable
94 SET_PARAM_HEAD(&bl32_image_ep_info, PARAM_EP, VERSION_1, 0); in bl31_early_platform_setup2()
95 SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE); in bl31_early_platform_setup2()
96 bl32_image_ep_info.pc = BL32_BASE; in bl31_early_platform_setup2()
97 bl32_image_ep_info.spsr = 0; in bl31_early_platform_setup2()
104 bl32_image_ep_info.args.arg0 = BL32_SIZE; in bl31_early_platform_setup2()
105 bl32_image_ep_info.args.arg1 = BL32_BASE; in bl31_early_platform_setup2()
110 bl32_image_ep_info.args.arg3 = BL32_FDT_OVERLAY_ADDR; in bl31_early_platform_setup2()
166 return &bl32_image_ep_info; in bl31_plat_get_next_image_ep_info()
/external/trusty/arm-trusted-firmware/plat/imx/imx93/
Dimx93_bl31_setup.c39 static entry_point_info_t bl32_image_ep_info; variable
80 SET_PARAM_HEAD(&bl32_image_ep_info, PARAM_EP, VERSION_1, 0); in bl31_early_platform_setup2()
81 SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE); in bl31_early_platform_setup2()
82 bl32_image_ep_info.pc = BL32_BASE; in bl31_early_platform_setup2()
83 bl32_image_ep_info.spsr = 0; in bl31_early_platform_setup2()
92 bl32_image_ep_info.args.arg3 = BL32_FDT_OVERLAY_ADDR; in bl31_early_platform_setup2()
96 &bl32_image_ep_info, &bl33_image_ep_info); in bl31_early_platform_setup2()
150 return &bl32_image_ep_info; in bl31_plat_get_next_image_ep_info()
/external/trusty/arm-trusted-firmware/plat/xilinx/zynqmp/
Dbl31_zynqmp_setup.c30 static entry_point_info_t bl32_image_ep_info; variable
47 next_image_info = &bl32_image_ep_info; in bl31_plat_get_next_image_ep_info()
59 bl32_image_ep_info.pc = BL32_BASE; in bl31_set_default_config()
60 bl32_image_ep_info.spsr = arm_get_spsr_for_bl32_entry(); in bl31_set_default_config()
94 SET_PARAM_HEAD(&bl32_image_ep_info, PARAM_EP, VERSION_1, 0); in bl31_early_platform_setup2()
95 SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE); in bl31_early_platform_setup2()
105 enum xbl_handoff ret = xbl_handover(&bl32_image_ep_info, in bl31_early_platform_setup2()
112 if (bl32_image_ep_info.pc != 0) { in bl31_early_platform_setup2()
113 NOTICE("BL31: Secure code at 0x%lx\n", bl32_image_ep_info.pc); in bl31_early_platform_setup2()
/external/trusty/arm-trusted-firmware/plat/amd/versal2/
Dbl31_setup.c34 static entry_point_info_t bl32_image_ep_info; variable
51 return &bl32_image_ep_info; in bl31_plat_get_next_image_ep_info()
59 bl32_image_ep_info.pc = BL32_BASE; in bl31_set_default_config()
60 bl32_image_ep_info.spsr = arm_get_spsr_for_bl32_entry(); in bl31_set_default_config()
63 bl32_image_ep_info.args.arg3 = XILINX_OF_BOARD_DTB_ADDR; in bl31_set_default_config()
146 SET_PARAM_HEAD(&bl32_image_ep_info, PARAM_EP, VERSION_1, 0); in bl31_early_platform_setup2()
147 SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE); in bl31_early_platform_setup2()
151 rc = transfer_list_populate_ep_info(&bl32_image_ep_info, &bl33_image_ep_info); in bl31_early_platform_setup2()
162 NOTICE("BL31: Secure code at 0x%lx\n", bl32_image_ep_info.pc); in bl31_early_platform_setup2()
/external/arm-trusted-firmware/plat/xilinx/versal/
Dbl31_versal_setup.c24 static entry_point_info_t bl32_image_ep_info; variable
41 return &bl32_image_ep_info; in bl31_plat_get_next_image_ep_info()
49 bl32_image_ep_info.pc = BL32_BASE; in bl31_set_default_config()
50 bl32_image_ep_info.spsr = arm_get_spsr_for_bl32_entry(); in bl31_set_default_config()
101 SET_PARAM_HEAD(&bl32_image_ep_info, PARAM_EP, VERSION_1, 0); in bl31_early_platform_setup2()
102 SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE); in bl31_early_platform_setup2()
107 enum fsbl_handoff ret = fsbl_atf_handover(&bl32_image_ep_info, in bl31_early_platform_setup2()
116 NOTICE("BL31: Secure code at 0x%lx\n", bl32_image_ep_info.pc); in bl31_early_platform_setup2()
/external/arm-trusted-firmware/plat/marvell/armada/common/
Dmarvell_bl31_setup.c27 static entry_point_info_t bl32_image_ep_info; variable
50 ? &bl33_image_ep_info : &bl32_image_ep_info; in bl31_plat_get_next_image_ep_info()
79 SET_PARAM_HEAD(&bl32_image_ep_info, in marvell_bl31_early_platform_setup()
83 SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE); in marvell_bl31_early_platform_setup()
84 bl32_image_ep_info.pc = BL32_BASE; in marvell_bl31_early_platform_setup()
85 bl32_image_ep_info.spsr = marvell_get_spsr_for_bl32_entry(); in marvell_bl31_early_platform_setup()
126 bl32_image_ep_info = *bl_params->ep_info; in marvell_bl31_early_platform_setup()
/external/trusty/arm-trusted-firmware/plat/marvell/armada/common/
Dmarvell_bl31_setup.c27 static entry_point_info_t bl32_image_ep_info; variable
50 ? &bl33_image_ep_info : &bl32_image_ep_info; in bl31_plat_get_next_image_ep_info()
79 SET_PARAM_HEAD(&bl32_image_ep_info, in marvell_bl31_early_platform_setup()
83 SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE); in marvell_bl31_early_platform_setup()
84 bl32_image_ep_info.pc = BL32_BASE; in marvell_bl31_early_platform_setup()
85 bl32_image_ep_info.spsr = marvell_get_spsr_for_bl32_entry(); in marvell_bl31_early_platform_setup()
126 bl32_image_ep_info = *bl_params->ep_info; in marvell_bl31_early_platform_setup()
/external/arm-trusted-firmware/plat/xilinx/zynqmp/
Dbl31_zynqmp_setup.c27 static entry_point_info_t bl32_image_ep_info; variable
44 return &bl32_image_ep_info; in bl31_plat_get_next_image_ep_info()
53 bl32_image_ep_info.pc = BL32_BASE; in bl31_set_default_config()
54 bl32_image_ep_info.spsr = arm_get_spsr_for_bl32_entry(); in bl31_set_default_config()
102 SET_PARAM_HEAD(&bl32_image_ep_info, PARAM_EP, VERSION_1, 0); in bl31_early_platform_setup2()
103 SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE); in bl31_early_platform_setup2()
113 enum fsbl_handoff ret = fsbl_atf_handover(&bl32_image_ep_info, in bl31_early_platform_setup2()
122 if (bl32_image_ep_info.pc) { in bl31_early_platform_setup2()
123 VERBOSE("BL31: Secure code at 0x%lx\n", bl32_image_ep_info.pc); in bl31_early_platform_setup2()
/external/trusty/arm-trusted-firmware/plat/imx/imx8m/imx8mm/
Dimx8mm_bl31_setup.c113 static entry_point_info_t bl32_image_ep_info; variable
192 SET_PARAM_HEAD(&bl32_image_ep_info, PARAM_EP, VERSION_1, 0); in bl31_early_platform_setup2()
193 SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE); in bl31_early_platform_setup2()
194 bl32_image_ep_info.pc = BL32_BASE; in bl31_early_platform_setup2()
195 bl32_image_ep_info.spsr = 0; in bl31_early_platform_setup2()
202 bl32_image_ep_info.args.arg0 = BL32_SIZE; in bl31_early_platform_setup2()
203 bl32_image_ep_info.args.arg1 = BL32_BASE; in bl31_early_platform_setup2()
208 bl32_image_ep_info.args.arg3 = BL32_FDT_OVERLAY_ADDR; in bl31_early_platform_setup2()
212 &bl32_image_ep_info, &bl33_image_ep_info); in bl31_early_platform_setup2()
215 &bl32_image_ep_info, in bl31_early_platform_setup2()
[all …]
/external/trusty/arm-trusted-firmware/plat/imx/imx8m/imx8mq/
Dimx8mq_bl31_setup.c66 static entry_point_info_t bl32_image_ep_info; variable
180 SET_PARAM_HEAD(&bl32_image_ep_info, PARAM_EP, VERSION_1, 0); in bl31_early_platform_setup2()
181 SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE); in bl31_early_platform_setup2()
182 bl32_image_ep_info.pc = BL32_BASE; in bl31_early_platform_setup2()
183 bl32_image_ep_info.spsr = 0; in bl31_early_platform_setup2()
190 bl32_image_ep_info.args.arg0 = BL32_SIZE; in bl31_early_platform_setup2()
191 bl32_image_ep_info.args.arg1 = BL32_BASE; in bl31_early_platform_setup2()
196 bl32_image_ep_info.args.arg3 = BL32_FDT_OVERLAY_ADDR; in bl31_early_platform_setup2()
247 return &bl32_image_ep_info; in bl31_plat_get_next_image_ep_info()
/external/trusty/arm-trusted-firmware/plat/imx/imx8m/imx8mp/
Dimx8mp_bl31_setup.c113 static entry_point_info_t bl32_image_ep_info; variable
199 SET_PARAM_HEAD(&bl32_image_ep_info, PARAM_EP, VERSION_1, 0); in bl31_early_platform_setup2()
200 SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE); in bl31_early_platform_setup2()
201 bl32_image_ep_info.pc = BL32_BASE; in bl31_early_platform_setup2()
202 bl32_image_ep_info.spsr = 0; in bl31_early_platform_setup2()
209 bl32_image_ep_info.args.arg0 = BL32_SIZE; in bl31_early_platform_setup2()
210 bl32_image_ep_info.args.arg1 = BL32_BASE; in bl31_early_platform_setup2()
215 bl32_image_ep_info.args.arg3 = BL32_FDT_OVERLAY_ADDR; in bl31_early_platform_setup2()
219 &bl32_image_ep_info, &bl33_image_ep_info); in bl31_early_platform_setup2()
222 &bl32_image_ep_info, in bl31_early_platform_setup2()
[all …]
/external/arm-trusted-firmware/plat/layerscape/common/
Dls_bl31_setup.c23 static entry_point_info_t bl32_image_ep_info; variable
51 ? &bl33_image_ep_info : &bl32_image_ep_info; in bl31_plat_get_next_image_ep_info()
82 SET_PARAM_HEAD(&bl32_image_ep_info, in ls_bl31_early_platform_setup()
86 SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE); in ls_bl31_early_platform_setup()
87 bl32_image_ep_info.pc = BL32_BASE; in ls_bl31_early_platform_setup()
88 bl32_image_ep_info.spsr = ls_get_spsr_for_bl32_entry(); in ls_bl31_early_platform_setup()
132 bl32_image_ep_info = *bl_params->ep_info; in ls_bl31_early_platform_setup()
/external/trusty/arm-trusted-firmware/plat/arm/common/
Darm_bl31_setup.c35 static entry_point_info_t bl32_image_ep_info; variable
114 next_image_info = &bl32_image_ep_info; in bl31_plat_get_next_image_ep_info()
179 bl32_image_ep_info = *ep; in arm_bl31_early_platform_setup()
204 SET_PARAM_HEAD(&bl32_image_ep_info, in arm_bl31_early_platform_setup()
208 SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE); in arm_bl31_early_platform_setup()
209 bl32_image_ep_info.pc = BL32_BASE; in arm_bl31_early_platform_setup()
210 bl32_image_ep_info.spsr = arm_get_spsr_for_bl32_entry(); in arm_bl31_early_platform_setup()
219 bl32_image_ep_info.args.arg0 = ARM_TRUSTED_SRAM_BASE + in arm_bl31_early_platform_setup()
273 bl32_image_ep_info = *bl_params->ep_info; in arm_bl31_early_platform_setup()
284 bl32_image_ep_info.args.arg2 = in arm_bl31_early_platform_setup()
[all …]
/external/trusty/arm-trusted-firmware/plat/xilinx/versal_net/
Dbl31_versal_net_setup.c30 static entry_point_info_t bl32_image_ep_info; variable
47 return &bl32_image_ep_info; in bl31_plat_get_next_image_ep_info()
55 bl32_image_ep_info.pc = BL32_BASE; in bl31_set_default_config()
56 bl32_image_ep_info.spsr = arm_get_spsr_for_bl32_entry(); in bl31_set_default_config()
138 SET_PARAM_HEAD(&bl32_image_ep_info, PARAM_EP, VERSION_1, 0); in bl31_early_platform_setup2()
139 SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE); in bl31_early_platform_setup2()
152 xbl_ret = xbl_handover(&bl32_image_ep_info, &bl33_image_ep_info, in bl31_early_platform_setup2()
170 NOTICE("BL31: Secure code at 0x%lx\n", bl32_image_ep_info.pc); in bl31_early_platform_setup2()
/external/trusty/arm-trusted-firmware/plat/nuvoton/npcm845x/
Dnpcm845x_bl31_setup.c34 static entry_point_info_t bl32_image_ep_info; variable
84 ? &bl33_image_ep_info : &bl32_image_ep_info; in bl31_plat_get_next_image_ep_info()
164 SET_PARAM_HEAD(&bl32_image_ep_info, in bl31_early_platform_setup2()
168 SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE); in bl31_early_platform_setup2()
169 bl32_image_ep_info.pc = BL32_BASE; in bl31_early_platform_setup2()
170 bl32_image_ep_info.spsr = arm_get_spsr_for_bl32_entry(); in bl31_early_platform_setup2()
180 bl32_image_ep_info.args.arg0 = ARM_TRUSTED_SRAM_BASE + in bl31_early_platform_setup2()
250 bl32_image_ep_info = *bl_params->ep_info; in bl31_early_platform_setup2()
/external/arm-trusted-firmware/plat/allwinner/common/
Dsunxi_bl31_setup.c30 static entry_point_info_t bl32_image_ep_info; variable
90 SET_PARAM_HEAD(&bl32_image_ep_info, PARAM_EP, VERSION_1, 0); in bl31_early_platform_setup2()
91 SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE); in bl31_early_platform_setup2()
92 bl32_image_ep_info.pc = BL32_BASE; in bl31_early_platform_setup2()
195 if ((type == SECURE) && bl32_image_ep_info.pc) in bl31_plat_get_next_image_ep_info()
196 return &bl32_image_ep_info; in bl31_plat_get_next_image_ep_info()
/external/trusty/arm-trusted-firmware/plat/allwinner/common/
Dsunxi_bl31_setup.c29 static entry_point_info_t bl32_image_ep_info; variable
89 SET_PARAM_HEAD(&bl32_image_ep_info, PARAM_EP, VERSION_1, 0); in bl31_early_platform_setup2()
90 SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE); in bl31_early_platform_setup2()
91 bl32_image_ep_info.pc = BL32_BASE; in bl31_early_platform_setup2()
197 if ((type == SECURE) && bl32_image_ep_info.pc) in bl31_plat_get_next_image_ep_info()
198 return &bl32_image_ep_info; in bl31_plat_get_next_image_ep_info()
/external/trusty/arm-trusted-firmware/plat/xilinx/versal/
Dbl31_versal_setup.c31 static entry_point_info_t bl32_image_ep_info; variable
48 return &bl32_image_ep_info; in bl31_plat_get_next_image_ep_info()
56 bl32_image_ep_info.pc = (uintptr_t)BL32_BASE; in bl31_set_default_config()
57 bl32_image_ep_info.spsr = (uint32_t)arm_get_spsr_for_bl32_entry(); in bl31_set_default_config()
115 SET_PARAM_HEAD(&bl32_image_ep_info, PARAM_EP, VERSION_1, 0); in bl31_early_platform_setup2()
116 SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE); in bl31_early_platform_setup2()
131 enum xbl_handoff ret = xbl_handover(&bl32_image_ep_info, in bl31_early_platform_setup2()
144 NOTICE("BL31: Secure code at 0x%lx\n", bl32_image_ep_info.pc); in bl31_early_platform_setup2()
/external/arm-trusted-firmware/plat/imx/imx8m/imx8mp/
Dimx8mp_bl31_setup.c55 static entry_point_info_t bl32_image_ep_info; variable
127 SET_PARAM_HEAD(&bl32_image_ep_info, PARAM_EP, VERSION_1, 0); in bl31_early_platform_setup2()
128 SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE); in bl31_early_platform_setup2()
129 bl32_image_ep_info.pc = BL32_BASE; in bl31_early_platform_setup2()
130 bl32_image_ep_info.spsr = 0; in bl31_early_platform_setup2()
178 return &bl32_image_ep_info; in bl31_plat_get_next_image_ep_info()
/external/arm-trusted-firmware/plat/imx/imx8m/imx8mm/
Dimx8mm_bl31_setup.c57 static entry_point_info_t bl32_image_ep_info; variable
129 SET_PARAM_HEAD(&bl32_image_ep_info, PARAM_EP, VERSION_1, 0); in bl31_early_platform_setup2()
130 SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE); in bl31_early_platform_setup2()
131 bl32_image_ep_info.pc = BL32_BASE; in bl31_early_platform_setup2()
132 bl32_image_ep_info.spsr = 0; in bl31_early_platform_setup2()
178 return &bl32_image_ep_info; in bl31_plat_get_next_image_ep_info()
/external/arm-trusted-firmware/plat/imx/imx8m/imx8mn/
Dimx8mn_bl31_setup.c57 static entry_point_info_t bl32_image_ep_info; variable
129 SET_PARAM_HEAD(&bl32_image_ep_info, PARAM_EP, VERSION_1, 0); in bl31_early_platform_setup2()
130 SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE); in bl31_early_platform_setup2()
131 bl32_image_ep_info.pc = BL32_BASE; in bl31_early_platform_setup2()
132 bl32_image_ep_info.spsr = 0; in bl31_early_platform_setup2()
178 return &bl32_image_ep_info; in bl31_plat_get_next_image_ep_info()
/external/arm-trusted-firmware/plat/arm/common/
Darm_bl31_setup.c29 static entry_point_info_t bl32_image_ep_info; variable
98 next_image_info = &bl32_image_ep_info; in bl31_plat_get_next_image_ep_info()
132 SET_PARAM_HEAD(&bl32_image_ep_info, in arm_bl31_early_platform_setup()
136 SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE); in arm_bl31_early_platform_setup()
137 bl32_image_ep_info.pc = BL32_BASE; in arm_bl31_early_platform_setup()
138 bl32_image_ep_info.spsr = arm_get_spsr_for_bl32_entry(); in arm_bl31_early_platform_setup()
147 bl32_image_ep_info.args.arg0 = ARM_TRUSTED_SRAM_BASE + in arm_bl31_early_platform_setup()
193 bl32_image_ep_info = *bl_params->ep_info; in arm_bl31_early_platform_setup()
/external/arm-trusted-firmware/plat/brcm/common/
Dbrcm_bl31_setup.c29 static entry_point_info_t bl32_image_ep_info; variable
65 ? &bl33_image_ep_info : &bl32_image_ep_info; in bl31_plat_get_next_image_ep_info()
103 SET_PARAM_HEAD(&bl32_image_ep_info, in brcm_bl31_early_platform_setup()
107 SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE); in brcm_bl31_early_platform_setup()
108 bl32_image_ep_info.pc = BL32_BASE; in brcm_bl31_early_platform_setup()
109 bl32_image_ep_info.spsr = brcm_get_spsr_for_bl32_entry(); in brcm_bl31_early_platform_setup()
167 bl32_image_ep_info = *bl_params->ep_info; in brcm_bl31_early_platform_setup()
/external/trusty/arm-trusted-firmware/plat/socionext/synquacer/
Dsq_bl31_setup.c20 static entry_point_info_t bl32_image_ep_info; variable
44 return type == NON_SECURE ? &bl33_image_ep_info : &bl32_image_ep_info; in bl31_plat_get_next_image_ep_info()
66 bl32_image_ep_info = *bl_params->ep_info; in bl31_early_platform_setup2()
136 SET_PARAM_HEAD(&bl32_image_ep_info, in bl31_early_platform_setup2()
140 SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE); in bl31_early_platform_setup2()
141 bl32_image_ep_info.pc = BL32_BASE; in bl31_early_platform_setup2()
142 bl32_image_ep_info.spsr = sq_get_spsr_for_bl32_entry(); in bl31_early_platform_setup2()

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