1 /*
2 * Copyright (c) 2018-2023, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <assert.h>
8 #include <stdbool.h>
9
10 #include <platform_def.h>
11
12 #include <arch_helpers.h>
13 #include <common/bl_common.h>
14 #include <common/debug.h>
15 #include <context.h>
16 #include <drivers/arm/tzc380.h>
17 #include <drivers/console.h>
18 #include <drivers/generic_delay_timer.h>
19 #include <lib/el3_runtime/context_mgmt.h>
20 #include <lib/mmio.h>
21 #include <lib/xlat_tables/xlat_tables_v2.h>
22 #include <plat/common/platform.h>
23
24 #include <dram.h>
25 #include <gpc.h>
26 #include <imx_aipstz.h>
27 #include <imx_uart.h>
28 #include <imx8m_caam.h>
29 #include <imx8m_ccm.h>
30 #include <plat_imx8.h>
31
32 #define TRUSTY_PARAMS_LEN_BYTES (4096*2)
33
34 /*
35 * Avoid the pointer dereference of the canonical mmio_read_8() implementation.
36 * This prevents the compiler from mis-interpreting the MMIO access as an
37 * illegal memory access to a very low address (the IMX ROM is mapped at 0).
38 */
mmio_read_8_ldrb(uintptr_t address)39 static uint8_t mmio_read_8_ldrb(uintptr_t address)
40 {
41 uint8_t reg;
42
43 __asm__ volatile ("ldrb %w0, [%1]" : "=r" (reg) : "r" (address));
44
45 return reg;
46 }
47
48 static const mmap_region_t imx_mmap[] = {
49 MAP_REGION_FLAT(GPV_BASE, GPV_SIZE, MT_DEVICE | MT_RW), /* GPV map */
50 MAP_REGION_FLAT(IMX_ROM_BASE, IMX_ROM_SIZE, MT_MEMORY | MT_RO), /* ROM map */
51 MAP_REGION_FLAT(IMX_AIPS_BASE, IMX_AIPS_SIZE, MT_DEVICE | MT_RW), /* AIPS map */
52 MAP_REGION_FLAT(IMX_GIC_BASE, IMX_GIC_SIZE, MT_DEVICE | MT_RW), /* GIC map */
53 MAP_REGION_FLAT(IMX_DDRPHY_BASE, IMX_DDR_IPS_SIZE, MT_DEVICE | MT_RW), /* DDRMIX map */
54 MAP_REGION_FLAT(IMX_DRAM_BASE, IMX_DRAM_SIZE, MT_MEMORY | MT_RW | MT_NS),
55 {0},
56 };
57
58 static const struct aipstz_cfg aipstz[] = {
59 {AIPSTZ1_BASE, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, },
60 {AIPSTZ2_BASE, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, },
61 {AIPSTZ3_BASE, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, },
62 {AIPSTZ4_BASE, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, },
63 {0},
64 };
65
66 static entry_point_info_t bl32_image_ep_info;
67 static entry_point_info_t bl33_image_ep_info;
68
69 static uint32_t imx_soc_revision;
70
imx_soc_info_handler(uint32_t smc_fid,u_register_t x1,u_register_t x2,u_register_t x3)71 int imx_soc_info_handler(uint32_t smc_fid, u_register_t x1, u_register_t x2,
72 u_register_t x3)
73 {
74 return imx_soc_revision;
75 }
76
77 #define ANAMIX_DIGPROG 0x6c
78 #define ROM_SOC_INFO_A0 0x800
79 #define ROM_SOC_INFO_B0 0x83C
80 #define OCOTP_SOC_INFO_B1 0x40
81
imx8mq_soc_info_init(void)82 static void imx8mq_soc_info_init(void)
83 {
84 uint32_t rom_version;
85 uint32_t ocotp_val;
86
87 imx_soc_revision = mmio_read_32(IMX_ANAMIX_BASE + ANAMIX_DIGPROG);
88 rom_version = mmio_read_8_ldrb(IMX_ROM_BASE + ROM_SOC_INFO_A0);
89 if (rom_version == 0x10)
90 return;
91
92 rom_version = mmio_read_8_ldrb(IMX_ROM_BASE + ROM_SOC_INFO_B0);
93 if (rom_version == 0x20) {
94 imx_soc_revision &= ~0xff;
95 imx_soc_revision |= rom_version;
96 return;
97 }
98
99 /* 0xff0055aa is magic number for B1 */
100 ocotp_val = mmio_read_32(IMX_OCOTP_BASE + OCOTP_SOC_INFO_B1);
101 if (ocotp_val == 0xff0055aa) {
102 imx_soc_revision &= ~0xff;
103 if (rom_version == 0x22) {
104 imx_soc_revision |= 0x22;
105 } else {
106 imx_soc_revision |= 0x21;
107 }
108 return;
109 }
110 }
111
112 /* get SPSR for BL33 entry */
get_spsr_for_bl33_entry(void)113 static uint32_t get_spsr_for_bl33_entry(void)
114 {
115 unsigned long el_status;
116 unsigned long mode;
117 uint32_t spsr;
118
119 /* figure out what mode we enter the non-secure world */
120 el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT;
121 el_status &= ID_AA64PFR0_ELX_MASK;
122
123 mode = (el_status) ? MODE_EL2 : MODE_EL1;
124
125 spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS);
126 return spsr;
127 }
128
bl31_tz380_setup(void)129 static void bl31_tz380_setup(void)
130 {
131 unsigned int val;
132
133 val = mmio_read_32(IMX_IOMUX_GPR_BASE + IOMUXC_GPR10);
134 if ((val & GPR_TZASC_EN) != GPR_TZASC_EN)
135 return;
136
137 tzc380_init(IMX_TZASC_BASE);
138 /*
139 * Need to substact offset 0x40000000 from CPU address when
140 * programming tzasc region for i.mx8mq. Enable 1G-5G S/NS RW
141 */
142 tzc380_configure_region(0, 0x00000000, TZC_ATTR_REGION_SIZE(TZC_REGION_SIZE_4G) |
143 TZC_ATTR_REGION_EN_MASK | TZC_ATTR_SP_ALL);
144 }
145
bl31_early_platform_setup2(u_register_t arg0,u_register_t arg1,u_register_t arg2,u_register_t arg3)146 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
147 u_register_t arg2, u_register_t arg3)
148 {
149 unsigned int console_base = IMX_BOOT_UART_BASE;
150 static console_t console;
151 int i;
152 /* enable CSU NS access permission */
153 for (i = 0; i < 64; i++) {
154 mmio_write_32(IMX_CSU_BASE + i * 4, 0xffffffff);
155 }
156
157 imx_aipstz_init(aipstz);
158
159 if (console_base == 0U) {
160 console_base = imx8m_uart_get_base();
161 }
162
163 console_imx_uart_register(console_base, IMX_BOOT_UART_CLK_IN_HZ,
164 IMX_CONSOLE_BAUDRATE, &console);
165 /* This console is only used for boot stage */
166 console_set_scope(&console, CONSOLE_FLAG_BOOT);
167
168 imx8m_caam_init();
169
170 /*
171 * tell BL3-1 where the non-secure software image is located
172 * and the entry state information.
173 */
174 bl33_image_ep_info.pc = PLAT_NS_IMAGE_OFFSET;
175 bl33_image_ep_info.spsr = get_spsr_for_bl33_entry();
176 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE);
177
178 #if defined(SPD_opteed) || defined(SPD_trusty)
179 /* Populate entry point information for BL32 */
180 SET_PARAM_HEAD(&bl32_image_ep_info, PARAM_EP, VERSION_1, 0);
181 SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE);
182 bl32_image_ep_info.pc = BL32_BASE;
183 bl32_image_ep_info.spsr = 0;
184
185 /* Pass TEE base and size to bl33 */
186 bl33_image_ep_info.args.arg1 = BL32_BASE;
187 bl33_image_ep_info.args.arg2 = BL32_SIZE;
188
189 #ifdef SPD_trusty
190 bl32_image_ep_info.args.arg0 = BL32_SIZE;
191 bl32_image_ep_info.args.arg1 = BL32_BASE;
192 #else
193 /* Make sure memory is clean */
194 mmio_write_32(BL32_FDT_OVERLAY_ADDR, 0);
195 bl33_image_ep_info.args.arg3 = BL32_FDT_OVERLAY_ADDR;
196 bl32_image_ep_info.args.arg3 = BL32_FDT_OVERLAY_ADDR;
197 #endif
198 #endif
199
200 bl31_tz380_setup();
201 }
202
bl31_plat_arch_setup(void)203 void bl31_plat_arch_setup(void)
204 {
205 const mmap_region_t bl_regions[] = {
206 MAP_REGION_FLAT(BL31_START, BL31_SIZE,
207 MT_MEMORY | MT_RW | MT_SECURE),
208 MAP_REGION_FLAT(BL_CODE_BASE, BL_CODE_END - BL_CODE_BASE,
209 MT_MEMORY | MT_RO | MT_SECURE),
210 #if USE_COHERENT_MEM
211 MAP_REGION_FLAT(BL_COHERENT_RAM_BASE,
212 BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE,
213 MT_DEVICE | MT_RW | MT_SECURE),
214 #endif
215 /* Map TEE memory */
216 MAP_REGION_FLAT(BL32_BASE, BL32_SIZE, MT_MEMORY | MT_RW),
217 {0},
218 };
219
220 setup_page_tables(bl_regions, imx_mmap);
221 /* enable the MMU */
222 enable_mmu_el3(0);
223 }
224
bl31_platform_setup(void)225 void bl31_platform_setup(void)
226 {
227 generic_delay_timer_init();
228
229 /* init the GICv3 cpu and distributor interface */
230 plat_gic_driver_init();
231 plat_gic_init();
232
233 /* determine SOC revision for erratas */
234 imx8mq_soc_info_init();
235
236 /* gpc init */
237 imx_gpc_init();
238
239 dram_info_init(SAVED_DRAM_TIMING_BASE);
240 }
241
bl31_plat_get_next_image_ep_info(unsigned int type)242 entry_point_info_t *bl31_plat_get_next_image_ep_info(unsigned int type)
243 {
244 if (type == NON_SECURE)
245 return &bl33_image_ep_info;
246 if (type == SECURE)
247 return &bl32_image_ep_info;
248
249 return NULL;
250 }
251
plat_get_syscnt_freq2(void)252 unsigned int plat_get_syscnt_freq2(void)
253 {
254 return COUNTER_FREQUENCY;
255 }
256
257 #ifdef SPD_trusty
plat_trusty_set_boot_args(aapcs64_params_t * args)258 void plat_trusty_set_boot_args(aapcs64_params_t *args)
259 {
260 args->arg0 = BL32_SIZE;
261 args->arg1 = BL32_BASE;
262 args->arg2 = TRUSTY_PARAMS_LEN_BYTES;
263 }
264 #endif
265