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Searched refs:hasMVEIntegerOps (Results 1 – 25 of 34) sorted by relevance

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/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/ARM/
DARMTargetTransformInfo.cpp108 if (ST->hasMVEIntegerOps()) in getPreferredAddressingMode()
462 (ST->hasNEON() || ST->hasMVEIntegerOps())) { in getCFInstrCost()
503 if ((ST->hasMVEIntegerOps() && in getCastInstrCost()
551 if (SrcTy.isVector() && ST->hasMVEIntegerOps()) { in getCastInstrCost()
580 if (SrcTy.isVector() && ST->hasMVEIntegerOps()) { in getCastInstrCost()
815 if (SrcTy.isVector() && ST->hasMVEIntegerOps()) { in getCastInstrCost()
838 if (ISD == ISD::TRUNCATE && ST->hasMVEIntegerOps() && in getCastInstrCost()
869 int BaseCost = ST->hasMVEIntegerOps() && Src->isVectorTy() in getCastInstrCost()
902 if (ST->hasMVEIntegerOps() && (Opcode == Instruction::InsertElement || in getVectorInstrCost()
1014 if (ST->hasMVEIntegerOps() && ValTy->isVectorTy() && in getCmpSelInstrCost()
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DARMSelectionDAGInfo.cpp177 if (Subtarget.hasMVEIntegerOps() && in EmitTargetCodeForMemcpy()
306 if (Subtarget.hasMVEIntegerOps() && in EmitTargetCodeForMemset()
DARMTargetTransformInfo.h155 if (ST->hasMVEIntegerOps()) in getNumberOfRegisters()
172 if (ST->hasMVEIntegerOps()) in getRegisterBitWidth()
DMVEVPTBlockPass.cpp317 if (!STI.isThumb2() || !STI.hasMVEIntegerOps()) in runOnMachineFunction()
DARMISelLowering.cpp821 if (Subtarget->hasMVEIntegerOps()) in ARMTargetLowering()
854 if (Subtarget->hasMVEIntegerOps() || Subtarget->hasNEON()) { in ARMTargetLowering()
1012 if (Subtarget->hasNEON() || Subtarget->hasMVEIntegerOps()) { in ARMTargetLowering()
1020 if (Subtarget->hasMVEIntegerOps()) { in ARMTargetLowering()
1167 if (Subtarget->hasMVEIntegerOps()) in ARMTargetLowering()
1570 if (Subtarget->hasMVEIntegerOps()) in ARMTargetLowering()
1887 if ((Subtarget->hasMVEIntegerOps() && in getSetCCResultType()
1911 if (Subtarget->hasMVEIntegerOps()) { in getRegClassFor()
6639 if (ST->hasMVEIntegerOps()) { in Expand64BitShift()
6724 assert(ST->hasMVEIntegerOps() && in LowerVSETCC()
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DARMSubtarget.cpp393 return hasMVEIntegerOps(); in enableSubRegLiveness()
DMVETailPredication.cpp142 if (!ST->hasMVEIntegerOps() || !ST->hasV8_1MMainlineOps()) { in runOnLoop()
DMVELaneInterleavingPass.cpp376 if (!ST->hasMVEIntegerOps()) in runOnFunction()
DARMPredicates.td32 def HasMVEInt : Predicate<"Subtarget->hasMVEIntegerOps()">,
DARMRegisterInfo.td485 return 1 + MF.getSubtarget<ARMSubtarget>().hasMVEIntegerOps();
525 return 1 + MF.getSubtarget<ARMSubtarget>().hasMVEIntegerOps();
DARMBaseRegisterInfo.cpp276 if (MF.getSubtarget<ARMSubtarget>().hasMVEIntegerOps()) in getLargestLegalSuperClass()
DARMBaseInstrInfo.cpp1212 Subtarget.hasMVEIntegerOps()) { in storeRegToStackSlot()
1260 } else if (Subtarget.hasMVEIntegerOps()) { in storeRegToStackSlot()
1281 Subtarget.hasMVEIntegerOps()) { in storeRegToStackSlot()
1467 Subtarget.hasMVEIntegerOps()) { in loadRegFromStackSlot()
1510 } else if (Subtarget.hasMVEIntegerOps()) { in loadRegFromStackSlot()
1531 Subtarget.hasMVEIntegerOps()) { in loadRegFromStackSlot()
DMVEGatherScatterLowering.cpp1251 if (!ST->hasMVEIntegerOps()) in runOnFunction()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DARMTargetTransformInfo.cpp207 if (SrcTy.isVector() && ST->hasMVEIntegerOps()) { in getCastInstrCost()
379 if (SrcTy.isVector() && ST->hasMVEIntegerOps()) { in getCastInstrCost()
405 int BaseCost = ST->hasMVEIntegerOps() && Src->isVectorTy() in getCastInstrCost()
433 if (ST->hasMVEIntegerOps() && (Opcode == Instruction::InsertElement || in getVectorInstrCost()
472 int BaseCost = ST->hasMVEIntegerOps() && ValTy->isVectorTy() in getCmpSelInstrCost()
500 if (!EnableMaskedLoadStores || !ST->hasMVEIntegerOps()) in isLegalMaskedLoad()
521 if (!EnableMaskedGatherScatters || !ST->hasMVEIntegerOps()) in isLegalMaskedGather()
646 if (ST->hasMVEIntegerOps()) { in getShuffleCost()
663 int BaseCost = ST->hasMVEIntegerOps() && Tp->isVectorTy() in getShuffleCost()
770 int BaseCost = ST->hasMVEIntegerOps() && Ty->isVectorTy() in getArithmeticInstrCost()
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DARMTargetTransformInfo.h130 if (ST->hasMVEIntegerOps()) in getNumberOfRegisters()
144 if (ST->hasMVEIntegerOps()) in getRegisterBitWidth()
DMVEVPTBlockPass.cpp182 if (!STI.isThumb2() || !STI.hasMVEIntegerOps()) in runOnMachineFunction()
DMVEGatherScatterLowering.cpp283 if (!ST->hasMVEIntegerOps()) in runOnFunction()
DARMISelLowering.cpp747 if (Subtarget->hasMVEIntegerOps()) in ARMTargetLowering()
776 if (Subtarget->hasMVEIntegerOps() || Subtarget->hasNEON()) { in ARMTargetLowering()
937 if (Subtarget->hasNEON() || Subtarget->hasMVEIntegerOps()) { in ARMTargetLowering()
1079 if (Subtarget->hasMVEIntegerOps()) in ARMTargetLowering()
1718 if (Subtarget->hasMVEIntegerOps() && in getSetCCResultType()
1733 if (Subtarget->hasNEON() || Subtarget->hasMVEIntegerOps()) { in getRegClassFor()
6144 if (ST->hasMVEIntegerOps()) { in Expand64BitShift()
6229 assert(ST->hasMVEIntegerOps() && in LowerVSETCC()
6320 if (ST->hasMVEIntegerOps()) { in LowerVSETCC()
7090 assert(ST->hasMVEIntegerOps() && "LowerBUILD_VECTOR_i1 called without MVE!"); in LowerBUILD_VECTOR_i1()
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DARMPredicates.td32 def HasMVEInt : Predicate<"Subtarget->hasMVEIntegerOps()">,
DARMSubtarget.h585 bool hasMVEIntegerOps() const { return HasMVEIntegerOps; } in hasMVEIntegerOps() function
DMVETailPredication.cpp137 if (!ST->hasMVEIntegerOps() || !ST->hasV8_1MMainlineOps()) { in runOnLoop()
DARMRegisterInfo.td443 return 1 + MF.getSubtarget<ARMSubtarget>().hasMVEIntegerOps();
483 return 1 + MF.getSubtarget<ARMSubtarget>().hasMVEIntegerOps();
/external/swiftshader/third_party/llvm-16.0/configs/common/lib/Target/ARM/
DARMGenFastISel.inc288 if ((Subtarget->hasMVEIntegerOps())) {
297 if ((Subtarget->hasMVEIntegerOps())) {
306 if ((Subtarget->hasMVEIntegerOps())) {
326 if ((Subtarget->hasMVEIntegerOps())) {
335 if ((Subtarget->hasMVEIntegerOps())) {
344 if ((Subtarget->hasMVEIntegerOps())) {
369 if ((Subtarget->hasMVEIntegerOps())) {
386 if ((Subtarget->hasMVEIntegerOps())) {
403 if ((Subtarget->hasMVEIntegerOps())) {
413 if ((Subtarget->hasMVEIntegerOps())) {
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/external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/ARM/
DARMGenFastISel.inc302 if ((Subtarget->hasMVEIntegerOps())) {
319 if ((Subtarget->hasMVEIntegerOps())) {
336 if ((Subtarget->hasMVEIntegerOps())) {
432 if ((Subtarget->hasMVEIntegerOps())) {
463 if ((Subtarget->hasMVEIntegerOps())) {
484 if ((Subtarget->hasMVEIntegerOps())) {
505 if ((Subtarget->hasMVEIntegerOps())) {
540 if ((Subtarget->hasMVEIntegerOps())) {
561 if ((Subtarget->hasMVEIntegerOps())) {
582 if ((Subtarget->hasMVEIntegerOps())) {
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DARMGenDAGISel.inc2763 /* 5553*/ OPC_CheckPatternPredicate, 8, // (Subtarget->hasMVEIntegerOps())
2774 /* 5581*/ OPC_CheckPatternPredicate, 8, // (Subtarget->hasMVEIntegerOps())
2784 /* 5608*/ OPC_CheckPatternPredicate, 8, // (Subtarget->hasMVEIntegerOps())
2961 /* 5940*/ OPC_CheckPatternPredicate, 8, // (Subtarget->hasMVEIntegerOps())
2989 /* 5996*/ OPC_CheckPatternPredicate, 8, // (Subtarget->hasMVEIntegerOps())
3014 /* 6046*/ OPC_CheckPatternPredicate, 8, // (Subtarget->hasMVEIntegerOps())
3042 /* 6101*/ OPC_CheckPatternPredicate, 8, // (Subtarget->hasMVEIntegerOps())
3070 /* 6157*/ OPC_CheckPatternPredicate, 8, // (Subtarget->hasMVEIntegerOps())
3095 /* 6207*/ OPC_CheckPatternPredicate, 8, // (Subtarget->hasMVEIntegerOps())
3123 /* 6262*/ OPC_CheckPatternPredicate, 8, // (Subtarget->hasMVEIntegerOps())
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