Searched refs:hsync_width (Results 1 – 18 of 18) sorted by relevance
13 (mode->xres + mode->hfront_porch + mode->hsync_width)17 mode->hsync_width + mode->hback_porch)
40 int hsync_width; /* the width of HSYNC pulses */ member
76 config->hsync_width, config->vsync_width); in update_display_mode()91 WRITEL(config->vsync_width << 16 | config->hsync_width, in update_display_mode()
625 config->hfront_porch + config->hsync_width - 7) * in tegra_dc_dp_calc_config()1363 config->hsync_width = edid.mode.hspw; in tegra_dp_update_config()
621 hsync_end = config->hsync_width - 1; in tegra_dc_sor_config_panel()
68 int hsync_width; member
54 config->hsync_width; in tegra_dc_calc_refresh()87 WRITEL(config->vsync_width << 16 | config->hsync_width, in update_display_mode()
620 htotal = config->hsync_width + config->hback_porch + in tegra_dc_sor_config_panel()628 hsync_end = config->hsync_width - 1; in tegra_dc_sor_config_panel()
610 config->hfront_porch + config->hsync_width - 7) * in tegra_dc_dp_calc_config()1322 config->hsync_width = edid.mode.hspw; in tegra_dp_update_config()
20 register "hsync_width" = "80"
44 register "hsync_width" = "30"
56 register "hsync_width" = "30"
59 int htotal, hactive, hsync_offset, hsync_width, hsync_polarity; member
824 ¶ms->hsync_width); in video_params_from_xml()
258 u32 hsync_width; member
959 video_params.hsync_width, mode_hsync_width); in check_mode()979 igt_assert(video_params.hsync_width == mode_hsync_width); in check_mode()