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1## SPDX-License-Identifier: GPL-2.0-only
2
3chip soc/nvidia/tegra210
4	device cpu_cluster 0 on
5		device cpu 0 on end
6		device cpu 1 on end
7		device cpu 2 on end
8		device cpu 3 on end
9	end
10
11	register "display_controller" = "TEGRA_ARM_DISPLAYA"
12	register "xres" = "1366"
13	register "yres" = "768"
14
15	# framebuffer resolution
16	register "display_xres" = "1368"
17	register "display_yres" = "678"
18
19	# bits per pixel and color depth
20	register "framebuffer_bits_per_pixel" = "16"
21	register "color_depth" = "6"
22
23	register "panel_bits_per_pixel" = "18"
24
25# How to compute these: xrandr --verbose will give you this:
26#Detailed mode: Clock 285.250 MHz, 272 mm x 181 mm
27#               2560 2608 2640 2720 hborder 0
28#               1700 1703 1713 1749 vborder 0
29#Then you can compute your values:
30#H front porch = 2608 - 2560 = 48
31#H sync = 2640 - 2608 = 32
32#H back porch = 2720 - 2640 = 80
33#V front porch = 1703 - 1700 = 3
34#V sync = 1713 - 1703 = 10
35#V back porch = 1749 - 1713 = 36
36#href_to_sync and vref_to_sync are from the vendor
37#this is just an example for a Pixel panel; other panels differ.
38# Here is a peppy panel:
39#  1366x768 (0x45)   76.4MHz -HSync -VSync *current +preferred
40#        h: width  1366 start 1502 end 1532 total 1592
41#        v: height  768 start  776 end  788 total  800
42	register "href_to_sync" = "1"
43	register "hfront_porch" = "136"
44	register "hsync_width" = "30"
45	register "hback_porch" = "60"
46
47	register "vref_to_sync" = "1"
48	register "vfront_porch" = "8"
49	register "vsync_width" = "12"
50	register "vback_porch" = "12"
51
52	register "pixel_clock" = "76400000"
53
54	register "win_opt" = "SOR_ENABLE"
55
56	#
57	# dp specific fields
58	#
59	register "dp.pwm" = "1"
60
61	# various panel delay time
62	register "dp.vdd_to_hpd_delay_ms" = "200"
63	register "dp.hpd_unplug_min_us" = "2000"
64	register "dp.hpd_plug_min_us" = "250"
65	register "dp.hpd_irq_min_us" = "250"
66
67	# link configurations
68	register "dp.lane_count" = "1"
69	register "dp.enhanced_framing" = "1"
70	register "dp.link_bw" = "10"
71	# "10" is defined as SOR_LINK_SPEED_G2_7 in sor.h
72
73	register "dp.drive_current" = "0x40404040"
74	register "dp.preemphasis" = "0x0f0f0f0f"
75	register "dp.postcursor" = "0"
76end
77