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/external/trusty/arm-trusted-firmware/fdts/
Drtsm_ve-motherboard.dtsi108 interrupts = <15>;
138 interrupts = <11>;
146 interrupts = <9>, <10>;
158 interrupts = <12>;
166 interrupts = <13>;
174 interrupts = <5>;
182 interrupts = <6>;
190 interrupts = <7>;
198 interrupts = <8>;
206 interrupts = <0>;
[all …]
Dfvp-foundation-motherboard.dtsi17 interrupts = <0 15 4>;
66 interrupts = <0 5 4>;
74 interrupts = <0 6 4>;
82 interrupts = <0 7 4>;
90 interrupts = <0 8 4>;
98 interrupts = <0 0 4>;
106 interrupts = <0 2 4>;
114 interrupts = <0 3 4>;
122 interrupts = <0 4 4>;
130 interrupts = <0 0x2a 4>;
Dstm32mp151.dtsi92 interrupts-extended = <&exti 27 IRQ_TYPE_LEVEL_HIGH>;
101 interrupts-extended = <&exti 28 IRQ_TYPE_LEVEL_HIGH>;
110 interrupts-extended = <&exti 30 IRQ_TYPE_LEVEL_HIGH>;
120 interrupts-extended = <&exti 31 IRQ_TYPE_LEVEL_HIGH>;
130 interrupts-extended = <&exti 22 IRQ_TYPE_LEVEL_HIGH>,
144 interrupts-extended = <&exti 32 IRQ_TYPE_LEVEL_HIGH>;
153 interrupts-extended = <&exti 33 IRQ_TYPE_LEVEL_HIGH>;
162 interrupts-extended = <&exti 29 IRQ_TYPE_LEVEL_HIGH>;
185 interrupts-extended = <&exti 44 IRQ_TYPE_LEVEL_HIGH>;
201 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
[all …]
Dcorstone700.dtsi43 interrupts = <1 9 0xf08>;
77 interrupts = <0 19 4>;
86 interrupts = <0 20 4>;
93 interrupts = <1 13 0xf08>,
108 interrupts = <0 2 0xf04>;
119 interrupts = <0 12 4>;
131 interrupts = <0 47 4>;
143 interrupts = <0 45 4>;
Dmorello-fvp.dts126 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
132 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
138 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
144 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
150 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
156 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
164 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
196 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
Da5ds.dts60 interrupts = <0 84 4>;
93 interrupts = <0 6 0xf04>;
104 interrupts = <1 9 0xf04>;
111 interrupts = <0 8 0xf04>;
120 interrupts = <0 9 0xf04>;
135 interrupts = <0 2 0xf04>;
151 interrupts = <0 43 0xf04>;
Dstm32mp131.dtsi84 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
93 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
102 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
111 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
120 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
129 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
142 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
154 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
163 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
173 interrupts-extended = <&exti 23 IRQ_TYPE_LEVEL_HIGH>,
[all …]
/external/arm-trusted-firmware/fdts/
Drtsm_ve-motherboard.dtsi29 interrupts = <0 15 4>;
78 interrupts = <0 11 4>;
86 interrupts = <0 9 4 0 10 4>;
98 interrupts = <0 12 4>;
106 interrupts = <0 13 4>;
114 interrupts = <0 5 4>;
122 interrupts = <0 6 4>;
130 interrupts = <0 7 4>;
138 interrupts = <0 8 4>;
146 interrupts = <0 0 4>;
[all …]
Drtsm_ve-motherboard-aarch32.dtsi30 interrupts = <15>;
79 interrupts = <11>;
87 interrupts = <9 10>;
99 interrupts = <12>;
107 interrupts = <13>;
115 interrupts = <5>;
123 interrupts = <6>;
131 interrupts = <7>;
139 interrupts = <8>;
147 interrupts = <0>;
[all …]
Dfvp-foundation-motherboard.dtsi17 interrupts = <0 15 4>;
66 interrupts = <0 5 4>;
74 interrupts = <0 6 4>;
82 interrupts = <0 7 4>;
90 interrupts = <0 8 4>;
98 interrupts = <0 0 4>;
106 interrupts = <0 2 4>;
114 interrupts = <0 3 4>;
122 interrupts = <0 4 4>;
130 interrupts = <0 0x2a 4>;
Dstm32mp151.dtsi90 interrupts-extended = <&exti 27 IRQ_TYPE_LEVEL_HIGH>;
99 interrupts-extended = <&exti 28 IRQ_TYPE_LEVEL_HIGH>;
108 interrupts-extended = <&exti 30 IRQ_TYPE_LEVEL_HIGH>;
118 interrupts-extended = <&exti 31 IRQ_TYPE_LEVEL_HIGH>;
128 interrupts = <&exti 22 IRQ_TYPE_LEVEL_HIGH>,
142 interrupts-extended = <&exti 32 IRQ_TYPE_LEVEL_HIGH>;
151 interrupts-extended = <&exti 33 IRQ_TYPE_LEVEL_HIGH>;
160 interrupts-extended = <&exti 29 IRQ_TYPE_LEVEL_HIGH>;
183 interrupts-extended = <&exti 44 IRQ_TYPE_LEVEL_HIGH>;
199 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
[all …]
Dmorello-fvp.dts99 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
105 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
111 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
117 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
123 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
129 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
137 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
169 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
Dcorstone700.dtsi43 interrupts = <1 9 0xf08>;
77 interrupts = <0 19 4>;
86 interrupts = <0 20 4>;
93 interrupts = <1 13 0xf08>,
108 interrupts = <0 2 0xf04>;
119 interrupts = <0 12 4>;
131 interrupts = <0 47 4>;
143 interrupts = <0 45 4>;
Da5ds.dts60 interrupts = <0 84 4>;
93 interrupts = <0 6 0xf04>;
104 interrupts = <1 9 0xf04>;
111 interrupts = <0 8 0xf04>;
120 interrupts = <0 9 0xf04>;
135 interrupts = <0 2 0xf04>;
151 interrupts = <0 43 0xf04>;
Dmorello.dtsi31 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
36 interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>;
46 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
55 interrupts = <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
101 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
/external/crosvm/devices/src/virtio/vhost/
Dscmi.rs37 interrupts: Option<Vec<Event>>, field
49 let mut interrupts = Vec::new(); in new() localVariable
51 interrupts.push(Event::new().map_err(Error::VhostIrqCreate)?); in new()
57 interrupts: Some(interrupts), in new()
76 if let Some(interrupt) = &self.interrupts { in keep_rds()
125 let interrupts = self.interrupts.take().context("missing interrupts")?; in activate() localVariable
130 interrupts, in activate()
Dvsock.rs46 interrupts: Option<Vec<Event>>, field
88 let mut interrupts = Vec::new(); in new() localVariable
90 interrupts.push(Event::new().map_err(Error::VhostIrqCreate)?); in new()
97 interrupts: Some(interrupts), in new()
111 interrupts: None, in new_for_testing()
133 if let Some(interrupt) = &self.interrupts { in keep_rds()
188 let interrupts = self.interrupts.take().context("missing interrupts")?; in activate() localVariable
224 interrupts, in activate()
266 self.interrupts = Some(worker.vhost_interrupt); in reset()
290 self.interrupts = Some(worker.vhost_interrupt); in virtio_sleep()
/external/rust/android-crates-io/crates/portable-atomic/src/imp/interrupt/
DREADME.md1 # Implementation of disabling interrupts
8 The `unsafe-assume-single-core` implementation uses privileged instructions to disable interrupts, …
9 …t available, or if the instructions used are not sufficient to disable interrupts in the system, i…
15 - On Armv6-M, this disables interrupts by modifying the PRIMASK register.
16 - On pre-v6 Arm, this disables interrupts by modifying the I (IRQ mask) bit of the CPSR.
17 …ble-fiq` feature (or `portable_atomic_disable_fiq` cfg), this disables interrupts by modifying the…
18 - On RISC-V (without A-extension), this disables interrupts by modifying the MIE (Machine Interrupt…
19 … the `s-mode` feature (or `portable_atomic_s_mode` cfg), this disables interrupts by modifying the…
20 …MO instructions even if A-extension is disabled. For other RMWs, this disables interrupts as usual.
21 - On MSP430, this disables interrupts by modifying the GIE (Global Interrupt Enable) bit of the sta…
[all …]
/external/perfetto/src/traced/probes/ftrace/
Dprintk_formats_parser_unittest.cc32 std::string format = R"(0x0 : "Rescheduling interrupts" in TEST()
33 0x0 : "Function call interrupts" in TEST()
34 0x0 : "CPU stop interrupts" in TEST()
35 0x0 : "Timer broadcast interrupts" in TEST()
36 0x0 : "IRQ work interrupts" in TEST()
37 0x0 : "CPU wakeup interrupts" in TEST()
/external/pigweed/pw_cpu_exception_cortex_m/
Dexception_entry_test_util.cc78 uint32_t** interrupts = reinterpret_cast<uint32_t**>(&ram_vector_table); in InstallVectorTableEntries() local
79 interrupts[kHardFaultIsrNum] = exception_entry_addr; in InstallVectorTableEntries()
82 interrupts[kMemFaultIsrNum] = exception_entry_addr; in InstallVectorTableEntries()
83 interrupts[kBusFaultIsrNum] = exception_entry_addr; in InstallVectorTableEntries()
84 interrupts[kUsageFaultIsrNum] = exception_entry_addr; in InstallVectorTableEntries()
/external/coreboot/src/mainboard/sifive/hifive-unmatched/
Dfu740-c000.dtsi165 // clint is mainly used by openSBI and not the OS, since interrupts-extended currently only
166 // contains machine mode interrupts which the OS will ignore if not running in machine mode
170 interrupts-extended = <&cpu0_intc 3 &cpu0_intc 7
184 interrupts-extended =
202 interrupts = <39>;
210 interrupts = <40>;
218 interrupts = <52>;
230 interrupts = <53>;
243 interrupts = <41>;
254 interrupts = <42>;
[all …]
/external/crosvm/docs/book/src/architecture/
Dinterrupts.md13 - MSI: message signaled interrupts. In this document, synonymous with MSI-X.
14 - MSI-X: message signaled interrupts - extended
24 MSI is used to refer to the concept of message signaled interrupts, but it always refers to
25 interrupts sent via MSI-X because that is what CrosVM uses.
27 ### Legacy interrupts (INTx)
29 These interrupts are traditionally delivered via dedicated signal lines to PICs and/or the IOAPIC.
31 interrupts. These typically are the first 24 GSIs, and are serviced either by the PIC (during very
72 ## The fundamental deception on x86_64: there are no legacy interrupts (usually)
74 After very early boot, the PIC is switched off and legacy interrupts somewhat cease to be legacy.
75 Instead of being handled by the PIC, legacy interrupts are handled by the IOAPIC, and all the IOAPIC
[all …]
/external/trusty/arm-trusted-firmware/docs/components/
Dexception-handling.rst108 executing in EL3, or has delegated the execution to a lower EL. For interrupts,
117 interrupts. Dispatchers handling such exceptions must therefore explicitly
133 unstacked in strictly the reverse order. For interrupts, the GIC ensures this is
134 the case; for non-interrupts, the |EHF| monitors and asserts this. See
143 top-level handler for interrupts that target EL3, as described in the
147 - On GICv3 systems, when executing in S-EL1, pending Non-secure interrupts of
150 interrupts at S-EL1. Essentially, this deprecates the routing mode described
151 as :ref:`CSS=0, TEL3=0 <EL3 interrupts>`.
153 In order for S-EL1 software to handle Non-secure interrupts while having
154 |EHF| enabled, the dispatcher must adopt a model where Non-secure interrupts
[all …]
/external/arm-trusted-firmware/docs/components/
Dexception-handling.rst108 executing in EL3, or has delegated the execution to a lower EL. For interrupts,
117 interrupts. Dispatchers handling such exceptions must therefore explicitly
133 unstacked in strictly the reverse order. For interrupts, the GIC ensures this is
134 the case; for non-interrupts, the |EHF| monitors and asserts this. See
143 top-level handler for interrupts that target EL3, as described in the
147 - On GICv3 systems, when executing in S-EL1, pending Non-secure interrupts of
150 interrupts at S-EL1. Essentially, this deprecates the routing mode described
151 as :ref:`CSS=0, TEL3=0 <EL3 interrupts>`.
153 In order for S-EL1 software to handle Non-secure interrupts while having
154 |EHF| enabled, the dispatcher must adopt a model where Non-secure interrupts
[all …]
/external/arm-trusted-firmware/docs/design/
Dinterrupt-framework-design.rst4 This framework is responsible for managing interrupts routed to EL3. It also
8 #. It should be possible to route interrupts meant to be handled by secure
9 software (Secure interrupts) to EL3, when execution is in non-secure state
13 that secure interrupts are under the control of the secure software with
17 #. It should be possible to route interrupts meant to be handled by
18 non-secure software (Non-secure interrupts) to the last executed exception
64 to the First Exception Level (FEL) capable of handling interrupts. When
84 which ones are valid or invalid. EL3 interrupts are currently supported only
95 Secure-EL1 interrupts
100 control of handling secure interrupts.
[all …]

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