Home
last modified time | relevance | path

Searched refs:vs_stage (Results 1 – 6 of 6) sorted by relevance

/external/mesa3d/src/intel/vulkan_hasvk/
Danv_pipeline.c592 struct anv_pipeline_stage *vs_stage, in anv_pipeline_link_vs() argument
596 elk_nir_link_shaders(compiler, vs_stage->nir, next_stage->nir); in anv_pipeline_link_vs()
603 struct anv_pipeline_stage *vs_stage) in anv_pipeline_compile_vs() argument
609 (vs_stage->nir->info.per_view_outputs & VARYING_BIT_POS) ? in anv_pipeline_compile_vs()
613 assert(!(vs_stage->nir->info.per_view_outputs & ~VARYING_BIT_POS)); in anv_pipeline_compile_vs()
616 &vs_stage->prog_data.vs.base.vue_map, in anv_pipeline_compile_vs()
617 vs_stage->nir->info.outputs_written, in anv_pipeline_compile_vs()
618 vs_stage->nir->info.separate_shader, in anv_pipeline_compile_vs()
621 vs_stage->num_stats = 1; in anv_pipeline_compile_vs()
625 .nir = vs_stage->nir, in anv_pipeline_compile_vs()
[all …]
/external/mesa3d/src/amd/vulkan/nir/
Dradv_nir_lower_vs_inputs.c396 radv_nir_lower_vs_inputs(nir_shader *shader, const struct radv_shader_stage *vs_stage, in radv_nir_lower_vs_inputs() argument
402 .info = &vs_stage->info, in radv_nir_lower_vs_inputs()
403 .args = &vs_stage->args, in radv_nir_lower_vs_inputs()
Dradv_nir.h41 bool radv_nir_lower_vs_inputs(nir_shader *shader, const struct radv_shader_stage *vs_stage,
/external/mesa3d/src/amd/vulkan/
Dradv_shader_info.c1778 struct radv_shader_stage *vs_stage = producer; in radv_link_shaders_info() local
1781 vs_stage->info.vs.tcs_inputs_via_lds = tcs_stage->nir->info.inputs_read; in radv_link_shaders_info()
1784 vs_stage->info.workgroup_size = in radv_link_shaders_info()
1798 vs_stage->info.vs.tcs_in_out_eq = in radv_link_shaders_info()
1801 …vs_stage->nir->info.float_controls_execution_mode == tcs_stage->nir->info.float_controls_execution… in radv_link_shaders_info()
1803 if (vs_stage->info.vs.tcs_in_out_eq) { in radv_link_shaders_info()
1804 vs_stage->info.vs.tcs_inputs_via_temp = vs_stage->nir->info.outputs_written & in radv_link_shaders_info()
1805 … ~vs_stage->nir->info.outputs_accessed_indirectly & in radv_link_shaders_info()
1807 …vs_stage->info.vs.tcs_inputs_via_lds = tcs_stage->nir->info.tess.tcs_cross_invocation_inputs_read | in radv_link_shaders_info()
1811 … vs_stage->nir->info.outputs_accessed_indirectly); in radv_link_shaders_info()
Dradv_pipeline_graphics.c1255 radv_link_vs(const struct radv_device *device, struct radv_shader_stage *vs_stage, struct radv_shad… in radv_link_vs() argument
1258 assert(vs_stage->nir->info.stage == MESA_SHADER_VERTEX); in radv_link_vs()
1260 if (radv_should_export_multiview(vs_stage, gfx_state)) { in radv_link_vs()
1261 NIR_PASS(_, vs_stage->nir, radv_nir_export_multiview); in radv_link_vs()
1269 radv_link_shaders(device, vs_stage, next_stage, gfx_state); in radv_link_vs()
1555 radv_graphics_shaders_fill_linked_vs_io_info(struct radv_shader_stage *vs_stage, in radv_graphics_shaders_fill_linked_vs_io_info() argument
1559 vs_stage->info.vs.num_linked_outputs = num_reserved_slots; in radv_graphics_shaders_fill_linked_vs_io_info()
1560 vs_stage->info.outputs_linked = true; in radv_graphics_shaders_fill_linked_vs_io_info()
/external/mesa3d/src/intel/vulkan/
Danv_pipeline.c1183 struct anv_pipeline_stage *vs_stage, in anv_pipeline_link_vs() argument
1187 brw_nir_link_shaders(compiler, vs_stage->nir, next_stage->nir); in anv_pipeline_link_vs()
1194 struct anv_pipeline_stage *vs_stage, in anv_pipeline_compile_vs() argument
1202 (vs_stage->nir->info.per_view_outputs & VARYING_BIT_POS) ? in anv_pipeline_compile_vs()
1206 assert(!(vs_stage->nir->info.per_view_outputs & ~VARYING_BIT_POS)); in anv_pipeline_compile_vs()
1209 &vs_stage->prog_data.vs.base.vue_map, in anv_pipeline_compile_vs()
1210 vs_stage->nir->info.outputs_written, in anv_pipeline_compile_vs()
1211 vs_stage->nir->info.separate_shader, in anv_pipeline_compile_vs()
1214 vs_stage->num_stats = 1; in anv_pipeline_compile_vs()
1218 .nir = vs_stage->nir, in anv_pipeline_compile_vs()
[all …]