Home
last modified time | relevance | path

Searched refs:vsync_width (Results 1 – 18 of 18) sorted by relevance

/external/coreboot/src/soc/nvidia/tegra210/
Dchip.h46 int vsync_width; member
Ddc.c76 config->hsync_width, config->vsync_width); in update_display_mode()
91 WRITEL(config->vsync_width << 16 | config->hsync_width, in update_display_mode()
Dsor.c620 vsync_end = config->vsync_width - 1; in tegra_dc_sor_config_panel()
Ddp.c1367 config->vsync_width = edid.mode.vspw; in tegra_dp_update_config()
/external/coreboot/src/soc/nvidia/tegra124/
Dchip.h72 int vsync_width; member
Ddisplay.c56 config->vsync_width; in tegra_dc_calc_refresh()
87 WRITEL(config->vsync_width << 16 | config->hsync_width, in update_display_mode()
Dsor.c618 vtotal = config->vsync_width + config->vback_porch + in tegra_dc_sor_config_panel()
627 vsync_end = config->vsync_width - 1; in tegra_dc_sor_config_panel()
Ddp.c1326 config->vsync_width = edid.mode.vspw; in tegra_dp_update_config()
/external/coreboot/src/mainboard/google/smaug/
Ddevicetree.cb25 register "vsync_width" = "4"
/external/coreboot/src/soc/nvidia/tegra210/include/soc/
Ddisplay.h21 mode->vsync_width + mode->vback_porch)
/external/coreboot/src/mainboard/google/foster/
Ddevicetree.cb49 register "vsync_width" = "12"
/external/coreboot/src/mainboard/google/nyan_blaze/
Ddevicetree.cb61 register "vsync_width" = "12"
/external/coreboot/src/mainboard/google/nyan/
Ddevicetree.cb61 register "vsync_width" = "12"
/external/coreboot/src/mainboard/google/nyan_big/
Ddevicetree.cb61 register "vsync_width" = "12"
/external/igt-gpu-tools/lib/
Digt_chamelium.h60 int vtotal, vactive, vsync_offset, vsync_width, vsync_polarity; member
Digt_chamelium.c832 &params->vsync_width); in video_params_from_xml()
/external/coreboot/src/soc/mediatek/mt8173/include/soc/
Dddp.h259 u32 vsync_width; member
/external/igt-gpu-tools/tests/
Dkms_chamelium.c961 video_params.vsync_width, mode_vsync_width); in check_mode()
980 igt_assert(video_params.vsync_width == mode_vsync_width); in check_mode()