1 /*
2 * Copyright (C) 2023 The Android Open Source Project
3 *
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
7 *
8 * http://www.apache.org/licenses/LICENSE-2.0
9 *
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 */
16
17 #include "managed_register_riscv64.h"
18
19 #include "base/globals.h"
20 #include "gtest/gtest.h"
21
22 namespace art HIDDEN {
23 namespace riscv64 {
24
TEST(Riscv64ManagedRegister,NoRegister)25 TEST(Riscv64ManagedRegister, NoRegister) {
26 Riscv64ManagedRegister reg = ManagedRegister::NoRegister().AsRiscv64();
27 EXPECT_TRUE(reg.IsNoRegister());
28 }
29
TEST(Riscv64ManagedRegister,XRegister)30 TEST(Riscv64ManagedRegister, XRegister) {
31 Riscv64ManagedRegister reg = Riscv64ManagedRegister::FromXRegister(Zero);
32 EXPECT_FALSE(reg.IsNoRegister());
33 EXPECT_TRUE(reg.IsXRegister());
34 EXPECT_FALSE(reg.IsFRegister());
35 EXPECT_EQ(Zero, reg.AsXRegister());
36
37 reg = Riscv64ManagedRegister::FromXRegister(RA);
38 EXPECT_FALSE(reg.IsNoRegister());
39 EXPECT_TRUE(reg.IsXRegister());
40 EXPECT_FALSE(reg.IsFRegister());
41 EXPECT_EQ(RA, reg.AsXRegister());
42
43 reg = Riscv64ManagedRegister::FromXRegister(SP);
44 EXPECT_FALSE(reg.IsNoRegister());
45 EXPECT_TRUE(reg.IsXRegister());
46 EXPECT_FALSE(reg.IsFRegister());
47 EXPECT_EQ(SP, reg.AsXRegister());
48
49 reg = Riscv64ManagedRegister::FromXRegister(GP);
50 EXPECT_FALSE(reg.IsNoRegister());
51 EXPECT_TRUE(reg.IsXRegister());
52 EXPECT_FALSE(reg.IsFRegister());
53 EXPECT_EQ(GP, reg.AsXRegister());
54
55 reg = Riscv64ManagedRegister::FromXRegister(T0);
56 EXPECT_FALSE(reg.IsNoRegister());
57 EXPECT_TRUE(reg.IsXRegister());
58 EXPECT_FALSE(reg.IsFRegister());
59 EXPECT_EQ(T0, reg.AsXRegister());
60
61 reg = Riscv64ManagedRegister::FromXRegister(T2);
62 EXPECT_FALSE(reg.IsNoRegister());
63 EXPECT_TRUE(reg.IsXRegister());
64 EXPECT_FALSE(reg.IsFRegister());
65 EXPECT_EQ(T2, reg.AsXRegister());
66
67 reg = Riscv64ManagedRegister::FromXRegister(S0);
68 EXPECT_FALSE(reg.IsNoRegister());
69 EXPECT_TRUE(reg.IsXRegister());
70 EXPECT_FALSE(reg.IsFRegister());
71 EXPECT_EQ(S0, reg.AsXRegister());
72
73 reg = Riscv64ManagedRegister::FromXRegister(A0);
74 EXPECT_FALSE(reg.IsNoRegister());
75 EXPECT_TRUE(reg.IsXRegister());
76 EXPECT_FALSE(reg.IsFRegister());
77 EXPECT_EQ(A0, reg.AsXRegister());
78
79 reg = Riscv64ManagedRegister::FromXRegister(A7);
80 EXPECT_FALSE(reg.IsNoRegister());
81 EXPECT_TRUE(reg.IsXRegister());
82 EXPECT_FALSE(reg.IsFRegister());
83 EXPECT_EQ(A7, reg.AsXRegister());
84
85 reg = Riscv64ManagedRegister::FromXRegister(S2);
86 EXPECT_FALSE(reg.IsNoRegister());
87 EXPECT_TRUE(reg.IsXRegister());
88 EXPECT_FALSE(reg.IsFRegister());
89 EXPECT_EQ(S2, reg.AsXRegister());
90
91 reg = Riscv64ManagedRegister::FromXRegister(T3);
92 EXPECT_FALSE(reg.IsNoRegister());
93 EXPECT_TRUE(reg.IsXRegister());
94 EXPECT_FALSE(reg.IsFRegister());
95 EXPECT_EQ(T3, reg.AsXRegister());
96 }
97
TEST(Riscv64ManagedRegister,FRegister)98 TEST(Riscv64ManagedRegister, FRegister) {
99 Riscv64ManagedRegister reg = Riscv64ManagedRegister::FromFRegister(FT0);
100 EXPECT_FALSE(reg.IsNoRegister());
101 EXPECT_FALSE(reg.IsXRegister());
102 EXPECT_TRUE(reg.IsFRegister());
103 EXPECT_EQ(FT0, reg.AsFRegister());
104 EXPECT_TRUE(reg.Equals(Riscv64ManagedRegister::FromFRegister(FT0)));
105
106 reg = Riscv64ManagedRegister::FromFRegister(FT1);
107 EXPECT_FALSE(reg.IsNoRegister());
108 EXPECT_FALSE(reg.IsXRegister());
109 EXPECT_TRUE(reg.IsFRegister());
110 EXPECT_EQ(FT1, reg.AsFRegister());
111 EXPECT_TRUE(reg.Equals(Riscv64ManagedRegister::FromFRegister(FT1)));
112
113 reg = Riscv64ManagedRegister::FromFRegister(FS0);
114 EXPECT_FALSE(reg.IsNoRegister());
115 EXPECT_FALSE(reg.IsXRegister());
116 EXPECT_TRUE(reg.IsFRegister());
117 EXPECT_EQ(FS0, reg.AsFRegister());
118 EXPECT_TRUE(reg.Equals(Riscv64ManagedRegister::FromFRegister(FS0)));
119
120 reg = Riscv64ManagedRegister::FromFRegister(FA0);
121 EXPECT_FALSE(reg.IsNoRegister());
122 EXPECT_FALSE(reg.IsXRegister());
123 EXPECT_TRUE(reg.IsFRegister());
124 EXPECT_EQ(FA0, reg.AsFRegister());
125 EXPECT_TRUE(reg.Equals(Riscv64ManagedRegister::FromFRegister(FA0)));
126
127 reg = Riscv64ManagedRegister::FromFRegister(FA7);
128 EXPECT_FALSE(reg.IsNoRegister());
129 EXPECT_FALSE(reg.IsXRegister());
130 EXPECT_TRUE(reg.IsFRegister());
131 EXPECT_EQ(FA7, reg.AsFRegister());
132 EXPECT_TRUE(reg.Equals(Riscv64ManagedRegister::FromFRegister(FA7)));
133
134 reg = Riscv64ManagedRegister::FromFRegister(FS4);
135 EXPECT_FALSE(reg.IsNoRegister());
136 EXPECT_FALSE(reg.IsXRegister());
137 EXPECT_TRUE(reg.IsFRegister());
138 EXPECT_EQ(FS4, reg.AsFRegister());
139 EXPECT_TRUE(reg.Equals(Riscv64ManagedRegister::FromFRegister(FS4)));
140
141 reg = Riscv64ManagedRegister::FromFRegister(FT11);
142 EXPECT_FALSE(reg.IsNoRegister());
143 EXPECT_FALSE(reg.IsXRegister());
144 EXPECT_TRUE(reg.IsFRegister());
145 EXPECT_EQ(FT11, reg.AsFRegister());
146 EXPECT_TRUE(reg.Equals(Riscv64ManagedRegister::FromFRegister(FT11)));
147 }
148
TEST(Riscv64ManagedRegister,Equals)149 TEST(Riscv64ManagedRegister, Equals) {
150 ManagedRegister no_reg = ManagedRegister::NoRegister();
151 EXPECT_TRUE(no_reg.Equals(Riscv64ManagedRegister::NoRegister()));
152 EXPECT_FALSE(no_reg.Equals(Riscv64ManagedRegister::FromXRegister(Zero)));
153 EXPECT_FALSE(no_reg.Equals(Riscv64ManagedRegister::FromXRegister(A1)));
154 EXPECT_FALSE(no_reg.Equals(Riscv64ManagedRegister::FromXRegister(S2)));
155 EXPECT_FALSE(no_reg.Equals(Riscv64ManagedRegister::FromFRegister(FT0)));
156 EXPECT_FALSE(no_reg.Equals(Riscv64ManagedRegister::FromFRegister(FT11)));
157
158 Riscv64ManagedRegister reg_Zero = Riscv64ManagedRegister::FromXRegister(Zero);
159 EXPECT_FALSE(reg_Zero.Equals(Riscv64ManagedRegister::NoRegister()));
160 EXPECT_TRUE(reg_Zero.Equals(Riscv64ManagedRegister::FromXRegister(Zero)));
161 EXPECT_FALSE(reg_Zero.Equals(Riscv64ManagedRegister::FromXRegister(A1)));
162 EXPECT_FALSE(reg_Zero.Equals(Riscv64ManagedRegister::FromXRegister(S2)));
163 EXPECT_FALSE(reg_Zero.Equals(Riscv64ManagedRegister::FromFRegister(FT0)));
164 EXPECT_FALSE(reg_Zero.Equals(Riscv64ManagedRegister::FromFRegister(FT11)));
165
166 Riscv64ManagedRegister reg_A1 = Riscv64ManagedRegister::FromXRegister(A1);
167 EXPECT_FALSE(reg_A1.Equals(Riscv64ManagedRegister::NoRegister()));
168 EXPECT_FALSE(reg_A1.Equals(Riscv64ManagedRegister::FromXRegister(Zero)));
169 EXPECT_FALSE(reg_A1.Equals(Riscv64ManagedRegister::FromXRegister(A0)));
170 EXPECT_TRUE(reg_A1.Equals(Riscv64ManagedRegister::FromXRegister(A1)));
171 EXPECT_FALSE(reg_A1.Equals(Riscv64ManagedRegister::FromXRegister(S2)));
172 EXPECT_FALSE(reg_A1.Equals(Riscv64ManagedRegister::FromFRegister(FT0)));
173 EXPECT_FALSE(reg_A1.Equals(Riscv64ManagedRegister::FromFRegister(FT11)));
174
175 Riscv64ManagedRegister reg_S2 = Riscv64ManagedRegister::FromXRegister(S2);
176 EXPECT_FALSE(reg_S2.Equals(Riscv64ManagedRegister::NoRegister()));
177 EXPECT_FALSE(reg_S2.Equals(Riscv64ManagedRegister::FromXRegister(Zero)));
178 EXPECT_FALSE(reg_S2.Equals(Riscv64ManagedRegister::FromXRegister(A1)));
179 EXPECT_FALSE(reg_S2.Equals(Riscv64ManagedRegister::FromXRegister(S1)));
180 EXPECT_TRUE(reg_S2.Equals(Riscv64ManagedRegister::FromXRegister(S2)));
181 EXPECT_FALSE(reg_S2.Equals(Riscv64ManagedRegister::FromFRegister(FT0)));
182 EXPECT_FALSE(reg_S2.Equals(Riscv64ManagedRegister::FromFRegister(FT11)));
183
184 Riscv64ManagedRegister reg_F0 = Riscv64ManagedRegister::FromFRegister(FT0);
185 EXPECT_FALSE(reg_F0.Equals(Riscv64ManagedRegister::NoRegister()));
186 EXPECT_FALSE(reg_F0.Equals(Riscv64ManagedRegister::FromXRegister(Zero)));
187 EXPECT_FALSE(reg_F0.Equals(Riscv64ManagedRegister::FromXRegister(A1)));
188 EXPECT_FALSE(reg_F0.Equals(Riscv64ManagedRegister::FromXRegister(S2)));
189 EXPECT_TRUE(reg_F0.Equals(Riscv64ManagedRegister::FromFRegister(FT0)));
190 EXPECT_FALSE(reg_F0.Equals(Riscv64ManagedRegister::FromFRegister(FT1)));
191 EXPECT_FALSE(reg_F0.Equals(Riscv64ManagedRegister::FromFRegister(FT11)));
192
193 Riscv64ManagedRegister reg_F31 = Riscv64ManagedRegister::FromFRegister(FT11);
194 EXPECT_FALSE(reg_F31.Equals(Riscv64ManagedRegister::NoRegister()));
195 EXPECT_FALSE(reg_F31.Equals(Riscv64ManagedRegister::FromXRegister(Zero)));
196 EXPECT_FALSE(reg_F31.Equals(Riscv64ManagedRegister::FromXRegister(A1)));
197 EXPECT_FALSE(reg_F31.Equals(Riscv64ManagedRegister::FromXRegister(S2)));
198 EXPECT_FALSE(reg_F31.Equals(Riscv64ManagedRegister::FromFRegister(FT0)));
199 EXPECT_FALSE(reg_F31.Equals(Riscv64ManagedRegister::FromFRegister(FT1)));
200 EXPECT_TRUE(reg_F31.Equals(Riscv64ManagedRegister::FromFRegister(FT11)));
201 }
202
203 } // namespace riscv64
204 } // namespace art
205