1 /* 2 * This file is auto-generated. Modifications will be lost. 3 * 4 * See https://android.googlesource.com/platform/bionic/+/master/libc/kernel/ 5 * for more information. 6 */ 7 #ifndef _ASM_X86_KVM_H 8 #define _ASM_X86_KVM_H 9 #include <linux/const.h> 10 #include <linux/bits.h> 11 #include <linux/types.h> 12 #include <linux/ioctl.h> 13 #include <linux/stddef.h> 14 #define KVM_PIO_PAGE_OFFSET 1 15 #define KVM_COALESCED_MMIO_PAGE_OFFSET 2 16 #define KVM_DIRTY_LOG_PAGE_OFFSET 64 17 #define DE_VECTOR 0 18 #define DB_VECTOR 1 19 #define BP_VECTOR 3 20 #define OF_VECTOR 4 21 #define BR_VECTOR 5 22 #define UD_VECTOR 6 23 #define NM_VECTOR 7 24 #define DF_VECTOR 8 25 #define TS_VECTOR 10 26 #define NP_VECTOR 11 27 #define SS_VECTOR 12 28 #define GP_VECTOR 13 29 #define PF_VECTOR 14 30 #define MF_VECTOR 16 31 #define AC_VECTOR 17 32 #define MC_VECTOR 18 33 #define XM_VECTOR 19 34 #define VE_VECTOR 20 35 #define __KVM_HAVE_PIT 36 #define __KVM_HAVE_IOAPIC 37 #define __KVM_HAVE_IRQ_LINE 38 #define __KVM_HAVE_MSI 39 #define __KVM_HAVE_USER_NMI 40 #define __KVM_HAVE_MSIX 41 #define __KVM_HAVE_MCE 42 #define __KVM_HAVE_PIT_STATE2 43 #define __KVM_HAVE_XEN_HVM 44 #define __KVM_HAVE_VCPU_EVENTS 45 #define __KVM_HAVE_DEBUGREGS 46 #define __KVM_HAVE_XSAVE 47 #define __KVM_HAVE_XCRS 48 #define KVM_NR_INTERRUPTS 256 49 struct kvm_pic_state { 50 __u8 last_irr; 51 __u8 irr; 52 __u8 imr; 53 __u8 isr; 54 __u8 priority_add; 55 __u8 irq_base; 56 __u8 read_reg_select; 57 __u8 poll; 58 __u8 special_mask; 59 __u8 init_state; 60 __u8 auto_eoi; 61 __u8 rotate_on_auto_eoi; 62 __u8 special_fully_nested_mode; 63 __u8 init4; 64 __u8 elcr; 65 __u8 elcr_mask; 66 }; 67 #define KVM_IOAPIC_NUM_PINS 24 68 struct kvm_ioapic_state { 69 __u64 base_address; 70 __u32 ioregsel; 71 __u32 id; 72 __u32 irr; 73 __u32 pad; 74 union { 75 __u64 bits; 76 struct { 77 __u8 vector; 78 __u8 delivery_mode : 3; 79 __u8 dest_mode : 1; 80 __u8 delivery_status : 1; 81 __u8 polarity : 1; 82 __u8 remote_irr : 1; 83 __u8 trig_mode : 1; 84 __u8 mask : 1; 85 __u8 reserve : 7; 86 __u8 reserved[4]; 87 __u8 dest_id; 88 } fields; 89 } redirtbl[KVM_IOAPIC_NUM_PINS]; 90 }; 91 #define KVM_IRQCHIP_PIC_MASTER 0 92 #define KVM_IRQCHIP_PIC_SLAVE 1 93 #define KVM_IRQCHIP_IOAPIC 2 94 #define KVM_NR_IRQCHIPS 3 95 #define KVM_RUN_X86_SMM (1 << 0) 96 #define KVM_RUN_X86_BUS_LOCK (1 << 1) 97 #define KVM_RUN_X86_GUEST_MODE (1 << 2) 98 struct kvm_regs { 99 __u64 rax, rbx, rcx, rdx; 100 __u64 rsi, rdi, rsp, rbp; 101 __u64 r8, r9, r10, r11; 102 __u64 r12, r13, r14, r15; 103 __u64 rip, rflags; 104 }; 105 #define KVM_APIC_REG_SIZE 0x400 106 struct kvm_lapic_state { 107 char regs[KVM_APIC_REG_SIZE]; 108 }; 109 struct kvm_segment { 110 __u64 base; 111 __u32 limit; 112 __u16 selector; 113 __u8 type; 114 __u8 present, dpl, db, s, l, g, avl; 115 __u8 unusable; 116 __u8 padding; 117 }; 118 struct kvm_dtable { 119 __u64 base; 120 __u16 limit; 121 __u16 padding[3]; 122 }; 123 struct kvm_sregs { 124 struct kvm_segment cs, ds, es, fs, gs, ss; 125 struct kvm_segment tr, ldt; 126 struct kvm_dtable gdt, idt; 127 __u64 cr0, cr2, cr3, cr4, cr8; 128 __u64 efer; 129 __u64 apic_base; 130 __u64 interrupt_bitmap[(KVM_NR_INTERRUPTS + 63) / 64]; 131 }; 132 struct kvm_sregs2 { 133 struct kvm_segment cs, ds, es, fs, gs, ss; 134 struct kvm_segment tr, ldt; 135 struct kvm_dtable gdt, idt; 136 __u64 cr0, cr2, cr3, cr4, cr8; 137 __u64 efer; 138 __u64 apic_base; 139 __u64 flags; 140 __u64 pdptrs[4]; 141 }; 142 #define KVM_SREGS2_FLAGS_PDPTRS_VALID 1 143 struct kvm_fpu { 144 __u8 fpr[8][16]; 145 __u16 fcw; 146 __u16 fsw; 147 __u8 ftwx; 148 __u8 pad1; 149 __u16 last_opcode; 150 __u64 last_ip; 151 __u64 last_dp; 152 __u8 xmm[16][16]; 153 __u32 mxcsr; 154 __u32 pad2; 155 }; 156 struct kvm_msr_entry { 157 __u32 index; 158 __u32 reserved; 159 __u64 data; 160 }; 161 struct kvm_msrs { 162 __u32 nmsrs; 163 __u32 pad; 164 struct kvm_msr_entry entries[]; 165 }; 166 struct kvm_msr_list { 167 __u32 nmsrs; 168 __u32 indices[]; 169 }; 170 #define KVM_MSR_FILTER_MAX_BITMAP_SIZE 0x600 171 struct kvm_msr_filter_range { 172 #define KVM_MSR_FILTER_READ (1 << 0) 173 #define KVM_MSR_FILTER_WRITE (1 << 1) 174 #define KVM_MSR_FILTER_RANGE_VALID_MASK (KVM_MSR_FILTER_READ | KVM_MSR_FILTER_WRITE) 175 __u32 flags; 176 __u32 nmsrs; 177 __u32 base; 178 __u8 * bitmap; 179 }; 180 #define KVM_MSR_FILTER_MAX_RANGES 16 181 struct kvm_msr_filter { 182 #define KVM_MSR_FILTER_DEFAULT_ALLOW (0 << 0) 183 #define KVM_MSR_FILTER_DEFAULT_DENY (1 << 0) 184 #define KVM_MSR_FILTER_VALID_MASK (KVM_MSR_FILTER_DEFAULT_DENY) 185 __u32 flags; 186 struct kvm_msr_filter_range ranges[KVM_MSR_FILTER_MAX_RANGES]; 187 }; 188 struct kvm_cpuid_entry { 189 __u32 function; 190 __u32 eax; 191 __u32 ebx; 192 __u32 ecx; 193 __u32 edx; 194 __u32 padding; 195 }; 196 struct kvm_cpuid { 197 __u32 nent; 198 __u32 padding; 199 struct kvm_cpuid_entry entries[]; 200 }; 201 struct kvm_cpuid_entry2 { 202 __u32 function; 203 __u32 index; 204 __u32 flags; 205 __u32 eax; 206 __u32 ebx; 207 __u32 ecx; 208 __u32 edx; 209 __u32 padding[3]; 210 }; 211 #define KVM_CPUID_FLAG_SIGNIFCANT_INDEX (1 << 0) 212 #define KVM_CPUID_FLAG_STATEFUL_FUNC (1 << 1) 213 #define KVM_CPUID_FLAG_STATE_READ_NEXT (1 << 2) 214 struct kvm_cpuid2 { 215 __u32 nent; 216 __u32 padding; 217 struct kvm_cpuid_entry2 entries[]; 218 }; 219 struct kvm_pit_channel_state { 220 __u32 count; 221 __u16 latched_count; 222 __u8 count_latched; 223 __u8 status_latched; 224 __u8 status; 225 __u8 read_state; 226 __u8 write_state; 227 __u8 write_latch; 228 __u8 rw_mode; 229 __u8 mode; 230 __u8 bcd; 231 __u8 gate; 232 __s64 count_load_time; 233 }; 234 struct kvm_debug_exit_arch { 235 __u32 exception; 236 __u32 pad; 237 __u64 pc; 238 __u64 dr6; 239 __u64 dr7; 240 }; 241 #define KVM_GUESTDBG_USE_SW_BP 0x00010000 242 #define KVM_GUESTDBG_USE_HW_BP 0x00020000 243 #define KVM_GUESTDBG_INJECT_DB 0x00040000 244 #define KVM_GUESTDBG_INJECT_BP 0x00080000 245 #define KVM_GUESTDBG_BLOCKIRQ 0x00100000 246 struct kvm_guest_debug_arch { 247 __u64 debugreg[8]; 248 }; 249 struct kvm_pit_state { 250 struct kvm_pit_channel_state channels[3]; 251 }; 252 #define KVM_PIT_FLAGS_HPET_LEGACY 0x00000001 253 #define KVM_PIT_FLAGS_SPEAKER_DATA_ON 0x00000002 254 struct kvm_pit_state2 { 255 struct kvm_pit_channel_state channels[3]; 256 __u32 flags; 257 __u32 reserved[9]; 258 }; 259 struct kvm_reinject_control { 260 __u8 pit_reinject; 261 __u8 reserved[31]; 262 }; 263 #define KVM_VCPUEVENT_VALID_NMI_PENDING 0x00000001 264 #define KVM_VCPUEVENT_VALID_SIPI_VECTOR 0x00000002 265 #define KVM_VCPUEVENT_VALID_SHADOW 0x00000004 266 #define KVM_VCPUEVENT_VALID_SMM 0x00000008 267 #define KVM_VCPUEVENT_VALID_PAYLOAD 0x00000010 268 #define KVM_VCPUEVENT_VALID_TRIPLE_FAULT 0x00000020 269 #define KVM_X86_SHADOW_INT_MOV_SS 0x01 270 #define KVM_X86_SHADOW_INT_STI 0x02 271 struct kvm_vcpu_events { 272 struct { 273 __u8 injected; 274 __u8 nr; 275 __u8 has_error_code; 276 __u8 pending; 277 __u32 error_code; 278 } exception; 279 struct { 280 __u8 injected; 281 __u8 nr; 282 __u8 soft; 283 __u8 shadow; 284 } interrupt; 285 struct { 286 __u8 injected; 287 __u8 pending; 288 __u8 masked; 289 __u8 pad; 290 } nmi; 291 __u32 sipi_vector; 292 __u32 flags; 293 struct { 294 __u8 smm; 295 __u8 pending; 296 __u8 smm_inside_nmi; 297 __u8 latched_init; 298 } smi; 299 struct { 300 __u8 pending; 301 } triple_fault; 302 __u8 reserved[26]; 303 __u8 exception_has_payload; 304 __u64 exception_payload; 305 }; 306 struct kvm_debugregs { 307 __u64 db[4]; 308 __u64 dr6; 309 __u64 dr7; 310 __u64 flags; 311 __u64 reserved[9]; 312 }; 313 struct kvm_xsave { 314 __u32 region[1024]; 315 __u32 extra[]; 316 }; 317 #define KVM_MAX_XCRS 16 318 struct kvm_xcr { 319 __u32 xcr; 320 __u32 reserved; 321 __u64 value; 322 }; 323 struct kvm_xcrs { 324 __u32 nr_xcrs; 325 __u32 flags; 326 struct kvm_xcr xcrs[KVM_MAX_XCRS]; 327 __u64 padding[16]; 328 }; 329 #define KVM_SYNC_X86_REGS (1UL << 0) 330 #define KVM_SYNC_X86_SREGS (1UL << 1) 331 #define KVM_SYNC_X86_EVENTS (1UL << 2) 332 #define KVM_SYNC_X86_VALID_FIELDS (KVM_SYNC_X86_REGS | KVM_SYNC_X86_SREGS | KVM_SYNC_X86_EVENTS) 333 struct kvm_sync_regs { 334 struct kvm_regs regs; 335 struct kvm_sregs sregs; 336 struct kvm_vcpu_events events; 337 }; 338 #define KVM_X86_QUIRK_LINT0_REENABLED (1 << 0) 339 #define KVM_X86_QUIRK_CD_NW_CLEARED (1 << 1) 340 #define KVM_X86_QUIRK_LAPIC_MMIO_HOLE (1 << 2) 341 #define KVM_X86_QUIRK_OUT_7E_INC_RIP (1 << 3) 342 #define KVM_X86_QUIRK_MISC_ENABLE_NO_MWAIT (1 << 4) 343 #define KVM_X86_QUIRK_FIX_HYPERCALL_INSN (1 << 5) 344 #define KVM_X86_QUIRK_MWAIT_NEVER_UD_FAULTS (1 << 6) 345 #define KVM_X86_QUIRK_SLOT_ZAP_ALL (1 << 7) 346 #define KVM_STATE_NESTED_FORMAT_VMX 0 347 #define KVM_STATE_NESTED_FORMAT_SVM 1 348 #define KVM_STATE_NESTED_GUEST_MODE 0x00000001 349 #define KVM_STATE_NESTED_RUN_PENDING 0x00000002 350 #define KVM_STATE_NESTED_EVMCS 0x00000004 351 #define KVM_STATE_NESTED_MTF_PENDING 0x00000008 352 #define KVM_STATE_NESTED_GIF_SET 0x00000100 353 #define KVM_STATE_NESTED_SMM_GUEST_MODE 0x00000001 354 #define KVM_STATE_NESTED_SMM_VMXON 0x00000002 355 #define KVM_STATE_NESTED_VMX_VMCS_SIZE 0x1000 356 #define KVM_STATE_NESTED_SVM_VMCB_SIZE 0x1000 357 #define KVM_STATE_VMX_PREEMPTION_TIMER_DEADLINE 0x00000001 358 #define KVM_X86_GRP_SYSTEM 0 359 #define KVM_X86_XCOMP_GUEST_SUPP 0 360 #define KVM_X86_GRP_SEV 1 361 #define KVM_X86_SEV_VMSA_FEATURES 0 362 struct kvm_vmx_nested_state_data { 363 __u8 vmcs12[KVM_STATE_NESTED_VMX_VMCS_SIZE]; 364 __u8 shadow_vmcs12[KVM_STATE_NESTED_VMX_VMCS_SIZE]; 365 }; 366 struct kvm_vmx_nested_state_hdr { 367 __u64 vmxon_pa; 368 __u64 vmcs12_pa; 369 struct { 370 __u16 flags; 371 } smm; 372 __u16 pad; 373 __u32 flags; 374 __u64 preemption_timer_deadline; 375 }; 376 struct kvm_svm_nested_state_data { 377 __u8 vmcb12[KVM_STATE_NESTED_SVM_VMCB_SIZE]; 378 }; 379 struct kvm_svm_nested_state_hdr { 380 __u64 vmcb_pa; 381 }; 382 struct kvm_nested_state { 383 __u16 flags; 384 __u16 format; 385 __u32 size; 386 union { 387 struct kvm_vmx_nested_state_hdr vmx; 388 struct kvm_svm_nested_state_hdr svm; 389 __u8 pad[120]; 390 } hdr; 391 union { 392 __DECLARE_FLEX_ARRAY(struct kvm_vmx_nested_state_data, vmx); 393 __DECLARE_FLEX_ARRAY(struct kvm_svm_nested_state_data, svm); 394 } data; 395 }; 396 struct kvm_pmu_event_filter { 397 __u32 action; 398 __u32 nevents; 399 __u32 fixed_counter_bitmap; 400 __u32 flags; 401 __u32 pad[4]; 402 __u64 events[]; 403 }; 404 #define KVM_PMU_EVENT_ALLOW 0 405 #define KVM_PMU_EVENT_DENY 1 406 #define KVM_PMU_EVENT_FLAG_MASKED_EVENTS _BITUL(0) 407 #define KVM_PMU_EVENT_FLAGS_VALID_MASK (KVM_PMU_EVENT_FLAG_MASKED_EVENTS) 408 struct kvm_x86_mce { 409 __u64 status; 410 __u64 addr; 411 __u64 misc; 412 __u64 mcg_status; 413 __u8 bank; 414 __u8 pad1[7]; 415 __u64 pad2[3]; 416 }; 417 #define KVM_XEN_HVM_CONFIG_HYPERCALL_MSR (1 << 0) 418 #define KVM_XEN_HVM_CONFIG_INTERCEPT_HCALL (1 << 1) 419 #define KVM_XEN_HVM_CONFIG_SHARED_INFO (1 << 2) 420 #define KVM_XEN_HVM_CONFIG_RUNSTATE (1 << 3) 421 #define KVM_XEN_HVM_CONFIG_EVTCHN_2LEVEL (1 << 4) 422 #define KVM_XEN_HVM_CONFIG_EVTCHN_SEND (1 << 5) 423 #define KVM_XEN_HVM_CONFIG_RUNSTATE_UPDATE_FLAG (1 << 6) 424 #define KVM_XEN_HVM_CONFIG_PVCLOCK_TSC_UNSTABLE (1 << 7) 425 #define KVM_XEN_HVM_CONFIG_SHARED_INFO_HVA (1 << 8) 426 struct kvm_xen_hvm_config { 427 __u32 flags; 428 __u32 msr; 429 __u64 blob_addr_32; 430 __u64 blob_addr_64; 431 __u8 blob_size_32; 432 __u8 blob_size_64; 433 __u8 pad2[30]; 434 }; 435 struct kvm_xen_hvm_attr { 436 __u16 type; 437 __u16 pad[3]; 438 union { 439 __u8 long_mode; 440 __u8 vector; 441 __u8 runstate_update_flag; 442 union { 443 __u64 gfn; 444 #define KVM_XEN_INVALID_GFN ((__u64) - 1) 445 __u64 hva; 446 } shared_info; 447 struct { 448 __u32 send_port; 449 __u32 type; 450 __u32 flags; 451 #define KVM_XEN_EVTCHN_DEASSIGN (1 << 0) 452 #define KVM_XEN_EVTCHN_UPDATE (1 << 1) 453 #define KVM_XEN_EVTCHN_RESET (1 << 2) 454 union { 455 struct { 456 __u32 port; 457 __u32 vcpu; 458 __u32 priority; 459 } port; 460 struct { 461 __u32 port; 462 __s32 fd; 463 } eventfd; 464 __u32 padding[4]; 465 } deliver; 466 } evtchn; 467 __u32 xen_version; 468 __u64 pad[8]; 469 } u; 470 }; 471 #define KVM_XEN_ATTR_TYPE_LONG_MODE 0x0 472 #define KVM_XEN_ATTR_TYPE_SHARED_INFO 0x1 473 #define KVM_XEN_ATTR_TYPE_UPCALL_VECTOR 0x2 474 #define KVM_XEN_ATTR_TYPE_EVTCHN 0x3 475 #define KVM_XEN_ATTR_TYPE_XEN_VERSION 0x4 476 #define KVM_XEN_ATTR_TYPE_RUNSTATE_UPDATE_FLAG 0x5 477 #define KVM_XEN_ATTR_TYPE_SHARED_INFO_HVA 0x6 478 struct kvm_xen_vcpu_attr { 479 __u16 type; 480 __u16 pad[3]; 481 union { 482 __u64 gpa; 483 #define KVM_XEN_INVALID_GPA ((__u64) - 1) 484 __u64 hva; 485 __u64 pad[8]; 486 struct { 487 __u64 state; 488 __u64 state_entry_time; 489 __u64 time_running; 490 __u64 time_runnable; 491 __u64 time_blocked; 492 __u64 time_offline; 493 } runstate; 494 __u32 vcpu_id; 495 struct { 496 __u32 port; 497 __u32 priority; 498 __u64 expires_ns; 499 } timer; 500 __u8 vector; 501 } u; 502 }; 503 #define KVM_XEN_VCPU_ATTR_TYPE_VCPU_INFO 0x0 504 #define KVM_XEN_VCPU_ATTR_TYPE_VCPU_TIME_INFO 0x1 505 #define KVM_XEN_VCPU_ATTR_TYPE_RUNSTATE_ADDR 0x2 506 #define KVM_XEN_VCPU_ATTR_TYPE_RUNSTATE_CURRENT 0x3 507 #define KVM_XEN_VCPU_ATTR_TYPE_RUNSTATE_DATA 0x4 508 #define KVM_XEN_VCPU_ATTR_TYPE_RUNSTATE_ADJUST 0x5 509 #define KVM_XEN_VCPU_ATTR_TYPE_VCPU_ID 0x6 510 #define KVM_XEN_VCPU_ATTR_TYPE_TIMER 0x7 511 #define KVM_XEN_VCPU_ATTR_TYPE_UPCALL_VECTOR 0x8 512 #define KVM_XEN_VCPU_ATTR_TYPE_VCPU_INFO_HVA 0x9 513 enum sev_cmd_id { 514 KVM_SEV_INIT = 0, 515 KVM_SEV_ES_INIT, 516 KVM_SEV_LAUNCH_START, 517 KVM_SEV_LAUNCH_UPDATE_DATA, 518 KVM_SEV_LAUNCH_UPDATE_VMSA, 519 KVM_SEV_LAUNCH_SECRET, 520 KVM_SEV_LAUNCH_MEASURE, 521 KVM_SEV_LAUNCH_FINISH, 522 KVM_SEV_SEND_START, 523 KVM_SEV_SEND_UPDATE_DATA, 524 KVM_SEV_SEND_UPDATE_VMSA, 525 KVM_SEV_SEND_FINISH, 526 KVM_SEV_RECEIVE_START, 527 KVM_SEV_RECEIVE_UPDATE_DATA, 528 KVM_SEV_RECEIVE_UPDATE_VMSA, 529 KVM_SEV_RECEIVE_FINISH, 530 KVM_SEV_GUEST_STATUS, 531 KVM_SEV_DBG_DECRYPT, 532 KVM_SEV_DBG_ENCRYPT, 533 KVM_SEV_CERT_EXPORT, 534 KVM_SEV_GET_ATTESTATION_REPORT, 535 KVM_SEV_SEND_CANCEL, 536 KVM_SEV_INIT2, 537 KVM_SEV_SNP_LAUNCH_START = 100, 538 KVM_SEV_SNP_LAUNCH_UPDATE, 539 KVM_SEV_SNP_LAUNCH_FINISH, 540 KVM_SEV_NR_MAX, 541 }; 542 struct kvm_sev_cmd { 543 __u32 id; 544 __u32 pad0; 545 __u64 data; 546 __u32 error; 547 __u32 sev_fd; 548 }; 549 struct kvm_sev_init { 550 __u64 vmsa_features; 551 __u32 flags; 552 __u16 ghcb_version; 553 __u16 pad1; 554 __u32 pad2[8]; 555 }; 556 struct kvm_sev_launch_start { 557 __u32 handle; 558 __u32 policy; 559 __u64 dh_uaddr; 560 __u32 dh_len; 561 __u32 pad0; 562 __u64 session_uaddr; 563 __u32 session_len; 564 __u32 pad1; 565 }; 566 struct kvm_sev_launch_update_data { 567 __u64 uaddr; 568 __u32 len; 569 __u32 pad0; 570 }; 571 struct kvm_sev_launch_secret { 572 __u64 hdr_uaddr; 573 __u32 hdr_len; 574 __u32 pad0; 575 __u64 guest_uaddr; 576 __u32 guest_len; 577 __u32 pad1; 578 __u64 trans_uaddr; 579 __u32 trans_len; 580 __u32 pad2; 581 }; 582 struct kvm_sev_launch_measure { 583 __u64 uaddr; 584 __u32 len; 585 __u32 pad0; 586 }; 587 struct kvm_sev_guest_status { 588 __u32 handle; 589 __u32 policy; 590 __u32 state; 591 }; 592 struct kvm_sev_dbg { 593 __u64 src_uaddr; 594 __u64 dst_uaddr; 595 __u32 len; 596 __u32 pad0; 597 }; 598 struct kvm_sev_attestation_report { 599 __u8 mnonce[16]; 600 __u64 uaddr; 601 __u32 len; 602 __u32 pad0; 603 }; 604 struct kvm_sev_send_start { 605 __u32 policy; 606 __u32 pad0; 607 __u64 pdh_cert_uaddr; 608 __u32 pdh_cert_len; 609 __u32 pad1; 610 __u64 plat_certs_uaddr; 611 __u32 plat_certs_len; 612 __u32 pad2; 613 __u64 amd_certs_uaddr; 614 __u32 amd_certs_len; 615 __u32 pad3; 616 __u64 session_uaddr; 617 __u32 session_len; 618 __u32 pad4; 619 }; 620 struct kvm_sev_send_update_data { 621 __u64 hdr_uaddr; 622 __u32 hdr_len; 623 __u32 pad0; 624 __u64 guest_uaddr; 625 __u32 guest_len; 626 __u32 pad1; 627 __u64 trans_uaddr; 628 __u32 trans_len; 629 __u32 pad2; 630 }; 631 struct kvm_sev_receive_start { 632 __u32 handle; 633 __u32 policy; 634 __u64 pdh_uaddr; 635 __u32 pdh_len; 636 __u32 pad0; 637 __u64 session_uaddr; 638 __u32 session_len; 639 __u32 pad1; 640 }; 641 struct kvm_sev_receive_update_data { 642 __u64 hdr_uaddr; 643 __u32 hdr_len; 644 __u32 pad0; 645 __u64 guest_uaddr; 646 __u32 guest_len; 647 __u32 pad1; 648 __u64 trans_uaddr; 649 __u32 trans_len; 650 __u32 pad2; 651 }; 652 struct kvm_sev_snp_launch_start { 653 __u64 policy; 654 __u8 gosvw[16]; 655 __u16 flags; 656 __u8 pad0[6]; 657 __u64 pad1[4]; 658 }; 659 #define KVM_SEV_SNP_PAGE_TYPE_NORMAL 0x1 660 #define KVM_SEV_SNP_PAGE_TYPE_ZERO 0x3 661 #define KVM_SEV_SNP_PAGE_TYPE_UNMEASURED 0x4 662 #define KVM_SEV_SNP_PAGE_TYPE_SECRETS 0x5 663 #define KVM_SEV_SNP_PAGE_TYPE_CPUID 0x6 664 struct kvm_sev_snp_launch_update { 665 __u64 gfn_start; 666 __u64 uaddr; 667 __u64 len; 668 __u8 type; 669 __u8 pad0; 670 __u16 flags; 671 __u32 pad1; 672 __u64 pad2[4]; 673 }; 674 #define KVM_SEV_SNP_ID_BLOCK_SIZE 96 675 #define KVM_SEV_SNP_ID_AUTH_SIZE 4096 676 #define KVM_SEV_SNP_FINISH_DATA_SIZE 32 677 struct kvm_sev_snp_launch_finish { 678 __u64 id_block_uaddr; 679 __u64 id_auth_uaddr; 680 __u8 id_block_en; 681 __u8 auth_key_en; 682 __u8 vcek_disabled; 683 __u8 host_data[KVM_SEV_SNP_FINISH_DATA_SIZE]; 684 __u8 pad0[3]; 685 __u16 flags; 686 __u64 pad1[4]; 687 }; 688 #define KVM_X2APIC_API_USE_32BIT_IDS (1ULL << 0) 689 #define KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK (1ULL << 1) 690 struct kvm_hyperv_eventfd { 691 __u32 conn_id; 692 __s32 fd; 693 __u32 flags; 694 __u32 padding[3]; 695 }; 696 #define KVM_HYPERV_CONN_ID_MASK 0x00ffffff 697 #define KVM_HYPERV_EVENTFD_DEASSIGN (1 << 0) 698 #define KVM_PMU_ENCODE_MASKED_ENTRY(event_select,mask,match,exclude) (((event_select) & 0xFFULL) | (((event_select) & 0XF00ULL) << 24) | (((mask) & 0xFFULL) << 56) | (((match) & 0xFFULL) << 8) | ((__u64) (! ! (exclude)) << 55)) 699 #define KVM_PMU_MASKED_ENTRY_EVENT_SELECT (__GENMASK_ULL(7, 0) | __GENMASK_ULL(35, 32)) 700 #define KVM_PMU_MASKED_ENTRY_UMASK_MASK (__GENMASK_ULL(63, 56)) 701 #define KVM_PMU_MASKED_ENTRY_UMASK_MATCH (__GENMASK_ULL(15, 8)) 702 #define KVM_PMU_MASKED_ENTRY_EXCLUDE (_BITULL(55)) 703 #define KVM_PMU_MASKED_ENTRY_UMASK_MASK_SHIFT (56) 704 #define KVM_VCPU_TSC_CTRL 0 705 #define KVM_VCPU_TSC_OFFSET 0 706 #define KVM_EXIT_HYPERCALL_LONG_MODE _BITULL(0) 707 #define KVM_X86_DEFAULT_VM 0 708 #define KVM_X86_SW_PROTECTED_VM 1 709 #define KVM_X86_SEV_VM 2 710 #define KVM_X86_SEV_ES_VM 3 711 #define KVM_X86_SNP_VM 4 712 #endif 713