1 /* 2 * This file is auto-generated. Modifications will be lost. 3 * 4 * See https://android.googlesource.com/platform/bionic/+/master/libc/kernel/ 5 * for more information. 6 */ 7 #ifndef __BNXT_RE_UVERBS_ABI_H__ 8 #define __BNXT_RE_UVERBS_ABI_H__ 9 #include <linux/types.h> 10 #include <rdma/ib_user_ioctl_cmds.h> 11 #define BNXT_RE_ABI_VERSION 1 12 #define BNXT_RE_CHIP_ID0_CHIP_NUM_SFT 0x00 13 #define BNXT_RE_CHIP_ID0_CHIP_REV_SFT 0x10 14 #define BNXT_RE_CHIP_ID0_CHIP_MET_SFT 0x18 15 enum { 16 BNXT_RE_UCNTX_CMASK_HAVE_CCTX = 0x1ULL, 17 BNXT_RE_UCNTX_CMASK_HAVE_MODE = 0x02ULL, 18 BNXT_RE_UCNTX_CMASK_WC_DPI_ENABLED = 0x04ULL, 19 BNXT_RE_UCNTX_CMASK_DBR_PACING_ENABLED = 0x08ULL, 20 BNXT_RE_UCNTX_CMASK_POW2_DISABLED = 0x10ULL, 21 BNXT_RE_UCNTX_CMASK_MSN_TABLE_ENABLED = 0x40, 22 }; 23 enum bnxt_re_wqe_mode { 24 BNXT_QPLIB_WQE_MODE_STATIC = 0x00, 25 BNXT_QPLIB_WQE_MODE_VARIABLE = 0x01, 26 BNXT_QPLIB_WQE_MODE_INVALID = 0x02, 27 }; 28 enum { 29 BNXT_RE_COMP_MASK_REQ_UCNTX_POW2_SUPPORT = 0x01, 30 BNXT_RE_COMP_MASK_REQ_UCNTX_VAR_WQE_SUPPORT = 0x02, 31 }; 32 struct bnxt_re_uctx_req { 33 __aligned_u64 comp_mask; 34 }; 35 struct bnxt_re_uctx_resp { 36 __u32 dev_id; 37 __u32 max_qp; 38 __u32 pg_size; 39 __u32 cqe_sz; 40 __u32 max_cqd; 41 __u32 rsvd; 42 __aligned_u64 comp_mask; 43 __u32 chip_id0; 44 __u32 chip_id1; 45 __u32 mode; 46 __u32 rsvd1; 47 }; 48 struct bnxt_re_pd_resp { 49 __u32 pdid; 50 __u32 dpi; 51 __u64 dbr; 52 } __attribute__((packed, aligned(4))); 53 struct bnxt_re_cq_req { 54 __aligned_u64 cq_va; 55 __aligned_u64 cq_handle; 56 }; 57 enum bnxt_re_cq_mask { 58 BNXT_RE_CQ_TOGGLE_PAGE_SUPPORT = 0x1, 59 }; 60 struct bnxt_re_cq_resp { 61 __u32 cqid; 62 __u32 tail; 63 __u32 phase; 64 __u32 rsvd; 65 __aligned_u64 comp_mask; 66 }; 67 struct bnxt_re_resize_cq_req { 68 __aligned_u64 cq_va; 69 }; 70 enum bnxt_re_qp_mask { 71 BNXT_RE_QP_REQ_MASK_VAR_WQE_SQ_SLOTS = 0x1, 72 }; 73 struct bnxt_re_qp_req { 74 __aligned_u64 qpsva; 75 __aligned_u64 qprva; 76 __aligned_u64 qp_handle; 77 __aligned_u64 comp_mask; 78 __u32 sq_slots; 79 }; 80 struct bnxt_re_qp_resp { 81 __u32 qpid; 82 __u32 rsvd; 83 }; 84 struct bnxt_re_srq_req { 85 __aligned_u64 srqva; 86 __aligned_u64 srq_handle; 87 }; 88 enum bnxt_re_srq_mask { 89 BNXT_RE_SRQ_TOGGLE_PAGE_SUPPORT = 0x1, 90 }; 91 struct bnxt_re_srq_resp { 92 __u32 srqid; 93 __u32 rsvd; 94 __aligned_u64 comp_mask; 95 }; 96 enum bnxt_re_shpg_offt { 97 BNXT_RE_BEG_RESV_OFFT = 0x00, 98 BNXT_RE_AVID_OFFT = 0x10, 99 BNXT_RE_AVID_SIZE = 0x04, 100 BNXT_RE_END_RESV_OFFT = 0xFF0 101 }; 102 enum bnxt_re_objects { 103 BNXT_RE_OBJECT_ALLOC_PAGE = (1U << UVERBS_ID_NS_SHIFT), 104 BNXT_RE_OBJECT_NOTIFY_DRV, 105 BNXT_RE_OBJECT_GET_TOGGLE_MEM, 106 }; 107 enum bnxt_re_alloc_page_type { 108 BNXT_RE_ALLOC_WC_PAGE = 0, 109 BNXT_RE_ALLOC_DBR_BAR_PAGE, 110 BNXT_RE_ALLOC_DBR_PAGE, 111 }; 112 enum bnxt_re_var_alloc_page_attrs { 113 BNXT_RE_ALLOC_PAGE_HANDLE = (1U << UVERBS_ID_NS_SHIFT), 114 BNXT_RE_ALLOC_PAGE_TYPE, 115 BNXT_RE_ALLOC_PAGE_DPI, 116 BNXT_RE_ALLOC_PAGE_MMAP_OFFSET, 117 BNXT_RE_ALLOC_PAGE_MMAP_LENGTH, 118 }; 119 enum bnxt_re_alloc_page_attrs { 120 BNXT_RE_DESTROY_PAGE_HANDLE = (1U << UVERBS_ID_NS_SHIFT), 121 }; 122 enum bnxt_re_alloc_page_methods { 123 BNXT_RE_METHOD_ALLOC_PAGE = (1U << UVERBS_ID_NS_SHIFT), 124 BNXT_RE_METHOD_DESTROY_PAGE, 125 }; 126 enum bnxt_re_notify_drv_methods { 127 BNXT_RE_METHOD_NOTIFY_DRV = (1U << UVERBS_ID_NS_SHIFT), 128 }; 129 enum bnxt_re_get_toggle_mem_type { 130 BNXT_RE_CQ_TOGGLE_MEM = 0, 131 BNXT_RE_SRQ_TOGGLE_MEM, 132 }; 133 enum bnxt_re_var_toggle_mem_attrs { 134 BNXT_RE_TOGGLE_MEM_HANDLE = (1U << UVERBS_ID_NS_SHIFT), 135 BNXT_RE_TOGGLE_MEM_TYPE, 136 BNXT_RE_TOGGLE_MEM_RES_ID, 137 BNXT_RE_TOGGLE_MEM_MMAP_PAGE, 138 BNXT_RE_TOGGLE_MEM_MMAP_OFFSET, 139 BNXT_RE_TOGGLE_MEM_MMAP_LENGTH, 140 }; 141 enum bnxt_re_toggle_mem_attrs { 142 BNXT_RE_RELEASE_TOGGLE_MEM_HANDLE = (1U << UVERBS_ID_NS_SHIFT), 143 }; 144 enum bnxt_re_toggle_mem_methods { 145 BNXT_RE_METHOD_GET_TOGGLE_MEM = (1U << UVERBS_ID_NS_SHIFT), 146 BNXT_RE_METHOD_RELEASE_TOGGLE_MEM, 147 }; 148 #endif 149