1 _____ ____ _____ ______ ____ ____ ____ _______ 2 / ____/ __ \| __ \| ____| _ \ / __ \ / __ \__ __| 3 | | | | | | |__) | |__ | |_) | | | | | | | | | 4 | | | | | | _ /| __| | _ <| | | | | | | | | 5 | |___| |__| | | \ \| |____| |_) | |__| | |__| | | | 6 \_____\____/|_| \_\______|____/ \____/ \____/ |_| 7 8 __ __ _____ _____ ____ 9 /\ | \/ | __ \ / ____| |___ \ 10 / \ | \ / | | | | | (___ __) | 11 / /\ \ | |\/| | | | | \___ \ |__ < 12 / ____ \| | | | |__| | ____) | ___) | 13 /_/ \_\_| |_|_____/ |_____/ |____/ 14 15 16 S3 in coreboot (V 1.2) 17---------------------------------------- 18 Zheng Bao 19 <zheng.bao@amd.com> 20 <fishbaozi@gmail.com> 21 22Introduction 23============ 24This document is about how the feature S3 is implemented on coreboot, 25specifically on AMD platform. This topic deals with ACPI spec, hardware, 26BIOS, OS. We try to help coreboot users to realize their own S3. 27 28S3 in a nutshell 29================ 30The S3 sleeping state is a low wake latency sleeping state where all 31system context is lost except system memory. [1]. S3 is a ACPI 32definition. 33To enter S3, write 3 in SLP_TYPx and set the SLP_EN bit (See ACPI 34registers). But if you do that, board can not resume at where it 35sleeps, because you don't save the context. More often than not, we 36make the board go into S3 by the tools which OSes provide. For 37windows, click Start->sleep. For linux, some distribution provide a 38tools called pm-suspend, which can make the system goto S3. If 39pm-suspend is not available, we can run "echo mem > /sys/power/state", 40but this way may not save all the needed context. 41In S3 state, the power is off. So when the power button is pressed, 42BIOS runs as it does in cold boot. If BIOS didn't detect whether 43board boots or resumes, it would go the same way as boot. It is not 44what we expect. BIOS detects the SLP_TYPx. If it is 3, it means BIOS 45are waking up. 46BIOS is responsible for restore the machine state as it is before 47sleep. It needs restore the memory controller, not overwriting memory 48which is not marked as reserved. For the peripheral which loses its 49registers, BIOS needs to write the original value. 50When everything is done, BIOS needs to find out the wakeup vector 51provided by OSes and jump there. OSes also have work to do. We can go 52to linux kernel or some other open source projects to find out how they 53handle S3 resume. 54 55ACPI registers 56============== 57ACPI specification defines a group of registers. OSes handle all these 58registers to read and write status to all the platform. 59On AMD platform, these registers are provided by southbridge. For 60example, Hudson uses PMIO 60:6F to define ACPI registers. 61OSes don't have any specific driver to know where these registers 62are. BIOS has the responsibility to allocated the IO resources and 63write all these address to FADT, a ACPI defined table. 64 65Memory Layout 66============= 67Restoring memory is the most important job done by BIOS. When the 68power is off, the memory is maintained by standby power. BIOS need to 69make sure that when flow goes to OS, everything in memory should be 70the same as it was. 71 72The chip vendor will provide a way, or code, to wake up the memory 73from sleeping. In AGESA 2008 arch, it is called AmdInitResume. 74 75The BIOS itself needs some memory to run. Either, BIOS marks the erea 76as reserved in e820, or BIOS saves the content into reserved space. 77 78Here is the address Map for S3 Resume. Assumingly the total memory is 1GB. 7900000000 --- 00100000 BIOS Reserved area. 8000100000 --- 00200000 Free 8100200000 --- 01000000 coreboot ramstage area. 8201000000 --- 2e160000 Free 832e160000 --- 2e170000 ACPI table 842e170000 --- 2ef70000 OSRAM 852ef70000 --- 2efe0000 Stack in highmem 862efe0000 --- 2f000000 heap in highmem 872f000000 TOM 88 89AMD requirements in S3 90====================== 91Chip vendor like AMD will provide bunch of routines to restore the 92board.[2] 93 * AmdS3Save: It is called in cold boot, save required register into 94 non-volatile storage. Currently, we use SPI flash to store the data. 95 * AmdInitResume: Restore the memory controller. 96 * AmdS3LateRestore: Called after AmdInitResume, restore other 97 register that memory. 98 * (SouthBridge)InitS3EarlyRestore, (SouthBridge)InitS3LateRestore: 99 Provided by Southbridge vendor code. Early is called before PCI 100 enumeration, and Late is called after that. 101 102Lifecycle of booting, sleeping and waking coreboot and Ubuntu 103============================================================= 1041. Cold boot. 105For a system with S3 feature, the BIOS needs to save some data to 106non-volatile storage at cold boot stage. What data need to be save are 107provided by AmdS3Save. After the wrapper calls the AmdS3Save, it gets 108the VolatileStorage and NvStorage, which are where the data are 109located. It is the wrappers's responsibility to save the data.[3][4] 110Currently, the wrappers allocate a CBFS modules in BIOS image. To do 111that, the wrapper needs to have the ability to write flash chips. It 112is not as comprehensive as flashrom. But for the SST chip on Parmer, 113MX chip on Thather, coreboot works well.[5] 114 1152. OS goes in S3. 116For Linux, besides the kernel needs to do some saving, most distributions 117run some scripts. For Ubuntu, scripts are located at /usr/lib/pm-utils/sleep.d. 118 # ls /usr/lib/pm-utils/sleep.d 119 000kernel-change 49bluetooth 90clock 95led 120 00logging 55NetworkManager 94cpufreq 98video-quirk-db-handler 121 00powersave 60_wpa_supplicant 95anacron 99video 122 01PulseAudio 75modules 95hdparm-apm 123The script with lower prefix runs before the one with higher prefix. 12499video is the last one. 125Those scripts have hooks called hibernate, suspend, thaw, resume. For 126each script, suspend is called when system sleeps and wakeup is called 127when system wakeups. 128 1293. Firmware detects S3 wakeup 130As we mentioned, Firmware detects the SLP_TYPx to find out if the board 131wakes up. In romstage.c, AmdInitReset and AmdInitEarly are called 132as they are during cold boot. AmdInitResume and AmdS3LateRestore are 133called only during resume. For whole ramstage, coreboot goes through 134almost the same way as cold boot, other than not calling the AmdInitMid, 135AmdInitLate and AmdS3Save, and restoring all the MTRRs. 136At last step of coreboot stage, coreboot finds out the wakeup vector in FADT, 137written by OS, and jump. 138 1394. OS resumes. 140When Linux resumes, all the sleeping scripts call their resume 141hooks. If we are more lucky, all the scripts can go through. More 142chances that the 99video hangs or fails to get the display 143back. Sometimes it can fixed if CONFIG_S3_VGA_ROM_RUN is unset in 144coreboot/Kconfig. That needs more troubleshooting. 145 146 147Reference 148========= 149[1] ACPI40a, http://www.acpi.info/spec40a.htm 150[2] coreboot Vendorcode, {top}/src/vendorcode/amd/agesa/{family}/Proc/Common/ 151[3] coreboot AGESA wrapper, {top}/src/mainboard/amd/parmer/agesawrapper.c 152[4] coreboot AGESA wrapper, {top}/src/cpu/amd/agesa/s3_resume.c 153[5] coreboot Southbridge, {top}/src/southbridge/amd/agesa/hudson/spi.c 154