1# Dell OptiPlex 9010 2 3This page describes how to run coreboot on Dell OptiPlex 9010 SFF. 4 5 6 7## Technology 8 9```{eval-rst} 10+------------+---------------------------------------------------------------+ 11| CPU | Intel Core 2nd Gen (Sandybridge) or 3rd Gen (Ivybridge) | 12+------------+---------------------------------------------------------------+ 13| DRAM | Up to 4 DIMM slots, up to 32GB 1600MHz non-ECC DDR3 SDRAM | 14+------------+---------------------------------------------------------------+ 15| Chipset | Intel Q77 Express | 16+------------+---------------------------------------------------------------+ 17| Super I/O | SMSC SCH5545 (or SCH5544) with Environmental Controller | 18+------------+---------------------------------------------------------------+ 19| TPM | ST Microelectronics ST33ZP24 | 20+------------+---------------------------------------------------------------+ 21| Boot | From USB, SATA, NVMe (using PCIe x4 expansion card) | 22+------------+---------------------------------------------------------------+ 23| Power | 200W-275W PSU | 24+------------+---------------------------------------------------------------+ 25``` 26 27More specifications on [Dell OptiPlex 9010 specifications]. 28 29## Required proprietary blobs 30 31```{eval-rst} 32+------------------+---------------------------------+---------------------+ 33| Binary file | Apply | Required / Optional | 34+==================+=================================+=====================+ 35| smsc_sch5545.bin | SMSC SCH5545 EC | Optional | 36+------------------+---------------------------------+---------------------+ 37| microcode | CPU microcode | Required | 38+------------------+---------------------------------+---------------------+ 39``` 40 41Microcode updates are automatically included into the coreboot image by build 42system from the `3rdparty/intel-microcode` submodule. 43 44SMSC SC5545 EC firmware is optional, however lack of the binary will result in 45EC malfunction after power failure and fans running at full speed. The blob can 46be extracted from original firmware. It should be located under a file with 47GUID D386BEB8-4B54-4E69-94F5-06091F67E0D3, raw section. The file begins with a 48signature `SMSCUBIM`. The easiest way to do this is to use [UEFITool] and 49`Extract body` option on the raw section of the file. 50 51## Flashing coreboot 52 53```{eval-rst} 54+---------------------+--------------------------+ 55| Type | Value | 56+=====================+==========================+ 57| Socketed flash | no | 58+---------------------+--------------------------+ 59| Model | MX25L6406E/MX25L3206E | 60+---------------------+--------------------------+ 61| Size | 8 + 4 MiB | 62+---------------------+--------------------------+ 63| Package | SOIC-16 + SOIC-8 | 64+---------------------+--------------------------+ 65| Write protection | chipset PRR | 66+---------------------+--------------------------+ 67| Dual BIOS feature | no | 68+---------------------+--------------------------+ 69| Internal flashing | yes | 70+---------------------+--------------------------+ 71``` 72 73### Internal programming 74 75The SPI flash can be accessed using [flashrom]. 76 77 flashrom -p internal -w coreboot.rom --ifd -i bios 78 79Internal programming will not work when migrating from original UEFI firmware. 80One will have to short the SERVICE_MODE jumper to enable HMRFPO and then boot 81the machine to flash it. 82 83### External programming 84 85The external access to flash chip is available through standard SOP-8 clip 86and/or SOP-16 clip on the right side of the CPU fan (marked on the board 87image). The voltage of SPI flash is 3.3V. 88 89There are no restrictions as to the programmer device. It is only recommended 90to flash firmware without supplying power. There are no diodes connected to the 91flash chips. External programming can be performed, for example using OrangePi 92and Armbian. You can use linux_spi driver which provides communication with SPI 93devices. Example command to program SPI flash with OrangePi using linux_spi: 94 95 flashrom -w coreboot.rom -p linux_spi:dev=/dev/spidev1.0,spispeed=16000 96 97## Schematics 98 99There are no schematics for SFF, but if one looks for MT/DT schematics, they 100can be found publicly. Most of the schematics should match the SFF (although 101MT/DT has additional PCIe and PCI slot). 102 103## Known issues 104 105- There seems to be a problem with DRAM clearing on reboot. The SSKPD register 106 still contains 0xCAFE which leads to reset loop. 107 108## Untested 109 110Not all mainboard's peripherals and functions were tested because of lack of 111the cables or not being populated on the board case. 112 113- Internal USB 2.0 header 114- Wake from S3 using serial port 115- Wake-on-Lan from ACPI S4/S5 116 117## Working 118 119- USB 3.0 and 2.0 rear and front ports (SeaBIOS and Linux 4.19) 120- Gigabit Ethernet 121- VGA and 2x DP port using libgfxinit 122- flashrom 123- PCIe x1 WiFi in PCIe x4 slot 124- NVMe PCIe x4 using PCIe x4 expansion card 125- PCIe x16 PEG port using Dell Radeon HD 7570 126- SATA ports (SATA disks and DVD) 127- Super I/O serial port 0 (RS232 DB9 connector on the rear side) 128- SMBus (reading SPD from DIMMs) 129- CPU initialization using Intel i7-3770 130- Sandy Bridge/Ivy Bridge native RAM initialization 131- SeaBIOS payload (version rel-1.13.0) 132- PS/2 keyboard and mouse (including wake support) 133- LPC debug header (requires soldering of the pin header and shorting RF24 for 134 LPC clock) 135- USB debug dongle (the most bottom USB 2.0 port under RJ45 on the read side) 136- SMSC SCH5545 Super I/O initialization 137- SMSC SCH5545 EC initialization and firmware update 138- SMSC SCH5545 EC automatic fan control 139- TPM 1.2 140- Booting Debian 10, Ubuntu 18.04, QubesOS R4.01 141- Boot with cleaned ME 142- Intruder detection 143- Wake-on-Lan from ACPI S3 144 145[flashrom]: https://flashrom.org/Flashrom 146[Dell OptiPlex 9010 specifications]: https://www.dell.com/downloads/global/products/optix/en/dell_optiplex_9010_spec_sheet.pdf 147[UEFITool]: https://github.com/LongSoft/UEFITool 148