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1# HP Compaq 8200 Elite SFF
2
3This page describes how to run coreboot on the [Compaq 8200 Elite SFF] desktop
4from [HP].
5
6## TODO
7
8The following things are still missing from this coreboot port:
9
10- Extended HWM reporting
11- Advanced LED control
12- Advanced power configuration in S3
13
14## Flashing coreboot
15
16```{eval-rst}
17+---------------------+-------------------------+
18| Type                | Value                   |
19+=====================+=========================+
20| Socketed flash      | no                      |
21+---------------------+-------------------------+
22| Model               | MX25L6406E/MX25L6408E   |
23+---------------------+-------------------------+
24| Size                | 8 MiB                   |
25+---------------------+-------------------------+
26| In circuit flashing | yes                     |
27+---------------------+-------------------------+
28| Package             | SOIC-8                  |
29+---------------------+-------------------------+
30| Write protection    | bios region             |
31+---------------------+-------------------------+
32| Dual BIOS feature   | No                      |
33+---------------------+-------------------------+
34| Internal flashing   | yes                     |
35+---------------------+-------------------------+
36```
37
38### Flash layout
39The original layout of the flash should look like this:
40```
4100000000:00000fff fd
4200510000:007fffff bios
4300003000:0050ffff me
4400001000:00002fff gbe
45```
46
47### Internal programming
48
49The SPI flash can be accessed using [flashrom].
50```console
51$ flashrom -p internal -c MX25L6406E/MX25L6408E -w coreboot.rom
52```
53
54After shorting the FDO jumper you gain access to the full flash, but you
55still cannot write in the bios region due to SPI protected ranges.
56
57**Position of FDO jumper close to the IO and second fan connector**
58![][compaq_8200_jumper]
59
60[compaq_8200_jumper]: compaq_8200_sff_jumper.jpg
61
62To write to the bios region you can use an [IFD Hack] originally developed
63for MacBooks, but with modified values described in this guide.
64You should read both guides before attempting the procedure.
65
66Since you can still write in the flash descriptor, you can shrink
67the ME and then move the bios region into where the ME originally was.
68coreboot does not by default restrict writing to any part of the flash, so
69you will first flash a small coreboot build and after it boots, flash
70the full one.
71
72The temporary flash layout with the neutered ME firmware should look like this:
73```
7400000000:00000fff fd
7500023000:001fffff bios
7600003000:00022fff me
7700001000:00002fff gbe
7800200000:007fffff pd
79```
80
81It is very important to use these exact numbers or you will need to fix it
82using external flashing, but you should already be familiar with the risks
83if you got this far.
84
85The temporary ROM chip size to set in menuconfig is 2 MB but the default
86CBFS size is too large for that, you can use up to about 0x1D0000.
87
88When building both the temporary and the permanent installation, don't forget
89to also add the gigabit ethernet configuration when adding the flash descriptor
90and ME firmware.
91
92You can pad the ROM to the required 8MB with zeros using:
93```console
94$ dd if=/dev/zero of=6M.bin bs=1024 count=6144
95$ cat coreboot.rom 6M.bin > coreboot8.rom
96```
97
98If you want to continue using the neutered ME firmware use this flash layout
99for stage 2:
100```
10100000000:00000fff fd
10200023000:007fffff bios
10300003000:00022fff me
10400001000:00002fff gbe
105```
106
107If you want to use the original ME firmware use the original flash layout.
108
109More about flashing internally and getting the flash layout [here](../../tutorial/flashing_firmware/index.md).
110
111### External programming
112
113External programming with an SPI adapter and [flashrom] does work, but it powers the
114whole southbridge complex. You need to supply enough current through the programming adapter.
115
116If you want to use a SOIC pomona test clip, you have to cut the 2nd DRAM DIMM holder,
117as otherwise there's not enough space near the flash.
118
119**Position of SOIC-8 flash IC near 2nd DIMM holder**
120![][compaq_8200_flash1]
121
122[compaq_8200_flash1]: compaq_8200_sff_flash1.jpg
123
124**Closeup view of SOIC-8 flash IC**
125![][compaq_8200_flash2]
126
127[compaq_8200_flash2]: compaq_8200_sff_flash2.jpg
128
129## Technology
130
131```{eval-rst}
132+------------------+--------------------------------------------------+
133| Northbridge      | :doc:`../../northbridge/intel/sandybridge/index` |
134+------------------+--------------------------------------------------+
135| Southbridge      | bd82x6x                                          |
136+------------------+--------------------------------------------------+
137| CPU              | model_206ax                                      |
138+------------------+--------------------------------------------------+
139| SuperIO          | :doc:`../../superio/nuvoton/npcd378`             |
140+------------------+--------------------------------------------------+
141| EC               |                                                  |
142+------------------+--------------------------------------------------+
143| Coprocessor      | Intel ME                                         |
144+------------------+--------------------------------------------------+
145```
146[IFD Hack]: https://review.coreboot.org/plugins/gitiles/coreboot/+/refs/changes/70/38770/4/Documentation/flash_tutorial/int_macbook.md/
147[Compaq 8200 Elite SFF]: https://support.hp.com/us-en/document/c03414707
148[HP]: https://www.hp.com/
149[flashrom]: https://flashrom.org/Flashrom
150