1 /* 2 * 3 * Copyright 2014 Google Inc. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. The name of the author may not be used to endorse or promote products 14 * derived from this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #ifndef __ARCH_ARM64_MMU_H__ 30 #define __ARCH_ARM64_MMU_H__ 31 32 #include <libpayload.h> 33 34 struct mmu_memrange { 35 uint64_t base; 36 uint64_t size; 37 uint64_t type; 38 }; 39 40 struct mmu_ranges { 41 struct mmu_memrange entries[SYSINFO_MAX_MEM_RANGES]; 42 size_t used; 43 }; 44 45 /* 46 * Symbols taken from linker script 47 * They mark the start and end of the region used by payload 48 */ 49 extern char _start[], _end[]; 50 51 /* Memory attributes for mmap regions 52 * These attributes act as tag values for memrange regions 53 */ 54 55 #define TYPE_NORMAL_MEM 1 56 #define TYPE_DEV_MEM 2 57 #define TYPE_DMA_MEM 3 58 59 /* Descriptor attributes */ 60 61 #define INVALID_DESC 0x0 62 #define BLOCK_DESC 0x1 63 #define TABLE_DESC 0x3 64 #define PAGE_DESC 0x3 65 66 /* Block descriptor */ 67 #define BLOCK_NS (1 << 5) 68 69 #define BLOCK_AP_RW (0 << 7) 70 #define BLOCK_AP_RO (1 << 7) 71 72 #define BLOCK_ACCESS (1 << 10) 73 74 #define BLOCK_XN (1UL << 54) 75 76 #define BLOCK_SH_SHIFT (8) 77 #define BLOCK_SH_NON_SHAREABLE (0 << BLOCK_SH_SHIFT) 78 #define BLOCK_SH_UNPREDICTABLE (1 << BLOCK_SH_SHIFT) 79 #define BLOCK_SH_OUTER_SHAREABLE (2 << BLOCK_SH_SHIFT) 80 #define BLOCK_SH_INNER_SHAREABLE (3 << BLOCK_SH_SHIFT) 81 82 /* XLAT Table Init Attributes */ 83 84 #define VA_START 0x0 85 #define BITS_PER_VA 48 86 #define MIN_64_BIT_ADDR (1UL << 32) 87 /* Granule size of 4KB is being used */ 88 #define GRANULE_SIZE_SHIFT 12 89 #define GRANULE_SIZE (1 << GRANULE_SIZE_SHIFT) 90 #define XLAT_TABLE_MASK (~(0UL) << GRANULE_SIZE_SHIFT) 91 #define GRANULE_SIZE_MASK ((1 << GRANULE_SIZE_SHIFT) - 1) 92 93 #define BITS_RESOLVED_PER_LVL (GRANULE_SIZE_SHIFT - 3) 94 #define L0_ADDR_SHIFT (GRANULE_SIZE_SHIFT + BITS_RESOLVED_PER_LVL * 3) 95 #define L1_ADDR_SHIFT (GRANULE_SIZE_SHIFT + BITS_RESOLVED_PER_LVL * 2) 96 #define L2_ADDR_SHIFT (GRANULE_SIZE_SHIFT + BITS_RESOLVED_PER_LVL * 1) 97 #define L3_ADDR_SHIFT (GRANULE_SIZE_SHIFT + BITS_RESOLVED_PER_LVL * 0) 98 99 #define L0_ADDR_MASK (((1UL << BITS_RESOLVED_PER_LVL) - 1) << L0_ADDR_SHIFT) 100 #define L1_ADDR_MASK (((1UL << BITS_RESOLVED_PER_LVL) - 1) << L1_ADDR_SHIFT) 101 #define L2_ADDR_MASK (((1UL << BITS_RESOLVED_PER_LVL) - 1) << L2_ADDR_SHIFT) 102 #define L3_ADDR_MASK (((1UL << BITS_RESOLVED_PER_LVL) - 1) << L3_ADDR_SHIFT) 103 104 /* These macros give the size of the region addressed by each entry of a xlat 105 table at any given level */ 106 #define L3_XLAT_SIZE (1UL << L3_ADDR_SHIFT) 107 #define L2_XLAT_SIZE (1UL << L2_ADDR_SHIFT) 108 #define L1_XLAT_SIZE (1UL << L1_ADDR_SHIFT) 109 #define L0_XLAT_SIZE (1UL << L0_ADDR_SHIFT) 110 111 /* Block indices required for MAIR */ 112 #define BLOCK_INDEX_MEM_DEV_NGNRNE 0 113 #define BLOCK_INDEX_MEM_DEV_NGNRE 1 114 #define BLOCK_INDEX_MEM_DEV_GRE 2 115 #define BLOCK_INDEX_MEM_NORMAL_NC 3 116 #define BLOCK_INDEX_MEM_NORMAL 4 117 118 #define BLOCK_INDEX_SHIFT 2 119 120 /* MAIR attributes */ 121 #define MAIR_ATTRIBUTES ((0x00 << (BLOCK_INDEX_MEM_DEV_NGNRNE*8)) | \ 122 (0x04 << (BLOCK_INDEX_MEM_DEV_NGNRE*8)) | \ 123 (0x0c << (BLOCK_INDEX_MEM_DEV_GRE*8)) | \ 124 (0x44 << (BLOCK_INDEX_MEM_NORMAL_NC*8)) | \ 125 (0xffUL << (BLOCK_INDEX_MEM_NORMAL*8))) 126 127 /* TCR attributes */ 128 #define TCR_TOSZ (64 - BITS_PER_VA) 129 130 #define TCR_IRGN0_SHIFT 8 131 #define TCR_IRGN0_NM_NC (0x00 << TCR_IRGN0_SHIFT) 132 #define TCR_IRGN0_NM_WBWAC (0x01 << TCR_IRGN0_SHIFT) 133 #define TCR_IRGN0_NM_WTC (0x02 << TCR_IRGN0_SHIFT) 134 #define TCR_IRGN0_NM_WBNWAC (0x03 << TCR_IRGN0_SHIFT) 135 136 #define TCR_ORGN0_SHIFT 10 137 #define TCR_ORGN0_NM_NC (0x00 << TCR_ORGN0_SHIFT) 138 #define TCR_ORGN0_NM_WBWAC (0x01 << TCR_ORGN0_SHIFT) 139 #define TCR_ORGN0_NM_WTC (0x02 << TCR_ORGN0_SHIFT) 140 #define TCR_ORGN0_NM_WBNWAC (0x03 << TCR_ORGN0_SHIFT) 141 142 #define TCR_SH0_SHIFT 12 143 #define TCR_SH0_NC (0x0 << TCR_SH0_SHIFT) 144 #define TCR_SH0_OS (0x2 << TCR_SH0_SHIFT) 145 #define TCR_SH0_IS (0x3 << TCR_SH0_SHIFT) 146 147 #define TCR_TG0_SHIFT 14 148 #define TCR_TG0_4KB (0x0 << TCR_TG0_SHIFT) 149 #define TCR_TG0_64KB (0x1 << TCR_TG0_SHIFT) 150 #define TCR_TG0_16KB (0x2 << TCR_TG0_SHIFT) 151 152 #define TCR_PS_SHIFT 16 153 #define TCR_PS_4GB (0x0 << TCR_PS_SHIFT) 154 #define TCR_PS_64GB (0x1 << TCR_PS_SHIFT) 155 #define TCR_PS_1TB (0x2 << TCR_PS_SHIFT) 156 #define TCR_PS_4TB (0x3 << TCR_PS_SHIFT) 157 #define TCR_PS_16TB (0x4 << TCR_PS_SHIFT) 158 #define TCR_PS_256TB (0x5 << TCR_PS_SHIFT) 159 160 #define TCR_TBI_SHIFT 20 161 #define TCR_TBI_USED (0x0 << TCR_TBI_SHIFT) 162 #define TCR_TBI_IGNORED (0x1 << TCR_TBI_SHIFT) 163 164 #define DMA_DEFAULT_SIZE (32 * MiB) 165 #define TTB_DEFAULT_SIZE 0x100000 166 167 #define MB_SIZE (1UL << 20) 168 169 /* Initialize the MMU TTB tables using the mmu_ranges */ 170 uint64_t mmu_init(struct mmu_ranges *mmu_ranges); 171 172 /* Enable the mmu based on previous mmu_init(). */ 173 void mmu_enable(void); 174 175 /* Disable mmu */ 176 void mmu_disable(void); 177 178 /* Change a memory type for a range of bytes at runtime. */ 179 void mmu_config_range(void *start, size_t size, uint64_t tag); 180 181 /* 182 * Based on the memory ranges provided in coreboot tables, 183 * initialize the mmu_memranges used for mmu initialization 184 * cb_ranges -> Memory ranges present in cb tables 185 * mmu_ranges -> mmu_memranges initialized by this function 186 */ 187 struct mmu_memrange* mmu_init_ranges_from_sysinfo(struct memrange *cb_ranges, 188 uint64_t ncb, 189 struct mmu_ranges *mmu_ranges); 190 191 /* 192 * Functions for handling the initialization of memory ranges and enabling mmu 193 * before coreboot tables are parsed 194 */ 195 void mmu_presysinfo_memory_used(uint64_t base, uint64_t size); 196 void mmu_presysinfo_enable(void); 197 198 /* 199 * Functions for exposing the used memory ranges to payloads. The ranges contain 200 * all used memory ranges that are actually used by payload. i.e. _start -> _end 201 * in linker script, the coreboot tables and framebuffer/DMA allocated in MMU 202 * initialization. 203 */ 204 const struct mmu_ranges *mmu_get_used_ranges(void); 205 #endif // __ARCH_ARM64_MMU_H__ 206