1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 3 #ifndef ARMV7_H 4 #define ARMV7_H 5 6 /* Cortex-A9 revisions */ 7 #define MIDR_CORTEX_A9_R0P1 0x410FC091 8 #define MIDR_CORTEX_A9_R1P2 0x411FC092 9 #define MIDR_CORTEX_A9_R1P3 0x411FC093 10 #define MIDR_CORTEX_A9_R2P10 0x412FC09A 11 12 /* Cortex-A15 revisions */ 13 #define MIDR_CORTEX_A15_R0P0 0x410FC0F0 14 15 /* CCSIDR */ 16 #define CCSIDR_LINE_SIZE_OFFSET 0 17 #define CCSIDR_LINE_SIZE_MASK 0x7 18 #define CCSIDR_ASSOCIATIVITY_OFFSET 3 19 #define CCSIDR_ASSOCIATIVITY_MASK (0x3FF << 3) 20 #define CCSIDR_NUM_SETS_OFFSET 13 21 #define CCSIDR_NUM_SETS_MASK (0x7FFF << 13) 22 23 /* 24 * Values for InD field in CSSELR 25 * Selects the type of cache 26 */ 27 #define ARMV7_CSSELR_IND_DATA_UNIFIED 0 28 #define ARMV7_CSSELR_IND_INSTRUCTION 1 29 30 /* Values for Ctype fields in CLIDR */ 31 #define ARMV7_CLIDR_CTYPE_NO_CACHE 0 32 #define ARMV7_CLIDR_CTYPE_INSTRUCTION_ONLY 1 33 #define ARMV7_CLIDR_CTYPE_DATA_ONLY 2 34 #define ARMV7_CLIDR_CTYPE_INSTRUCTION_DATA 3 35 #define ARMV7_CLIDR_CTYPE_UNIFIED 4 36 37 /* 38 * CP15 Barrier instructions 39 * Please note that we have separate barrier instructions in ARMv7 40 * However, we use the CP15 based instructions because we use 41 * -march=armv5 in U-Boot 42 */ 43 #define CP15ISB (asm volatile ("mcr p15, 0, %0, c7, c5, 4" : : "r" (0))) 44 #define CP15DSB (asm volatile ("mcr p15, 0, %0, c7, c10, 4" : : "r" (0))) 45 #define CP15DMB (asm volatile ("mcr p15, 0, %0, c7, c10, 5" : : "r" (0))) 46 47 #endif /* ARMV7_H */ 48