1 /* SPDX-License-Identifier: GPL-2.0-only */
2
3 #include <acpi/acpi.h>
4 #include <acpi/acpigen.h>
5 #include <console/console.h>
6 #include <cpu/cpu.h>
7 #include <cpu/intel/speedstep.h>
8 #include <cpu/intel/turbo.h>
9 #include <cpu/x86/msr.h>
10 #include <device/device.h>
11 #include <types.h>
12
13 #include "model_2065x.h"
14 #include "chip.h"
15
get_cores_per_package(void)16 static int get_cores_per_package(void)
17 {
18 struct cpuinfo_x86 c;
19 struct cpuid_result result;
20 int cores = 1;
21
22 get_fms(&c, cpuid_eax(1));
23 if (c.x86 != 6)
24 return 1;
25
26 result = cpuid_ext(0xb, 1);
27 cores = result.ebx & 0xff;
28
29 return cores;
30 }
31
generate_C_state_entries(void)32 static void generate_C_state_entries(void)
33 {
34 /* TODO */
35 }
36
37 static acpi_tstate_t tss_table_fine[] = {
38 { 100, 1000, 0, 0x00, 0 },
39 { 94, 940, 0, 0x1f, 0 },
40 { 88, 880, 0, 0x1e, 0 },
41 { 82, 820, 0, 0x1d, 0 },
42 { 75, 760, 0, 0x1c, 0 },
43 { 69, 700, 0, 0x1b, 0 },
44 { 63, 640, 0, 0x1a, 0 },
45 { 57, 580, 0, 0x19, 0 },
46 { 50, 520, 0, 0x18, 0 },
47 { 44, 460, 0, 0x17, 0 },
48 { 38, 400, 0, 0x16, 0 },
49 { 32, 340, 0, 0x15, 0 },
50 { 25, 280, 0, 0x14, 0 },
51 { 19, 220, 0, 0x13, 0 },
52 { 13, 160, 0, 0x12, 0 },
53 };
54
55 static acpi_tstate_t tss_table_coarse[] = {
56 { 100, 1000, 0, 0x00, 0 },
57 { 88, 875, 0, 0x1f, 0 },
58 { 75, 750, 0, 0x1e, 0 },
59 { 63, 625, 0, 0x1d, 0 },
60 { 50, 500, 0, 0x1c, 0 },
61 { 38, 375, 0, 0x1b, 0 },
62 { 25, 250, 0, 0x1a, 0 },
63 { 13, 125, 0, 0x19, 0 },
64 };
65
generate_T_state_entries(int core,int cores_per_package)66 static void generate_T_state_entries(int core, int cores_per_package)
67 {
68 /* Indicate SW_ALL coordination for T-states */
69 acpigen_write_TSD_package(core, cores_per_package, SW_ALL);
70
71 /* Indicate FFixedHW so OS will use MSR */
72 acpigen_write_empty_PTC();
73
74 /* Set a T-state limit that can be modified in NVS */
75 acpigen_write_TPC("\\TLVL");
76
77 /*
78 * CPUID.(EAX=6):EAX[5] indicates support
79 * for extended throttle levels.
80 */
81 if (cpuid_eax(6) & (1 << 5))
82 acpigen_write_TSS_package(
83 ARRAY_SIZE(tss_table_fine), tss_table_fine);
84 else
85 acpigen_write_TSS_package(
86 ARRAY_SIZE(tss_table_coarse), tss_table_coarse);
87 }
88
calculate_power(int tdp,int p1_ratio,int ratio)89 static int calculate_power(int tdp, int p1_ratio, int ratio)
90 {
91 u32 m;
92 u32 power;
93
94 /*
95 * M = ((1.1 - ((p1_ratio - ratio) * 0.00625)) / 1.1) ^ 2
96 *
97 * Power = (ratio / p1_ratio) * m * tdp
98 */
99
100 m = (110000 - ((p1_ratio - ratio) * 625)) / 11;
101 m = (m * m) / 1000;
102
103 power = ((ratio * 100000 / p1_ratio) / 100);
104 power *= (m / 100) * (tdp / 1000);
105 power /= 1000;
106
107 return (int)power;
108 }
109
generate_P_state_entries(int core,int cores_per_package)110 static void generate_P_state_entries(int core, int cores_per_package)
111 {
112 int ratio_min, ratio_max, ratio_turbo, ratio_step;
113 int coord_type, power_max, num_entries;
114 int ratio, power, clock, clock_max;
115 msr_t msr;
116
117 /* Determine P-state coordination type from MISC_PWR_MGMT[0] */
118 msr = rdmsr(MSR_MISC_PWR_MGMT);
119 if (msr.lo & MISC_PWR_MGMT_EIST_HW_DIS)
120 coord_type = SW_ANY;
121 else
122 coord_type = HW_ALL;
123
124 /* Get bus ratio limits and calculate clock speeds */
125 msr = rdmsr(MSR_PLATFORM_INFO);
126 ratio_min = (msr.hi >> (40-32)) & 0xff; /* Max Efficiency Ratio */
127
128 /* Max Non-Turbo Ratio */
129 ratio_max = (msr.lo >> 8) & 0xff;
130
131 clock_max = ratio_max * IRONLAKE_BCLK + ratio_max / 3;
132
133 /* Calculate CPU TDP in mW */
134 power_max = 25000;
135
136 /* Write _PCT indicating use of FFixedHW */
137 acpigen_write_empty_PCT();
138
139 /* Write _PPC with no limit on supported P-state */
140 acpigen_write_PPC_NVS();
141
142 /* Write PSD indicating configured coordination type */
143 acpigen_write_PSD_package(core, cores_per_package, coord_type);
144
145 /* Add P-state entries in _PSS table */
146 acpigen_write_name("_PSS");
147
148 /* Determine ratio points */
149 ratio_step = PSS_RATIO_STEP;
150 num_entries = (ratio_max - ratio_min) / ratio_step;
151 while (num_entries > PSS_MAX_ENTRIES-1) {
152 ratio_step <<= 1;
153 num_entries >>= 1;
154 }
155
156 /* P[T] is Turbo state if enabled */
157 if (get_turbo_state() == TURBO_ENABLED) {
158 /* _PSS package count including Turbo */
159 acpigen_write_package(num_entries + 2);
160
161 msr = rdmsr(MSR_TURBO_RATIO_LIMIT);
162 ratio_turbo = msr.lo & 0xff;
163
164 /* Add entry for Turbo ratio */
165 acpigen_write_PSS_package(
166 clock_max + 1, /*MHz*/
167 power_max, /*mW*/
168 PSS_LATENCY_TRANSITION, /*lat1*/
169 PSS_LATENCY_BUSMASTER, /*lat2*/
170 ratio_turbo, /*control*/
171 ratio_turbo); /*status*/
172 } else {
173 /* _PSS package count without Turbo */
174 acpigen_write_package(num_entries + 1);
175 }
176
177 /* First regular entry is max non-turbo ratio */
178 acpigen_write_PSS_package(
179 clock_max, /*MHz*/
180 power_max, /*mW*/
181 PSS_LATENCY_TRANSITION, /*lat1*/
182 PSS_LATENCY_BUSMASTER, /*lat2*/
183 ratio_max, /*control*/
184 ratio_max); /*status*/
185
186 /* Generate the remaining entries */
187 for (ratio = ratio_min + ((num_entries - 1) * ratio_step);
188 ratio >= ratio_min; ratio -= ratio_step) {
189 /* Calculate power at this ratio */
190 power = calculate_power(power_max, ratio_max, ratio);
191 clock = ratio * IRONLAKE_BCLK + ratio / 3;
192
193 acpigen_write_PSS_package(
194 clock, /*MHz*/
195 power, /*mW*/
196 PSS_LATENCY_TRANSITION, /*lat1*/
197 PSS_LATENCY_BUSMASTER, /*lat2*/
198 ratio, /*control*/
199 ratio); /*status*/
200 }
201
202 /* Fix package length */
203 acpigen_pop_len();
204 }
205
generate_cpu_entry(int cpu,int core,int cores_per_package)206 static void generate_cpu_entry(int cpu, int core, int cores_per_package)
207 {
208 /* Generate Scope(\_SB) { Device(CPUx */
209 acpigen_write_processor_device(cpu * cores_per_package + core);
210
211 /* Generate P-state tables */
212 generate_P_state_entries(cpu, cores_per_package);
213
214 /* Generate C-state tables */
215 generate_C_state_entries();
216
217 /* Generate T-state tables */
218 generate_T_state_entries(cpu, cores_per_package);
219
220 acpigen_write_processor_device_end();
221 }
222
generate_cpu_entries(const struct device * device)223 void generate_cpu_entries(const struct device *device)
224 {
225 int totalcores = dev_count_cpu();
226 int cores_per_package = get_cores_per_package();
227 int numcpus = totalcores / cores_per_package;
228
229 printk(BIOS_DEBUG, "Found %d CPU(s) with %d core(s) each.\n",
230 numcpus, cores_per_package);
231
232 for (int cpu_id = 0; cpu_id < numcpus; cpu_id++)
233 for (int core_id = 0; core_id < cores_per_package; core_id++)
234 generate_cpu_entry(cpu_id, core_id, cores_per_package);
235
236 /* PPKG is usually used for thermal management
237 of the first and only package. */
238 acpigen_write_processor_package("PPKG", 0, cores_per_package);
239
240 /* Add a method to notify processor nodes */
241 acpigen_write_processor_cnot(cores_per_package);
242 }
243
244 struct chip_operations cpu_intel_model_2065x_ops = {
245 .name = "Intel Arrandale CPU",
246 };
247