1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 3 #include <arch/romstage.h> 4 #include <arch/symbols.h> 5 #include <cbfs.h> 6 #include <cbmem.h> 7 #include <console/console.h> 8 #include <commonlib/helpers.h> 9 #include <cpu/x86/mtrr.h> 10 #include <fsp/car.h> 11 #include <fsp/util.h> 12 fill_postcar_frame(struct postcar_frame * pcf)13void fill_postcar_frame(struct postcar_frame *pcf) 14 { 15 /* Cache at least 8 MiB below the top of ram, and at most 8 MiB 16 * above top of the ram. This satisfies MTRR alignment requirement 17 * with different TSEG size configurations. */ 18 const uintptr_t top_of_ram = ALIGN_DOWN(cbmem_top(), 8 * MiB); 19 postcar_frame_add_mtrr(pcf, top_of_ram - 8*MiB, 16*MiB, MTRR_TYPE_WRBACK); 20 } 21 22 /* This is the romstage entry called from cpu/intel/car/romstage.c */ mainboard_romstage_entry(void)23void mainboard_romstage_entry(void) 24 { 25 /* Need to locate the current FSP_INFO_HEADER. The cache-as-ram 26 * is still enabled. We can directly access work buffer here. */ 27 void *fsp = cbfs_map("fsp.bin", NULL); 28 29 if (!fsp) 30 die_with_post_code(POSTCODE_INVALID_CBFS, "Unable to locate fsp.bin"); 31 32 /* This leaks a mapping which this code assumes is benign as 33 * the flash is memory mapped CPU's address space. */ 34 FSP_INFO_HEADER *fih = find_fsp((uintptr_t)fsp); 35 36 if (!fih) 37 die("Invalid FSP header\n"); 38 39 cache_as_ram_stage_main(fih); 40 } 41