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1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 
3 #ifndef _DRIVERS_INTEL_USB4_RETIMER_H_
4 #define _DRIVERS_INTEL_USB4_RETIMER_H_
5 
6 /* Flags representing mux state */
7 #define USB_PD_MUX_NONE               0      /* Open switch */
8 #define USB_PD_MUX_USB_ENABLED        BIT(0) /* USB connected */
9 #define USB_PD_MUX_DP_ENABLED         BIT(1) /* DP connected */
10 #define USB_PD_MUX_SAFE_MODE          BIT(5) /* DP is in safe mode */
11 #define USB_PD_MUX_TBT_COMPAT_ENABLED BIT(6) /* TBT compat enabled */
12 #define USB_PD_MUX_USB4_ENABLED       BIT(7) /* USB4 enabled */
13 
14 /* USB Retimer firmware update mux mask */
15 #define USB_RETIMER_FW_UPDATE_MUX_MASK (USB_PD_MUX_USB_ENABLED | \
16 					USB_PD_MUX_DP_ENABLED  | \
17 					USB_PD_MUX_SAFE_MODE   | \
18 					USB_PD_MUX_TBT_COMPAT_ENABLED | \
19 					USB_PD_MUX_USB4_ENABLED)
20 
21 #define USB_RETIMER_FW_UPDATE_OP_SHIFT		4
22 #define USB_RETIMER_FW_UPDATE_ERROR		0xfe
23 #define USB_RETIMER_FW_UPDATE_INVALID_MUX	0xff
24 
25 /* Retimer firmware update operations */
26 #define USB_RETIMER_FW_UPDATE_SUSPEND_PD 1 /* Suspend PD port */
27 #define USB_RETIMER_FW_UPDATE_RESUME_PD  2 /* Resume PD port  */
28 #define USB_RETIMER_FW_UPDATE_GET_MUX    3 /* Read current USB MUX  */
29 #define USB_RETIMER_FW_UPDATE_SET_USB    4 /* Set MUX to USB mode   */
30 #define USB_RETIMER_FW_UPDATE_SET_SAFE   5 /* Set MUX to Safe mode  */
31 #define USB_RETIMER_FW_UPDATE_SET_TBT    6 /* Set MUX to TBT mode   */
32 #define USB_RETIMER_FW_UPDATE_DISCONNECT 7 /* Set MUX to disconnect */
33 
34 struct usb4_retimer_dsm_uuid {
35 	const char *uuid;
36 	void (**callbacks)(uint8_t port, void *);
37 	size_t count;
38 	void *arg;
39 };
40 
41 const char *ec_retimer_fw_update_path(void);
42 void ec_retimer_fw_update(uint8_t data);
43 /*
44  * This function will convert CPU physical port mapping to abstract
45  * EC port mapping. For example, board might have enabled TCSS port 1
46  * and 3 as per physical port mapping. Since only 2 TCSS ports are enabled
47  * EC will name it as port 0 and port 1. So there will be mismatch when
48  * coreboot sends index for port 3.
49  * Each SoC code using retimer driver needs to implement this function
50  * since SoC will have physical port details.
51  */
52 int retimer_get_index_for_typec(uint8_t typec_port);
53 
54 #endif /* _DRIVERS_INTEL_USB4_RETIMER_H_ */
55