1 /* SPDX-License-Identifier: GPL-2.0-only */
2
3 #ifndef DEVICE_PNP_HWM5_CONF_H
4 #define DEVICE_PNP_HWM5_CONF_H
5
6 #include <device/pnp.h>
7 #include <stdint.h>
8
9 /* The address/data register pair for the indirect/indexed IO space of the
10 * hardware monitor (HWM) that does temperature and voltage sensing and fan
11 * control in ITE, Nuvoton and Winbond super IO chips aren't at offset 0 and 1
12 * of the corresponding IO address region, but at offset 5 and 6. */
13
14 /*
15 * u8 pnp_read_hwm5_index(u16 base, u8 reg)
16 * Description:
17 * This routine reads indexed I/O registers. The reg byte is written
18 * to the index register at I/O address = base + 5. The result is then
19 * read from the data register at I/O address = base + 6.
20 *
21 * Parameters:
22 * @param[in] u16 base = The I/O address of the base index register.
23 * @param[in] u8 reg = The offset within the indexed space.
24 * @param[out] u8 result = The value read back from the data register.
25 */
pnp_read_hwm5_index(u16 base,u8 reg)26 static inline u8 pnp_read_hwm5_index(u16 base, u8 reg)
27 {
28 return pnp_read_index(base + 5, reg);
29 }
30
31 /*
32 * void pnp_write_hwm5_index(u16 base, u8 reg, u8 value)
33 * Description:
34 * This routine writes indexed I/O registers. The reg byte is written
35 * to the index register at I/O address = base + 5. The value byte is then
36 * written to the data register at I/O address = base + 6.
37 *
38 * Parameters:
39 * @param[in] u16 base = The address of the base index register.
40 * @param[in] u8 reg = The offset within the indexed space.
41 * @param[in] u8 value = The value to be written to the data register.
42 */
pnp_write_hwm5_index(u16 base,u8 reg,u8 value)43 static inline void pnp_write_hwm5_index(u16 base, u8 reg, u8 value)
44 {
45 pnp_write_index(base + 5, reg, value);
46 }
47
48 /*
49 * void pnp_unset_and_set_hwm5_index(u16 base, u8 reg, u8 unset, u8 set)
50 * Description:
51 * This routine unsets and sets bits from indexed I/O registers. The
52 * reg byte is written to the index register at I/O address = base + 5.
53 * The value byte to update is data register at I/O address = base + 6.
54 *
55 * Unlike and-then-or style operations, no bitwise negation is necessary
56 * to specify the bits to unset. Because the bitwise negation implicitly
57 * promotes operands to int before operating, one may have to explicitly
58 * downcast the result if the data width is smaller than that of an int.
59 * Since warnings are errors in coreboot, explicit casting is necessary.
60 *
61 * Performing said negation inside this routine alleviates this problem,
62 * while allowing the compiler to warn if the input parameters overflow.
63 * Casting outside this function would silence valid compiler warnings.
64 *
65 * Parameters:
66 * @param[in] u16 base = The address of the base index register.
67 * @param[in] u8 reg = The offset within the indexed space.
68 * @param[in] u8 unset = Bitmask with ones to the bits to unset from the data register.
69 * @param[in] u8 set = Bitmask with ones to the bits to set from the data register.
70 */
pnp_unset_and_set_hwm5_index(u16 base,u8 reg,u8 unset,u8 set)71 static inline void pnp_unset_and_set_hwm5_index(u16 base, u8 reg, u8 unset, u8 set)
72 {
73 pnp_unset_and_set_index(base + 5, reg, unset, set);
74 }
75
76 #endif /* DEVICE_PNP_HWM5_CONF_H */
77