1 /* SPDX-License-Identifier: GPL-2.0-only */
2
3 #include <gpio.h>
4 #include "gpio.h"
5
6 /*
7 * As a rule of thumb, GPIO pins used by coreboot should be initialized at
8 * bootblock while GPIO pins used only by the OS should be initialized at
9 * ramstage.
10 */
11 static const struct soc_amd_gpio gpio_set_stage_ram[] = {
12 /* I2S SDIN */
13 PAD_NF(GPIO_7, ACP_I2S_SDIN, PULL_NONE),
14 /* I2S LRCLK */
15 PAD_NF(GPIO_8, ACP_I2S_LRCLK, PULL_NONE),
16 /* not Blink */
17 PAD_GPI(GPIO_11, PULL_UP),
18 /* APU_ALS_INT# */
19 PAD_SCI(GPIO_24, PULL_UP, EDGE_LOW),
20 /* NFC IRQ */
21 PAD_INT(GPIO_69, PULL_UP, EDGE_LOW, STATUS),
22 };
23
mainboard_program_gpios(void)24 void mainboard_program_gpios(void)
25 {
26 gpio_configure_pads(gpio_set_stage_ram, ARRAY_SIZE(gpio_set_stage_ram));
27 }
28