1 /* SPDX-License-Identifier: GPL-2.0-only */
2
3 #include <soc/amd/stoneyridge/chip.h>
4 #include <amdblocks/agesawrapper.h>
5
6 #define DIMMS_PER_CHANNEL 1
7 #if DIMMS_PER_CHANNEL > MAX_DIMMS_PER_CH
8 #error "Too many DIMM sockets defined for the mainboard"
9 #endif
10
11 static const PSO_ENTRY DDR4PlatformMemoryConfiguration[] = {
12 DRAM_TECHNOLOGY(ANY_SOCKET, DDR4_TECHNOLOGY),
13 NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, CHANNEL_A, 1),
14 NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, CHANNEL_B, 1),
15 NUMBER_OF_CHANNELS_SUPPORTED(ANY_SOCKET, MAX_DRAM_CH),
16 MOTHER_BOARD_LAYERS(LAYERS_6),
17 MEMCLK_DIS_MAP(ANY_SOCKET, CHANNEL_A, 0x01, 0x02, 0x00, 0x00,
18 0x00, 0x00, 0x00, 0x00),
19 MEMCLK_DIS_MAP(ANY_SOCKET, CHANNEL_B, 0x01, 0x02, 0x08, 0x04,
20 0x00, 0x00, 0x00, 0x00),
21 CKE_TRI_MAP(ANY_SOCKET, CHANNEL_A, 0x01, 0x02, 0x00, 0x00),
22 CKE_TRI_MAP(ANY_SOCKET, CHANNEL_B, 0x05, 0x0A, 0x00, 0x00),
23 ODT_TRI_MAP(ANY_SOCKET, CHANNEL_A, 0x01, 0x00, 0x02, 0x00),
24 ODT_TRI_MAP(ANY_SOCKET, CHANNEL_B, 0x01, 0x04, 0x02, 0x08),
25 CS_TRI_MAP(ANY_SOCKET, CHANNEL_A, 0x01, 0x02, 0x00, 0x00, 0x00,
26 0x00, 0x00, 0x00),
27 CS_TRI_MAP(ANY_SOCKET, CHANNEL_B, 0x01, 0x02, 0x04, 0x08, 0x00,
28 0x00, 0x00, 0x00),
29 PSO_END
30 };
31
OemPostParams(AMD_POST_PARAMS * PostParams)32 void OemPostParams(AMD_POST_PARAMS *PostParams)
33 {
34 PostParams->MemConfig.PlatformMemoryConfiguration =
35 (PSO_ENTRY *)DDR4PlatformMemoryConfiguration;
36 PostParams->MemConfig.CfgUmaAbove4G = TRUE;
37 }
38