1/* SPDX-License-Identifier: GPL-2.0-only */ 2 3/* DefinitionBlock Statement */ 4#include <acpi/acpi.h> 5DefinitionBlock ( 6 "dsdt.aml", 7 "DSDT", 8 ACPI_DSDT_REV_2, 9 OEM_ID, 10 ACPI_TABLE_CREATOR, 11 0x00010001 /* OEM Revision */ 12 ) 13{ /* Start of ASL file */ 14 #include <acpi/dsdt_top.asl> 15 #include <globalnvs.asl> 16 17 /* Describe the USB Overcurrent pins */ 18 #include "acpi/usb_oc.asl" 19 20 /* PCI IRQ mapping for the Southbridge */ 21 #include <pcie.asl> 22 23 /* Power state notification */ 24 #include <pnot.asl> 25 26 /* Contains the supported sleep states for this chipset */ 27 #include <soc/amd/common/acpi/sleepstates.asl> 28 29 /* Contains the Sleep methods (WAK, PTS, GTS, etc.) */ 30 #include "acpi/sleep.asl" 31 32 /* System Bus */ 33 Scope(\_SB) { /* Start \_SB scope */ 34 /* global utility methods expected within the \_SB scope */ 35 #include <arch/x86/acpi/globutil.asl> 36 37 /* IRQ Routing mapping for this platform (in \_SB scope) */ 38 #include "acpi/routing.asl" 39 40 Device(PWRB) { 41 Name(_HID, EISAID("PNP0C0C")) 42 Name(_UID, 0xAA) 43 Name(_PRW, Package () {3, 0x04}) 44 Name(_STA, 0x0B) 45 } 46 47 /* Describe the SOC */ 48 #include <soc.asl> 49 50 /* Describe the Fintek F81803A SIO */ 51 #define SUPERIO_DEV SIO0 52 #define SUPERIO_PNP_BASE 0x4E 53 #define F81803A_SHOW_UARTA 54 #define F81803A_SHOW_PME 55 #include <superio/fintek/f81803a/acpi/superio.asl> 56 57 } /* End \_SB scope */ 58 59 /* Define the General Purpose Events for the platform */ 60 #include "acpi/gpe.asl" 61} 62/* End of ASL file */ 63