1 /* SPDX-License-Identifier: GPL-2.0-only */
2
3 #include <device/pnp_ops.h>
4 #include <superio/nuvoton/common/nuvoton.h>
5 #include <superio/nuvoton/nct6776/nct6776.h>
6 #include <southbridge/intel/lynxpoint/pch.h>
7
8 #define GLOBAL_DEV PNP_DEV(0x2e, 0)
9 #define SERIAL_DEV PNP_DEV(0x2e, NCT6776_SP1)
10 #define ACPI_DEV PNP_DEV(0x2e, NCT6776_ACPI)
11
12 /*
13 * Asrock B85M Pro4 Super I/O GPIOs
14 *
15 * +------+-----+---------------------------+
16 * | GPIO | Pin | Description |
17 * +------+-----+---------------------------+
18 * | GP00 | 2 | N/C |
19 * | GP01 | 4 | CPU Fan 4-pin tach enable |
20 * | GP02 | 5 | CPU Fan 3-pin tach enable |
21 * | GP03 | 8 | CPU Fan 3-pin FON# signal |
22 * | GP04 | 9 | N/C |
23 * | GP05 | 11 | N/C (+1.05V_PCH_GPIO) |
24 * | GP06 | 12 | N/C (+1.5V_PCH_GPIO) |
25 * | GP07 | 13 | N/C |
26 * +------+-----+---------------------------+
27 * | GP10 | 123 | N/C (VCCM_OV1) |
28 * | GP11 | 122 | N/C (VCCM_OV2) |
29 * | GP12 | 121 | N/C (VCCM_OV3) |
30 * | GP13 | 120 | N/C (VCCM_STEP) |
31 * | GP14 | 119 | Assert HDA_SDO (SIO_GP14) |
32 * | GP15 | 118 | N/C (PWM_THROTTLE) |
33 * | GP16 | 117 | OTP for VCORE (OTE_GATE1) |
34 * | GP17 | 116 | N/C (IMON_GPIO) |
35 * +------+-----+---------------------------+
36 * | GP70 | 93 | PWR_FANIN |
37 * | GP71 | 92 | N/C |
38 * | GP72 | 91 | N/C (SIO_PIN91) |
39 * | GP73 | 90 | CHA2_FANIN |
40 * | GP74 | 89 | N/C (SIO_PIN89) |
41 * | GP75 | 88 | N/C (SIO_PIN88) |
42 * | GP76 | 87 | HDA reset gate (GP76) |
43 * | GP77 | 86 | HDD_LED gate |
44 * +------+-----+---------------------------+
45 */
46
mainboard_config_superio(void)47 void mainboard_config_superio(void)
48 {
49 nuvoton_pnp_enter_conf_state(GLOBAL_DEV);
50
51 /* Select SIO pin mux states */
52 pnp_write_config(GLOBAL_DEV, 0x1b, 0x68);
53 pnp_write_config(GLOBAL_DEV, 0x1c, 0x80);
54 pnp_write_config(GLOBAL_DEV, 0x24, 0x1c);
55 pnp_write_config(GLOBAL_DEV, 0x27, 0xd0);
56 pnp_write_config(GLOBAL_DEV, 0x2a, 0x62);
57 pnp_write_config(GLOBAL_DEV, 0x2c, 0x80);
58 pnp_write_config(GLOBAL_DEV, 0x2f, 0x03);
59
60 /* Power RAM in S3 and let the PCH handle power failure actions */
61 pnp_set_logical_device(ACPI_DEV);
62 pnp_write_config(ACPI_DEV, 0xe4, 0x70);
63
64 nuvoton_pnp_exit_conf_state(GLOBAL_DEV);
65
66 /* Enable UART */
67 nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
68 }
69