1## SPDX-License-Identifier: GPL-2.0-only 2 3chip soc/intel/skylake 4 5 register "deep_sx_config" = "DSX_EN_WAKE_PIN" 6 7 register "eist_enable" = "1" 8 9 # GPE configuration 10 # Note that GPE events called out in ASL code rely on this 11 # route. i.e. If this route changes then the affected GPE 12 # offset bits also need to be changed. 13 register "gpe0_dw0" = "GPP_B" 14 register "gpe0_dw1" = "GPP_D" 15 register "gpe0_dw2" = "GPP_E" 16 17 # Enable DPTF 18 register "dptf_enable" = "1" 19 20 # FSP Configuration 21 register "PrimaryDisplay" = "Display_PEG" 22 23 # Enabling SLP_S3#, SLP_S4#, SLP_SUS and SLP_A Stretch 24 # SLP_S3 Minimum Assertion Width. Values 0: 60us, 1: 1ms, 2: 50ms, 3: 2s 25 register "PmConfigSlpS3MinAssert" = "0x02" 26 27 # SLP_S4 Minimum Assertion Width. Values 0: default, 1: 1s, 2: 2s, 3: 3s, 4: 4s 28 register "PmConfigSlpS4MinAssert" = "0x04" 29 30 # SLP_SUS Minimum Assertion Width. Values 0: 0ms, 1: 500ms, 2: 1s, 3: 4s 31 register "PmConfigSlpSusMinAssert" = "0x03" 32 33 # SLP_A Minimum Assertion Width. Values 0: 0ms, 1: 4s, 2: 98ms, 3: 2s 34 register "PmConfigSlpAMinAssert" = "0x03" 35 36 # PL2 override 91W 37 register "power_limits_config" = "{ 38 .tdp_pl2_override = 91, 39 }" 40 41 # Send an extra VR mailbox command for the PS4 exit issue 42 register "SendVrMbxCmd" = "2" 43 44 device domain 0 on 45 device ref system_agent on 46 subsystemid 0x1849 0x191f 47 end 48 device ref peg0 on 49 subsystemid 0x1849 0x1901 50 register "Peg0MaxLinkWidth" = "Peg0_x16" 51 52 # Configure PCIe clockgen in PCH 53 register "PcieRpClkReqSupport[0]" = "1" 54 register "PcieRpClkReqNumber[0]" = "0" 55 register "PcieRpClkSrcNumber[0]" = "0" 56 end 57 device ref igpu on 58 subsystemid 0x1849 0x1912 59 end 60 device ref sa_thermal on end 61 device ref south_xhci on 62 subsystemid 0x1849 0xa131 63 64 register "usb2_ports" = "{ 65 [0] = USB2_PORT_MID(OC0), 66 [1] = USB2_PORT_MID(OC0), 67 [2] = USB2_PORT_MID(OC4), 68 [3] = USB2_PORT_MID(OC4), 69 [4] = USB2_PORT_MID(OC2), 70 [5] = USB2_PORT_MID(OC2), 71 [6] = USB2_PORT_MID(OC0), 72 [7] = USB2_PORT_MID(OC0), 73 [8] = USB2_PORT_MID(OC0), 74 [9] = USB2_PORT_MID(OC0), 75 [10] = USB2_PORT_MID(OC1), 76 [11] = USB2_PORT_MID(OC1), 77 [12] = USB2_PORT_MID(OC_SKIP), 78 [13] = USB2_PORT_MID(OC_SKIP), 79 }" 80 register "usb3_ports" = "{ 81 [0] = USB3_PORT_DEFAULT(OC0), 82 [1] = USB3_PORT_DEFAULT(OC0), 83 [2] = USB3_PORT_DEFAULT(OC3), 84 [3] = USB3_PORT_DEFAULT(OC3), 85 [4] = USB3_PORT_DEFAULT(OC1), 86 [5] = USB3_PORT_DEFAULT(OC1), 87 [6] = USB3_PORT_DEFAULT(OC_SKIP), 88 [7] = USB3_PORT_DEFAULT(OC_SKIP), 89 [8] = USB3_PORT_DEFAULT(OC_SKIP), 90 [9] = USB3_PORT_DEFAULT(OC_SKIP), 91 }" 92 end 93 device ref thermal on 94 subsystemid 0x1849 0xa131 95 end 96 device ref heci1 on 97 subsystemid 0x1849 0xa131 98 end 99 device ref sata on 100 subsystemid 0x1849 0xa102 101 register "SataSalpSupport" = "1" 102 # SATA4 and SATA5 are located in the lower right corner of the board, 103 # but they are not populated. This is because the same PCB is used to 104 # make boards with better PCHs, which can have up to six SATA ports. 105 # However, the H110 PCH only has four SATA ports, which explains why 106 # two connectors are missing. 107 register "SataPortsEnable" = "{ 108 [0] = 1, 109 [1] = 1, 110 [2] = 1, 111 [3] = 1, 112 }" 113 end 114 device ref pcie_rp1 on end 115 device ref pcie_rp5 on 116 register "PcieRpEnable[4]" = "1" 117 register "PcieRpClkReqSupport[4]" = "1" 118 register "PcieRpClkReqNumber[4]" = "2" 119 register "PcieRpAdvancedErrorReporting[4]" = "1" 120 register "PcieRpLtrEnable[4]" = "1" 121 register "PcieRpClkSrcNumber[4]" = "2" 122 register "PcieRpHotPlug[4]" = "1" 123 end 124 device ref pcie_rp6 on 125 register "PcieRpEnable[5]" = "1" 126 127 # Disable CLKREQ#, since onboard LAN is always present 128 register "PcieRpClkReqSupport[5]" = "0" 129 register "PcieRpAdvancedErrorReporting[5]" = "1" 130 register "PcieRpLtrEnable[5]" = "1" 131 register "PcieRpClkSrcNumber[5]" = "1" 132 end 133 device ref pcie_rp7 on 134 register "PcieRpEnable[6]" = "1" 135 register "PcieRpClkReqSupport[6]" = "1" 136 register "PcieRpClkReqNumber[6]" = "3" 137 register "PcieRpAdvancedErrorReporting[6]" = "1" 138 register "PcieRpLtrEnable[6]" = "1" 139 register "PcieRpClkSrcNumber[6]" = "3" 140 register "PcieRpHotPlug[6]" = "1" 141 end 142 device ref lpc_espi on 143 subsystemid 0x1849 0x1a43 144 145 # Set @0x280-0x2ff I/O Range for SuperIO HWM 146 register "gen1_dec" = "0x007c0281" 147 148 # Set LPC Serial IRQ mode 149 register "serirq_mode" = "SERIRQ_CONTINUOUS" 150 151 chip superio/common 152 device pnp 2e.0 on # passes SIO base addr to SSDT gen 153 154 chip superio/nuvoton/nct6791d 155 device pnp 2e.1 on 156 # Global Control Registers 157 # Device IRQ Polarity 158 irq 0x13 = 0x00 159 irq 0x14 = 0x00 160 # Global Option 161 irq 0x24 = 0xfb 162 irq 0x27 = 0x10 163 # Multi Function 164 irq 0x1a = 0xb0 165 irq 0x1b = 0xe6 166 irq 0x2a = 0x04 167 irq 0x2c = 0x40 168 irq 0x2d = 0x03 169 170 # Parallel Port 171 io 0x60 = 0x0378 172 irq 0x70 = 7 173 drq 0x74 = 4 # No DMA 174 irq 0xf0 = 0x3c # Printer mode 175 end 176 device pnp 2e.2 on # UART A 177 io 0x60 = 0x03f8 178 irq 0x70 = 4 179 end 180 device pnp 2e.3 on # IR 181 io 0x60 = 0x02f8 182 irq 0x70 = 3 183 end 184 device pnp 2e.5 on # PS/2 KBC 185 io 0x60 = 0x0060 186 io 0x62 = 0x0064 187 irq 0x70 = 1 # Keyboard 188 irq 0x72 = 12 # Mouse 189 end 190 device pnp 2e.6 off end # CIR 191 device pnp 2e.7 on # GPIO6 192 irq 0xf6 = 0xff 193 irq 0xf7 = 0xff 194 irq 0xf8 = 0xff 195 end 196 device pnp 2e.107 on # GPIO7 197 irq 0xe0 = 0x7f 198 irq 0xe1 = 0x0d 199 end 200 device pnp 2e.207 on # GPIO8 201 irq 0xe6 = 0xff 202 irq 0xe7 = 0xff 203 irq 0xed = 0xff 204 end 205 device pnp 2e.8 off end # WDT 206 device pnp 2e.108 on end # GPIO0 207 device pnp 2e.308 off end # GPIO base 208 device pnp 2e.408 off end # WDTMEM 209 device pnp 2e.708 on end # GPIO1 210 device pnp 2e.9 on end # GPIO2 211 device pnp 2e.109 on # GPIO3 212 irq 0xe4 = 0x7b 213 irq 0xe5 = 0x02 214 irq 0xea = 0x04 215 end 216 device pnp 2e.209 on # GPIO4 217 irq 0xf0 = 0x7f 218 irq 0xf1 = 0x80 219 end 220 device pnp 2e.309 on # GPIO5 221 irq 0xf4 = 0xdf 222 irq 0xf5 = 0xd5 223 end 224 device pnp 2e.a on 225 # Power RAM in S3 and let the PCH 226 # handle power failure actions 227 irq 0xe4 = 0x70 228 # Set HWM reset source to LRESET# 229 irq 0xe7 = 0x01 230 end # ACPI 231 device pnp 2e.b on # HWM, LED 232 io 0x60 = 0x0290 233 io 0x62 = 0 234 irq 0x70 = 0 235 end 236 device pnp 2e.d off end # BCLK, WDT2, WDT_MEM 237 device pnp 2e.e off end # CIR wake-up 238 device pnp 2e.f off end # GPIO PP/OD 239 device pnp 2e.14 off end # SVID, Port 80 UART 240 device pnp 2e.16 off end # DS5 241 device pnp 2e.116 off end # DS3 242 device pnp 2e.316 on end # PCHDSW 243 device pnp 2e.416 off end # DSWWOPT 244 device pnp 2e.516 on end # DS3OPT 245 device pnp 2e.616 on end # DSDSS 246 device pnp 2e.716 off end # DSPU 247 end # chip superio/nuvoton/nct6791d 248 249 end # device pnp 2e.0 250 end # chip superio/common 251 252 chip drivers/pc80/tpm 253 device pnp 4e.0 on end # TPM module 254 end 255 end 256 device ref hda on 257 register "PchHdaVcType" = "Vc1" 258 end 259 device ref smbus on end 260 device ref fast_spi on end 261 end 262end 263