1/* SPDX-License-Identifier: GPL-2.0-only */ 2 3#include <southbridge/intel/i82371eb/i82371eb.h> 4 5#define SUPERIO_PNP_BASE 0x3F0 6#define SUPERIO_SHOW_UARTA 7#define SUPERIO_SHOW_UARTB 8#define SUPERIO_SHOW_FDC 9#define SUPERIO_SHOW_LPT 10 11#include <acpi/acpi.h> 12 13DefinitionBlock ( 14 "dsdt.aml", 15 "DSDT", 16 ACPI_DSDT_REV_2, 17 OEM_ID, 18 ACPI_TABLE_CREATOR, 19 1 20 ) 21{ 22 #include <acpi/dsdt_top.asl> 23 /* \_SB scope defining the main processor is generated in SSDT. */ 24 25 #include <arch/x86/acpi/post.asl> 26 27 /* 28 * Intel 82371EB (PIIX4E) datasheet, section 7.2.3, page 142 29 * 30 * 0: soft off/suspend to disk S5 31 * 1: suspend to ram S3 32 * 2: powered on suspend, context lost S2 33 * Note: 'context lost' means the CPU restarts at the reset 34 * vector 35 * 3: powered on suspend, CPU context lost S1 36 * Note: Looks like 'CPU context lost' does _not_ mean the 37 * CPU restarts at the reset vector. Most likely only 38 * caches are lost, so both 0x3 and 0x4 map to ACPI S1 39 * 4: powered on suspend, context maintained S1 40 * 5: working (clock control) S0 41 * 6: reserved 42 * 7: reserved 43 */ 44 Name (\_S0, Package () { 0x05, 0x05, 0x00, 0x00 }) 45 Name (\_S1, Package () { 0x03, 0x03, 0x00, 0x00 }) 46 Name (\_S5, Package () { 0x00, 0x00, 0x00, 0x00 }) 47 48 OperationRegion (GPOB, SystemIO, DEFAULT_PMBASE+DEVCTL, 0x10) 49 Field (GPOB, ByteAcc, NoLock, Preserve) 50 { 51 Offset (0x03), 52 TO12, 1, /* Device trap 12 */ 53 Offset (0x08), 54 FANM, 1, /* GPO0, meant for fan */ 55 Offset (0x09), 56 PLED, 1, /* GPO8, meant for power LED. Per PIIX4 datasheet */ 57 , 3, /* this goes low when power is cut from its core. */ 58 , 2, 59 , 16, 60 MSG0, 1 /* GPO30, message LED */ 61 } 62 63 /* Prepare To Sleep, Arg0 is target S-state */ 64 Method (\_PTS, 1, NotSerialized) 65 { 66 /* Disable fan, blink power LED, if not turning off */ 67 If (Arg0 != 0x05) 68 { 69 FANM = 0 70 PLED = 0 71 } 72 73 /* Arms SMI for device 12 */ 74 TO12 = 1 75 /* Put out a POST code */ 76 DBG0 = Arg0 | 0xF0 77 } 78 79 Method (\_WAK, 1, NotSerialized) 80 { 81 /* Re-enable fan, stop power led blinking */ 82 FANM = 1 83 PLED = 1 84 /* wake OK */ 85 Return(Package(0x02){0x00, 0x00}) 86 } 87 88 /* Root of the bus hierarchy */ 89 Scope (\_SB) 90 { 91 #include <southbridge/intel/i82371eb/acpi/intx.asl> 92 93 PCI_INTX_DEV(LNKA, \_SB.PCI0.PX40.PIRA, 1) 94 PCI_INTX_DEV(LNKB, \_SB.PCI0.PX40.PIRB, 2) 95 PCI_INTX_DEV(LNKC, \_SB.PCI0.PX40.PIRC, 3) 96 PCI_INTX_DEV(LNKD, \_SB.PCI0.PX40.PIRD, 4) 97 98 /* Top PCI device */ 99 Device (PCI0) 100 { 101 Name (_HID, EisaId ("PNP0A03")) 102 Name (_UID, 0x00) 103 Name (_BBN, 0x00) 104 105 /* PCI Routing Table */ 106 Name (_PRT, Package () { 107 Package (0x04) { 0x0001FFFF, 0, LNKA, 0 }, 108 Package (0x04) { 0x0001FFFF, 1, LNKB, 0 }, 109 Package (0x04) { 0x0001FFFF, 2, LNKC, 0 }, 110 Package (0x04) { 0x0001FFFF, 3, LNKD, 0 }, 111 112 Package (0x04) { 0x0004FFFF, 0, LNKA, 0 }, 113 Package (0x04) { 0x0004FFFF, 1, LNKB, 0 }, 114 Package (0x04) { 0x0004FFFF, 2, LNKC, 0 }, 115 Package (0x04) { 0x0004FFFF, 3, LNKD, 0 }, 116 117#if CONFIG(BOARD_ASUS_P2B_LS) 118 Package (0x04) { 0x0006FFFF, 0, LNKD, 0 }, 119 Package (0x04) { 0x0006FFFF, 1, LNKA, 0 }, 120 Package (0x04) { 0x0006FFFF, 2, LNKB, 0 }, 121 Package (0x04) { 0x0006FFFF, 3, LNKC, 0 }, 122#endif 123 Package (0x04) { 0x0009FFFF, 0, LNKD, 0 }, 124 Package (0x04) { 0x0009FFFF, 1, LNKA, 0 }, 125 Package (0x04) { 0x0009FFFF, 2, LNKB, 0 }, 126 Package (0x04) { 0x0009FFFF, 3, LNKC, 0 }, 127 128 Package (0x04) { 0x000AFFFF, 0, LNKC, 0 }, 129 Package (0x04) { 0x000AFFFF, 1, LNKD, 0 }, 130 Package (0x04) { 0x000AFFFF, 2, LNKA, 0 }, 131 Package (0x04) { 0x000AFFFF, 3, LNKB, 0 }, 132 133#if CONFIG(BOARD_ASUS_P2B_LS) 134 Package (0x04) { 0x0007FFFF, 0, LNKC, 0 }, 135 Package (0x04) { 0x0007FFFF, 1, LNKD, 0 }, 136 Package (0x04) { 0x0007FFFF, 2, LNKA, 0 }, 137 Package (0x04) { 0x0007FFFF, 3, LNKB, 0 }, 138#endif 139 Package (0x04) { 0x000BFFFF, 0, LNKB, 0 }, 140 Package (0x04) { 0x000BFFFF, 1, LNKC, 0 }, 141 Package (0x04) { 0x000BFFFF, 2, LNKD, 0 }, 142 Package (0x04) { 0x000BFFFF, 3, LNKA, 0 }, 143 144 Package (0x04) { 0x000CFFFF, 0, LNKA, 0 }, 145 Package (0x04) { 0x000CFFFF, 1, LNKB, 0 }, 146 Package (0x04) { 0x000CFFFF, 2, LNKC, 0 }, 147 Package (0x04) { 0x000CFFFF, 3, LNKD, 0 }, 148 149#if CONFIG(BOARD_ASUS_P3B_F) 150 Package (0x04) { 0x000DFFFF, 0, LNKD, 0 }, 151 Package (0x04) { 0x000DFFFF, 1, LNKA, 0 }, 152 Package (0x04) { 0x000DFFFF, 2, LNKB, 0 }, 153 Package (0x04) { 0x000DFFFF, 3, LNKC, 0 }, 154 155 Package (0x04) { 0x000EFFFF, 0, LNKC, 0 }, 156 Package (0x04) { 0x000EFFFF, 1, LNKD, 0 }, 157 Package (0x04) { 0x000EFFFF, 2, LNKA, 0 }, 158 Package (0x04) { 0x000EFFFF, 3, LNKB, 0 }, 159#endif 160 }) 161 #include <northbridge/intel/i440bx/acpi/sb_pci0_crs.asl> 162 #include <southbridge/intel/i82371eb/acpi/isabridge.asl> 163 164 #include <southbridge/intel/i82371eb/acpi/i82371eb.asl> 165 #include <superio/winbond/w83977tf/acpi/superio.asl> 166 } 167 } 168 169 /* ACPI Message */ 170 Scope (\_SI) 171 { 172 Method (_MSG, 1, NotSerialized) 173 { 174 If (Arg0 == 0) 175 { 176 MSG0 = 1 177 } 178 Else 179 { 180 MSG0 = 0 181 } 182 } 183 } 184} 185