1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2
3 #include <cbmem.h>
4 #include <symbols.h>
5 #include <device/device.h>
6 #include <bootmem.h>
7 #include <mainboard/addressmap.h>
8
bootmem_platform_add_ranges(void)9 void bootmem_platform_add_ranges(void)
10 {
11 bootmem_add_range((uintptr_t)_bl31, REGION_SIZE(bl31), BM_MEM_BL31);
12 }
13
mainboard_enable(struct device * dev)14 static void mainboard_enable(struct device *dev)
15 {
16 }
17
18 struct chip_operations mainboard_ops = {
19 .enable_dev = mainboard_enable,
20 };
21
22 struct chip_operations mainboard_emulation_qemu_aarch64_ops = { };
23
qemu_aarch64_domain_read_resources(struct device * dev)24 static void qemu_aarch64_domain_read_resources(struct device *dev)
25 {
26 struct resource *res;
27 int index = 0;
28 /* Initialize the system-wide I/O space constraints. */
29 res = new_resource(dev, index++);
30 res->limit = 0xffff;
31 res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED;
32
33 /* Initialize the system-wide memory resources constraints. */
34 res = new_resource(dev, index++);
35 res->base = VIRT_PCIE_LOW_MMIO_BASE;
36 res->limit = VIRT_PCIE_LOW_MMIO_LIMIT;
37 res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED;
38
39 res = new_resource(dev, index++);
40 res->base = VIRT_PCIE_HIGH_MMIO_BASE;
41 res->limit = VIRT_PCIE_HIGH_MMIO_LIMIT;
42 res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED;
43
44 mmio_range(dev, index++, VIRT_PCIE_ECAM_BASE, VIRT_PCIE_ECAM_SIZE);
45
46 ram_from_to(dev, index++, (uintptr_t)_dram, cbmem_top());
47 }
48
49 struct device_operations qemu_aarch64_pci_domain_ops = {
50 .read_resources = qemu_aarch64_domain_read_resources,
51 .set_resources = pci_domain_set_resources,
52 .scan_bus = pci_host_bridge_scan_bus,
53 };
54