1 /* SPDX-License-Identifier: GPL-2.0-only */
2
3 #define __SIMPLE_DEVICE__
4
5 #include <assert.h>
6 #include <console/console.h>
7 #include <cpu/x86/smm.h>
8 #include <device/pci_ops.h>
9 #include <mainboard/emulation/qemu-i440fx/memory.h>
10 #include <mainboard/emulation/qemu-i440fx/fw_cfg.h>
11 #include <cpu/intel/smm_reloc.h>
12
13 #include "q35.h"
14
encode_pciexbar_length(void)15 static uint32_t encode_pciexbar_length(void)
16 {
17 switch (CONFIG_ECAM_MMCONF_BUS_NUMBER) {
18 case 256: return 0 << 1;
19 case 128: return 1 << 1;
20 case 64: return 2 << 1;
21 default: return dead_code_t(uint32_t);
22 }
23 }
24
make_pciexbar(void)25 uint32_t make_pciexbar(void)
26 {
27 return CONFIG_ECAM_MMCONF_BASE_ADDRESS | encode_pciexbar_length() | 1;
28 }
29
30 /* Check that MCFG is active. If it's not, QEMU was started for machine PC */
mainboard_machine_check(void)31 void mainboard_machine_check(void)
32 {
33 if (pci_read_config32(HOST_BRIDGE, D0F0_PCIEXBAR_LO) != make_pciexbar())
34 die("You must run qemu for machine Q35 (-M q35)");
35 }
36
37 /* QEMU-specific register */
38 #define EXT_TSEG_MBYTES 0x50
39 #define SMRAMC 0x9d
40 #define C_BASE_SEG ((0 << 2) | (1 << 1) | (0 << 0))
41 #define G_SMRAME (1 << 3)
42 #define D_LCK (1 << 4)
43 #define D_CLS (1 << 5)
44 #define D_OPEN (1 << 6)
45 #define ESMRAMC 0x9e
46 #define T_EN (1 << 0)
47 #define TSEG_SZ_MASK (3 << 1)
48 #define H_SMRAME (1 << 7)
49
50 /* Decodes TSEG region size to bytes. */
decode_tseg_size(u8 esmramc)51 static size_t decode_tseg_size(u8 esmramc)
52 {
53 /* If we intent to enable TSEG, fake it always enabled. */
54 if (CONFIG(SMM_TSEG))
55 esmramc |= T_EN;
56
57 if (!(esmramc & T_EN))
58 return 0;
59
60 switch ((esmramc & TSEG_SZ_MASK) >> 1) {
61 case 0:
62 return 1 * MiB;
63 case 1:
64 return 2 * MiB;
65 case 2:
66 return 8 * MiB;
67 default:
68 return pci_read_config16(HOST_BRIDGE, EXT_TSEG_MBYTES) * MiB;
69 }
70 }
71
smm_region(uintptr_t * start,size_t * size)72 void smm_region(uintptr_t *start, size_t *size)
73 {
74 uint8_t esmramc = pci_read_config8(HOST_BRIDGE, ESMRAMC);
75
76 *size = decode_tseg_size(esmramc);
77 *start = qemu_get_memory_size() * KiB - *size;
78 printk(BIOS_SPEW, "SMM_BASE: 0x%08lx, SMM_SIZE: %zu MiB\n", *start, *size / MiB);
79 }
80
smm_open(void)81 void smm_open(void)
82 {
83 /* Set D_OPEN */
84 if (CONFIG(SMM_ASEG))
85 pci_write_config8(HOST_BRIDGE, SMRAMC, D_OPEN | G_SMRAME | C_BASE_SEG);
86
87 if (CONFIG(SMM_TSEG))
88 pci_and_config8(HOST_BRIDGE, ESMRAMC, ~T_EN);
89 }
90
smm_close(void)91 void smm_close(void)
92 {
93 /* Clear D_OPEN */
94 if (CONFIG(SMM_ASEG))
95 pci_write_config8(HOST_BRIDGE, SMRAMC, G_SMRAME | C_BASE_SEG);
96
97 if (CONFIG(SMM_TSEG))
98 pci_or_config8(HOST_BRIDGE, ESMRAMC, T_EN);
99 }
100
smm_lock(void)101 void smm_lock(void)
102 {
103 /*
104 * LOCK the SMM memory window and enable normal SMM.
105 * After running this function, only a full reset can
106 * make the SMM registers writable again.
107 */
108 printk(BIOS_DEBUG, "Locking SMM.\n");
109
110 pci_write_config8(HOST_BRIDGE, SMRAMC, D_LCK | G_SMRAME | C_BASE_SEG);
111 }
112