1chip soc/intel/skylake 2 3 register "deep_s5_enable_ac" = "0" 4 register "deep_s5_enable_dc" = "0" 5 register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN" 6 7 # GPE configuration 8 # Note that GPE events called out in ASL code rely on this 9 # route. i.e. If this route changes then the affected GPE 10 # offset bits also need to be changed. 11 register "gpe0_dw0" = "GPP_C" 12 register "gpe0_dw1" = "GPP_D" 13 register "gpe0_dw2" = "GPP_E" 14 15 # Set the fixed lpc ranges 16 # enable COMA at 3f8 and COMB at 3e8 (instead of the default 2f8) 17 # enable the embedded controller 18 register "lpc_iod" = "0x0070" 19 register "lpc_ioe" = "LPC_IOE_COMA_EN | LPC_IOE_COMB_EN | LPC_IOE_EC_62_66" 20 21 # "Intel SpeedStep Technology" 22 register "eist_enable" = "1" 23 24 # DPTF 25 register "dptf_enable" = "1" 26 27 # FSP Configuration 28 register "ScsEmmcHs400Enabled" = "1" 29 register "SkipExtGfxScan" = "1" 30 register "SaGv" = "SaGv_Enabled" 31 32 # Enabling SLP_S3#, SLP_S4#, SLP_SUS and SLP_A Stretch 33 # SLP_S3 Minimum Assertion Width. Values 0: 60us, 1: 1ms, 2: 50ms, 3: 2s 34 register "PmConfigSlpS3MinAssert" = "2" 35 36 # SLP_S4 Minimum Assertion Width. Values 0: default, 1: 1s, 2: 2s, 3: 3s, 4: 4s 37 register "PmConfigSlpS4MinAssert" = "4" 38 39 # SLP_SUS Minimum Assertion Width. Values 0: 0ms, 1: 500ms, 2: 1s, 3: 4s 40 register "PmConfigSlpSusMinAssert" = "3" 41 42 # SLP_A Minimum Assertion Width. Values 0: 0ms, 1: 4s, 2: 98ms, 3: 2s 43 register "PmConfigSlpAMinAssert" = "3" 44 45 # VR Settings Configuration for 4 Domains 46 #+----------------+-------+-------+-------+-------+ 47 #| Domain/Setting | SA | IA | GTUS | GTS | 48 #+----------------+-------+-------+-------+-------+ 49 #| Psi1Threshold | 20A | 20A | 20A | 20A | 50 #| Psi2Threshold | 5A | 5A | 5A | 5A | 51 #| Psi3Threshold | 1A | 1A | 1A | 1A | 52 #| Psi3Enable | 1 | 1 | 1 | 1 | 53 #| Psi4Enable | 1 | 1 | 1 | 1 | 54 #| ImonSlope | 0 | 0 | 0 | 0 | 55 #| ImonOffset | 0 | 0 | 0 | 0 | 56 #| IccMax | 5.1A | 32A | 35A | 31A | 57 #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | 58 #+----------------+-------+-------+-------+-------+ 59 register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ 60 .vr_config_enable = 1, 61 .psi1threshold = VR_CFG_AMP(20), 62 .psi2threshold = VR_CFG_AMP(5), 63 .psi3threshold = VR_CFG_AMP(1), 64 .psi3enable = 1, 65 .psi4enable = 1, 66 .imon_slope = 0, 67 .imon_offset = 0, 68 .icc_max = VR_CFG_AMP(5.1), 69 .voltage_limit = 1520 70 }" 71 72 register "domain_vr_config[VR_IA_CORE]" = "{ 73 .vr_config_enable = 1, 74 .psi1threshold = VR_CFG_AMP(20), 75 .psi2threshold = VR_CFG_AMP(5), 76 .psi3threshold = VR_CFG_AMP(1), 77 .psi3enable = 1, 78 .psi4enable = 1, 79 .imon_slope = 0, 80 .imon_offset = 0, 81 .icc_max = VR_CFG_AMP(32), 82 .voltage_limit = 1520 83 }" 84 85 register "domain_vr_config[VR_GT_UNSLICED]" = "{ 86 .vr_config_enable = 1, 87 .psi1threshold = VR_CFG_AMP(20), 88 .psi2threshold = VR_CFG_AMP(5), 89 .psi3threshold = VR_CFG_AMP(1), 90 .psi3enable = 1, 91 .psi4enable = 1, 92 .imon_slope = 0, 93 .imon_offset = 0, 94 .icc_max = VR_CFG_AMP(35), 95 .voltage_limit = 1520 96 }" 97 98 register "domain_vr_config[VR_GT_SLICED]" = "{ 99 .vr_config_enable = 1, 100 .psi1threshold = VR_CFG_AMP(20), 101 .psi2threshold = VR_CFG_AMP(5), 102 .psi3threshold = VR_CFG_AMP(1), 103 .psi3enable = 1, 104 .psi4enable = 1, 105 .imon_slope = 0, 106 .imon_offset = 0, 107 .icc_max = VR_CFG_AMP(31), 108 .voltage_limit = 1520 109 }" 110 111 # Send an extra VR mailbox command for the PS4 exit issue 112 register "SendVrMbxCmd" = "2" 113 114 # Must leave UART0 enabled or SD/eMMC will not work as PCI 115 register "SerialIoDevMode" = "{ 116 [PchSerialIoIndexI2C0] = PchSerialIoDisabled, 117 [PchSerialIoIndexI2C1] = PchSerialIoDisabled, 118 [PchSerialIoIndexI2C2] = PchSerialIoDisabled, 119 [PchSerialIoIndexI2C3] = PchSerialIoDisabled, 120 [PchSerialIoIndexI2C4] = PchSerialIoDisabled, 121 [PchSerialIoIndexI2C5] = PchSerialIoDisabled, 122 [PchSerialIoIndexSpi0] = PchSerialIoDisabled, 123 [PchSerialIoIndexSpi1] = PchSerialIoDisabled, 124 [PchSerialIoIndexUart0] = PchSerialIoPci, 125 [PchSerialIoIndexUart1] = PchSerialIoDisabled, 126 [PchSerialIoIndexUart2] = PchSerialIoDisabled, 127 }" 128 129 device domain 0 on 130 device ref igpu on end 131 device ref sa_thermal on end 132 device ref gmm on end 133 device ref south_xhci on 134 register "usb2_ports" = "{ 135 [0] = USB2_PORT_TYPE_C(OC_SKIP), /* USB-C Port 2 */ 136 [1] = USB2_PORT_MID(OC1), /* USB3_TYPE-A Port 1 */ 137 [2] = USB2_PORT_MID(OC1), /* USB3_TYPE-A Port 2 */ 138 [3] = USB2_PORT_TYPE_C(OC_SKIP), /* USB-C Port 1 */ 139 [4] = USB2_PORT_SHORT(OC_SKIP), /* M2 Port */ 140 [6] = USB2_PORT_SHORT(OC_SKIP), /* Audio board */ 141 }" 142 143 register "usb3_ports" = "{ 144 [0] = USB3_PORT_DEFAULT(OC_SKIP), /* USB-C Port 2 */ 145 [1] = USB3_PORT_DEFAULT(OC_SKIP), /* USB3_TYPE-A Port 1 */ 146 [2] = USB3_PORT_DEFAULT(OC_SKIP), /* USB3_TYPE-A Port 2 */ 147 [3] = USB3_PORT_DEFAULT(OC_SKIP), /* USB-C Port 1 */ 148 }" 149 end 150 device ref south_xdci on end 151 device ref thermal on end 152 device ref heci1 on end 153 device ref sata on 154 register "SataSalpSupport" = "1" 155 register "SataPortsEnable[0]" = "1" 156 end 157 device ref pcie_rp3 on 158 # x1 baseboard WWAN 159 # PCIE Port 3 x1 -> Module x1 : Mapped to PCIe 2 on the baseboard 160 register "PcieRpEnable[2]" = "1" 161 register "PcieRpClkReqSupport[2]" = "0" 162 register "PcieRpMaxPayload[2]" = "RpMaxPayload_256" 163 register "PcieRpLtrEnable[2]" = "1" 164 register "PcieRpAdvancedErrorReporting[2]" = "1" 165 register "pcie_rp_aspm[2]" = "AspmDisabled" 166 end 167 device ref pcie_rp6 on 168 # x1 baseboard i210 169 # PCIE Port 6 x1 -> BASEBOARD x1 i210 : Mapped to PCIe 4 on the baseboard 170 register "PcieRpEnable[5]" = "1" 171 register "PcieRpClkReqSupport[5]" = "0" 172 register "PcieRpMaxPayload[5]" = "RpMaxPayload_256" 173 register "PcieRpLtrEnable[5]" = "1" 174 register "PcieRpAdvancedErrorReporting[5]" = "1" 175 register "pcie_rp_aspm[5]" = "AspmDisabled" 176 end 177 device ref pcie_rp9 on 178 # x4 FPGA 179 # PCIE Port 9 x4 -> BASEBOARD PEG0-3 FPGA 180 register "PcieRpEnable[8]" = "1" 181 register "PcieRpClkReqSupport[8]" = "0" 182 register "PcieRpHotPlug[8]" = "1" 183 register "PcieRpMaxPayload[8]" = "RpMaxPayload_256" 184 register "PcieRpLtrEnable[8]" = "1" 185 register "PcieRpAdvancedErrorReporting[8]" = "1" 186 register "pcie_rp_aspm[8]" = "AspmDisabled" 187 end 188 device ref uart0 on end 189 device ref emmc on end 190 device ref lpc_espi on 191 register "serirq_mode" = "SERIRQ_CONTINUOUS" 192 193 # CPLD host command ranges are in 0x280-0x2BF 194 # EC PNP registers are at 0x6e and 0x6f 195 register "gen1_dec" = "0x003c0281" 196 register "gen3_dec" = "0x0004006d" 197 198 chip drivers/pc80/tpm 199 device pnp 0c31.0 on end 200 end 201 end 202 device ref hda on end # for HDMI only 203 device ref smbus on end 204 device ref fast_spi on end 205 device ref gbe on end 206 end 207end 208