1FLASH@0xfe000000 0x2000000 { 2 SI_ALL@0x0 0x500000 { 3 SI_DESC@0x0 0x1000 4 SI_ME@0x1000 0x4ff000 5 } 6 SI_BIOS@0x500000 0x1b00000 { 7 # Place RW_LEGACY at the start of BIOS region such that the rest 8 # of BIOS regions start at 16MiB boundary. Since this is a 32MiB 9 # SPI flash only the top 16MiB actually gets memory mapped. 10 RW_LEGACY(CBFS)@0x0 0xf00000 11 RW_SECTION_A@0xf00000 0x3e0000 { 12 VBLOCK_A@0x0 0x10000 13 FW_MAIN_A(CBFS)@0x10000 0x3cffc0 14 RW_FWID_A@0x3dffc0 0x40 15 } 16 RW_SECTION_B@0x12e0000 0x3e0000 { 17 VBLOCK_B@0x0 0x10000 18 FW_MAIN_B(CBFS)@0x10000 0x3cffc0 19 RW_FWID_B@0x3dffc0 0x40 20 } 21 RW_MISC@0x16c0000 0x40000 { 22 UNIFIED_MRC_CACHE(PRESERVE)@0x0 0x30000 { 23 RECOVERY_MRC_CACHE@0x0 0x10000 24 RW_MRC_CACHE@0x10000 0x20000 25 } 26 RW_ELOG(PRESERVE)@0x30000 0x4000 27 RW_SHARED@0x34000 0x4000 { 28 SHARED_DATA@0x0 0x2000 29 VBLOCK_DEV@0x2000 0x2000 30 } 31 RW_VPD(PRESERVE)@0x38000 0x2000 32 RW_NVRAM(PRESERVE)@0x3a000 0x6000 33 } 34 # Make WP_RO region align with SPI vendor 35 # memory protected range specification. 36 WP_RO@0x1700000 0x400000 { 37 RO_VPD(PRESERVE)@0x0 0x4000 38 RO_SECTION@0x4000 0x3fc000 { 39 FMAP@0x0 0x800 40 RO_FRID@0x800 0x40 41 RO_FRID_PAD@0x840 0x7c0 42 GBB@0x1000 0x3000 43 COREBOOT(CBFS)@0x4000 0x3f8000 44 } 45 } 46 } 47} 48