1 /* SPDX-License-Identifier: GPL-2.0-only */
2
3 #include <soc/amd/stoneyridge/chip.h>
4 #include <amdblocks/agesawrapper.h>
5 #include <gpio.h>
6 #include <console/console.h>
7 #include <soc/pci_devs.h>
8
9 #define DIMMS_PER_CHANNEL 1
10 #if DIMMS_PER_CHANNEL > MAX_DIMMS_PER_CH
11 #error "Too many DIMM sockets defined for the mainboard"
12 #endif
13
14 static const PSO_ENTRY DDR4PlatformMemoryConfiguration[] = {
15 DRAM_TECHNOLOGY(ANY_SOCKET, DDR4_TECHNOLOGY),
16 NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, ANY_CHANNEL, DIMMS_PER_CHANNEL),
17 NUMBER_OF_CHANNELS_SUPPORTED(ANY_SOCKET, MAX_DRAM_CH),
18 MOTHER_BOARD_LAYERS(LAYERS_6),
19 MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL,
20 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00),
21 CKE_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0xff, 0xff, 0xff, 0xff),
22 ODT_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0xff, 0xff, 0xff, 0xff),
23 CS_TRI_MAP(ANY_SOCKET, ANY_CHANNEL,
24 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00),
25 PSO_END
26 };
27 /* Liara-specific 2T memory configuration */
28 static const PSO_ENTRY DDR4_2T_MemoryConfiguration[] = {
29 DRAM_TECHNOLOGY(ANY_SOCKET, DDR4_TECHNOLOGY),
30 NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, ANY_CHANNEL, DIMMS_PER_CHANNEL),
31 NUMBER_OF_CHANNELS_SUPPORTED(ANY_SOCKET, MAX_DRAM_CH),
32 MOTHER_BOARD_LAYERS(LAYERS_6),
33 MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL,
34 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00),
35 CKE_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0xff, 0xff, 0xff, 0xff),
36 ODT_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0xff, 0xff, 0xff, 0xff),
37 CS_TRI_MAP(ANY_SOCKET, ANY_CHANNEL,
38 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00),
39 TBLDRV_CONFIG_TO_OVERRIDE(DIMMS_PER_CHANNEL, ANY_SPEED, VOLT_ANY_,
40 ANY_),
41 TBLDRV_CONFIG_ENTRY_SLOWACCMODE(1),
42 PSO_END
43 };
44
OemPostParams(AMD_POST_PARAMS * PostParams)45 void OemPostParams(AMD_POST_PARAMS *PostParams)
46 {
47 if (CONFIG(BOARD_GOOGLE_LIARA) || CONFIG(BOARD_GOOGLE_TREEYA))
48 PostParams->MemConfig.PlatformMemoryConfiguration =
49 (PSO_ENTRY *)DDR4_2T_MemoryConfiguration;
50 else
51 PostParams->MemConfig.PlatformMemoryConfiguration =
52 (PSO_ENTRY *)DDR4PlatformMemoryConfiguration;
53 /*
54 * Bank interleaving is enabled by default in AGESA. However, from AMD's
55 * explanation, bank interleaving is really chip select interleave,
56 * requiring 2 chip select arriving to the DIMM (rank interleaving). As
57 * both kahlee and grunt are hardware limited to a single chip select
58 * arriving at the DIMM, interleave will not work. This causes AGESA to
59 * throw a warning. To avoid the warning, interleaving needs to be
60 * disabled.
61 */
62 PostParams->MemConfig.EnableBankIntlv = FALSE;
63 }
64
set_board_env_params(GNB_ENV_CONFIGURATION * params)65 void set_board_env_params(GNB_ENV_CONFIGURATION *params)
66 {
67 const struct soc_amd_stoneyridge_config *cfg;
68 const struct device *dev = pcidev_path_on_root(GNB_DEVFN);
69 if (!dev || !dev->chip_info) {
70 printk(BIOS_WARNING, "Cannot find SoC devicetree config\n");
71 return;
72 }
73 cfg = dev->chip_info;
74 if (cfg->lvds_poseq_blon_to_varybl && cfg->lvds_poseq_varybl_to_blon) {
75 /*
76 * GPIO 133 - Backlight enable (active low)
77 * Pass control of the backlight to the video BIOS
78 */
79 gpio_set(GPIO_133, 0);
80 printk(BIOS_INFO, "Change panel init timing\n");
81 params->LvdsPowerOnSeqVaryBlToBlon =
82 cfg->lvds_poseq_varybl_to_blon;
83 params->LvdsPowerOnSeqBlonToVaryBl =
84 cfg->lvds_poseq_blon_to_varybl;
85 printk(BIOS_INFO, "LvdsPowerOnSeqVaryBlToBlon: %dms\n",
86 (params->LvdsPowerOnSeqVaryBlToBlon)*4);
87 printk(BIOS_INFO, "LvdsPowerOnSeqBlonToVaryBl: %dms\n",
88 (params->LvdsPowerOnSeqBlonToVaryBl)*4);
89 }
90 params->EDPv1_4VSMode = EDP_VS_HIGH_VDIFF_MODE;
91 }
92