1 /* SPDX-License-Identifier: GPL-2.0-only */
2
3 #include <bootmode.h>
4 #include <boot/coreboot_tables.h>
5 #include <southbridge/intel/bd82x6x/pch.h>
6 #include <southbridge/intel/common/gpio.h>
7 #include <types.h>
8 #include <vendorcode/google/chromeos/chromeos.h>
9 #include "onboard.h"
10
11 #define GPIO_EC_IN_RW 21
12
fill_lb_gpios(struct lb_gpios * gpios)13 void fill_lb_gpios(struct lb_gpios *gpios)
14 {
15 struct lb_gpio chromeos_gpios[] = {
16 /* Lid: the "switch" comes from the EC */
17 {-1, ACTIVE_HIGH, get_lid_switch(), "lid"},
18
19 /* Power Button: hard-coded as not pressed; we'll detect later
20 * presses via SMI. */
21 {-1, ACTIVE_HIGH, 0, "power"},
22
23 /* Did we load the VGA Option ROM? */
24 /* -1 indicates that this is a pseudo GPIO */
25 {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"},
26 };
27 lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios));
28 }
29
get_write_protect_state(void)30 int get_write_protect_state(void)
31 {
32 return get_gpio(GPIO_SPI_WP);
33 }
34
35 static const struct cros_gpio cros_gpios[] = {
36 CROS_GPIO_REC_AL(GPIO_REC_MODE, CROS_GPIO_DEVICE_NAME),
37 CROS_GPIO_WP_AH(GPIO_SPI_WP, CROS_GPIO_DEVICE_NAME),
38 };
39 DECLARE_CROS_GPIOS(cros_gpios);
40
get_ec_is_trusted(void)41 int get_ec_is_trusted(void)
42 {
43 /* EC is trusted if not in RW. */
44 return !get_gpio(GPIO_EC_IN_RW);
45 }
46