1chip northbridge/intel/sandybridge 2 # IGD Displays 3 register "gfx" = "GMA_STATIC_DISPLAYS(0)" 4 5 # Enable DisplayPort Hotplug with 6ms pulse 6 register "gpu_dp_d_hotplug" = "0x06" 7 8 # Enable Panel as eDP and configure power delays 9 register "gpu_panel_port_select" = "PANEL_PORT_DP_A" 10 register "gpu_panel_power_cycle_delay" = "6" # 500ms 11 register "gpu_panel_power_up_delay" = "2000" # 200ms 12 register "gpu_panel_power_down_delay" = "500" # 50ms 13 register "gpu_panel_power_backlight_on_delay" = "2000" # 200ms 14 register "gpu_panel_power_backlight_off_delay" = "2000" # 200ms 15 16 # Set backlight PWM values for eDP 17 register "gpu_cpu_backlight" = "0x00000200" 18 register "gpu_pch_backlight" = "0x04000000" 19 20 register "ec_present" = "1" 21 register "ddr3lv_support" = "1" 22 # FIXME: Native raminit requires reduced max clock 23 register "max_mem_clock_mhz" = "CONFIG(USE_NATIVE_RAMINIT) ? 666 : 800" 24 25 device domain 0 on 26 subsystemid 0x1ae0 0xc000 inherit 27 device ref host_bridge on end # host bridge 28 device ref igd on end # vga controller 29 30 chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH 31 # GPI routing 32 # 0 No effect (default) 33 # 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set) 34 # 2 SCI (if corresponding GPIO_EN bit is also set) 35 register "alt_gp_smi_en" = "0x0100" 36 register "gpi7_routing" = "2" 37 register "gpi8_routing" = "1" 38 39 register "sata_port_map" = "0x1" 40 41 register "sata_port0_gen3_tx" = "0x00880a7f" 42 43 # EC range is 0x800-0x9ff 44 # Please note: you MUST not change this unless 45 # you also change romstage.c:pch_enable_lpc 46 register "gen1_dec" = "0x00fc0801" 47 register "gen2_dec" = "0x00fc0901" 48 49 # Enable zero-based linear PCIe root port functions 50 register "pcie_port_coalesce" = "true" 51 52 register "usb_port_config" = "{ 53 { 0, 0, -1 }, /* P0: Empty */ 54 { 1, 0, 0 }, /* P1: Left USB 1 (OC0) */ 55 { 1, 0, 1 }, /* P2: Left USB 2 (OC1) */ 56 { 1, 0, -1 }, /* P3: SDCARD (no OC) */ 57 { 0, 0, -1 }, /* P4: Empty */ 58 { 1, 0, -1 }, /* P5: WWAN (no OC) */ 59 { 0, 0, -1 }, /* P6: Empty */ 60 { 0, 0, -1 }, /* P7: Empty */ 61 { 1, 0, -1 }, /* P8: Camera (no OC) */ 62 { 1, 0, -1 }, /* P9: Bluetooth (no OC) */ 63 { 0, 0, -1 }, /* P10: Empty */ 64 { 0, 0, -1 }, /* P11: Empty */ 65 { 0, 0, -1 }, /* P12: Empty */ 66 { 0, 0, -1 }, /* P13: Empty */ 67 }" 68 69 device ref mei1 on end # Management Engine Interface 1 70 device ref mei2 off end # Management Engine Interface 2 71 device ref me_ide_r off end # Management Engine IDE-R 72 device ref me_kt off end # Management Engine KT 73 device ref gbe off end # Intel Gigabit Ethernet 74 device ref ehci2 on end # USB2 EHCI #2 75 device ref hda on end # High Definition Audio 76 device ref pcie_rp1 off end # PCIe Port #1 (WLAN remapped) 77 device ref pcie_rp2 off end # PCIe Port #2 78 device ref pcie_rp3 on end # PCIe Port #3 (WLAN actual) 79 device ref pcie_rp4 off end # PCIe Port #4 80 device ref pcie_rp5 off end # PCIe Port #5 81 device ref pcie_rp6 off end # PCIe Port #6 82 device ref pcie_rp7 off end # PCIe Port #7 83 device ref pcie_rp8 off end # PCIe Port #8 84 device ref ehci1 on end # USB2 EHCI #1 85 device ref pci_bridge off end # PCI bridge 86 device ref lpc on 87 chip drivers/pc80/tpm 88 device pnp 0c31.0 on end 89 end 90 chip ec/google/chromeec 91 # We only have one init function that 92 # we need to call to initialize the 93 # keyboard part of the EC. 94 device pnp ff.1 on # dummy address 95 end 96 end 97 end # LPC bridge 98 device ref sata1 on end # SATA Controller 1 99 device ref smbus on end # SMBus 100 device ref sata2 off end # SATA Controller 2 101 device ref thermal on end # Thermal 102 end 103 end 104end 105