1 /* SPDX-License-Identifier: GPL-2.0-only */
2
3 #include <bootmode.h>
4 #include <boot/coreboot_tables.h>
5 #include <soc/gpio.h>
6 #include <types.h>
7 #include <vendorcode/google/chromeos/chromeos.h>
8
9 /* The WP status pin lives on GPIO_SSUS_6 which is pad 36 in the SUS well. */
10 #define WP_STATUS_PAD 36
11
12 /* The EC_IN_RW lives on SCGPIO59 */
13 #define EC_IN_RW_PAD 59
14
fill_lb_gpios(struct lb_gpios * gpios)15 void fill_lb_gpios(struct lb_gpios *gpios)
16 {
17 struct lb_gpio chromeos_gpios[] = {
18 {-1, ACTIVE_HIGH, get_lid_switch(), "lid"},
19 {-1, ACTIVE_HIGH, 0, "power"},
20 {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"},
21 };
22 lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios));
23 }
24
get_write_protect_state(void)25 int get_write_protect_state(void)
26 {
27 /*
28 * The vboot loader queries this function in romstage. The GPIOs have
29 * not been set up yet as that configuration is done in ramstage. The
30 * hardware defaults to an input but there is a 20K pulldown. Externally
31 * there is a 10K pullup. Disable the internal pull in romstage so that
32 * there isn't any ambiguity in the reading.
33 */
34 if (ENV_ROMSTAGE_OR_BEFORE)
35 ssus_disable_internal_pull(WP_STATUS_PAD);
36
37 /* WP is enabled when the pin is reading high. */
38 return ssus_get_gpio(WP_STATUS_PAD);
39 }
40
41 static const struct cros_gpio cros_gpios[] = {
42 CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME),
43 CROS_GPIO_WP_AH(0x2006, CROS_GPIO_DEVICE_NAME),
44 };
45 DECLARE_CROS_GPIOS(cros_gpios);
46
get_ec_is_trusted(void)47 int get_ec_is_trusted(void)
48 {
49 /* EC is trusted if not in RW. */
50 return !score_get_gpio(EC_IN_RW_PAD);
51 }
52