1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 3 #include <soc/irq.h> 4 #include <soc/pci_devs.h> 5 #include <soc/pm.h> 6 7 #define PCI_DEV_PIRQ_ROUTES \ 8 PCI_DEV_PIRQ_ROUTE(GFX_DEV, A, B, C, D), \ 9 PCI_DEV_PIRQ_ROUTE(SDIO_DEV, A, B, C, D), \ 10 PCI_DEV_PIRQ_ROUTE(SD_DEV, C, D, E, F), \ 11 PCI_DEV_PIRQ_ROUTE(SATA_DEV, A, B, C, D), \ 12 PCI_DEV_PIRQ_ROUTE(XHCI_DEV, A, B, C, D), \ 13 PCI_DEV_PIRQ_ROUTE(LPE_DEV, A, B, C, D), \ 14 PCI_DEV_PIRQ_ROUTE(MMC45_DEV, D, E, F, G), \ 15 PCI_DEV_PIRQ_ROUTE(SIO1_DEV, A, B, C, D), \ 16 PCI_DEV_PIRQ_ROUTE(TXE_DEV, A, B, C, D), \ 17 PCI_DEV_PIRQ_ROUTE(HDA_DEV, A, B, C, D), \ 18 PCI_DEV_PIRQ_ROUTE(PCIE_DEV, A, B, C, D), \ 19 PCI_DEV_PIRQ_ROUTE(EHCI_DEV, A, B, C, D), \ 20 PCI_DEV_PIRQ_ROUTE(SIO2_DEV, B, C, D, E), \ 21 PCI_DEV_PIRQ_ROUTE(PCU_DEV, A, B, C, D) 22 23 #define PIRQ_PIC_ROUTES \ 24 PIRQ_PIC(A, DISABLE), \ 25 PIRQ_PIC(B, DISABLE), \ 26 PIRQ_PIC(C, DISABLE), \ 27 PIRQ_PIC(D, DISABLE), \ 28 PIRQ_PIC(E, DISABLE), \ 29 PIRQ_PIC(F, DISABLE), \ 30 PIRQ_PIC(G, DISABLE), \ 31 PIRQ_PIC(H, DISABLE) 32 33 /* CORE bank DIRQs - up to 16 supported */ 34 #define TPAD_IRQ_OFFSET 0 35 #define TOUCH_IRQ_OFFSET 1 36 #define I8042_IRQ_OFFSET 2 37 #define ALS_IRQ_OFFSET 3 38 /* Corresponding SCORE GPIO pins */ 39 #define TPAD_IRQ_GPIO 55 40 #define TOUCH_IRQ_GPIO 72 41 #define I8042_IRQ_GPIO 101 42 #define ALS_IRQ_GPIO 70 43 44 /* SUS bank DIRQs - up to 16 supported */ 45 #define CODEC_IRQ_OFFSET 0 46 /* Corresponding SUS GPIO pins */ 47 #define CODEC_IRQ_GPIO 9 48