1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 3 #include <acpi/acpi.h> 4 #include <cpu/x86/smm.h> 5 6 #include <ec/google/chromeec/smm.h> 7 #include "ec.h" 8 9 #include <soc/pm.h> 10 11 /* The wake gpio is SUS_GPIO[0]. */ 12 #define WAKE_GPIO_EN SUS_GPIO_EN0 13 14 /* The entire 32-bit ALT_GPIO_SMI register is passed as a parameter. Note, that 15 * this includes the enable bits in the lower 16 bits. */ mainboard_smi_gpi(uint32_t alt_gpio_smi)16void mainboard_smi_gpi(uint32_t alt_gpio_smi) 17 { 18 if (alt_gpio_smi & (1 << EC_SMI_GPI)) 19 chromeec_smi_process_events(); 20 } 21 mainboard_smi_sleep(uint8_t slp_typ)22void mainboard_smi_sleep(uint8_t slp_typ) 23 { 24 /* Disable USB charging if required */ 25 chromeec_set_usb_charge_mode(slp_typ); 26 27 switch (slp_typ) { 28 case ACPI_S3: 29 /* Enable wake pin in GPE block. */ 30 enable_gpe(WAKE_GPIO_EN); 31 break; 32 } 33 34 chromeec_smi_sleep(slp_typ, MAINBOARD_EC_S3_WAKE_EVENTS, MAINBOARD_EC_S5_WAKE_EVENTS); 35 } 36 mainboard_smi_apmc(uint8_t apmc)37int mainboard_smi_apmc(uint8_t apmc) 38 { 39 chromeec_smi_apmc(apmc, MAINBOARD_EC_SCI_EVENTS, MAINBOARD_EC_SMI_EVENTS); 40 return 0; 41 } 42