1 /* SPDX-License-Identifier: GPL-2.0-only */
2
3 #include <stdint.h>
4 #include <console/console.h>
5 #include <northbridge/intel/sandybridge/sandybridge.h>
6 #include <northbridge/intel/sandybridge/raminit.h>
7 #include <southbridge/intel/bd82x6x/pch.h>
8 #include <southbridge/intel/common/gpio.h>
9 #include <bootmode.h>
10 #include <ec/quanta/it8518/ec.h>
11 #include "ec.h"
12 #include "onboard.h"
13
mainboard_late_rcba_config(void)14 void mainboard_late_rcba_config(void)
15 {
16 /*
17 * GFX INTA -> PIRQA (MSI)
18 * D20IP_XHCI XHCI INTA -> PIRQD (MSI)
19 * D26IP_E2P EHCI #2 INTA -> PIRQF
20 * D27IP_ZIP HDA INTA -> PIRQA (MSI)
21 * D28IP_P2IP WLAN INTA -> PIRQD
22 * D28IP_P3IP Card Reader INTB -> PIRQE
23 * D28IP_P6IP LAN INTC -> PIRQB
24 * D29IP_E1P EHCI #1 INTA -> PIRQD
25 * D31IP_SIP SATA INTA -> PIRQB (MSI)
26 * D31IP_SMIP SMBUS INTB -> PIRQH
27 */
28
29 /* Device interrupt pin register (board specific) */
30 RCBA32(D31IP) = (NOINT << D31IP_TTIP) | (NOINT << D31IP_SIP2) |
31 (INTB << D31IP_SMIP) | (INTA << D31IP_SIP);
32 RCBA32(D30IP) = (NOINT << D30IP_PIP);
33 RCBA32(D29IP) = (INTA << D29IP_E1P);
34 RCBA32(D28IP) = (NOINT << D28IP_P1IP) | (INTA << D28IP_P2IP) |
35 (INTB << D28IP_P3IP) | (NOINT << D28IP_P4IP) |
36 (NOINT << D28IP_P5IP) | (INTC << D28IP_P6IP) |
37 (NOINT << D28IP_P7IP) | (NOINT << D28IP_P8IP);
38 RCBA32(D27IP) = (INTA << D27IP_ZIP);
39 RCBA32(D26IP) = (INTA << D26IP_E2P);
40 RCBA32(D25IP) = (NOINT << D25IP_LIP);
41 RCBA32(D22IP) = (NOINT << D22IP_MEI1IP);
42 RCBA32(D20IP) = (INTA << D20IP_XHCIIP);
43
44 /* Device interrupt route registers */
45 DIR_ROUTE(D31IR, PIRQB, PIRQH, PIRQA, PIRQC);
46 DIR_ROUTE(D29IR, PIRQD, PIRQE, PIRQF, PIRQG);
47 DIR_ROUTE(D28IR, PIRQD, PIRQE, PIRQB, PIRQC);
48 DIR_ROUTE(D27IR, PIRQA, PIRQB, PIRQC, PIRQD);
49 DIR_ROUTE(D26IR, PIRQF, PIRQB, PIRQC, PIRQD);
50 DIR_ROUTE(D25IR, PIRQA, PIRQB, PIRQC, PIRQD);
51 DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD);
52 DIR_ROUTE(D20IR, PIRQD, PIRQE, PIRQF, PIRQG);
53 }
54
55 /*
56 * The Stout EC needs to be reset to RW mode. It is important that
57 * the RTC_PWR_STS is not set until ramstage EC init.
58 */
early_ec_init(void)59 static void early_ec_init(void)
60 {
61 u8 ec_status = ec_read(EC_STATUS_REG);
62 int rec_mode = get_recovery_mode_switch();
63
64 if (((ec_status & 0x3) == EC_IN_RO_MODE) ||
65 ((ec_status & 0x3) == EC_IN_RECOVERY_MODE)) {
66 printk(BIOS_DEBUG, "EC Cold Boot Detected\n");
67 if (!rec_mode) {
68 /*
69 * Tell EC to exit RO mode
70 */
71 printk(BIOS_DEBUG, "EC will exit RO mode and boot normally\n");
72 ec_write_cmd(EC_CMD_EXIT_BOOT_BLOCK);
73 die("wait for ec to reset");
74 }
75 } else {
76 printk(BIOS_DEBUG, "EC Warm Boot Detected\n");
77 ec_write_cmd(EC_CMD_WARM_RESET);
78 }
79 }
80
mainboard_fill_pei_data(struct pei_data * pei_data)81 void mainboard_fill_pei_data(struct pei_data *pei_data)
82 {
83 /* TODO: Confirm if nortbridge_fill_pei_data() gets .system_type right (should be 0) */
84 }
85
mainboard_early_init(int s3resume)86 void mainboard_early_init(int s3resume)
87 {
88 /* Do ec reset as early as possible, but skip it on S3 resume */
89 if (!s3resume) {
90 early_ec_init();
91 }
92 }
93