1 /* SPDX-License-Identifier: GPL-2.0-only */
2
3 #include <bootmode.h>
4 #include <types.h>
5 #include <console/console.h>
6 #include <ec/quanta/it8518/ec.h>
7 #include <device/device.h>
8 #include <southbridge/intel/bd82x6x/pch.h>
9 #include <southbridge/intel/common/pmbase.h>
10 #include "ec.h"
11
stout_ec_init(void)12 void stout_ec_init(void)
13 {
14 printk(BIOS_DEBUG,"%s: EC FW version %x%x\n", __func__,
15 ec_read(EC_FW_VER), ec_read(EC_FW_VER + 1));
16
17 /*
18 * Important: get_recovery_mode_switch() must be called in EC init.
19 */
20 get_recovery_mode_switch();
21
22 /* Unmute */
23 ec_kbc_write_cmd(EC_KBD_CMD_UNMUTE);
24
25 /*
26 * Set USB Power off in S3 (enabled in S3 path if requested in gnvs)
27 * Bit0 of 0x0D/Bit0 of 0x26
28 * 0/0 All USB port off
29 * 1/0 USB on, all USB port didn't support wake up
30 * 0/1 USB on, yellow port support wake up charge, but may not support
31 * charge smart phone.
32 * 1/1 USB on, yellow port in AUTO mode and didn't support wake up system.
33 */
34 ec_write(EC_PERIPH_CNTL_3, ec_read(EC_PERIPH_CNTL_3) & 0xE);
35 ec_write(EC_USB_S3_EN, ec_read(EC_USB_S3_EN) & 0xE);
36
37 // TODO: Power Limit Setting
38 }
39
stout_ec_finalize_smm(void)40 void stout_ec_finalize_smm(void)
41 {
42 u8 ec_reg, critical_shutdown = 0;
43
44 /*
45 * Check EC for error conditions.
46 */
47
48 /* Fan Error : Peripheral Status 3 (0x35) bit 4 */
49 ec_reg = ec_read(EC_PERIPH_STAT_3);
50
51 if (ec_reg & 0x8) {
52 printk(BIOS_ERR, " EC Fan Error\n");
53 critical_shutdown = 1;
54 }
55
56 /* Thermal Device Error : Peripheral Status 3 (0x35) bit 8 */
57 if (ec_reg & 0x80) {
58 printk(BIOS_ERR, " EC Thermal Device Error\n");
59 critical_shutdown = 1;
60 }
61
62 /* Critical Battery Error */
63 ec_reg = ec_read(EC_MBAT_STATUS);
64
65 if ((ec_reg & 0xCF) == 0xC0) {
66 printk(BIOS_ERR, " EC Critical Battery Error\n");
67 critical_shutdown = 1;
68 }
69
70 if ((ec_reg & 0x8F) == 0x8F) {
71 printk(BIOS_ERR, " EC Read Battery Error\n");
72 }
73
74 if (critical_shutdown) {
75 printk(BIOS_ERR, "EC critical_shutdown");
76
77 /* Go to S5 */
78 write_pmbase32(PM1_CNT, read_pmbase32(PM1_CNT) | (0xf << 10));
79 }
80 }
81